Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device.The array substrate is provided with a fan-out region, the array substrate comprises a plurality of fan-out data line sets located in the fan-out region and arranged in the first direction, and each fan-out data line set comprises a plurality of fan-out data lines located in the fan-out region and arranged in the first direction; the plurality of fan-out data lines comprise a first fan-out data line and a second fan-out data line which are positioned on the first metal layer, and a third fan-out data line positioned on the second metal layer; the repairing line is positioned on the second metal layer; in the first direction, the first fan-out data lines and the second fan-out data lines are sequentially arranged, and third fan-out data lines or repair lines are arranged between the adjacent first fan-out data lines and second fan-out data lines. According to the technical scheme, the fan-out data lines corresponding to the same pixel can be located on the same metal layer, and the problem of uneven display caused by process fluctuation is avoided.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] With the development of display technology, people have higher and higher requirements for the resolution of display panels. In order to achieve high resolution, more data lines need to be laid in the display panel, which will increase the space occupied by the lower border area of ​​the display panel, which is not conducive to improving the screen-to-body ratio of the display panel. How to achieve high resolution without excessively squeezing the space of the lower border of the display panel is an important issue that needs to be solved at present. Summary of the invention

[0003] In order to solve the above problems, embodiments of the present application provide an array substrate, a display panel and a display device.

[0004] In a first aspect, an embodiment of the present application provides an array substrate having a fan-out area, the array substrate comprising: a plurality of fan-out data line groups located in the fan-out area, the plurality of fan-out data line groups being arranged along a first direction, each fan-out data line group comprising: a plurality of fan-out data lines, the plurality of fan-out data lines comprising a first fan-out data line and a second fan-out data line located in a first metal layer, and a third fan-out data line located in the second metal layer; a repair line located in the second metal layer; along the first direction, the first fan-out data line and the second fan-out data line are arranged in sequence, and a third fan-out data line or a repair line is provided between adjacent first fan-out data lines and second fan-out data lines.

[0005] In combination with the first aspect, along the first direction, the first fan-out data line, the third fan-out data line, the second fan-out data line and the repair line are arranged in sequence; or, along the first direction, the repair line, the first fan-out data line, the third fan-out data line and the second fan-out data line are arranged in sequence; or, along the first direction, the first fan-out data line, the repair line, the second fan-out data line and the third fan-out data line are arranged in sequence; or, along the first direction, the third fan-out data line, the first fan-out data line, the repair line and the second fan-out data line are arranged in sequence.

[0006] In combination with the first aspect, along the thickness direction of the array substrate, the orthographic projection of the repair line on the first metal layer does not overlap with the first fan-out data line and / or the second fan-out data line; preferably, the gap distance between the orthographic projection of the repair line on the first metal layer and the first fan-out data line or the second fan-out data line is greater than or equal to 0.4um and less than or equal to 1um.

[0007] In combination with the first aspect, along the thickness direction of the array substrate, the orthographic projection of the third fan-out data line on the first metal layer does not overlap with the first fan-out data line and / or the second fan-out data line; preferably, the gap distance between the orthographic projection of the third fan-out data line on the first metal layer and the first fan-out data line or the second fan-out data line is greater than or equal to 0.4um and less than or equal to 1um.

[0008] In combination with the first aspect, the fan-out data line group also includes a connecting lead, which is electrically connected to the repair line; preferably, the connecting lead is located in the third metal layer, and the connecting lead is connected to the repair line through a via; preferably, a first insulating layer is arranged between the first metal layer and the second metal layer, and a second insulating layer is arranged between the second metal layer and the third metal layer; preferably, the connecting lead extends along a first direction, and along the thickness direction of the array substrate, the orthographic projection of the connecting lead on the first metal layer overlaps with at least one of the first fan-out data line and the second fan-out data line, and / or the orthographic projection of the connecting lead on the second metal layer overlaps with the third fan-out data line; preferably, the array substrate also includes a display area, the fan-out area is located on one side of the display area, and the distance between the connecting lead and the edge of the display area is greater than or equal to 3um and less than or equal to 8um.

[0009] In combination with the first aspect, if any fan-out data line in any fan-out data line group is damaged, the damaged fan-out data line is electrically connected to a repair line in the fan-out data line group via a connecting lead in the fan-out data line group.

[0010] In combination with the first aspect, the repair line in the fan-out data line group is not electrically connected to the fan-out data line in the fan-out data line group.

[0011] In combination with the first aspect, the array substrate also includes a display area, and the fan-out area is located on one side of the display area; the array substrate also includes multiple data lines located in the display area, the multiple data lines are arranged along a first direction and extend along a second direction, and the second direction intersects with the first direction; a data line is electrically connected to a fan-out data line; preferably, the data line is electrically connected to the fan-out data line through a connecting via; preferably, the array substrate also includes a binding area, and the binding area is located on the side of the fan-out area away from the display area; the fan-out data line and the repair line are respectively electrically connected to the driving chip through the binding area.

[0012] In a second aspect, an embodiment of the present application provides a method for preparing an array substrate, which is used to prepare the above-mentioned array substrate, the method comprising: when any fan-out data line in any fan-out data line group is damaged, using a laser process to achieve electrical connection between the damaged fan-out data line and a repair line in the fan-out data line group.

[0013] In a third aspect, an embodiment of the present application provides a display panel, comprising the above-mentioned array substrate, or an array substrate prepared according to the above-mentioned method.

[0014] In a fourth aspect, an embodiment of the present application provides a display device, comprising the above-mentioned display panel.

[0015] Through the above technical solution, adjacent metal lines (for example, the first fan-out data line, the second fan-out data line, the third fan-out data line, and the repair line) are arranged in different layers, and by setting the repair line, the fan-out data lines corresponding to the same pixel can be located in the same metal layer, avoiding the problem of uneven display caused by process fluctuations. Furthermore, by setting connecting leads, when any fan-out data line is damaged, the connecting leads can be used to connect the damaged fan-out data line and the repair line, and the damaged fan-out data line can be replaced by the repair line, without replacing the array substrate, thereby improving the overall yield of the array substrate and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a structural schematic diagram of an array substrate provided in one embodiment of the present application.

[0017] Figure 2 yes Figure 1 The shown schematic cross-sectional view of the array substrate along line A1A2.

[0018] Figure 3 Detailed description of the invention Figure 4 is a schematic structural diagram of an array substrate provided in yet another embodiment of the present application.

[0019] Figure 4 yes Figure 3 The shown schematic cross-sectional view of the array substrate along line A1A2.

[0020] Figure 5 Detailed description of the invention Figure 4 is a schematic structural diagram of an array substrate provided in yet another embodiment of the present application.

[0021] Figure 6 yes Figure 5 The shown schematic cross-sectional view of the array substrate along line A1A2.

[0022] Figure 7 Detailed description of the invention Figure 4 is a schematic structural diagram of an array substrate provided in yet another embodiment of the present application.

[0023] Figure 8 yes Figure 7 The shown schematic cross-sectional view of the array substrate along line A1A2.

[0024] Fig. 9 Detailed description of the invention Figure 4 is a schematic structural diagram of an array substrate provided in yet another embodiment of the present application.

[0025] Fig.10 yes Fig. 9 The shown schematic cross-sectional view of the array substrate along line B1B2.

[0026] Figures 11a-11c yes Fig. 9 The shown schematic cross-sectional view of the array substrate along line B1B2.

[0027] Fig.12 It is a schematic diagram of the structure of a display device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] In order to achieve high resolution, it is necessary to set more data lines in the display panel. Too many data lines will occupy the space of the lower frame, which is not conducive to improving the screen ratio of the display panel. In order to solve this problem, the data lines (i.e., fan-out data lines) in the lower frame area are usually arranged in different layers, and the fan-out data lines arranged in different layers are arranged alternately. In this way, the distance between adjacent fan-out data lines can be reduced, which greatly reduces the occupied lower frame space compared to the same layer setting. However, the inventors have found that when the pixel arrangement is RGB pixel arrangement, the corresponding fan-out data lines are arranged alternately in sequence, i.e., R pixel fan-out data line-G pixel fan-out data line-B pixel fan-out data line-R pixel fan-out data line-G pixel fan-out data line-B pixel fan-out data line-…-R pixel fan-out data line-G pixel fan-out data line-B pixel fan-out data line. Since the fan-out data lines are arranged alternately in different layers, the fan-out data lines corresponding to the same pixel will be located in different metal layers. Due to process fluctuations, the line widths of data lines on different metal layers cannot be completely consistent, resulting in inconsistent voltages on the data lines of the same pixel, causing uneven display, namely mura, which affects the display effect of the display panel.

[0030] In order to solve the above technical problems, an embodiment of the present application provides an array substrate, which has a fan-out area, and the array substrate includes: a plurality of fan-out data line groups, which are located in the fan-out area, and the plurality of fan-out data line groups are arranged along a first direction, and each fan-out data line group includes: a plurality of fan-out data lines, and the plurality of fan-out data lines include a first fan-out data line and a second fan-out data line located in a first metal layer, and a third fan-out data line located in a second metal layer; a repair line located in the second metal layer; along the first direction, the first fan-out data line and the second fan-out data line are arranged in sequence, and a third fan-out data line or a repair line is arranged between adjacent first fan-out data lines and second fan-out data lines. In an embodiment of the present application, adjacent metal lines (for example, the first fan-out data line, the second fan-out data line, the third fan-out data line, and the repair line) are arranged in different layers, and by setting the repair line, the fan-out data lines corresponding to the same pixel can be located in the same metal layer, thereby avoiding the problem of uneven display caused by process fluctuations.

[0031] The technical solution of the present application is described below through specific embodiments.

[0032] Figure 1 It is a structural schematic diagram of an array substrate provided in one embodiment of the present application. Figure 2 yes Figure 1 The cross-sectional view of the array substrate along the A1A2 line is shown in FIG. Figure 1 and Figure 2 As shown, the array substrate has a fan-out area L2. The array substrate includes a plurality of fan-out data line groups 110, the fan-out data line groups 110 are located in the fan-out area L2, and the plurality of fan-out data line groups 110 are arranged along a first direction (ie, x direction).

[0033] In the embodiment of the present application, each fan-out data line group 110 includes a plurality of fan-out data lines and a repair line 114. Specifically, the plurality of fan-out data lines include a first fan-out data line 111, a second fan-out data line 112, and a third fan-out data line 113. Figure 2 As shown, the first fan-out data line 111 and the second fan-out data line 112 are located in the first metal layer 410, and the third fan-out data line 113 and the repair line 114 are located in the second metal layer 420. It can be understood that the "first metal layer" and "second metal layer" here are only used to distinguish different metal layers, and do not limit the position or preparation order of the first metal layer 410 and the second metal layer 420. For example, the first metal layer 410 can be prepared first, and the first metal layer 410 is close to the substrate, or the second metal layer 420 can be prepared first, and the second metal layer 420 is close to the substrate. A first insulating layer 510 is arranged between the first metal layer 410 and the second metal layer 420 to achieve electrical insulation between the first metal layer 410 and the second metal layer 420. It can be understood that the array substrate may also include other layers, Figure 2In order to illustrate the technical solution of the present application, only the first metal layer 410, the insulating layer 510 and the second metal layer 420 are shown.

[0034] In the embodiment of the present application, in each fan-out data line group, along the first direction (i.e., the x direction), the first fan-out data line 111 and the second fan-out data line 112 are arranged in sequence, and the third fan-out data line 113 is arranged between adjacent first fan-out data lines 111 and second fan-out data lines 112. That is, along the first direction, the first fan-out data line 111, the third fan-out data line 113, the second fan-out data line 112, and the repair line 114 are arranged in sequence.

[0035] In the embodiment of the present application, along the thickness direction (i.e., z direction) of the array substrate, the orthographic projection of the repair line 114 on the first metal layer 410 does not overlap with the first fan-out data line 111 and / or the second fan-out data line 112. Optionally, the gap distance between the orthographic projection of the repair line 114 on the first metal layer 410 and the first fan-out data line 111 or the second fan-out data line 112 is greater than or equal to 0.4um and less than or equal to 1um. Exemplarily, the gap distance between the orthographic projection of the repair line 114 on the first metal layer 410 and the first fan-out data line 111 or the second fan-out data line 112 is 0.4um, 0.5um, 0.6um, 0.7um, 0.8um, 0.9um, 1um. Since the first fan-out data line 111 or the second fan-out data line 112 and the repair line 114 are arranged in different layers, a smaller gap distance can be set compared to the same layer setting, thereby reducing the space occupied by the lower frame.

[0036] In the embodiment of the present application, along the thickness direction of the array substrate, the orthographic projection of the third fan-out data line 113 on the first metal layer 410 does not overlap with the first fan-out data line 111 and / or the second fan-out data line 112. Optionally, the gap distance between the orthographic projection of the third fan-out data line 113 on the first metal layer 410 and the first fan-out data line 111 or the second fan-out data line 112 is greater than or equal to 0.4um and less than or equal to 1um. Exemplarily, the gap distance between the orthographic projection of the third fan-out data line 113 on the first metal layer 410 and the first fan-out data line 111 or the second fan-out data line 112 is 0.4um, 0.5um, 0.6um, 0.7um, 0.8um, 0.9um, 1um. Since the first fan-out data line 111 or the second fan-out data line 112 and the third fan-out data line 113 are arranged in different layers, a smaller gap distance can be set compared to the same layer setting, thereby reducing the space occupied by the lower frame.

[0037] Continue to refer Figure 1, the array substrate also includes a display area L1, and the fan-out area L2 is located on one side of the display area L1. The array substrate also includes a plurality of data lines 210 located in the display area L1, and the plurality of data lines 210 are arranged along a first direction (i.e., the x direction) and extend along a second direction (i.e., the y direction), and the second direction intersects the first direction. Exemplarily, the angle between the second direction and the first direction is 90°. In the embodiment of the present application, a data line 210 is electrically connected to a fan-out data line, and a data line 210 corresponds to a color pixel. Figure 1 In the array substrate shown, exemplarily, the pixel arrangement is an RGB pixel arrangement, the first fan-out data line 111 is electrically connected to the data line 210 corresponding to the red pixel, the third fan-out data line 113 is electrically connected to the data line 210 corresponding to the green pixel, and the second fan-out data line 112 is electrically connected to the data line 210 corresponding to the blue pixel. Optionally, the data line 210 and the fan-out data line are located in different metal layers, and the data line 210 is electrically connected to the fan-out data line through a connecting via (not shown in the figure).

[0038] Continue to refer Figure 1 The array substrate further includes a binding area L3, which is located on a side of the fan-out area L2 away from the display area L1. The fan-out data lines (e.g., the first fan-out data lines 111, the second fan-out data lines 112, and the third fan-out data lines 113) and the repair lines 114 are electrically connected to the driver chip 30 through the binding area L3.

[0039] Figure 3 Detailed description of the invention Figure 4 is a schematic structural diagram of an array substrate provided in yet another embodiment of the present application. Figure 4 yes Figure 3 The cross-sectional view of the array substrate along the A1A2 line is shown in FIG. Figure 4 As shown, the array substrate and Figure 1 and Figure 2 The difference between the array substrate shown in FIG. 1 and FIG. 2 is that, along the first direction (ie, the x direction), the repair line 114, the first fan-out data line 111, the third fan-out data line 113, and the second fan-out data line 112 are arranged in sequence. Figure 1 The setting position of the repair line 114 in is different. Figure 3 In the array substrate shown, exemplarily, the pixel arrangement is an RGB pixel arrangement, the first fan-out data line 111 is electrically connected to the data line 210 corresponding to the red pixel, the third fan-out data line 113 is electrically connected to the data line 210 corresponding to the green pixel, and the second fan-out data line 112 is electrically connected to the data line 210 corresponding to the blue pixel. Optionally, the data line 210 and the fan-out data line are located in different metal layers, and the data line 210 is electrically connected to the fan-out data line through a connecting via (not shown in the figure).

[0040] Figure 5Detailed description of the invention Figure 4 is a schematic structural diagram of an array substrate provided in yet another embodiment of the present application. Figure 6 yes Figure 5 The cross-sectional view of the array substrate along the A1A2 line is shown in FIG. Figure 6 As shown, the array substrate and Figure 1 and Figure 2 The difference of the array substrate shown is that a repair line 114 is arranged between the first fan-out data line 111 and the second fan-out data line 112. Along the first direction (i.e., the x direction), the first fan-out data line 111, the repair line 114, the second fan-out data line 112, and the third fan-out data line 113 are arranged in sequence. Figure 5 In the array substrate shown, exemplarily, the pixel arrangement is an RGB pixel arrangement, the first fan-out data line 111 is electrically connected to the data line 210 corresponding to the red pixel, the second fan-out data line 112 is electrically connected to the data line 210 corresponding to the green pixel, and the third fan-out data line 113 is electrically connected to the data line 210 corresponding to the blue pixel. Optionally, the data line 210 and the fan-out data line are located in different metal layers, and the data line 210 is electrically connected to the fan-out data line through a connecting via (not shown in the figure).

[0041] Figure 7 Detailed description of the invention Figure 4 is a schematic structural diagram of an array substrate provided in yet another embodiment of the present application. Figure 8 yes Figure 7 The cross-sectional view of the array substrate along the A1A2 line is shown in FIG. Figure 8 As shown, the array substrate and Figure 1 and Figure 2 The difference of the array substrate shown is that a repair line 114 is arranged between the first fan-out data line 111 and the second fan-out data line 112. Along the first direction (i.e., the x direction), the third fan-out data line 113, the first fan-out data line 111, the repair line 114, and the second fan-out data line 112 are arranged in sequence. Figure 7 In the array substrate shown, exemplarily, the pixel arrangement is an RGB pixel arrangement, the third fan-out data line 113 is electrically connected to the data line 210 corresponding to the red pixel, the first fan-out data line 111 is electrically connected to the data line 210 corresponding to the green pixel, and the second fan-out data line 112 is electrically connected to the data line 210 corresponding to the blue pixel. Optionally, the data line 210 and the fan-out data line are located in different metal layers, and the data line 210 is electrically connected to the fan-out data line through a connecting via (not shown in the figure).

[0042] Fig. 9 Detailed description of the invention Figure 4 is a schematic structural diagram of an array substrate provided in yet another embodiment of the present application. Fig.10 yes Fig. 9 The schematic cross-sectional view of the array substrate along the line B1B2 is shown in FIG. Fig. 9 and Fig.10As shown, the array substrate further includes a connecting lead 115, and the connecting lead 115 is electrically connected to the repair line 114. Optionally, the connecting lead 115 is located in the third metal layer 430, and the connecting lead 115 is connected to the repair line 114 through a via. Optionally, a second insulating layer 520 is provided between the second metal layer 420 and the third metal layer 430. In the embodiment of the present application, the distance between the connecting lead 115 and the edge of the display area L1 is greater than or equal to 3um and less than or equal to 8um. Exemplarily, the distance between the connecting lead 115 and the edge of the display area L1 is 3um, 4um, 5um, 6um, 7um, 8um, preferably 5um.

[0043] In the embodiment of the present application, the connecting lead 115 extends along the first direction (i.e., the x direction), and along the thickness direction of the array substrate, the orthographic projection of the connecting lead 115 on the first metal layer 410 overlaps with at least one of the first fan-out data line 111 and the second fan-out data line 112, and / or the orthographic projection of the connecting lead 115 on the second metal layer 420 overlaps with the third fan-out data line 113. Fig. 9 and Fig.10 As shown, along the first direction, the first fan-out data line 111, the third fan-out data line 113, the second fan-out data line 112 and the repair line 114 are arranged in sequence, the connecting lead 115 is connected to the repair line 114 through a via, and the connecting lead 115 extends toward the first fan-out data line 111 until the orthographic projection of the connecting lead 115 on the first metal layer 410 overlaps with the first fan-out data line 111. At this time, when one of the first fan-out data line 111, the second fan-out data line 112 or the third fan-out data line 113 is damaged, the damaged fan-out data line and the repair line 114 can be connected by the connecting lead 115, and the repair line 114 can be used to replace the damaged fan-out data line for data transmission.

[0044] During the preparation of the array substrate, corrosion of the metal layer may occur (for example, the materials of the first metal layer and the second metal layer are molybdenum, which may be corroded), resulting in the breakage or poor contact of the fan-out data line, which may affect the display of the pixels on the display panel. In order to solve this technical problem, a connecting lead 115 is added in the embodiment of the present application. During the inspection, if a fan-out data line is detected to be damaged, the connecting lead 115 is used to connect the fan-out data line and the repair line, and the damaged fan-out data line is replaced by the repair line, without replacing the array substrate, thereby improving the yield of the array substrate and reducing the cost.

[0045] Specifically, if any fan-out data line in any fan-out data line group is damaged, the damaged fan-out data line is electrically connected to the repair line 114 in the fan-out data line group through the connecting lead 115 in the fan-out data line group. Optionally, the electrical connection between the damaged fan-out data line and the repair line 114 in the fan-out data line group is achieved using a laser process.

[0046] For example, Fig.11a As shown, the first fan-out data line 111 is damaged, and the first fan-out data line 111 and the repair line 114 are electrically connected through the connecting lead 115, wherein the first fan-out data line 111 and the connecting lead 115 are electrically connected through a via. Fig.11b As shown, the second fan-out data line 112 is damaged, and the second fan-out data line 112 and the repair line 114 are electrically connected through the connecting lead 115, wherein the second fan-out data line 112 and the connecting lead 115 are electrically connected through a via. Fig.11c As shown, the third fan-out data line 113 is damaged, and the third fan-out data line 113 and the repair line 114 are electrically connected through the connecting lead 115, wherein the third fan-out data line 113 and the connecting lead 115 are electrically connected through a via.

[0047] In the embodiment of the present application, by setting the repair line 114, the fan-out data lines corresponding to the same pixel can be located in the same metal layer, thereby avoiding the problem of uneven display caused by process fluctuations; further, by setting the connecting lead 115, when any fan-out data line is damaged, the connecting lead 115 can be used to connect the damaged fan-out data line and the repair line 114, and the repair line 114 can be used to replace the damaged fan-out data line, without replacing the array substrate, thereby improving the overall yield of the array substrate and reducing costs.

[0048] It can be understood that after the array substrate is inspected, if the fan-out data lines on the array substrate are intact (i.e., not damaged), there is no need to connect the repair line 114 and the fan-out data line. In addition, before the array substrate is inspected, it is not possible to determine whether the fan-out data line is damaged. At this time, the repair line 114 is not electrically connected to the fan-out data line. Therefore, the repair line 114 in the fan-out data line group 110 is not electrically connected to the fan-out data line in the fan-out data line group 110, which can be an intermediate product in the array substrate preparation process or a final product of the array substrate, and the embodiment of the present application is not limited thereto.

[0049] In a second aspect, the present application also provides a method for preparing an array substrate, which is applicable to the above array substrate. The method includes: when any fan-out data line in any fan-out data line group is damaged, using a laser process to electrically connect the damaged fan-out data line with a repair line in the fan-out data line group.

[0050] In a third aspect, an embodiment of the present application provides a display panel, which includes an array substrate and a plurality of pixel units. The array substrate is the array substrate described in the above embodiment, and the pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The driver chip connects the sub-pixels in the pixel unit through the fan-out data line and the data line of the display area, thereby driving the pixel unit to emit light.

[0051] In a fourth aspect, an embodiment of the present application provides a display device, which includes the display panel described in the above embodiment.

[0052] Fig.12 is a schematic diagram of the structure of a display device provided by an embodiment of the present application. Fig.12 As shown, the display device 1200 is a product with an image display function. For example, the display device 1200 can be used to display static images, such as pictures or photos. The display device 1200 can also be used to display dynamic images, such as videos.

[0053] The display device 1200 may be a laptop computer, a mobile phone, a handheld or portable computer, a camera, a camcorder, a vehicle-mounted smart central control screen, a calculator, a smart watch, a GPS navigator, an electronic photo, an electronic billboard or sign, a projector, etc.

[0054] The display device 1200 includes a display panel provided by any of the above embodiments, which may be an organic light emitting diode display panel or a quantum dot electroluminescent display panel.

[0055] In addition, the display device 1200 may also have functions such as taking photos, recording videos, fingerprint recognition, and face recognition. Accordingly, the display device 1200 also includes at least one functional module for implementing the above functions, such as an under-screen camera, an under-screen fingerprint recognition sensor, and the like.

[0056] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0057] The block diagrams of the devices, apparatuses, equipment, and systems involved in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagram. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open words, referring to "including but not limited to", and can be used interchangeably with them. The words "or" and "and" used here refer to the words "and / or" and can be used interchangeably with them, unless the context clearly indicates otherwise. The words "such as" used here refer to the phrase "such as but not limited to", and can be used interchangeably with them.

[0058] It should also be noted that in the apparatus, device and method of the present application, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present application.

[0059] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0060] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. An array substrate, characterized in that: Having a fan-out area, the array substrate comprises: A plurality of fan-out data line groups are located in the fan-out area, the plurality of fan-out data line groups are arranged along a first direction, and each of the fan-out data line groups includes: A plurality of fan-out data lines, the plurality of fan-out data lines comprising a first fan-out data line and a second fan-out data line located at the first metal layer, and a third fan-out data line located at the second metal layer; a repair line located at the second metal layer; Along the first direction, the first fan-out data lines and the second fan-out data lines are arranged in sequence, and the third fan-out data lines or the repair lines are arranged between adjacent first fan-out data lines and the second fan-out data lines.

2. The array substrate according to claim 1, characterized in that: Along the first direction, the first fan-out data line, the third fan-out data line, the second fan-out data line and the repair line are arranged in sequence; Alternatively, along the first direction, the repair line, the first fan-out data line, the third fan-out data line and the second fan-out data line are arranged in sequence; Alternatively, along the first direction, the first fan-out data line, the repair line, the second fan-out data line and the third fan-out data line are arranged in sequence; Alternatively, along the first direction, the third fan-out data line, the first fan-out data line, the repair line and the second fan-out data line are arranged in sequence.

3. The array substrate according to claim 1, characterized in that: Along the thickness direction of the array substrate, the orthographic projection of the repair line on the first metal layer does not overlap with the first fan-out data line and / or the second fan-out data line; Preferably, a gap distance between an orthographic projection of the repair line on the first metal layer and the first fan-out data line or the second fan-out data line is greater than or equal to 0.4 um and less than or equal to 1 um.

4. The array substrate according to claim 1, characterized in that: Along the thickness direction of the array substrate, the orthographic projection of the third fan-out data line on the first metal layer does not overlap with the first fan-out data line and / or the second fan-out data line; Preferably, a gap distance between an orthographic projection of the third fan-out data line on the first metal layer and the first fan-out data line or the second fan-out data line is greater than or equal to 0.4 um and less than or equal to 1 um.

5. The array substrate according to claim 1, characterized in that: The fan-out data line group further includes a connecting lead, wherein the connecting lead is electrically connected to the repair line; Preferably, the connecting lead is located in the third metal layer, and the connecting lead is connected to the repair line through a via; Preferably, a first insulating layer is provided between the first metal layer and the second metal layer, and a second insulating layer is provided between the second metal layer and the third metal layer; Preferably, the connecting lead extends along the first direction, and along the thickness direction of the array substrate, the orthographic projection of the connecting lead on the first metal layer overlaps with at least one of the first fan-out data line and the second fan-out data line, and / or the orthographic projection of the connecting lead on the second metal layer overlaps with the third fan-out data line; Preferably, the array substrate further comprises a display area, the fan-out area is located at one side of the display area, and the distance between the connecting lead and the edge of the display area is greater than or equal to 3 um and less than or equal to 8 um.

6. The array substrate according to claim 5, characterized in that: Any of the fan-out data lines in any of the fan-out data line groups is damaged, and the damaged fan-out data line is electrically connected to the repair line in the fan-out data line group through the connecting lead in the fan-out data line group.

7. The array substrate according to any one of claims 1 to 5, characterized in that: The repair line in the fan-out data line group is not electrically connected to the fan-out data line in the fan-out data line group.

8. The array substrate according to claim 1, characterized in that: The array substrate further comprises a display area, and the fan-out area is located at one side of the display area; The array substrate further comprises a plurality of data lines located in the display area, the plurality of data lines are arranged along the first direction and extend along a second direction, and the second direction intersects the first direction; One of the data lines is electrically connected to one of the fan-out data lines; Preferably, the data line is electrically connected to the fan-out data line through a connecting via; Preferably, the array substrate further comprises a binding area, and the binding area is located on a side of the fan-out area away from the display area; The fan-out data line and the repair line are electrically connected to the driving chip through the binding area respectively.

9. A method for preparing an array substrate, characterized in that: Applicable to the array substrate according to any one of claims 1 to 6, the method comprising: When any of the fan-out data lines in any of the fan-out data line groups is damaged, a laser process is used to electrically connect the damaged fan-out data line with the repair line in the fan-out data line group.

10. A display panel, characterized in that: The invention comprises an array substrate as claimed in any one of claims 1 to 8, or an array substrate prepared by the method according to claim 9.

11. A display device, characterized in that: Comprising the display panel according to claim 10.

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