Display substrate and display device

Abstract

According to the display substrate and the display device, the display substrate comprises a display area and a binding area connected with the display area, the display area comprises a plurality of data signal lines and K rows and L columns of sub-pixels, and K and L are both positive integers larger than 1; a plurality of first spaces are arranged among the K sub-pixel rows, a plurality of second spaces are arranged among the L sub-pixel columns, the first spaces are arranged between two adjacent sub-pixel rows, and the second spaces are arranged between two adjacent sub-pixel columns. At least one first space is provided with a first data connecting line, and at least one second space is provided with at least one second data connecting line; one end of the first data connecting line is electrically connected with one data signal line, and the other end of the first data connecting line is electrically connected with one second data connecting line; one end of the second data connection line is electrically connected with the first data line, and the other end is electrically connected with the binding area.

Description

[0001] This application is a divisional application of an application with an application date of September 9, 2022, application number 202280003189.2, and invention name “Display substrate, display device”. Technical Field

[0002] The present disclosure relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising a substrate, the substrate comprising a display area and a binding area located on one side of the display area, the display area comprising a plurality of first power lines, a plurality of data signal lines, at least one first data connection line, at least one second data connection line, at least one initial signal connection line, and K rows and L columns of sub-pixels, where K and L are both positive integers greater than 1; the second data connection line and the initial signal connection line are located between two adjacent columns of sub-pixels, and on a plane parallel to the display substrate, the first data connection line extends along a first direction, the second data connection line, the data signal line, the first power line, and the initial signal connection line extend along a second direction, and the first direction intersects with the second direction;

[0006] One end of the first data connection line is electrically connected to one of the data signal lines, and the other end is electrically connected to one of the second data connection lines; one end of the second data connection line is electrically connected to the first data connection line, and the other end extends to the binding area;

[0007] In the first direction, between two adjacent first power lines, there are two data signal lines, one initial signal connection line and at least one second data connection line, and the two data signal lines are located on both sides of the at least one second data connection line and the one initial signal connection line.

[0008] In an exemplary embodiment, in the first direction, between two adjacent first power lines: the at least one second data connection line includes at least two second data connection lines located on both sides of the one initial signal connection line, and the two second data connection lines located on both sides of the one initial signal connection line are symmetrically distributed relative to the one initial signal connection line.

[0009] In an exemplary embodiment, in the first direction, between two adjacent first power lines: the two data signal lines are symmetrically distributed with respect to the one initial signal connection line.

[0010] In an exemplary embodiment, at least one sub-pixel includes a pixel driving circuit, at least one pixel driving circuit includes a plurality of low-temperature polysilicon transistors, a plurality of oxide transistors, and a storage capacitor, and in a direction perpendicular to a plane where the display substrate is located, the display substrate includes a substrate and a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially stacked on the substrate;

[0011] The first semiconductor layer includes: an active layer of a plurality of low temperature polysilicon transistors;

[0012] The first conductive layer includes: control electrodes of a plurality of low temperature polysilicon transistors and a first electrode plate of a storage capacitor;

[0013] The second conductive layer includes: a second plate of a storage capacitor;

[0014] The second semiconductor layer includes: an active layer of a plurality of oxide transistors;

[0015] The third conductive layer includes: control electrodes of a plurality of oxide transistors;

[0016] The fourth conductive layer includes: the first data connection line, a first electrode and a second electrode of a plurality of low temperature polysilicon transistors;

[0017] The fifth conductive layer includes: the data signal line, the first power line and the second data connection line.

[0018] In an exemplary embodiment, in the first direction, between two adjacent first power lines: the at least one second data connection line includes at least two second data connection lines located on both sides of the one initial signal connection line, the two second data connection lines located on both sides of the one initial signal connection line are symmetrically distributed relative to the one initial signal connection line, and the two second data connection lines located on both sides of the one initial signal connection line are electrically connected to two different first data connection lines through two different vias.

[0019] In an exemplary embodiment, two adjacent columns of sub-pixels share one first power line.

[0020] In an exemplary embodiment, at least one sub-pixel further includes a fourteenth via hole, a thirteenth via hole, and an anode;

[0021] The plurality of low temperature polysilicon transistors include a fifth transistor and a sixth transistor, the thirteenth via hole is configured to electrically connect the anode and the sixth transistor, and the fourteenth via hole is configured to electrically connect the first power line and the fifth transistor;

[0022] The first power line is provided with a plurality of hollow structures, and in the same first power line: the plurality of hollow structures are arranged at intervals along the second direction, and in at least some of the plurality of hollow structures, each of the hollow structures is configured to accommodate two thirteenth vias in two adjacent columns of sub-pixels sharing the first power line.

[0023] In an exemplary embodiment, in the same row of sub-pixels, a central connection line between the thirteenth via hole and the fourteenth via hole of at least two adjacent sub-pixels extends along the first direction.

[0024] In an exemplary embodiment, at least one row of sub-pixels is provided with a light emission control line, and the light emission control line extends along the first direction;

[0025] In the same row of sub-pixels, the orthographic projections of the plurality of the thirteenth via holes and the plurality of the fourteenth via holes on the substrate at least partially overlap with the orthographic projections of the light emitting control lines in the row of sub-pixels on the substrate.

[0026] In an exemplary embodiment, in the first direction, in two columns of sub-pixels located on both sides of one of the initial signal connection lines, the first semiconductor layer is symmetrical with respect to the initial signal connection line, and the second semiconductor layer is symmetrical with respect to the initial signal connection line.

[0027] In an exemplary embodiment, at least one sub-pixel further includes an anode, and in the same sub-pixel, the pixel driving circuit is electrically connected to the anode;

[0028] The multiple low-temperature polysilicon transistors include a seventh transistor for resetting the anode of the light-emitting element, and at least one row of sub-pixels is provided with a second initial signal line. The second initial signal line is connected to the active layer of the seventh transistor in the first semiconductor layer of at least one row of sub-pixels through a via, and the second initial signal line is configured to write an initial voltage into the seventh transistor; the second initial signal line in the at least one row of sub-pixels is connected to at least one of the initial signal connection lines.

[0029] In an exemplary embodiment, the low-temperature polysilicon transistor in the pixel driving circuit includes a third transistor and a fourth transistor, the second electrode of the fourth transistor is electrically connected to the first electrode of the third transistor, and the first electrode of the fourth transistor is electrically connected to one of the data signal lines;

[0030] The shape of the active layer of the fourth transistor is a zigzag shape extending along the second direction, the active layer of the fourth transistor includes a first end, a second end and a main body, in the same sub-pixel, in the second direction, the main body is located between the first end and the second end, the first end is connected to the active layer of the third transistor, and the second end is located on a side of the main body away from the active layer of the third transistor;

[0031] At least a portion of the structure of the main body near the second end is bent in a direction away from the active layer of the third transistor, and in the first direction: the distance between at least a portion of the structure of the main body near the second end and the active layer of the third transistor is greater than the distance between the first end and the active layer of the third transistor, and greater than the distance between the second end and the active layer of the third transistor, and greater than the distance between at least a portion of the structure of the main body near the first end and the active layer of the third transistor.

[0032] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising the display substrate described in any of the above embodiments.

[0033] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shape and size of each component in the accompanying drawings do not reflect the actual proportion, and the purpose is only to illustrate the content of the present disclosure.

[0035] Figure 1 is a structural schematic diagram of a display device;

[0036] Figure 2 It is a structural schematic diagram of a display substrate;

[0037] Figure 3 It is a schematic diagram of the planar structure of a display area in a display substrate;

[0038] Figure 4 A schematic diagram of the cross-sectional structure of a display area in a display substrate;

[0039] Figure 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0040] Figure 6 is a working timing diagram of a pixel driving circuit;

[0041] Figure 7a Shown is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0042] Figure 7b Shown is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0043] Figure 8a Shown is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0044] Figure 8b Shown is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0045] Figure 8c Shown is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0046] Fig. 9 It is a schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure after a shielding layer pattern is formed;

[0047] Fig.10a It is a schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure after a first semiconductor layer pattern is formed;

[0048] Fig.10b Shown is a schematic diagram of a first semiconductor layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0049] Fig.11a It is a schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure after a first conductive layer pattern is formed;

[0050] Fig.11b Shown is a schematic diagram of a first conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0051] Fig.12aIt is a schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure after a second conductive layer pattern is formed;

[0052] Figure 12b Shown is a schematic diagram of a second conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0053] Fig.13a It is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a second semiconductor layer pattern is formed;

[0054] Fig.13b Shown is a schematic diagram of a second semiconductor layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0055] Fig.14a It is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a third conductive layer pattern is formed;

[0056] Fig.14b Shown is a schematic diagram of a third conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0057] Fig.15 It is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a sixth insulating layer pattern is formed;

[0058] Fig.16a It is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fourth conductive layer pattern is formed;

[0059] Fig.16b Shown is a schematic diagram of a fourth conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0060] Fig.16c It is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fourth conductive layer pattern is formed;

[0061] Fig.16d Shown is a schematic diagram of a fourth conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0062] Fig.17a It is a schematic diagram after forming a first planar layer pattern provided by an exemplary embodiment of the present disclosure;

[0063] Fig.17b It is a schematic diagram after forming a first planar layer pattern provided by an exemplary embodiment of the present disclosure;

[0064] Fig.18a It is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fifth conductive layer pattern is formed;

[0065] Fig.18b Shown is a schematic diagram of a fifth conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0066] Fig.18c It is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fifth conductive layer pattern is formed;

[0067] Fig.19a It is a schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure after a first semiconductor layer pattern is formed;

[0068] Fig.19b Shown is a schematic diagram of a first semiconductor layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0069] Fig.20a It is a schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure after a first conductive layer pattern is formed;

[0070] Fig.20b Shown is a schematic diagram of a first conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0071] Fig.21 It is a schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure after a second conductive layer pattern is formed;

[0072] Fig. 22 It is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a second semiconductor layer pattern is formed;

[0073] Fig.23a It is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a third conductive layer pattern is formed;

[0074] Figure 23b Shown is a schematic diagram of a third conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0075] Fig.24 It is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a sixth insulating layer pattern is formed;

[0076] Fig.25a It is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fourth conductive layer pattern is formed;

[0077] Fig.25b Shown is a schematic diagram of a fourth conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0078] Fig.25cIt is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fourth conductive layer pattern is formed;

[0079] Fig.25d Shown is a schematic diagram of a fourth conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0080] Fig.26a It is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a first planar layer pattern is formed;

[0081] Figure 26b It is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a first planar layer pattern is formed;

[0082] Fig.27a It is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fifth conductive layer pattern is formed;

[0083] Figure 27b Shown is a schematic diagram of a fifth conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0084] Fig.27c FIG. 1 is a schematic diagram of a display substrate after a fifth conductive layer pattern is formed thereon, provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0085] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The embodiments can be implemented in a number of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to the general design.

[0086] The proportions of the drawings in this disclosure can be used as a reference in actual processes, but are not limited thereto. For example, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual conditions. The drawings described in this disclosure are only schematic diagrams of the structure, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0087] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0088] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of describing each constituent element. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0089] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0090] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0091] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged. In the disclosed embodiments, the gate electrode may be referred to as a control electrode.

[0092] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0093] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0094] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0095] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0096] The term "about" in the embodiments of the present disclosure means that the limits are not strictly defined and a numerical value within the range of process and measurement errors is allowed.

[0097] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include at least one scan signal line, at least one data signal line, at least one light emitting signal line and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal, and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm. For example, the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number. The light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be constructed in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number.

[0098] Figure 2 FIG. 1 is a schematic diagram of the structure of a display substrate. Figure 2As shown, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area, including a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij being configured to display a dynamic picture or a still image, and the display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, so that the display substrate may be deformable, such as curling, bending, folding, or rolling up. In an exemplary embodiment, the display substrate may further include a display area boundary BD, and the display area boundary BD may be an edge of the display area 100 close to the binding area 200.

[0099] In an exemplary embodiment, the binding area 200 may include a fan-out area, a bending area, a driver chip area, and a binding pin area arranged in sequence along a direction away from the display area. The fan-out area is connected to the display area and includes a plurality of data fan-out lines. The data fan-out lines are configured to connect the data signal lines (Data Line) of the display area in a fan-out routing manner. The fan-out area occupies a large space, resulting in a large width of the lower frame. The bending area is connected to the fan-out area and may include a composite insulating layer provided with a groove, which is configured to bend the binding area to the back of the display area. The driver chip area may include an integrated circuit (IC) configured to be connected to a plurality of data fan-out lines. The binding pin area may include a binding pad configured to be bound and connected to an external flexible printed circuit (FPC).

[0100] In an exemplary embodiment, the border area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area arranged in sequence in a direction away from the display area. The circuit area is connected to the display area and may include at least a gate drive circuit, which is connected to the first scan signal line, the second scan signal line, the third scan signal line, and the light-emitting control line of the pixel drive circuit in the display area. The power line area is connected to the circuit area and may include at least a power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area. The crack dam area is connected to the power line area and may include at least a plurality of cracks set on the composite insulating layer. The cutting area is connected to the crack dam area and may include at least a cutting groove set on the composite insulating layer, and the cutting groove is configured so that after all the film layers of the display substrate are prepared, the cutting equipment cuts along the cutting groove respectively.

[0101] In an exemplary embodiment, the fan-out area in the binding area 200 and the power line area in the border area 300 may be provided with a first isolation dam and a second isolation dam, and the first isolation dam and the second isolation dam may extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area, and the edge of the display area is the edge on one side of the display area binding area or the border area.

[0102] Figure 3 FIG. 1 is a schematic diagram of a planar structure of a display area in a display substrate. Figure 3 As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 and a fourth sub-pixel P4 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting device, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scanning signal line, the data signal line and the light-emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0103] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement. In other exemplary embodiments, the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement or a square arrangement, etc., which is not limited in the present disclosure.

[0104] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangular arrangement, which is not limited in the present disclosure.

[0105] Figure 4 FIG. 1 is a schematic diagram of a cross-sectional structure of a display region in a display substrate, illustrating the structure of four sub-pixels in the display region. Figure 4As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and a packaging structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.

[0106] In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 of each sub-pixel may include a light-emitting device composed of a plurality of film layers, and the plurality of film layers may include at least an anode, a pixel definition layer, an organic light-emitting layer and a cathode, the anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0107] In an exemplary embodiment, the organic light emitting layer may include a light emitting layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all sub-pixels may be a common layer connected together, and the light emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated from each other.

[0108] Figure 5 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Figure 5As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit is respectively connected to 10 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, third scanning signal line S3, fourth scanning signal line S4, light emitting signal line E, first initial signal line INIT1, second initial signal line INIT2, first power line VDD and second power line VSS).

[0109] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the second node N2 is respectively connected to the second electrode of the first transistor T1, the control electrode of the third transistor T3, and the second end of the storage capacitor C, and the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.

[0110] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0111] In an exemplary embodiment, the control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, and the second electrode of the first transistor T1 is connected to the second node N2. When the turned-on scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the first initialization voltage to the second end of the storage capacitor C to initialize the storage capacitor C.

[0112] In an exemplary embodiment, a control electrode of the second transistor T2 is connected to the fourth scan signal line S4, a first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, and a second electrode of the second transistor T2 is connected to the third node N3. When a turned-on scan signal is applied to the fourth scan signal line S4, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode of the third transistor T3.

[0113] In an exemplary embodiment, the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor, and the third transistor T3 determines the size of the driving current flowing between the first power line VDD and the light emitting device according to the potential difference between its control electrode and the first electrode.

[0114] In an exemplary embodiment, a control electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the data signal line D, and a second electrode of the fourth transistor T4 is connected to the first node N1. When a turned-on scan signal is applied to the third scan signal line S3, the fourth transistor T4 inputs a data voltage of the data signal line D to the first node N1.

[0115] In an exemplary embodiment, a control electrode of the fifth transistor T5 is connected to the light emitting signal line E, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the first node N1. A control electrode of the sixth transistor T6 is connected to the light emitting signal line E, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. When a turned-on light emitting signal is applied to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the light emitting device to cause the light emitting device to emit light.

[0116] In an exemplary embodiment, the control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When the turned-on scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the second initial voltage to the first electrode of the light emitting device to initialize or release the charge accumulated in the first electrode of the light emitting device.

[0117] In an exemplary embodiment, the light-emitting device can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0118] In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD continuously provides a high level signal.

[0119] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.

[0120] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a low-temperature polysilicon transistor, or an oxide transistor, or a low-temperature polysilicon transistor and a metal oxide transistor. The active layer of the low-temperature polysilicon transistor is low-temperature polysilicon (LTPS), and the active layer of the metal oxide transistor is metal oxide semiconductor (Oxide). The low-temperature polysilicon transistor has the advantages of high mobility and fast charging, and the oxide transistor has the advantages of low leakage current. The low-temperature polysilicon transistor and the metal oxide transistor are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0121] Figure 6 This is a working timing diagram of a pixel driving circuit. Figure 5 The operation process of the pixel driving circuit of the example is described in detail. Figure 5 The pixel driving circuit in the embodiment includes 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C, the first transistor T1 and the second transistor T2 are N-type oxide transistors, and the third transistor T3 to the seventh transistor T7 are P-type low temperature polysilicon transistors. In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0122] The first stage A1 is called the reset stage. The signal of the second scan signal line S2 is a turn-on signal (high level), and the signals of the first scan signal line S1, the third scan signal line S3, the fourth scan signal line S4 and the light-emitting signal line E are turn-off signals. The turn-on signal of the second scan signal line S2 turns on the first transistor T1, and the signal of the first initial signal line INIT1 is provided to the second node N2 through the first transistor T1 to initialize (reset) the storage capacitor C and clear the original charge in the storage capacitor. The turn-off signals of the first scan signal line S1, the third scan signal line S3, the fourth scan signal line S4 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In this stage, the OLED does not emit light.

[0123] The second stage A2 is called the data writing stage or the threshold compensation stage. The signals of the first scanning signal line S1, the third scanning signal line S3 and the fourth scanning signal line S4 are the on signals, the signals of the second scanning signal line S2 and the light emitting signal line E are the off signals, and the data signal line D outputs the data voltage. In this stage, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The on signals of the first scanning signal line S1, the third scanning signal line S3 and the fourth scanning signal line S4 turn on the second transistor T2, the fourth transistor T4 and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3 and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage of the second end (the second node N2) of the storage capacitor C is Vd-|Vth|, Vd is the data voltage output by the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on so that the signal of the second initial signal line INIT2 is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the OLED is ensured not to emit light. The disconnection signal of the second scanning signal line S2 disconnects the first transistor T1, and the disconnection signal of the light-emitting signal line E disconnects the fifth transistor T5 and the sixth transistor T6.

[0124] The third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a conduction signal, and the signals of the first scanning signal line S1, the second scanning signal line S2, the third scanning signal line S3 and the fourth scanning signal line S4 are disconnection signals. The conduction signal of the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.

[0125] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0126] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0127] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0128] With the development of OLED display technology, consumers have higher and higher requirements for the display effect of display products, and extremely narrow borders have become a new trend in the development of display products. Therefore, the narrowing of the border or even the borderless design has received more and more attention in the design of OLED display products. At present, it is difficult to design the narrowing of the bottom border (the border on the side of the binding area) of the display device. In order to reduce the width of the bottom border, some display substrates mainly adopt the solution of reducing the length of the fan-out area or the bending area. However, under the existing process capability conditions, the bottom border is still much larger than the left and right borders.

[0129] The exemplary embodiments of the present disclosure provide a display substrate such as Figures 7a to 8c As shown, it may include: a display area and a binding area connected to the display area, the display area may include a plurality of data signal lines 71 and K rows and L columns of sub-pixels P, K and L are both positive integers greater than 1; a plurality of first spaces R1 are included between the K sub-pixel rows, a plurality of second spaces R2 are included between the L sub-pixel columns, the first space is located between two adjacent sub-pixel rows, the second space R2 is located between two adjacent sub-pixel columns, at least one first space R1 is provided with a first data connection line 68, at least one second space R2 is provided with at least one second data connection line 74, on a plane parallel to the display substrate, the first data connection line 68 extends along a first direction X, the second data connection line 74 extends along a second direction Y, and the first direction X intersects the second direction Y;

[0130] One end of the first data connection line 68 is electrically connected to one of the data signal lines 71, and the other end is electrically connected to one of the second data connection lines; one end of the second data connection line 74 is electrically connected to the first data connection line 68, and the other end is electrically connected to the binding area.

[0131] The display substrate provided by the embodiment of the present disclosure has a display area of ​​the display substrate including multiple data signal lines and K rows and L columns of sub-pixels, where K and L are both positive integers greater than 1; multiple first spaces R1 are included between the K sub-pixel rows, multiple second spaces are included between the L sub-pixel columns, the first space is located between two adjacent sub-pixel rows, the second space is located between two adjacent sub-pixel columns, at least one first space is provided with a first data connection line, and at least one second space is provided with at least one second data connection line; one end of the first data connection line is electrically connected to one of the data signal lines, and the other end is electrically connected to one of the second data connection lines; one end of the second data connection line is electrically connected to the first data connection line, and the other end is electrically connected to the binding area; the introduction of the first data connection line and the second data connection line in the display area greatly reduces the border of the display substrate, which is conducive to the realization of a narrow border of the display product.

[0132] In the disclosed embodiment, a data fan-out line (i.e., the first data connection line 68 and the second data connection line 74) is located in the display area (Fanout in AA, FIAA for short) structure is adopted, one end of the plurality of data fan-out lines is located in the display area of ​​the display substrate, and is correspondingly connected to the plurality of data signal lines in the display area, and the other end of the plurality of data fan-out lines extends to the binding area, and is correspondingly connected to the integrated circuit. Since there is no need to set a fan-shaped oblique line in the binding area, the width of the fan-out area is reduced, and the width of the lower frame of the display substrate is effectively reduced.

[0133] In an exemplary embodiment, one end of the first data connection line 68 can be electrically connected to one of the data signal lines 71 through a via, and the other end can be electrically connected to one of the second data connection lines through a via; or, one end of the first data connection line 68 and one of the data signal lines 71 can be an integrally formed structure set on the same layer, and the other end and one of the second data connection lines can be an integrally formed structure set on the same layer.

[0134] In an exemplary embodiment, the second data connection line 74 and the first data connection line 68 may be connected through a via, or the second data connection line 74 and the first data connection line 68 may be a molding structure disposed in the same layer.

[0135] In an exemplary embodiment, Figures 8a to 8c As shown, the first space R1 is further provided with a fourth data connection line 611, and the second space R2 is further provided with a third data connection line 610;

[0136] The same second space R2 is provided with at least one third data connection line 610 and at least one second data connection line 74;

[0137] The fourth data connection line 611 extends along the first direction X, one end of which is electrically connected to the data signal line, and the other end is connected to the third data line connection line 610; the third data connection line 610 extends along the second direction Y, one end of which is connected to the fourth data connection line 611, and the other end is electrically connected to the binding area.

[0138] In an exemplary embodiment, Figures 8a to 8c , Figure 25d to Figure 27c As shown, the first data connection line 68 and the second data connection line 74 may be connected through a via, and the third data connection line 610 and the fourth data connection line 611 may be an integrally formed structure.

[0139] In an exemplary embodiment, Figure 8c , Fig.27c As shown, the first data connection line 68 and the fourth data connection line 611 can be located in different first spaces R1, or the first data connection line 68 and the fourth data connection line 611 can be located in different first spaces R1 or in the same first space R1, and there is no overlapping area between the orthographic projections of the first data connection line 68 and the fourth data connection line 611 on the substrate, and there is no overlapping area between the orthographic projections of the first data connection line 68 and the third data connection line 610 on the substrate.

[0140] In an exemplary embodiment, Figures 8a to 8c As shown, in the same second space R2, the number of the third data connection line 610 is one, the number of the second data connection lines 74 is two, and in the plane where the display substrate is located, in the first direction X, the two second data connection lines 74 are located on both sides of the third data connection line 610, and the two second data connection lines 74 in the same second space R2 are connected to different first data connection lines 68; or in the same second space R2, the number of the third data connection line 610 is two, the number of the second data connection line 74 is one, and in the plane where the display substrate is located, in the first direction X, the two third data connection lines 610 are located on both sides of the second data connection line 74, and the two third data connection lines 610 in the same second space R2 are connected to different fourth data connection lines 611.

[0141] In an exemplary embodiment, Figure 7a and Figure 7b As shown, in the same second space R2 , the number of the second data connection lines 74 is three, and the three second data connection lines 74 are respectively connected to three different first data connection lines 68 .

[0142] In an exemplary embodiment, at least one subpixel P includes a pixel driving circuit, and in a plane perpendicular to the display substrate, the display substrate includes a substrate and a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially stacked on the substrate;

[0143] The first semiconductor layer includes: an active layer of multiple low-temperature polysilicon transistors located in the pixel driving circuit; the first conductive layer includes: control electrodes of multiple polysilicon transistors located in the pixel driving circuit and a first electrode plate of a storage capacitor; the second conductive layer includes: a second electrode plate of a storage capacitor located in the pixel driving circuit; the second semiconductor layer includes: an active layer of multiple oxide transistors located in the pixel driving circuit; the third conductive layer includes: control electrodes of multiple oxide transistors located in the pixel driving circuit; the fourth conductive layer includes: a first data connection line 68 and the first and second electrodes of multiple low-temperature polysilicon transistors located in the pixel driving circuit, and the first and second electrodes of multiple oxide transistors; the fifth conductive layer includes: a data signal line, a first power line, and a second data connection line 74.

[0144] The display substrate provided by the embodiment of the present disclosure adopts center compression for pixels, that is, the pitch (Pitch) of adjacent sub-pixels can remain unchanged, so that the Fanout wiring enters the display area and is placed in the gap compressed by the pixel driving circuit (that is, the first space and the second space mentioned above), and the Fanout wiring (including the data fan-out line) adopts the SD metal layer (that is, the fourth conductive layer and / or the fifth conductive layer) horizontally (including the first data connection line mentioned above and the fourth data connection line involved below) and vertically (including the second data connection line mentioned above and the third data connection line involved below). Without increasing the number of mask templates (BPMask), FIAA (Fanout In AA, the Fanout wiring is made in the AA area) is adopted to achieve a narrow frame, and the LTPO PPI can be increased to 430.

[0145] In an exemplary embodiment, the pitch may be the distance between the midpoints of two adjacent sub-pixels P. Figure 8a and Figure 8b As shown, L1 may be a pitch between two adjacent columns of sub-pixels along a first direction X, and L2 may be a pitch between two adjacent rows of sub-pixels along a second direction Y.

[0146] In an exemplary embodiment, pixel center compression can be understood as compressing the distance between components or component sizes in the pixel driving circuit to form the above-mentioned first space R1 and second space R2 to place the data fan-out line, thereby reducing the bottom frame of the display substrate, while keeping the pitch of adjacent sub-pixels unchanged, so that the resolution of the display substrate will not decrease.

[0147] In an exemplary embodiment, the display substrate further includes a light emitting element, and the plurality of low temperature polysilicon transistors include a seventh transistor for resetting an anode voltage of the light emitting element, such as Figure 23b As shown, the third conductive layer also includes a transfer connection electrode 53, such as Fig.25b As shown, the fourth conductive layer also includes a plurality of second initial signal lines 67. In the plane where the fourth conductive layer is located, the main part of the second initial signal line 67 is in a zigzag shape extending along the first direction X. The plurality of second initial signal lines 67 are arranged in an array along the first direction X and the second direction Y. The second initial signal line 67 is connected to the active layer of the seventh transistor in the first semiconductor layer through a via hole and is multiplexed as the first electrode of the seventh transistor. In the same sub-pixel row, two adjacent second initial signal lines 67 are connected to the same transfer connection electrode 53 through a transfer via hole.

[0148] In an exemplary embodiment, Figure 8b to Figure 8c , Figure 23b As shown, the via connection electrode 53 extends along the first direction X, and an orthographic projection of the via connection electrode 53 on the substrate and an orthographic projection of one of the second spaces R2 on the substrate have an overlapping area.

[0149] In an exemplary embodiment, Figures 8a to 8c As shown, the fourth conductive layer further includes a fourth data connection line 611 and a third data connection line 610, the orthographic projection of the fourth data connection line 611 on the substrate at least partially overlaps with the orthographic projection of one of the first spaces R1 on the substrate, and the orthographic projection of the fourth data connection line 611 on the substrate does not overlap with the orthographic projection of the first data connection line 68 on the substrate; the orthographic projection of the third data connection line 610 on the substrate at least partially overlaps with the orthographic projection of one of the second spaces R2 on the substrate. In an exemplary embodiment, the third data connection line 610 extends along the second direction Y, one end is connected to the fourth data connection line 611, and the other end is electrically connected to the binding area; the fourth data connection line 611 extends along the first direction X, one end is connected to the third data connection line 610, and the other end is electrically connected to one of the data signal lines in the fifth conductive layer through a via. In an exemplary embodiment, in the same second space R2, the orthographic projection of the second data connection line 74 on the substrate does not overlap with the orthographic projection of the third data connection line 610 on the substrate.

[0150] In an exemplary embodiment, Figure 8cAs shown, in the same second space R2, the number of the third data connection line 610 is one, the number of the second data connection line 74 is two, and the orthographic projection of the third data connection line 610 on the substrate is located between the orthographic projections of the two second data connection lines 74 on the substrate. Alternatively, in the same second space R2, the number of the third data connection line 610 is two, the number of the second data connection line 74 is one, and the orthographic projection of the second data connection line 74 on the substrate is located between the orthographic projections of the two third data connection lines 610 on the substrate.

[0151] In an exemplary embodiment, Figure 8b and Figure 8c As shown, the orthographic projections of the second data connection line 74 and the third data connection line 610 on the substrate overlap with the orthographic projection of the transfer connection electrode 53 on the substrate, and the orthographic projections of the second data connection line 74 and the third data connection line 610 on the substrate do not overlap with the orthographic projection of the second initial signal line 67 on the substrate.

[0152] In an exemplary embodiment, Figure 8b and Figure 8c As shown, the pixel driving circuit further includes: a first transistor T1 to a sixth transistor T6, and a storage capacitor;

[0153] On a plane parallel to the display substrate, in the same pixel driving circuit, in the first direction X, the sixth transistor T6 is located on one side of the storage capacitor, and the fifth transistor T5 and the fourth transistor T4 are located on the other side of the storage capacitor; in the second direction Y, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are located on the same side of the storage capacitor, and the fourth transistor T4, the first transistor T1, and the second transistor T2 are located on the other side of the storage capacitor, and the seventh transistor T7 is located on the side of the sixth transistor T6 away from the storage capacitor, and the first transistor T1 is located on the side of the second transistor T2 away from the storage capacitor, and the positive projection of the storage capacitor on the substrate and the positive projection of the third transistor T3 on the substrate have an overlapping area; the seventh transistor T7 in the i-th row sub-pixel is arranged in the i-1-th row sub-pixel, i=2, 3, ..., K;

[0154] In the second direction Y, in the two sub-pixel rows adjacent to the first data connection line 68, the first transistor T1 of the previous sub-pixel row and the fifth transistor T5 and the sixth transistor T6 of the next sub-pixel row are located on both sides of the first data connection line 68, and the seventh transistor T7 of the next sub-pixel row is located on the same side of the first data connection line 68 as the first transistor T1 of the previous sub-pixel row; in the two sub-pixel rows adjacent to the fourth data connection line 611, the first transistor of the previous sub-pixel row and the fifth transistor and the sixth transistor of the next sub-pixel row are located on both sides of the fourth data connection line 611, and the seventh transistor T7 of the next sub-pixel row is located on the same side of the first data connection line 68 as the first transistor T1 of the previous sub-pixel row. The seventh transistor of the pixel row and the first transistor of the previous sub-pixel row are located on the same side of the fourth data connection line 611; in the first direction X, the total number of the second data connection and the third data connection line 610 is three, and the three data connection lines are arranged along the first direction line X. The two data connection lines located on both sides are symmetrical with respect to the data connection line located in the middle position. In the same sub-pixel row, the first transistor T1 to the seventh transistor T7 and the storage capacitor in the two sub-pixel columns adjacent to the second data connection line 74 and the third data connection line 610 located in the same second space are symmetrically arranged with respect to the data connection line located in the middle position.

[0155] In an exemplary embodiment, Figure 8b , Figure 8c , 27a to Fig.27c As shown, in the fourth conductive layer, the fourth data connection line 611 and the first electrode of the fourth transistor T4 in one of the pixel driving circuits are integrally formed, and the first electrode 64 of the fourth transistor integrally formed with the fourth data connection line 611 (the fourth connection electrode 64 described below) is a strip structure or a folded line structure, and extends along the second direction Y, with one end connected to the fourth data connection line 611, and the other end electrically connected to the data signal line in the fifth conductive layer through a via hole; one end of the fourth data connection line 611 is connected to the first electrode 64 of the fourth transistor, and the other end is connected to the third data connection line 610;

[0156] The first data connection line 68 and the first electrode 64 of one of the fourth transistors are an integrally formed structure. The first electrode 64 of the fourth transistor integrally formed with the first data connection line 68 is a strip structure or a fold line structure, and extends along the second direction Y, with one end connected to the first data connection line 68, and the other end electrically connected to the data signal line in the fifth conductive layer through a via; one end of the first data connection line 68 is connected to the first electrode 64 of the fourth transistor, and the other end is electrically connected to the second data connection line 74 in the fifth conductive layer through a via.

[0157] In an exemplary embodiment, Figure 7bAs shown, in the same second space R2, the number of second data connection lines 74 is three, and the orthographic projections of the three second data connection lines 74 on the substrate do not overlap, and the three second data connection lines 74 are electrically connected to the first data connection lines 68 in three different first spaces R1 in the fourth conductive layer through three different vias.

[0158] In an exemplary embodiment, Figure 7b and Fig.16b As shown, the display substrate also includes a light-emitting element, and the multiple low-temperature polysilicon transistors include a seventh transistor T7 for resetting the anode voltage of the light-emitting element. The fourth conductive layer also includes an initial signal connection line 69 and multiple second initial signal lines 67; the second initial signal line 67 is connected to the active layer of the seventh transistor T7 in the first semiconductor layer through a via hole, and is multiplexed as the first electrode of the seventh transistor T7; in the plane where the fourth conductive layer is located, the main part of the second initial signal line 67 is a fold line extending along the first direction X, and the multiple second initial signal lines 67 are arranged along the second direction Y; the initial signal connection line 69 extends along the second direction Y and is integrally formed with the multiple second initial signal lines 67.

[0159] In an exemplary embodiment, Figure 7b , Figure 18a-18b As shown, among the three second data connection lines 74, the orthographic projection of the second data connection line 74 located in the middle position on the substrate has an overlapping area with the orthographic projection of the initial signal connection line 69 on the substrate, and the orthographic projection of the second data connection line 74 located on both sides on the substrate has an overlapping area with the orthographic projection of the second initial signal line 67 on the substrate.

[0160] In an exemplary embodiment, the pixel driving circuit further includes: a first transistor T1 to a sixth transistor T6, and a storage capacitor;

[0161] On a plane parallel to the display substrate, in the same pixel driving circuit, in the first direction X, the sixth transistor T6 is located on one side of the storage capacitor, and the fifth transistor T5 and the fourth transistor T4 are located on the other side of the storage capacitor; in the second direction Y, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are located on the same side of the storage capacitor, and the fourth transistor T4, the first transistor T1, and the second transistor T2 are located on the other side of the storage capacitor, and the seventh transistor T7 is located on the side of the sixth transistor T6 away from the storage capacitor, and the first transistor T1 is located on the side of the second transistor T2 away from the storage capacitor, and the positive projection of the storage capacitor on the substrate and the positive projection of the third transistor T3 on the substrate have an overlapping area; the seventh transistor T7 in the i-th row sub-pixel is arranged in the i-1-th row sub-pixel, i=2, 3, ..., K;

[0162] In the second direction Y, in two sub-pixel rows adjacent to the first data connection line 68, the first transistor T1 of the previous sub-pixel row and the fifth transistor T5 and the sixth transistor T6 of the next sub-pixel row are located on both sides of the first data connection line 68, and the seventh transistor T7 of the next sub-pixel row is located on the same side of the first data connection line 68 as the first transistor T1 of the previous sub-pixel row; in the first direction X, the three second data connection lines 74 are arranged in sequence, and the second data connection lines 74 located on both sides are symmetrical with respect to the second data connection line 74 located in the middle position. In the same sub-pixel row, the first transistor T1 to the seventh transistor T7 and the storage capacitor in the two sub-pixel columns adjacent to the three second data connection lines 74 are symmetrically arranged with respect to the second data connection line 74 located in the middle position.

[0163] In an exemplary embodiment, Figure 7b , Figures 16a to 16d As shown, in the fourth conductive layer, the first data connection line 68 and the first electrode 64 of one of the fourth transistors (the fourth connection electrode 64 described below) are an integrally formed structure, and the first electrode 64 of the fourth transistor integrally formed with the first data connection line 68 is a strip structure or a fold line structure, and extends along the second direction Y, with one end connected to the first data connection line 68, and the other end electrically connected to the data signal line in the fifth conductive layer through a via; one end of the first data connection line 68 is connected to the first electrode 64 of the fourth transistor, and the other end is electrically connected to the second data connection line 74 in the fifth conductive layer through a via.

[0164] In an exemplary embodiment, Figures 7a to 8c As shown, the orthographic projection of one end of the first data connection line 68 on the substrate has an overlapping area with the orthographic projection of one of the second data connection lines 74 on the substrate, and is electrically connected to the second data connection line 74 in the projection overlapping area through a via, and the orthographic projection of the other end on the substrate has an overlapping area with the orthographic projection of one of the data signal lines 71 on the substrate, and is electrically connected to the data signal line 71 through a via.

[0165] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes on a substrate (or substrate). If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0166] In an exemplary embodiment, taking 8 sub-pixels (2 sub-pixel rows and 4 sub-pixel columns) in a display area (AA) as an example, a process for preparing a display substrate may include the following operations.

[0167] (101) Prepare a substrate on a glass carrier. In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a bonding layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate. The first and second inorganic material layers are also called barrier layers, and the material of the bonding layer may be amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible material (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible material (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0168] (102) Forming a blocking layer pattern. In an exemplary embodiment, forming the blocking layer pattern may include: depositing a conductive film of the blocking layer on the substrate, patterning the conductive film of the blocking layer through a patterning process, and forming the blocking layer pattern on the substrate, such as Fig. 9 As shown, Fig. 9 This is a planar structural diagram of the shielding layer pattern in eight sub-pixels.

[0169] In an exemplary embodiment, the shielding layer pattern of each sub-pixel may include a first shielding structure 11, a second shielding structure 12, a third shielding structure 13 and a shielding block 14. The shielding block 14 may be in a rectangular shape, and the corners of the rectangle may be chamfered. The first shielding structure 11 may be in a strip shape extending along the first direction X, and the first shielding structure 11 is arranged on one side of the first direction X of the shielding block 14 and is connected to the shielding block 14. The second shielding structure 12 may be in a strip shape extending along the second direction Y, and the second shielding structure 12 is arranged on one side of the shielding block 14 in the opposite direction of the second direction Y, and is connected to the shielding block 14. The third shielding structure 13 may be in a broken line shape extending along the second direction Y, and the third shielding structure 13 is arranged on one side of the second direction Y of the shielding block 14 and is connected to the shielding block 14.

[0170] In an exemplary embodiment, the first shielding structure 11 of each sub-pixel is connected to the shielding block 14 of the adjacent sub-pixel in the first direction X, so that the shielding layers in one sub-pixel row are connected as one, forming an interconnected integrated structure.

[0171] In an exemplary embodiment, the second shielding structure 12 of each sub-pixel is connected to the third shielding structure 13 of the adjacent sub-pixel in the second direction Y, so that the shielding layers in one sub-pixel column are connected as one to form an interconnected integrated structure.

[0172] In an exemplary embodiment, the shielding layers in the sub-pixel rows and sub-pixel columns are connected as one, which can ensure that the shielding layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0173] In an exemplary embodiment, the blocking layer in the Nth column and the blocking layer in the N+1th column may be mirror-symmetrical with respect to the first center line, the blocking layer in the N+1th column and the blocking layer in the N+2th column may be mirror-symmetrical with respect to the second center line, the blocking layer in the N+2th column and the blocking layer in the N+3th column may be mirror-symmetrical with respect to the third center line, and the first center line, the second center line, and the third center line may be straight lines extending along the second direction Y between adjacent sub-pixel columns, respectively.

[0174] In an exemplary embodiment, the shapes of the shielding layers in a plurality of sub-pixel rows may be the same.

[0175] (103) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: depositing a first insulating film and a first semiconductor film in sequence on the substrate having the aforementioned pattern, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the shielding layer pattern, and a first semiconductor layer pattern disposed on the first insulating layer, such as Fig.10a and Fig.10b As shown, Fig.10a is a planar structure diagram of eight sub-pixels. Fig.10b for Fig.10a Schematic plan view of the first semiconductor layer in FIG.

[0176] In an exemplary embodiment, the first semiconductor layer pattern of each subpixel may include the active layers 23 to 27 of the third to seventh transistors T3 to T7 as an integral structure connected to each other.

[0177] In an exemplary embodiment, in the first direction X, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on the same side of the active layer 23 of the third transistor T3, and the active layer 26 of the sixth transistor T6 is located on the other side of the active layer 23 of the third transistor T3; in the second direction Y, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on both sides of the active layer 23 of the third transistor T3, and the active layer 25 of the fifth transistor T5, the active layer 26 of the sixth transistor T6, and the active layer 27 of the seventh transistor T7 are located on the same side of the active layer 23 of the third transistor T3, and the active layer 27 of the seventh transistor T7 is located on the side of the active layer 26 of the sixth transistor T6 away from the active layer 23 of the third transistor T3.

[0178] In an exemplary embodiment, the sub-pixel in the Mth row and the Nth column is taken as an example for description: in the first direction X, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the N+1th column, and the active layer 26 of the sixth transistor T6 is located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the N-1th column; in the second direction Y, the active layer 24 of the fourth transistor T4 is located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the M-1th row, the active layer 25 of the fifth transistor T5, the active layer 26 of the sixth transistor T6, and the active layer 27 of the seventh transistor T7 are located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the M+1th row, and the active layer 27 of the seventh transistor T7 is located on the side of the active layer 26 of the sixth transistor T6 away from the active layer 23 of the third transistor T3.

[0179] In an exemplary embodiment, the active layer 23 of the third transistor T3 may have an Ω shape, the active layer 24 of the fourth transistor T4 and the active layer 27 of the seventh transistor T7 may have an I shape, and the active layer 25 of the fifth transistor T5 and the active layer 26 of the sixth transistor T6 may have an L shape.

[0180] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the first region 23-1 of the active layer 23 of the third transistor T3 may be used as the second region 24-2 of the active layer 24 of the fourth transistor T4 and the second region 25-2 of the active layer 25 of the fifth transistor T5, the second region 23-2 of the active layer 23 of the third transistor T3 may be used as the first region 26-1 of the active layer 26 of the sixth transistor T6, the second region 26-2 of the active layer 26 of the sixth transistor T6 may be used as the second region 27-2 of the active layer 27 of the seventh transistor T7, and the first region 24-1 of the active layer 24 of the fourth transistor T4, the first region 25-1 of the active layer 25 of the fifth transistor T5, and the first region 27-1 of the active layer 27 of the seventh transistor T7 may be separately provided.

[0181] In an exemplary embodiment, the orthographic projection of the active layer 23 of the third transistor T3 on the substrate at least partially overlaps with the orthographic projection of the blocking block 14 on the substrate. In an exemplary embodiment, the orthographic projection of the channel region of the active layer 23 of the third transistor T3 on the substrate is within the range of the orthographic projection of the blocking block 14 on the substrate.

[0182] In an exemplary embodiment, the first region 25-1 of the active layer 25 of the fifth transistor T5 in the Nth column and the first region 25-1 of the active layer 25 of the fifth transistor T5 in the N-1th column are connected to each other, and the first region 25-1 of the active layer 25 of the fifth transistor T5 in the N+1th column and the first region 25-1 of the active layer 25 of the fifth transistor T5 in the N+2th column are connected to each other. In an exemplary embodiment, since the first region of the active layer of the fifth transistor T5 in each sub-pixel is connected to the first power line formed subsequently, by forming the first regions of the active layers of the fifth transistors T5 of adjacent sub-pixels into an integrated structure connected to each other, it can be ensured that the first electrodes of the fifth transistors T5 of adjacent sub-pixels have the same potential, which is conducive to improving the uniformity of the panel display, avoiding the display defect of the display substrate, and ensuring the display effect of the display substrate.

[0183] In an exemplary embodiment, the first semiconductor layer in the Nth column and the first semiconductor layer in the N+1th column may be mirror-symmetrical with respect to the first center line, the first semiconductor layer in the N+1th column and the first semiconductor layer in the N+2th column may be mirror-symmetrical with respect to the second center line, and the first semiconductor layer in the N+2th column and the first semiconductor layer in the N+3th column may be mirror-symmetrical with respect to the third center line.

[0184] In an exemplary embodiment, the first region 27 - 1 of the active layer 27 of the seventh transistor T7 in the i-th row of sub-pixels may be disposed in the i-1-th row of sub-pixels, i=2, 3, . . . , M+1.

[0185] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si), that is, the third transistor T3 to the seventh transistor T7 may be LTPS thin film transistors. In an exemplary embodiment, patterning the first semiconductor film by a patterning process may include: first forming an amorphous silicon (a-si) film on the first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and performing a crystallization treatment on the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, the polycrystalline silicon film is patterned to form a first semiconductor layer pattern.

[0186] (104) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, such as Fig.11a and Fig.11b As shown, Fig.11b for Fig.11a In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0187] In an exemplary embodiment, the first conductive layer pattern may include at least: a first scanning signal line 31, a light emitting control line 32, and a first electrode plate 33 of a storage capacitor. The main parts of the first scanning signal line 31 and the light emitting control line 32 may extend along the first direction X. In the same sub-pixel, the light emitting control line 32, the first electrode plate 33 of the storage capacitor, and the first scanning signal line 31 are arranged along the second direction Y.

[0188] In an exemplary embodiment, the first scan signal line 31 and the light emitting control line 32 are located on both sides of the first electrode plate 33 of the storage capacitor in the second direction Y. For example, in the second direction, the light emitting control line 32, the first electrode plate 33, and the first scan signal line 31 are arranged in sequence.

[0189] Take the Mth row and Nth column sub-pixel as an example: in the second direction Y, the light-emitting control line 32 can be located on the side of the first plate 33 of the storage capacitor in this sub-pixel close to the M-1th row sub-pixel; the first scanning signal line 31 can be located on the side of the first plate 33 of the storage capacitor in this sub-pixel close to the M+1th row sub-pixel.

[0190] In an exemplary embodiment, the first electrode plate 33 may be located between the light emitting control line 32 and the first scanning signal line 31, the first electrode plate 33 may be rectangular, the corners of the rectangular shape may be chamfered, and the orthographic projection of the first electrode plate 33 on the substrate and the orthographic projection of the active layer of the third transistor T3 on the substrate have an overlapping area. In an exemplary embodiment, the first electrode plate 33 may simultaneously serve as a plate of the storage capacitor and a control electrode of the third transistor T3.

[0191] In an exemplary embodiment, the area where the light emitting control line 32 overlaps with the active layer of the fifth transistor T5 serves as the control electrode of the fifth transistor T5, the area where the light emitting control line 32 overlaps with the active layer of the sixth transistor T6 serves as the control electrode of the sixth transistor T6, the area where the first scanning signal line 31 overlaps with the active layer of the fourth transistor T4 serves as the control electrode of the fourth transistor T4, and the area where the first scanning signal line 31 overlaps with the active layer of the seventh transistor T7 serves as the control electrode of the seventh transistor T7.

[0192] In an exemplary embodiment, the first scanning signal lines 31 and the light emitting control lines 32 may be designed with equal widths, or may be designed with unequal widths, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0193] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer can be conductorized using the first conductive layer as a shield, and the semiconductor layer in the area shielded by the first conductive layer forms the channel region of the third transistor T3 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the active layer 23 of the third transistor T3 to the active layer 27 of the seventh transistor T7 are both conductorized.

[0194] (105) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, such as Figure 12a to Figure 12b As shown, Fig.12a is a planar structure diagram of eight sub-pixels. Figure 12b for Fig.12a In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0195] In an exemplary embodiment, the second conductive layer pattern includes at least: a first shielding line 41, a second shielding line 42, a second plate 43 of a storage capacitor, and a first initial signal line 45. The main parts of the first shielding line 41, the second shielding line 42, and the first initial signal line 45 can extend along the first direction X. The second plate 43 of the storage capacitor serves as another plate of the storage capacitor. In the second direction Y, the second shielding line 42 is located between the first shielding line 41 and the second plate 43, and the first shielding line 41 is located between the second shielding line 42 and the first initial signal line 45. For example, in the same sub-pixel, the second plate 43 of the storage capacitor, the second shielding line 42, the first shielding line 41, and the first initial signal line 45 are arranged in sequence along the second direction Y.

[0196] In an exemplary embodiment, the first shielding line 41 is configured as a shielding layer of the first transistor T1, shielding the channel of the first transistor T1, and the second shielding line 42 is configured as a shielding layer of the second transistor T2, shielding the channel of the second transistor T2, and ensuring the electrical performance of the oxide first transistor T1 and the oxide second transistor T2. In an exemplary embodiment, the first shielding line 41 and the signal of the second scanning signal line 51 formed subsequently can be the same, that is, the first shielding line 41 and the second scanning signal line 51 formed subsequently are connected in parallel, and the two are connected to the same signal source, so that the first shielding line 41 can be used as the bottom gate electrode (i.e., the bottom control electrode) of the first transistor T1, forming the first transistor T1 with a double-gate structure; the second shielding line 42 and the signal of the third scanning signal line 52 formed subsequently can be the same, that is, the second shielding line 42 and the third scanning signal line 52 formed subsequently are connected in parallel, and the two are connected to the same signal source, so that the second shielding line 42 can be used as the bottom gate electrode (i.e., the bottom control electrode) of the second transistor T2, forming the second transistor T2 with a double-gate structure.

[0197] In an exemplary embodiment, the outline of the second electrode plate 43 may be rectangular, and the corners of the rectangle may be chamfered. The orthographic projection of the second electrode plate 43 on the substrate overlaps with the orthographic projection of the first electrode plate 33 on the substrate, and the first electrode plate 33 and the second electrode plate 43 constitute a storage capacitor of the pixel driving circuit. An opening 44 is provided on the second electrode plate 43, and the opening 44 may be located in the middle of the second electrode plate 43. The opening 44 may be rectangular, so that the second electrode plate 43 forms a ring structure. The opening 44 exposes the third insulating layer covering the first electrode plate 33, and the orthographic projection of the first electrode plate 33 on the substrate includes the orthographic projection of the opening 44 on the substrate. In an exemplary embodiment, the opening 44 is configured to accommodate a ninth via hole formed subsequently, and the ninth via hole is located in the opening 44 and exposes the first electrode plate 33, so that the second pole of the first transistor T1 formed subsequently is connected to the first electrode plate 33.

[0198] (106) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: depositing a fourth insulating film and a second semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, such as Figure 13a to Figure 13b As shown, Fig.13a is a planar structure diagram of eight sub-pixels. Fig.13b for Fig.13a Schematic plan view of the second semiconductor layer in FIG.

[0199] In an exemplary embodiment, the second semiconductor layer pattern in each sub-pixel includes at least an active layer 21 of a first transistor T1 and an active layer 22 of a second transistor T2, and the active layer 21 of the first transistor T1 and the active layer 22 of the second transistor T2 are an integral structure connected to each other.

[0200] In an exemplary embodiment, the active layer 21 of the first transistor T1 and the active layer 22 of the second transistor T2 may be shaped like an "I", the second region 21-2 of the active layer 21 of the first transistor T1 may serve as the first region 22-1 of the active layer 22 of the second transistor T2, and the first region 21-1 of the active layer 21 of the first transistor T1 and the second region 22-2 of the second active layer 22 may be separately provided.

[0201] In an exemplary embodiment, the second semiconductor layer in the Nth column and the second semiconductor layer in the N+1th column may be mirror-symmetrical with respect to the first center line, the second semiconductor layer in the N+1th column and the second semiconductor layer in the N+2th column may be mirror-symmetrical with respect to the second center line, and the second semiconductor layer in the N+2th column and the second semiconductor layer in the N+3th column may be mirror-symmetrical with respect to the third center line.

[0202] In an exemplary embodiment, the shapes of the second semiconductor layers in a plurality of sub-pixel rows may be the same.

[0203] In an exemplary embodiment, in the plane where the display substrate is located, in the first direction X, the active layer 21 of the first transistor T1 and the active layer 22 of the second transistor T2 are located on a side of the active layer 23 of the third transistor T3 away from the active layer 24 of the fourth transistor T4; in the second direction Y, the active layer 21 of the first transistor T1 and the active layer 22 of the second transistor T2 are located on a side of the active layer 23 of the third transistor T3 away from the active layer 25 of the fifth transistor T5, and the active layer 21 of the first transistor T1 is located on a side of the active layer 22 of the second transistor T2 away from the active layer 23 of the third transistor T3.

[0204] In an exemplary embodiment, the second semiconductor layer may be made of oxide, that is, the first transistor T1 and the second transistor T2 are oxide thin film transistors. In an exemplary embodiment, the oxide may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc oxynitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxysulfide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN) and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the second semiconductor film may be made of indium gallium zinc oxide (IGZO), and the electron mobility of indium gallium zinc oxide (IGZO) is higher than that of amorphous silicon. Since the leakage current of the IGZO TFT is relatively small, the first transistor T1 and the second transistor T2 are both N-type transistors, which can prevent the second node N2 from leaking during the light-emitting stage.

[0205] (107) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a fifth insulating film and a third conductive film in sequence on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, such as Figure 14a to Figure 14b As shown, Fig.14a is a planar structure diagram of eight sub-pixels. Fig.14b for Fig.14a In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0206] In an exemplary embodiment, the third conductive layer pattern includes at least: a second scan signal line 51 and a third scan signal line 52. The main parts of the second scan signal line 51 and the third scan signal line 52 can extend along the first direction X, and the third scan signal line 52 and the second scan signal line 51 are arranged in sequence along the second direction Y.

[0207] In an exemplary embodiment, the area where the second scan signal line 51 overlaps with the active layer 21 of the first transistor T1 serves as the control electrode of the first transistor T1 , and the area where the third scan signal line 52 overlaps with the active layer 22 of the second transistor T2 serves as the control electrode of the second transistor T2 .

[0208] In an exemplary embodiment, the signals of the first shielding line 41 and the second scanning signal line 51 can be the same, that is, the two are connected in parallel and connected to the same signal source, so that the first shielding line 41 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the first transistor T1, forming a first transistor T1 with a dual-gate structure.

[0209] In an exemplary embodiment, the signals of the second shielding line 42 and the third scanning signal line 52 can be the same, that is, the two are connected in parallel and connected to the same signal source, so that the second shielding line 42 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the second transistor T2, forming a second transistor T2 with a dual-gate structure.

[0210] (108) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer is provided with a plurality of via holes, such as Fig.15 As shown, Fig.15 This is a planar structure diagram of eight sub-pixels.

[0211] In an exemplary embodiment, the multiple via holes in each sub-pixel include at least: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9, a tenth via hole V10 and an eleventh via hole V11.

[0212] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the active layer 21 of the first transistor T1 on the substrate, and the sixth insulating layer and the fifth insulating layer in the first via hole V1 are etched away to expose the surface of the first region 21-1 of the active layer 21 of the first transistor T1. The first via hole V1 is configured to connect the first electrode of the first transistor T1 formed subsequently to the active layer 21 of the first transistor T1 through the via hole.

[0213] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is within the range of the orthographic projection of the active layer 22 of the second transistor T2 on the substrate, and the sixth insulating layer and the fifth insulating layer in the second via hole V2 are etched away to expose the surface of the second region 22-2 of the active layer 22 of the second transistor T2. The second via hole V2 is configured to connect the second electrode of the second transistor T2 formed subsequently to the active layer 22 of the second transistor T2 through the via hole.

[0214] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is within the range of the orthographic projection of the active layer 22 of the second transistor T2 on the substrate, and the sixth insulating layer and the fifth insulating layer in the third via hole V3 are etched away, exposing the surface of the first region 22-1 of the active layer 22 of the second transistor T2 (also the second region 21-2 of the active layer 21 of the first transistor T1). The third via hole V3 is configured to connect the second electrode of the first transistor T1 formed subsequently to the active layer 21 of the first transistor T1 through the via hole, and to connect the first electrode of the second transistor T2 formed subsequently to the active layer 22 of the second transistor T2 through the via hole.

[0215] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the active layer 24 of the fourth transistor T4 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the fourth via hole V4 are etched away to expose the first region 24-1 of the active layer 24 of the fourth transistor T4. The fourth via hole V4 is configured to connect the first electrode of the fourth transistor T4 formed subsequently to the active layer 24 of the fourth transistor T4 through the via hole.

[0216] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is within the range of the orthographic projection of the active layer 25 of the fifth transistor T5 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first region 25-1 of the active layer 25 of the fifth transistor T5. The fifth via hole V5 is configured to connect the first electrode of the subsequently formed fifth transistor T5 to the active layer 25 of the fifth transistor T5 through the via hole.

[0217] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is within the range of the orthographic projection of the active layer 26 of the sixth transistor T6 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first region 26-1 of the active layer 26 of the sixth transistor T6 (also the second region of the active layer 23 of the third transistor T3). The sixth via hole V6 is configured to connect the first electrode of the subsequently formed sixth transistor T6 to the active layer 26 of the sixth transistor T6 through the via hole, and to connect the second electrode of the subsequently formed third transistor T3 to the active layer 23 of the third transistor T3 through the via hole.

[0218] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is within the range of the orthographic projection of the active layer 26 of the sixth transistor T6 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the second region 26-2 of the active layer 26 of the sixth transistor T6 (also the second region 27-2 of the active layer 27 of the seventh transistor T7). The seventh via hole V7 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the active layer 26 of the sixth transistor T6 through the via hole, and to connect the second electrode of the subsequently formed seventh transistor T7 to the active layer 27 of the seventh transistor T7 through the via hole.

[0219] In an exemplary embodiment, the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the active layer 27 of the seventh transistor T7 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the eighth via hole V8 are etched away to expose the surface of the first region 27-1 of the active layer 27 of the seventh transistor T7. The eighth via hole V8 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the active layer 27 of the seventh transistor T7 through the via hole.

[0220] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is within the range of the orthographic projection of the opening 44 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, and the third insulating layer in the ninth via hole V9 are etched away to expose the surface of the first electrode plate 33. The ninth via hole V9 is configured to connect the second electrode of the first transistor T1 formed subsequently to the first electrode plate 33 through the via hole.

[0221] In an exemplary embodiment, the tenth via hole V10 is located within the range of the orthographic projection of the second electrode plate 43 on the substrate, and the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer in the tenth via hole V10 are etched away to expose the surface of the second electrode plate 43. The tenth via hole V10 is configured to connect the subsequently formed sixth connection electrode to the second electrode plate 43 through the via hole. In an exemplary embodiment, the tenth via hole V10 as a power via hole may include a plurality of the tenth via holes V10, and the plurality of tenth via holes V10 may be arranged in sequence along the second direction Y or the first direction X to increase the connection reliability between the first power line and the second electrode plate 43.

[0222] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first initial signal line 45 on the substrate, and the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first initial signal line 45. The eleventh via hole V11 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first initial signal line 45 through the via hole.

[0223] (109) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the sixth insulating layer, such as Figures 16a to 16d As shown, Fig.16a is a planar structure diagram of eight sub-pixels. Fig.16b for Fig.16a Schematic diagram of the fourth conductive layer in the figure. Fig.16c is a planar structure diagram of sixteen sub-pixels. Fig.16d for Fig.16c In an exemplary embodiment, the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0224] In an exemplary embodiment, the fourth conductive layer includes at least: a first connection electrode 61 , a second connection electrode 62 , a third connection electrode 63 , a fourth connection electrode 64 , a fifth connection electrode 65 , a sixth connection electrode 66 , a second initial signal line 67 , a first data connection line 68 , and an initial signal connection line 69 .

[0225] In the exemplary embodiment, the first connection electrode 61 is in a zigzag shape with a main portion extending along the second direction Y, and its first end is connected to the second region 21-2 of the active layer 21 of the first transistor T1 (also the first region 22-1 of the active layer 22 of the second transistor T2) through the third via hole V3, and its second end is connected to the first electrode plate 33 through the ninth via hole V9, so that the first electrode plate 33, the second electrode of the first transistor T1, and the first electrode of the second transistor T2 have the same potential. In the exemplary embodiment, the first connection electrode 61 can serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2.

[0226] In an exemplary embodiment, the second connection electrode 62 may be in a strip shape with a main portion extending along the first direction X. The second connection electrode 62 is connected to the first region 21-1 of the active layer 21 of the first transistor T1 through the first via hole V1, and is connected to the first initial signal line 45 in the sub-pixel of the row through the eleventh via hole V11 in the row of sub-pixels. In an exemplary embodiment, the second connection electrode 62 may serve as a first electrode of the first transistor T1, and the second connection electrode 62 is configured to be connected to the first initial signal line 45 and the active layer 21 of the first transistor T1.

[0227] In an exemplary embodiment, the Nth column and the N+1th column share the same second connection electrode 62, and the N+2th column and the N+3th column share the same second connection electrode 62. In an exemplary embodiment, since the second connection electrode 62 in each sub-pixel is connected to the first initial signal line 45, by forming an integrated structure in which adjacent sub-pixels share the same second connection electrode 62 and are connected to each other, it is possible to ensure that the second connection electrodes 62 of adjacent sub-pixels have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0228] In an exemplary embodiment, one end of the third connection electrode 63 is connected to the second region 22-2 of the active layer 22 of the second transistor T2 through the second via hole V2, and the other end of the third connection electrode 63 is connected to the second region 23-2 of the active layer 23 of the third transistor T3 (also the first region 26-1 of the active layer 26 of the sixth transistor T6) through the sixth via hole V6. In an exemplary embodiment, the third connection electrode 63 can simultaneously serve as the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, so that the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 have the same potential.

[0229] In an exemplary embodiment, the fourth connection electrode 64 is connected to the first region 24-1 of the active layer 24 of the fourth transistor T4 through the fourth via hole V4. In an exemplary embodiment, the fourth connection electrode 64 may serve as a first electrode of the fourth transistor T4 and is configured to be connected to a subsequently formed data signal line.

[0230] In an exemplary embodiment, the sixth connection electrode 66 is connected to the first region 25-1 of the active layer 25 of the fifth transistor T5 through the fifth via hole V5, and the sixth connection electrode 66 is connected to the second electrode plate 43 through the tenth via hole V10. In an exemplary embodiment, the sixth connection electrode 66 can serve as a first electrode of the fifth transistor T5, and is configured to be connected to a first power line formed subsequently.

[0231] In an exemplary embodiment, the fifth connection electrode 65 is connected to the second region 26-2 of the active layer 26 of the sixth transistor T6 (also the second region 27-2 of the active layer 27 of the seventh transistor T7) through the seventh via hole V7. In an exemplary embodiment, the fifth connection electrode 65 can serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the fifth connection electrode 65 is configured to be connected to the anode connection electrode of the light emitting element formed subsequently.

[0232] In an exemplary embodiment, the second initial signal line 67 may be in a zigzag shape with a main portion extending along the first direction X. The second initial signal line 67 is connected to the first region 27-1 of the active layer 27 of the plurality of seventh transistors T7 through the plurality of eighth via holes V8 in a sub-pixel row, and the initial voltage is written into the plurality of seventh transistors T7 in a sub-pixel row. In an exemplary embodiment, since the second initial signal line 67 is connected to the first region 27-1 of the active layer 27 of all the seventh transistors T7 in a sub-pixel row, it is possible to ensure that the first electrodes of all the seventh transistors T7 in a sub-pixel row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate. In an exemplary embodiment, the second initial signal line 67 may serve as the first electrode of the seventh transistor T7.

[0233] In an exemplary embodiment, the first data connection line 68 may be in the shape of a zigzag line with a main portion extending along the first direction X. In an exemplary embodiment, the first data connection line 68 is disposed between adjacent rows of sub-pixels. In an exemplary embodiment, one end of the first data connection line 68 is configured to be connected to a second data connection line formed subsequently through a via hole, and the other end is configured to be connected to a data signal line formed subsequently through a via hole. In an exemplary embodiment, Fig.16d As shown, one end of the first data connection line 68 is configured to be connected to the second data connection line formed subsequently through a via hole, and the other end is integrally formed with the fourth connection electrode 64 and is configured to be connected to the data signal line formed subsequently through a via hole. In an exemplary embodiment, the fourth connection electrode 64 connected to the first data connection line 68 can be a strip structure or a folded line structure extending along the second direction Y, such as Fig.16c and Fig.16d As shown, one end of the fourth connection electrode 64 connected to the first data connection line 68 is electrically connected to a subsequently formed data signal line through a via hole, and the other end is integrally formed with the first data connection line 68 .

[0234] In an exemplary embodiment, in the first direction X, the first data link line 68 may be located between two adjacent initial signal link lines 69 .

[0235] In an exemplary embodiment, the initial signal connection line 69 may be a strip-shaped structure whose main part extends along the second direction Y, and the initial signal connection line 69 is configured as a structure integrally formed with the second initial signal line 67. In an exemplary embodiment, one or more columns of sub-pixels may be arranged between two adjacent initial signal connection lines 69, for example, two sub-pixels are arranged between two adjacent initial signal connection lines 69. In an exemplary embodiment, the initial signal connection line 69 connects a plurality of second initial signal lines 67 arranged along the second direction Y into an integral structure, so that the plurality of second initial signal lines 67 have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, improving the low grayscale image quality, and ensuring the display effect of the display substrate.

[0236] (110) Forming a seventh insulating layer and a first planar layer pattern. In an exemplary embodiment, forming the seventh insulating layer and the first planar layer pattern may include: first depositing a seventh insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the first planar film and the seventh insulating film using a patterning process to form a seventh insulating layer covering the fourth conductive layer pattern and a first planar layer disposed on the seventh insulating layer, and a plurality of via holes are disposed on the seventh insulating layer and the first planar layer, such as Fig.17a and Fig.17b As shown, Fig.17a is a planar structure diagram of eight sub-pixels. Fig.17b This is a planar structure diagram of sixteen sub-pixels.

[0237] In an exemplary embodiment, the plurality of via holes in each sub-pixel includes at least a twelfth via hole V12 , a thirteenth via hole V13 , a fourteenth via hole V14 , and a fifteenth via hole V15 .

[0238] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the fourth connection electrode 64 on the substrate, and the first flat layer and the seventh insulating layer in the twelfth via hole V12 are etched away to expose the surface of the fourth connection electrode 64. The twelfth via hole V12 is configured to connect a subsequently formed data signal line to the fourth connection electrode 64 through the via hole.

[0239] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the fifth connection electrode 65 on the substrate, and the first flat layer and the seventh insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the fifth connection electrode 65. The thirteenth via hole V13 is configured to connect the anode connection electrode of the subsequently formed light emitting element to the fifth connection electrode 65 through the via hole.

[0240] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the sixth connection electrode 66 on the substrate, and the first flat layer and the seventh insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the sixth connection electrode 66. The fourteenth via hole V14 is configured to connect a first power line formed subsequently to the sixth connection electrode 66 through the via hole.

[0241] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the first data connection line 68 on the substrate, and the first planar layer and the seventh insulating layer in the fifteenth via hole V15 are etched away to expose the surface of the first data connection line 68. The fifteenth via hole V15 is configured to connect the second data connection line formed subsequently to the first data connection line 68 through the via hole.

[0242] In an exemplary embodiment, Fig.17b As shown, the orthographic projection of the twelfth via hole V12 disposed on the fourth connection electrode 64 connected to the first data connection line 68 on the substrate is within the range of the orthographic projection of the first data connection line 68 (i.e., the fourth connection electrode 64) on the substrate, and the first flat layer and the seventh insulating layer in the twelfth via hole V12 are etched away, exposing the surface of the first data connection line 68 (i.e., the fourth connection electrode 64). The twelfth via hole V12 is configured to allow a subsequently formed data signal line to be connected to the first data connection line 68 (i.e., the fourth connection electrode 64) through the via hole. The first data connection line 68 and the fourth connection electrode 64 share a via hole to be connected to the subsequently formed data signal line, which can save space for the pixel driving circuit. Fig.17b and Fig.18c As shown, one end of the first data connection line 68 is integrally formed with the fourth connection electrode 64 and electrically connected to the data signal line 71 through the twelfth via hole V12 , and the other end is electrically connected to the second data connection line 74 through the fifteenth via hole V15 .

[0243] (111) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern, patterning the fifth conductive film using a patterning process, and forming a fifth conductive layer disposed on the first planar layer, such as Figures 18a to 18c As shown, Fig.18a is a planar structure diagram of eight sub-pixels. Fig.18c is a planar structure diagram of sixteen sub-pixels. Fig.18b for Fig.18a In an exemplary embodiment, the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0244] In an exemplary embodiment, the fifth conductive layer at least includes: a data signal line 71, a first power line 72, an anode connection electrode 73 and a second data connection line 74. In an exemplary embodiment, the anode connection electrode 73 is an anode connection electrode of a light emitting element.

[0245] In an exemplary embodiment, the data signal line 71 is in a zigzag shape with a main portion extending along the second direction Y, and the data signal line 71 is connected to the fourth connection electrode 64 through the twelfth via hole V12. Since the fourth connection electrode 64 is connected to the first region 24-1 of the active layer 24 of the fourth transistor T4 through the via hole, the data signal line 71 is connected to the first electrode of the fourth transistor T4, and the data signal is written into the fourth transistor T4.

[0246] In an exemplary embodiment, the first power line 72 is in a zigzag shape with a main portion extending along the second direction Y, and the first power line 72 is connected to the sixth connection electrode 66 through the fourteenth via hole V14. Since the sixth connection electrode 66 is connected to the second electrode plate 43 through the via hole, the connection between the first power line 72 and the second electrode plate 43 is realized, and the power signal is written into the second electrode plate 43. Since the sixth connection electrode 66 is connected to the first region 25-1 of the active layer 25 of the fifth transistor T5 through the via hole, the connection between the first power line 72 and the first electrode of the fifth transistor T5 is realized, and the power signal is written into the fifth transistor T5.

[0247] In the exemplary embodiment, the anode connection electrode 73 is connected to the fifth connection electrode 65 through the thirteenth via hole V13. Since the fifth connection electrode 65 is connected to the second region 26-2 of the active layer 26 of the sixth transistor T6 (also the second region 27-2 of the active layer 27 of the seventh transistor T7) through the via hole, the anode connection electrode 73 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0248] In an exemplary embodiment, the main portion of the second data connection line 74 extends along the second direction Y, and the second data connection line 74 is connected to the first data connection line 68 through the fifteenth via hole V15. In an exemplary embodiment, the second data connection line 74 is disposed between two adjacent columns of sub-pixels. In an exemplary embodiment, three second data connection lines 74 may be disposed between two adjacent columns of sub-pixels, and the three adjacent second data connection lines 74 are respectively connected to the first data connection lines 68 in different sub-pixel rows through via holes.

[0249] In an exemplary embodiment, any second data connection line 74 is connected to the first data connection line 68 through the fifteenth via hole V15 in the display area, and is connected to an integrated circuit (IC) in the driving chip area in the binding area.

[0250] In an exemplary embodiment, taking 8 sub-pixels (2 sub-pixel rows and 4 sub-pixel columns) in the display area (AA) as an example, another process of preparing a display substrate may include the following operations.

[0251] (201) A substrate is prepared on a glass carrier. The preparation method is the same as that of the above (101) and will not be repeated here.

[0252] (202) forming a shielding layer pattern. The preparation method is the same as that of (102) above, and will not be repeated here. The shielding layer pattern formed is as follows: Fig. 9 shown.

[0253] (203) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: depositing a first insulating film and a first semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the shielding layer pattern, and a first semiconductor layer pattern disposed on the first insulating layer, such as Fig.19a and Fig.19b As shown, Fig.19a is a planar structure diagram of eight sub-pixels. Fig.19b for Fig.19a Schematic plan view of the first semiconductor layer in FIG.

[0254] In an exemplary embodiment, the first semiconductor layer pattern of each subpixel may include the active layers 23 to 27 of the third to seventh transistors T3 to T7 as an integral structure connected to each other.

[0255] In an exemplary embodiment, in the first direction X, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on the same side of the active layer 23 of the third transistor T3, and the active layer 26 of the sixth transistor T6 is located on the other side of the active layer 23 of the third transistor T3; in the second direction Y, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on both sides of the active layer 23 of the third transistor T3, and the active layer 25 of the fifth transistor T5, the active layer 26 of the sixth transistor T6, and the active layer 27 of the seventh transistor T7 are located on the same side of the active layer 23 of the third transistor T3, and the active layer 27 of the seventh transistor T7 is located on the side of the active layer 26 of the sixth transistor T6 away from the active layer 23 of the third transistor T3.

[0256] In an exemplary embodiment, the sub-pixel in the Mth row and the Nth column is taken as an example for description: in the first direction X, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the N+1th column, and the active layer 26 of the sixth transistor T6 is located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the N-1th column; in the second direction Y, the active layer 24 of the fourth transistor T4 is located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the M-1th row, the active layer 25 of the fifth transistor T5, the active layer 26 of the sixth transistor T6, and the active layer 27 of the seventh transistor T7 are located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the M+1th row, and the active layer 27 of the seventh transistor T7 is located on the side of the active layer 26 of the sixth transistor T6 away from the active layer 23 of the third transistor T3.

[0257] In an exemplary embodiment, the shape of the active layer 23 of the third transistor T3 may be "Ω"-shaped, the shape of the active layer 24 of the fourth transistor T4 may be a zigzag line extending along the second direction Y, the middle of the zigzag line is bent in a direction away from the active layer 31 of the third transistor T3, and the end of the zigzag line is bent in a direction close to the active layer 31 of the third transistor T3, the shape of the active layer 27 of the seventh transistor T7 may be "I"-shaped, and the shape of the active layer 25 of the fifth transistor T5 and the active layer 26 of the sixth transistor T6 may be "L"-shaped.

[0258] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the first region 23-1 of the active layer 23 of the third transistor T3 may be used as the second region 24-2 of the active layer 24 of the fourth transistor T4 and the second region 25-2 of the active layer 25 of the fifth transistor T5, the second region 23-2 of the active layer 23 of the third transistor T3 may be used as the first region 26-1 of the active layer 26 of the sixth transistor T6, the second region 26-2 of the active layer 26 of the sixth transistor T6 may be used as the second region 27-2 of the active layer 27 of the seventh transistor T7, and the first region 24-1 of the active layer 24 of the fourth transistor T4, the first region 25-1 of the active layer 25 of the fifth transistor T5, and the first region 27-1 of the active layer 27 of the seventh transistor T7 may be separately provided.

[0259] In an exemplary embodiment, the orthographic projection of the active layer 23 of the third transistor T3 on the substrate at least partially overlaps with the orthographic projection of the blocking block 14 on the substrate. In an exemplary embodiment, the orthographic projection of the channel region of the active layer 23 of the third transistor T3 on the substrate is within the range of the orthographic projection of the blocking block 14 on the substrate.

[0260] In an exemplary embodiment, the first region 25-1 of the active layer 25 of the fifth transistor T5 in the Nth column and the first region 25-1 of the active layer 25 of the fifth transistor T5 in the N-1th column are connected to each other, and the first region 25-1 of the active layer 25 of the fifth transistor T5 in the N+1th column and the first region 25-1 of the active layer 25 of the fifth transistor T5 in the N+2th column are connected to each other. In an exemplary embodiment, since the first region of the active layer of the fifth transistor T5 in each sub-pixel is connected to the first power line formed subsequently, by forming the first regions of the active layers of the fifth transistors T5 of adjacent sub-pixels into an integrated structure connected to each other, it can be ensured that the first electrodes of the fifth transistors T5 of adjacent sub-pixels have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0261] In an exemplary embodiment, the first semiconductor layer in the Nth column and the first semiconductor layer in the N+1th column may be mirror-symmetrical with respect to the first center line, the first semiconductor layer in the N+1th column and the first semiconductor layer in the N+2th column may be mirror-symmetrical with respect to the second center line, and the first semiconductor layer in the N+2th column and the first semiconductor layer in the N+3th column may be mirror-symmetrical with respect to the third center line.

[0262] In an exemplary embodiment, the first region 27 - 1 of the active layer 27 of the seventh transistor T7 in the i-th row of sub-pixels may be disposed in the i-1-th row of sub-pixels, i=2, 3, . . . , M+1.

[0263] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si), that is, the third transistor T3 to the seventh transistor T7 may be LTPS thin film transistors. In an exemplary embodiment, patterning the first semiconductor film by a patterning process may include: first forming an amorphous silicon (a-si) film on the first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and performing a crystallization treatment on the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, the polycrystalline silicon film is patterned to form a first semiconductor layer pattern.

[0264] (204) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, such as Fig.20a and Fig.20b As shown, Fig.20b for Fig.20a In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0265] In an exemplary embodiment, the first conductive layer pattern may include at least: a first scanning signal line 31, a light emitting control line 32, and a first electrode plate 33 of a storage capacitor. The main parts of the first scanning signal line 31 and the light emitting control line 32 may extend along the first direction X. In the same sub-pixel, the light emitting control line 32, the first electrode plate 33 of the storage capacitor, and the first scanning signal line 31 are arranged along the second direction Y.

[0266] In an exemplary embodiment, the first scan signal line 31 and the light emitting control line 32 are located on both sides of the first electrode plate 33 of the storage capacitor in the second direction Y. For example, in the second direction, the light emitting control line 32, the first electrode plate 33, and the first scan signal line 31 are arranged in sequence.

[0267] Take the Mth row and Nth column sub-pixel as an example: in the second direction Y, the light-emitting control line 32 can be located on the side of the first plate 33 of the storage capacitor in this sub-pixel close to the M-1th row sub-pixel; the first scanning signal line 31 can be located on the side of the first plate 33 of the storage capacitor in this sub-pixel close to the M+1th row sub-pixel.

[0268] In an exemplary embodiment, the first electrode plate 33 may be located between the light emitting control line 32 and the first scanning signal line 31, the first electrode plate 33 may be rectangular, the corners of the rectangular shape may be chamfered, and the orthographic projection of the first electrode plate 33 on the substrate and the orthographic projection of the active layer of the third transistor T3 on the substrate have an overlapping area. In an exemplary embodiment, the first electrode plate 33 may simultaneously serve as a plate of the storage capacitor and a control electrode of the third transistor T3.

[0269] In an exemplary embodiment, the area where the light emitting control line 32 overlaps with the active layer of the fifth transistor T5 serves as the control electrode of the fifth transistor T5, the area where the light emitting control line 32 overlaps with the active layer of the sixth transistor T6 serves as the control electrode of the sixth transistor T6, the area where the first scanning signal line 31 overlaps with the active layer of the fourth transistor T4 serves as the control electrode of the fourth transistor T4, and the area where the first scanning signal line 31 overlaps with the active layer of the seventh transistor T7 serves as the control electrode of the seventh transistor T7.

[0270] In an exemplary embodiment, the first scanning signal lines 31 and the light emitting control lines 32 may be designed with equal widths, or may be designed with unequal widths, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0271] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductor processing on the semiconductor layer, and the semiconductor layer in the area blocked by the first conductive layer forms the channel region of the third transistor T3 to the seventh transistor T7, and the semiconductor layer in the area not blocked by the first conductive layer is conductorized, that is, the first area and the second area of ​​the active layer 23 of the third transistor T3 to the active layer 27 of the seventh transistor T8 are both conductorized.

[0272] (205) A second conductive layer pattern is formed. The preparation method is the same as that of (105) above, and will not be repeated here. The second conductive layer pattern formed is as follows: Figure 12b As shown, Fig.21 Shown is a planar structure diagram of eight sub-pixels.

[0273] (206) A second semiconductor layer pattern is formed. The preparation method is the same as that of (106) above, and will not be repeated here. The second conductive layer pattern formed is as follows: Fig.13b As shown, Fig. 22 Shown is a planar structure diagram of eight sub-pixels.

[0274] (207) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a fifth insulating film and a third conductive film in sequence on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, such as Figure 23a to Figure 23b As shown, Fig.23a is a planar structure diagram of eight sub-pixels. Figure 23b for Fig.23a In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0275] In an exemplary embodiment, the third conductive layer pattern includes at least: a second scanning signal line 51, a third scanning signal line 52, the main parts of the second scanning signal line 51, the third scanning signal line 52, and the transfer connection electrode 53 can extend along the first direction X, and the third scanning signal line 52, the transfer connection electrode 53, and the second scanning signal line 51 are arranged in sequence along the second direction Y.

[0276] In an exemplary embodiment, the area where the second scan signal line 51 overlaps with the active layer 21 of the first transistor T1 serves as the control electrode of the first transistor T1 , and the area where the third scan signal line 52 overlaps with the active layer 22 of the second transistor T2 serves as the control electrode of the second transistor T2 .

[0277] In an exemplary embodiment, the transfer connection electrode 53 is connected to the second initial signal line 67 formed subsequently through a via hole, so that the potentials of multiple second initial signal lines 67 of sub-pixels in the same row are the same, thereby improving the display effect.

[0278] In an exemplary embodiment, the signals of the first shielding line 41 and the second scanning signal line 51 can be the same, that is, the two are connected in parallel and connected to the same signal source, so that the first shielding line 41 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the first transistor T1, forming a first transistor T1 with a dual-gate structure.

[0279] In an exemplary embodiment, the signals of the second shielding line 42 and the third scanning signal line 52 can be the same, that is, the two are connected in parallel and connected to the same signal source, so that the second shielding line 42 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the second transistor T2, forming a second transistor T2 with a dual-gate structure.

[0280] (208) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer is provided with a plurality of via holes, such as Fig.24 As shown, Fig.24 This is a planar structure diagram of eight sub-pixels.

[0281] In an exemplary embodiment, the multiple via holes in each sub-pixel include at least: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9, a tenth via hole V10, an eleventh via hole V11, and a transfer via hole Vm.

[0282] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the active layer 21 of the first transistor T1 on the substrate, and the sixth insulating layer and the fifth insulating layer in the first via hole V1 are etched away to expose the surface of the first region 21-1 of the active layer 21 of the first transistor T1. The first via hole V1 is configured to connect the first electrode of the first transistor T1 formed subsequently to the active layer 21 of the first transistor T1 through the via hole.

[0283] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is within the range of the orthographic projection of the active layer 22 of the second transistor T2 on the substrate, and the sixth insulating layer and the fifth insulating layer in the second via hole V2 are etched away to expose the surface of the second region 22-2 of the active layer 22 of the second transistor T2. The second via hole V2 is configured to connect the second electrode of the second transistor T2 formed subsequently to the active layer 22 of the second transistor T2 through the via hole.

[0284] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is within the range of the orthographic projection of the active layer 22 of the second transistor T2 on the substrate, and the sixth insulating layer and the fifth insulating layer in the third via hole V3 are etched away, exposing the surface of the first region 22-1 of the active layer 22 of the second transistor T2 (also the second region 21-2 of the active layer 21 of the first transistor T1). The third via hole V3 is configured to connect the second electrode of the first transistor T1 formed subsequently to the active layer 21 of the first transistor T1 through the via hole, and to connect the first electrode of the second transistor T2 formed subsequently to the active layer 22 of the second transistor T2 through the via hole.

[0285] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the active layer 24 of the fourth transistor T4 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the fourth via hole V4 are etched away to expose the first region 24-1 of the active layer 24 of the fourth transistor T4. The fourth via hole V4 is configured to connect the first electrode of the fourth transistor T4 formed subsequently to the active layer 24 of the fourth transistor T4 through the via hole.

[0286] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is within the range of the orthographic projection of the active layer 25 of the fifth transistor T5 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first region 25-1 of the active layer 25 of the fifth transistor T5. The fifth via hole V5 is configured to connect the first electrode of the subsequently formed fifth transistor T5 to the active layer 25 of the fifth transistor T5 through the via hole.

[0287] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is within the range of the orthographic projection of the active layer 26 of the sixth transistor T6 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first region 26-1 of the active layer 26 of the sixth transistor T6 (also the second region of the active layer 23 of the third transistor T3). The sixth via hole V6 is configured to connect the first electrode of the subsequently formed sixth transistor T6 to the active layer 26 of the sixth transistor T6 through the via hole, and to connect the second electrode of the subsequently formed third transistor T3 to the active layer 23 of the third transistor T3 through the via hole.

[0288] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is within the range of the orthographic projection of the active layer 26 of the sixth transistor T6 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the second region 26-2 of the active layer 26 of the sixth transistor T6 (also the second region 27-2 of the active layer 27 of the seventh transistor T7). The seventh via hole V7 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the active layer 26 of the sixth transistor T6 through the via hole, and to connect the second electrode of the subsequently formed seventh transistor T7 to the active layer 27 of the seventh transistor T7 through the via hole.

[0289] In an exemplary embodiment, the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the active layer 27 of the seventh transistor T7 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the eighth via hole V8 are etched away to expose the surface of the first region 27-1 of the active layer 27 of the seventh transistor T7. The eighth via hole V8 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the active layer 27 of the seventh transistor T7 through the via hole.

[0290] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is within the range of the orthographic projection of the opening 44 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, and the third insulating layer in the ninth via hole V9 are etched away to expose the surface of the first electrode plate 33. The ninth via hole V9 is configured to connect the second electrode of the first transistor T1 formed subsequently to the first electrode plate 33 through the via hole.

[0291] In an exemplary embodiment, the tenth via hole V10 is located within the range of the orthographic projection of the second electrode plate 43 on the substrate, and the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer in the tenth via hole V10 are etched away to expose the surface of the second electrode plate 43. The tenth via hole V10 is configured to connect the subsequently formed sixth connection electrode to the second electrode plate 43 through the via hole. In an exemplary embodiment, the tenth via hole V10 as a power via hole may include a plurality of the tenth via holes V10, and the plurality of tenth via holes V10 may be arranged in sequence along the second direction Y or the first direction X to increase the connection reliability between the first power line and the second electrode plate 43.

[0292] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first initial signal line 45 on the substrate, and the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first initial signal line 45. The eleventh via hole V11 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first initial signal line 45 through the via hole.

[0293] In an exemplary embodiment, the orthographic projection of the transfer via hole Vm on the substrate is within the range of the orthographic projection of the transfer connection electrode 53 on the substrate, and the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer in the transfer via hole Vm are etched away to expose the surface of the transfer connection electrode 53. The transfer via hole Vm is configured to connect two adjacent second initial signal lines in the same row formed subsequently through the via hole.

[0294] (209) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the sixth insulating layer, such as Figures 25a to 25d As shown, Fig.25a is a planar structure diagram of eight sub-pixels. Fig.25b for Fig.25a Schematic diagram of the fourth conductive layer in the figure. Fig.25c is a planar structure diagram of thirty-two sub-pixels. Fig.25d for Fig.25c In an exemplary embodiment, the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0295] In an exemplary embodiment, the fourth conductive layer includes at least: a first connection electrode 61, a second connection electrode 62, a third connection electrode 63, a fourth connection electrode 64, a fifth connection electrode 65, a sixth connection electrode 66, a second initial signal line 67, a first data connection line 68, a third data connection line 610, and a fourth data connection line 611.

[0296] In the exemplary embodiment, the first connection electrode 61 is in a zigzag shape with a main portion extending along the second direction Y, and its first end is connected to the second region 21-2 of the active layer 21 of the first transistor T1 (also the first region 22-1 of the active layer 22 of the second transistor T2) through the third via hole V3, and its second end is connected to the first electrode plate 33 through the ninth via hole V9, so that the first electrode plate 33, the second electrode of the first transistor T1, and the first electrode of the second transistor T2 have the same potential. In the exemplary embodiment, the first connection electrode 61 can serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2.

[0297] In an exemplary embodiment, the second connection electrode 62 may be in a strip shape with a main portion extending along the first direction X. The second connection electrode 62 is connected to the first region 21-1 of the active layer 21 of the first transistor T1 through the first via hole V1, and is connected to the first initial signal line 45 in the sub-pixel of the row through the eleventh via hole V11 in the row of sub-pixels. In an exemplary embodiment, the second connection electrode 62 may serve as a first electrode of the first transistor T1, and the second connection electrode 62 is configured to be connected to the first initial signal line 45 and the active layer 21 of the first transistor T1.

[0298] In an exemplary embodiment, the Nth column and the N+1th column share the same second connection electrode 62, and the N+2th column and the N+3th column share the same second connection electrode 62. In an exemplary embodiment, since the second connection electrode 62 in each sub-pixel is connected to the first initial signal line 45, by forming an integrated structure in which adjacent sub-pixels share the same second connection electrode 62 and are connected to each other, it is possible to ensure that the second connection electrodes 62 of adjacent sub-pixels have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0299] In an exemplary embodiment, one end of the third connection electrode 63 is connected to the second region 22-2 of the active layer 22 of the second transistor T2 through the second via hole V2, and the other end of the third connection electrode 63 is connected to the second region 23-2 of the active layer 23 of the third transistor T3 (also the first region 26-1 of the active layer 26 of the sixth transistor T6) through the sixth via hole V6. In an exemplary embodiment, the third connection electrode 63 can simultaneously serve as the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, so that the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 have the same potential.

[0300] In an exemplary embodiment, the fourth connection electrode 64 is connected to the first region 24-1 of the active layer 24 of the fourth transistor T4 through the fourth via hole V4. In an exemplary embodiment, the fourth connection electrode 64 may serve as a first electrode of the fourth transistor T4 and is configured to be connected to a subsequently formed data signal line.

[0301] In an exemplary embodiment, the sixth connection electrode 66 is connected to the first region 25-1 of the active layer 25 of the fifth transistor T5 through the fifth via hole V5, and the sixth connection electrode 66 is connected to the second electrode plate 43 through the tenth via hole V10. In an exemplary embodiment, the sixth connection electrode 66 can serve as a first electrode of the fifth transistor T5, and is configured to be connected to a first power line formed subsequently.

[0302] In an exemplary embodiment, the fifth connection electrode 65 is connected to the second region 26-2 of the active layer 26 of the sixth transistor T6 (also the second region 27-2 of the active layer 27 of the seventh transistor T7) through the seventh via hole V7. In an exemplary embodiment, the fifth connection electrode 65 can serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the fifth connection electrode 65 is configured to be connected to the anode connection electrode of the light emitting element formed subsequently.

[0303] In an exemplary embodiment, the second initial signal line 67 can be a zigzag shape with the main part extending along the first direction X. The second initial signal line 67 is connected to the first area 27-1 of the active layer 27 of the seventh transistor T7 in two adjacent columns through the eighth via V8 in a sub-pixel row, and the initial voltage is written into the seventh transistor T7 in two adjacent columns in a sub-pixel row; the second initial signal line 67 is connected to the transfer connection electrode 53 through the transfer via Vm, and the transfer connection electrode 53 electrically connects multiple second initial signal lines 67 in the same row to each other, so that the multiple second initial signal lines 67 in the same sub-pixel row have the same potential, which is beneficial to improving the uniformity of the panel and avoiding poor display of the display substrate. In an exemplary embodiment, the second initial signal line 67 can serve as the first electrode of the seventh transistor T7.

[0304] In an exemplary embodiment, the first data connection line 68 may be in a zigzag or strip shape, with the main portion extending along the first direction X. In an exemplary embodiment, the first data connection line 68 is disposed between adjacent rows of sub-pixels. In an exemplary embodiment, one end of the first data connection line 68 is configured to be connected to a second data connection line formed subsequently through a via hole, and the other end is configured to be connected to a data signal line formed subsequently through a via hole. In an exemplary embodiment, Fig.25d As shown, one end of the first data connection line 68 can be integrally formed with one of the fourth data connection electrodes 64, and the other end is electrically connected to the second data connection line formed subsequently through a via hole. Fig.25d As shown, the fourth connection electrode 64 connected to the first data connection line 68 can be a strip structure or a zigzag structure extending along the second direction Y, one end of which is integrally formed with the first data connection line 68, and the other end is electrically connected to the subsequently formed data signal line through the twelfth via hole V12.

[0305] In an exemplary embodiment, the fourth data connection line 611 may be in a zigzag or strip shape, the main portion of which extends along the first direction X. In an exemplary embodiment, the fourth data connection line 611 is disposed between adjacent rows of sub-pixels. In an exemplary embodiment, one end of the fourth data connection line 611 is connected to the third data connection line 610, and the other end is integrally formed with one of the fourth connection electrodes, and is configured to be connected to a subsequently formed data signal line through a via hole. In an exemplary embodiment, as Fig.25d As shown, the fourth connection electrode 64 connected to the fourth data connection line 611 can be a strip structure or a zigzag structure extending along the second direction Y, one end of which is integrally formed with the fourth data connection line 611, and the other end is electrically connected to the subsequently formed data signal line through the twelfth via hole V12.

[0306] The main part of the third data connection line 610 extends along the second direction Y, one end of the third data connection line 610 is connected to the fourth data connection line 611, and the other end is connected to the driving chip in the binding area. In an exemplary embodiment, the third data connection line 610 is arranged between two adjacent columns of sub-pixels. In an exemplary embodiment, two third data connection lines 610 may be arranged between two adjacent columns of sub-pixels, and two adjacent third data connection lines 610 are respectively connected to the fourth data connection lines 611 in different sub-pixel rows.

[0307] In an exemplary embodiment, any one of the third data connection lines 610 is connected to the fourth data connection line 611 in the display region, and is connected to an integrated circuit (IC) in the driving chip region in the binding region.

[0308] (210) Forming a seventh insulating layer and a first planar layer pattern. In an exemplary embodiment, forming the seventh insulating layer and the first planar layer pattern may include: first depositing a seventh insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the first planar film and the seventh insulating film using a patterning process to form a seventh insulating layer covering the fourth conductive layer pattern and a first planar layer disposed on the seventh insulating layer, and a plurality of via holes are disposed on the seventh insulating layer and the first planar layer, such as Fig.26a and Figure 26b As shown, 26a is a planar structure diagram of eight sub-pixels, Figure 26b This is a planar structural diagram of thirty-two sub-pixels.

[0309] In an exemplary embodiment, the plurality of via holes in each sub-pixel includes at least a twelfth via hole V12 , a thirteenth via hole V13 , a fourteenth via hole V14 , and a fifteenth via hole V15 .

[0310] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is within the range of the orthographic projection of the fourth connection electrode 64 on the substrate, and the first flat layer and the seventh insulating layer in the twelfth via hole V12 are etched away to expose the surface of the fourth connection electrode 64. The twelfth via hole V12 is configured to allow a subsequently formed data signal line to be connected to the fourth connection electrode 64 through the via hole. The first data connection line 68 and the fourth connection electrode 64 share a via hole (V12) to be connected to a subsequently formed data signal line, which can save space for a pixel driving circuit.

[0311] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the fifth connection electrode 65 on the substrate, and the first flat layer and the seventh insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the fifth connection electrode 65. The thirteenth via hole V13 is configured to connect the anode connection electrode of the subsequently formed light emitting element to the fifth connection electrode 65 through the via hole.

[0312] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the sixth connection electrode 66 on the substrate, and the first flat layer and the seventh insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the sixth connection electrode 66. The fourteenth via hole V14 is configured to connect a first power line formed subsequently to the sixth connection electrode 66 through the via hole.

[0313] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the first data connection line 68 on the substrate, and the first planar layer and the seventh insulating layer in the fifteenth via hole V15 are etched away to expose the surface of the first data connection line 68. The fifteenth via hole V15 is configured to connect the second data connection line formed subsequently to the first data connection line 68 through the via hole.

[0314] (211) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern, patterning the fifth conductive film using a patterning process, and forming a fifth conductive layer disposed on the first planar layer, such as Figures 27a to 27c As shown, Fig.27a is a planar structure diagram of eight sub-pixels. Figure 27b for Fig.27a A plan view of the fifth conductive layer in FIG. Fig.27c FIG. 1 is a planar structural diagram of thirty-two sub-pixels. In an exemplary embodiment, the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0315] In an exemplary embodiment, the fifth conductive layer at least includes: a data signal line 71, a first power line 72, an anode connection electrode 73 and a second data connection line 74. In an exemplary embodiment, the anode connection electrode 73 is an anode connection electrode of a light emitting element.

[0316] In an exemplary embodiment, the main portion of the data signal line 71 extends along the second direction Y, and the data signal line 71 is connected to the fourth connection electrode 64 through the twelfth via hole V12. Since the fourth connection electrode 64 is connected to the first region 24-1 of the active layer 24 of the fourth transistor T4 through the via hole, the data signal line 71 is connected to the first electrode of the fourth transistor T4, and the data signal is written into the fourth transistor T4.

[0317] In an exemplary embodiment, the first power line 72 is in a zigzag shape with a main portion extending along the second direction Y, and the first power line 72 is connected to the sixth connection electrode 66 through the fourteenth via hole V14. Since the sixth connection electrode 66 is connected to the second electrode plate 43 through the via hole, the connection between the first power line 72 and the second electrode plate 43 is realized, and the power signal is written into the second electrode plate 43. Since the sixth connection electrode 66 is connected to the first region 25-1 of the active layer 25 of the fifth transistor T5 through the via hole, the connection between the first power line 72 and the first electrode of the fifth transistor T5 is realized, and the power signal is written into the fifth transistor T5.

[0318] In the exemplary embodiment, the anode connection electrode 73 is connected to the fifth connection electrode 65 through the thirteenth via hole V13. Since the fifth connection electrode 65 is connected to the second region 26-2 of the active layer 26 of the sixth transistor T6 (also the second region 27-2 of the active layer 27 of the seventh transistor T7) through the via hole, the anode connection electrode 73 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0319] In an exemplary embodiment, the main portion of the second data connection line 74 extends along the second direction Y, and the second data connection line 74 is connected to the first data connection line 68 through the fifteenth via hole V15. In an exemplary embodiment, the second data connection line 74 is disposed between two adjacent columns of sub-pixels. In an exemplary embodiment, one second data connection line 74 may be disposed between two adjacent columns of sub-pixels.

[0320] In an exemplary embodiment, in the plane where the display substrate is located, two third data connection lines 610 and one second data connection line 74 are provided between two adjacent columns of sub-pixels, and in the first direction X, the second data connection line 74 is provided between the two third data connection lines 610. The two third data connection lines 610 between two adjacent columns of sub-pixels are connected to two fourth data connection lines 611 respectively located in the two first spaces R1, and one second data connection line 74 is connected to the first data connection line 68 in the first space R1 through a via hole.

[0321] like Figure 8c and Fig.27c As shown, 16 sub-pixels (2 sub-pixel rows and 8 sub-pixel columns) in the display area (AA) are prepared by the above (201) to (211). Figure 8c In the structure shown, in the second space R2 between the pixels in the N+3rd column and the N+4th column, and in the second space R2 between the pixels in the N+5th column and the N+6th column, in the same second space R2, the number of the third data connection line 610 is one, and the number of the second data connection lines 74 is two. In the plane where the display substrate is located, in the first direction X, the two second data connection lines 74 are located on both sides of the third data connection line 610, and the two second data connection lines 74 in the same second space R2 are connected to different first data connection lines 68. In the second space R2 between the pixels in the N+1th column and the N+2th column, in the same second space R2, the number of the third data connection line 610 is two, and the number of the second data connection line 74 is one. In the plane where the display substrate is located, in the first direction X, the two third data connection lines 610 are located on both sides of the second data connection line 74, and the two third data connection lines 610 in the same second space R2 are connected to different fourth data connection lines 611.

[0322] like Fig.27c As shown, there are thirty-two sub-pixels (4 sub-pixel rows and 8 sub-pixel columns) in the display area (AA) prepared by the above (201) to (211). Fig.27cIn the structure shown, in the second space R2 between the pixels in the N+1th column and the N+2th column and the second space R2 between the pixels in the N-3th column and the N-2th column, in the same second space R2, the number of the third data connection lines 610 is two, the number of the second data connection line 74 is one, in the plane where the display substrate is located, in the first direction X, the two third data connection lines 610 are located on both sides of the second data connection line 74, and the two third data connection lines 610 in the same second space R2 are connected to different fourth data connection lines 611; in the second space R2 between the pixels in the N-1th column and the Nth column, in the same second space R2, the number of the second data connection lines 74 is two, the number of the third data connection line 610 is one, in the plane where the display substrate is located, in the first direction X, the two second data connection lines 74 are located on both sides of the third data connection line 610, and the two second data connection lines 74 in the same second space R2 are connected to different first data connection lines 68.

[0323] At this point, the driving circuit layer is prepared on the substrate. In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving circuit layer may include a shielding layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially arranged on the substrate.

[0324] In an exemplary embodiment, the driving circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a seventh insulating layer and a first flat layer, the first insulating layer is arranged between the blocking layer and the first semiconductor layer, the second insulating layer is arranged between the first semiconductor layer and the first conductive layer, the third insulating layer is arranged between the first conductive layer and the second conductive layer, the fourth insulating layer is arranged between the second conductive layer and the second semiconductor layer, the fifth insulating layer is arranged between the second semiconductor layer and the third conductive layer, the sixth insulating layer is arranged between the third conductive layer and the fourth conductive layer, and the seventh insulating layer and the first flat layer are arranged between the fourth conductive layer and the fifth conductive layer.

[0325] In an exemplary embodiment, after the driving circuit layer is prepared, a light-emitting structure layer is prepared on the driving circuit layer, and the preparation process of the light-emitting structure layer may include the following operations. A second flat layer pattern is formed, and at least an anode via is provided on the second flat layer. An anode pattern is formed, and the anode is connected to the anode connection electrode through the anode via. An anode pixel definition layer is formed, and a pixel opening is provided on the pixel definition layer, and the pixel opening exposes the anode. An organic light-emitting layer is formed by evaporation or inkjet printing process, and a cathode is formed on the organic light-emitting layer. An encapsulation layer is formed, and the encapsulation layer may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.

[0326] In an exemplary embodiment, the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer and the seventh insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer. The first insulating layer may be called a buffer layer, which is used to improve the water and oxygen resistance of the substrate, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be called a gate insulating (GI) layer, the sixth insulating layer may be called an interlayer insulating (ILD) layer, and the seventh insulating layer may be called a passivation (PVX) layer.

[0327] The structure and preparation process shown above in the embodiment of the present disclosure are merely exemplary illustrations. In the exemplary implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. The display substrate of the embodiment of the present disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, etc., and the present disclosure does not limit this.

[0328] The present disclosure also provides a display device, comprising the display substrate of any of the above embodiments. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator.

[0329] The present disclosure also provides a method for preparing a display substrate, the display substrate comprising a display area and a binding area connected to the display area, the display area comprising a plurality of data signal lines and K rows and L columns of sub-pixels, K and L are both positive integers greater than 1; a plurality of first spaces are included between the K sub-pixel rows, a plurality of second spaces are included between the L sub-pixel columns, the first spaces are located between two adjacent sub-pixel rows, the second spaces are located between two adjacent sub-pixel columns, at least one first space is provided with a first data connection line, at least one second space is provided with at least one second data connection line, on a plane parallel to the display substrate, the first data connection line extends along a first direction, the second data connection line extends along a second direction, and the first direction intersects the second direction; the preparation method comprises:

[0330] One end of the first data connection line is electrically connected to one of the data signal lines, and the other end is electrically connected to one of the second data connection lines; one end of the second data connection line is electrically connected to the first data line, and the other end is electrically connected to the binding area.

[0331] The substrate and display device provided by the embodiments of the present disclosure have a display area of ​​the display substrate including multiple data signal lines and K rows and L columns of sub-pixels, where K and L are both positive integers greater than 1; multiple first spaces are included between the K sub-pixel rows, multiple second spaces are included between the L sub-pixel columns, the first space is located between two adjacent sub-pixel rows, the second space is located between two adjacent sub-pixel columns, at least one first space is provided with a first data connection line, and at least one second space is provided with at least one second data connection line; one end of the first data connection line is electrically connected to one of the data signal lines, and the other end is electrically connected to one of the second data connection lines; one end of the second data connection line is electrically connected to the first data line, and the other end is electrically connected to the binding area; the introduction of the first data connection line and the second data connection line in the display area greatly reduces the border of the display substrate, which is conducive to the realization of a narrow border of the display product.

[0332] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0333] In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.

[0334] Although the implementation methods disclosed in the embodiments of the present disclosure are as above, the contents are only implementation methods adopted to facilitate understanding of the embodiments of the present disclosure, and are not intended to limit the embodiments of the present disclosure. Any technician in the field to which the embodiments of the present disclosure belong may make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the embodiments of the present disclosure, but the scope of patent protection of the embodiments of the present disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, comprising a substrate, the substrate comprising a display area and a binding area located at one side of the display area, the display area comprising a plurality of first power lines, a plurality of data signal lines, at least one first data connection line, at least one second data connection line, at least one initial signal connection line, and K rows and L columns of sub-pixels, K and L are both positive integers greater than 1; the second data connection line and the initial signal connection line are located between two adjacent columns of sub-pixels, on a plane parallel to the display substrate, the first data connection line extends along a first direction, the second data connection line, the data signal line, the first power line, and the initial signal connection line extend along a second direction, and the first direction intersects the second direction; One end of the first data connection line is electrically connected to one of the data signal lines, and the other end is electrically connected to one of the second data connection lines; one end of the second data connection line is electrically connected to the first data connection line, and the other end extends to the binding area; In the first direction, between two adjacent first power lines, there are two data signal lines, one initial signal connection line and at least one second data connection line, and the two data signal lines are located on both sides of the at least one second data connection line and the one initial signal connection line.

2. The display substrate according to claim 1, wherein: In the first direction, between two adjacent first power lines: the at least one second data connection line includes at least two second data connection lines located on both sides of the one initial signal connection line, and the two second data connection lines located on both sides of the one initial signal connection line are symmetrically distributed relative to the one initial signal connection line.

3. The display substrate according to claim 1 or 2, wherein: In the first direction, between two adjacent first power lines: the two data signal lines are symmetrically distributed relative to the one initial signal connection line.

4. The display substrate according to claim 1, wherein: At least one sub-pixel includes a pixel driving circuit, at least one pixel driving circuit includes a plurality of low-temperature polysilicon transistors, a plurality of oxide transistors, and a storage capacitor, and in a direction perpendicular to the plane where the display substrate is located, the display substrate includes a substrate and a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially stacked on the substrate; The first semiconductor layer includes: an active layer of a plurality of low temperature polysilicon transistors; The first conductive layer includes: control electrodes of a plurality of low temperature polysilicon transistors and a first electrode plate of a storage capacitor; The second conductive layer includes: a second plate of a storage capacitor; The second semiconductor layer includes: an active layer of a plurality of oxide transistors; The third conductive layer includes: control electrodes of a plurality of oxide transistors; The fourth conductive layer includes: the first data connection line, a first electrode and a second electrode of a plurality of low temperature polysilicon transistors; The fifth conductive layer includes: the data signal line, the first power line and the second data connection line.

5. The display substrate according to claim 4, wherein: In the first direction, between two adjacent first power lines: the at least one second data connection line includes at least two second data connection lines located on both sides of the one initial signal connection line, the two second data connection lines located on both sides of the one initial signal connection line are symmetrically distributed relative to the one initial signal connection line, and the two second data connection lines located on both sides of the one initial signal connection line are electrically connected to two different first data connection lines through two different vias.

6. The display substrate according to claim 4, wherein: Two adjacent columns of sub-pixels share a first power line.

7. The display substrate according to claim 6, wherein: The at least one sub-pixel further includes a fourteenth via hole, a thirteenth via hole, and an anode; The plurality of low temperature polysilicon transistors include a fifth transistor and a sixth transistor, the thirteenth via hole is configured to electrically connect the anode and the sixth transistor, and the fourteenth via hole is configured to electrically connect the first power line and the fifth transistor; The first power line is provided with a plurality of hollow structures, and in the same first power line: the plurality of hollow structures are arranged at intervals along the second direction, and in at least some of the plurality of hollow structures, each of the hollow structures is configured to accommodate two thirteenth vias in two adjacent columns of sub-pixels sharing the first power line.

8. The display substrate according to claim 7, wherein: In the same row of sub-pixels, a central connection line between the thirteenth via hole and the fourteenth via hole of at least two adjacent sub-pixels extends along the first direction.

9. The display substrate according to claim 7 or 8, wherein: At least one row of sub-pixels is provided with a light emitting control line, and the light emitting control line extends along the first direction; In the same row of sub-pixels, the orthographic projections of the plurality of the thirteenth via holes and the plurality of the fourteenth via holes on the substrate at least partially overlap with the orthographic projections of the light emitting control lines in the row of sub-pixels on the substrate.

10. The display substrate according to claim 4, wherein: In the first direction, in two columns of sub-pixels located on both sides of one of the initial signal connection lines, the first semiconductor layer is symmetrical with respect to the initial signal connection line, and the second semiconductor layer is symmetrical with respect to the initial signal connection line.

11. The display substrate according to claim 10, wherein: At least one sub-pixel further comprises an anode, and in the same sub-pixel, the pixel driving circuit is electrically connected to the anode; The multiple low-temperature polysilicon transistors include a seventh transistor for resetting the anode of the light-emitting element, and at least one row of sub-pixels is provided with a second initial signal line. The second initial signal line is connected to the active layer of the seventh transistor in the first semiconductor layer of at least one row of sub-pixels through a via, and the second initial signal line is configured to write an initial voltage into the seventh transistor; the second initial signal line in the at least one row of sub-pixels is connected to at least one of the initial signal connection lines.

12. The display substrate according to claim 4, wherein: The low-temperature polysilicon transistor in the pixel driving circuit comprises a third transistor and a fourth transistor, the second electrode of the fourth transistor is electrically connected to the first electrode of the third transistor, and the first electrode of the fourth transistor is electrically connected to one of the data signal lines; The shape of the active layer of the fourth transistor is a zigzag shape extending along the second direction, the active layer of the fourth transistor includes a first end, a second end and a main body, in the same sub-pixel, in the second direction, the main body is located between the first end and the second end, the first end is connected to the active layer of the third transistor, and the second end is located on a side of the main body away from the active layer of the third transistor; At least a portion of the structure of the main body near the second end is bent in a direction away from the active layer of the third transistor, and in the first direction: the distance between at least a portion of the structure of the main body near the second end and the active layer of the third transistor is greater than the distance between the first end and the active layer of the third transistor, and greater than the distance between the second end and the active layer of the third transistor, and greater than the distance between at least a portion of the structure of the main body near the first end and the active layer of the third transistor.

13. A display device comprising the display substrate according to any one of claims 1 to 12.

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