Superconducting quantum chip processor folding bit processing method and process

Abstract

The invention discloses a superconductive quantum chip processor folding bit processing method and a superconductive quantum chip processor folding bit processing technology, and relates to the superconductive quantum calculation and micro-nano processing technology field, and the specific steps of the processing method are as follows: S100, substrate pretreatment and SiO2 pattern initial etching: selecting a silicon, SiC and GaN wafer of 12 inches or less as a base, applying an atomic force microscope and a stress tester, and carrying out surface processing on the substrate; according to the method, the focusing ion beam technology is introduced, folding processing of the superconducting quantum bits is achieved, the limitation of the traditional plane processing technology is greatly broken through, the traditional superconducting quantum bit processing method is mainly based on the plane processing technology, and the processing efficiency is greatly improved. In the prior art, processing of a complex three-dimensional structure is confronted with many challenges, the focusing ion beam technology is utilized, stress distribution of a thin film is accurately controlled, deformation with the height controllable in the set direction is achieved, and therefore folding of the superconducting quantum bit is easily achieved.

Description

Technical Field

[0001] The present invention relates to the field of superconducting quantum computing and micro-nano processing technology, and specifically to a method and process for folding bits of a superconducting quantum chip processor. Background Art

[0002] With the rapid development of quantum computing technology, superconducting quantum bits, as a quantum computing element with great potential, have become the focus of research on performance optimization and processing technology improvement. The field of superconducting quantum computing micro-nano processing has been exploring more efficient and precise processing methods to meet the growing demand for high-precision and miniaturized quantum bits. In this context, the present invention proposes a superconducting quantum bit folding processing method and process based on focused ion beam technology, aiming to provide a new processing method for the field of superconducting quantum computing.

[0003] However, traditional superconducting quantum bit processing methods are mainly based on planar processing technology, which faces huge challenges in realizing the processing of complex three-dimensional structures. In addition, traditional planar processing technology often has low accuracy when measuring the parallel chip magnetic field of superconducting chips, and cannot accurately obtain key information. This has created obstacles for in-depth research on the characteristics of superconducting materials and optimized chip design. More importantly, in terms of spatial utilization of wafers, existing technologies cannot fully realize their potential, resulting in limited integration of superconducting bits, restricting the large-scale development and application of superconducting quantum bits. Traditional technologies also lack effective means to study material electromagnetic defects, TLS, and crosstalk distribution between bits.

[0004] Therefore, the development of a folded bit processing method and process for a superconducting quantum chip processor has the advantages of high processing accuracy, good repeatability, and good process compatibility, and is expected to bring revolutionary changes to the field of superconducting quantum computing. Summary of the invention

[0005] The purpose of the present invention is to make up for the shortcomings of the prior art and provide a superconducting quantum chip processor folding bit processing method and process, which uses focused ion beam technology to accurately process superconducting thin film materials and planar structures, realizes the folding of superconducting quantum bits, thereby improving the performance and stability of quantum bits. It not only provides a new processing method for the field of superconducting quantum computing, but also effectively solves the problem that traditional planar processing technology is difficult to achieve complex three-dimensional structure processing and difficult to miniaturize. Through the folding of the film, the three-dimensional scale space of the wafer can be fully utilized, the integration of superconducting bits can be improved, and a solid foundation for the large-scale application of superconducting quantum bits is laid.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions: On the one hand, a method for processing folded bits of a superconducting quantum chip processor is provided, and the specific steps of the processing method are as follows:

[0007] S100, substrate pretreatment and initial engraving of SiO2 patterns: select silicon, SiC, and GaN wafers of 12 inches or less as the base, use atomic force microscopes and stress testers to detect the surface morphology and initial stress value of the substrate, and use KrF excimer lithography technology to etch SiO2 patterns. The design rules are based on the functional layout of superconducting bits and the requirements of electrical interconnection.

[0008] S200, dielectric layer deposition and performance enhancement: In the PECVD equipment, in the low temperature range of 80-100℃, SiH4 is used as the main gas source with a flow rate of 50-150sccm, a small amount of N2O is added with a flow rate of 5-15sccm, and 100-300W RF power is used to excite plasma to deposit SiO2 film. The film thickness is monitored in real time by means of an optical interferometer based on the principle of multi-beam interference to ensure that the film thickness uniformity deviation is within ±5% and the deposition rate is stable at 0.5-2nm / s. The temperature is raised to 400-600℃ at a rate of 5-10℃ / min, and annealed for 30-90min to reduce the stress to ≤50MPa, eliminate microscopic defects, increase the high temperature thermal budget to above 800℃, and achieve a mechanical strength of 8-12GPa of Knoop hardness;

[0009] S300, preparation of superconducting Josephson junction: Al / AlOx / Al Josephson junction was prepared in an electron beam evaporation chamber. Before depositing the BE-Al film, the film was treated with Degas at 150-200℃ for 30-60min to drive away impurities. The deposition temperature was selected to be room temperature to 150℃, the deposition rate was 0.1-0.3nm / s, the electron beam current was set to 10-30mA, the acceleration voltage was set to 5-10kV, the film thickness was monitored in real time by a quartz crystal microbalance, and a 10nm AlOx insulating layer was produced by oxidation. The O2 flow rate was regulated by a mass flow controller to 5-15sccm, and the chamber pressure was stabilized by a capacitive thin film vacuum gauge to 5×10 -3 -1×10 -2 Torr, oxidation time 20-40s, continue to deposit TE-Al film, and then spin-coat photoresist at 200-400μC / cm 2 Transfer the design pattern by electron beam exposure, and after development, BE and TE layers are etched by ion beam with an etching energy of 300-500eV, a beam current of 10-30mA, and an angle of 5-15° to form a Josephson junction;

[0010] S400, membrane suspended structure processing: use wet etching process to etch SiO2 film to achieve suspended state, etching temperature 20-25℃, etching time is determined according to SiO2 film thickness and pattern profile, with the help of reaction kinetics model combined with in-situ optical microscope to monitor the grayscale change and morphological characteristics of etching front in real time, dynamically optimize the etching process within 30-90s, and control the etching rate at 10-30nm / s to manufacture fan-shaped etching area, with fan radius 50-150μm, central angle 30-60°, accuracy ±2°, and suspension accuracy within ±10μm;

[0011] S500, FIB irradiation film folding: Fix the treated sample on the FIB stage with a 6-inch vacuum fixture with a clamping force of 50-100N, and evacuate to <10 -6 After Pa, start the electron beam and ion beam, calibrate the beam spot size, energy and scanning accuracy according to the standard calibration procedure of the equipment, tilt the stage 55°±1°, adjust the WD to 6mm±0.1mm to lock the processing area, draw the processing frame according to the design blueprint and set the size, irradiate with a current of 50PA±5PA and an energy of 30Kev, use SEM to collect images in real time to analyze the evolution of the film stress-strain field, fine-tune the parameters according to the strain rate of Ta film deformation of 0.005-0.02% / s, adjust the scanning rate by 0.5-2μm / s, dynamically optimize the beam spot size of 5-15nm, control the deformation rate to 0.05-0.2μm / s, and the directional accuracy to ±1°, until the Ta film stands up or reaches a curved shape, stop irradiation;

[0012] S600, advanced FIB deposition function: move the platinum probe to the processing position, heat up to 300-400℃ at 10-20℃ / min, draw the deposition area, 3-8μm long, 2-6μm wide, 1μm deep, with an accuracy of ±0.3μm, set 100-250PA current and 30Kev energy to start deposition according to the area of ​​the pattern, introduce argon gas into the chamber before deposition to drive away oxygen impurities, and the deposition rate is optimized and precisely controlled at 0.05-0.2μm / min based on the Pt deposition kinetics equation and finite element simulation of electric field distribution. Use atomic force microscopy to monitor the surface morphology for feedback regulation, and use SEM with energy spectrometer to monitor the uniformity of platinum atomic deposition distribution and thickness accuracy in real time. According to the Pt crystal growth model and thin film nucleation theory, the microstructure is verified by high-resolution transmission electron microscopy. The irradiation strategy is customized according to the material characteristics and thickness range of the film, and the through-hole layout is pre-planned in combination with the TSV process to avoid interference at each stage of film folding. Vertical electrical interconnection is achieved through TSV to improve integration and performance.

[0013] Furthermore, in the S100, the parameters of the line width, spacing, depth and pattern contour accuracy of the etching in the substrate pretreatment and the initial etching of the SiO2 pattern are set as follows: the line width is accurately calculated to be 100-500nm based on the bit transmission line width and coupling strength theory, the spacing is accurately calculated to be 200-800nm ​​based on the electromagnetic shielding and crosstalk suppression model, the depth is strictly determined to be 100-300nm based on the subsequent deposition film thickness and etching process compatibility, and the pattern contour accuracy is <±10nm.

[0014] Furthermore, in the S200, the thickness of the SiO2 film deposited in the dielectric layer deposition and performance enhancement is 200-300nm.

[0015] Furthermore, in the S300, in the preparation of the superconducting Josephson junction, the thickness of the BE-Al film is 95-105 nm, and the thickness of the TE-Al film is 98-102 nm.

[0016] Furthermore, in the S300, the rotation speed of the photoresist spin coating in the preparation of the superconducting Josephson junction is 3000-5000 rpm, and the thickness is 1-2 μm.

[0017] Furthermore, in the S400, in the processing of the suspended structure of the membrane layer, a wet etching process is used to etch the lower SiO2 film, and the solution used is a hydrofluoric acid HF solution.

[0018] Furthermore, in the S500, the beam current of the electron beam in the FIB irradiation film layer folding is 1-5nA, and the beam current of the ion beam is 50-100pA.

[0019] Furthermore, in the S600, FIB deposition function advancement, the thin film material properties involved in the FIB deposition function advancement are: single layer includes Nb, Al, Ta, TiN; multi-layer includes Nb / AlOx / Nb, Al / AlOx / Al.

[0020] Furthermore, in the S600, FIB deposition function is advanced, when the thickness is less than 100nm, the energy is reduced to 15-25Kev and the speed is increased to 1-3μm / s for fine-tuning; when the thickness is ≥300nm, the irradiation time is increased by 10-30min, and multi-segment irradiation is divided into 3-5 segments, and the energy of each segment is fine-tuned by ±5Kev.

[0021] On the other hand, a superconducting quantum chip processor folding bit processing technology, the specific steps of the processing technology are:

[0022] S100, substrate selection and initial engraving of SiO2 patterns: using 12-inch or smaller silicon, SiC, and GaN wafers as substrates, measuring the surface morphology and initial stress value by atomic force microscope and stress tester, etching SiO2 patterns by KrF excimer lithography, the line width is set to 100-500nm according to the bit transmission line width and coupling strength theory, the spacing is set to 200-800nm ​​according to the electromagnetic shielding and crosstalk suppression model, the depth is determined to be 100-300nm according to the subsequent process, and the pattern contour accuracy is <±10nm;

[0023] S200, dielectric layer deposition and quality improvement: In the low temperature range of 80-100℃ of PECVD equipment, 50-150sccm SiH4 is used as the main gas source, 5-15sccm N2O is used as the doping gas, and 100-300W RF power is used to excite plasma to deposit SiO2 film. The optical interferometer monitors the uniformity of the film thickness to within ±5%, and the deposition rate is 0.5-2nm / s. After depositing a 200-300nm thick film, the temperature is raised to 400-600℃ at 5-10℃ / min for annealing for 30-90min to reduce stress to ≤50MPa, eliminate micro defects, and improve thermal budget and mechanical strength.

[0024] S300, fine shaping of Josephson junction: Al / AlOx / Al Josephson junction is made in electron beam evaporation chamber, impurities are removed by degas treatment at 150-200℃ for 30-60min before BE-Al film is deposited, 95-105nm thick BE-Al film is deposited at a deposition temperature of room temperature to 150℃ and a deposition rate of 0.1-0.3nm / s, electron beam current is set at 10-30mA, acceleration voltage is 5-10kV and quartz crystal microbalance is used for monitoring, O2 flow is controlled at 5-15sccm to oxidize and make 10nm AlOx insulating layer, then 98-102nm thick TE-Al film is deposited, photoresist is spin-coated at 3000-5000rpm to form 1-2μm thick film, then electron beam exposure and development are performed, and BE and TE layers are etched by ion beam to form junction;

[0025] S400, the ingenious creation of the suspended film structure: the SiO2 film is wet-etched with hydrofluoric acid HF solution at 20-25°C. The etching time is determined by the film thickness and pattern. The reaction kinetics model is combined with in-situ optical microscope monitoring. The etching is optimized for 30-90s, and the rate is 10-30nm / s to make a sector area with a radius of 50-150μm, a central angle of 30-60°±2°, and a suspension accuracy within ±10μm.

[0026] S500, three-dimensional folding of FIB irradiated film: the sample is fixed on the 6-inch vacuum fixture FIB stage with a clamping force of 50-100N, and the vacuum is <10 -6After Pa, start the 1-5nA beam electron beam and 50-100pA beam ion beam, tilt the stage 55°±1°, adjust the WD 6mm±0.1mm to lock the processing area, set the irradiation parameters according to the blueprint processing frame, SEM image analysis of the film stress-strain field evolution, fine-tune according to the Ta film strain rate 0.005-0.02% / s, control the deformation rate 0.05-0.2μm / s and the direction accuracy ±1° until the Ta film reaches the target shape;

[0027] S600, an excellent advancement in FIB deposition performance: the platinum probe is moved to the processing position to draw the deposition area, which is 3-8μm long, 2-6μm wide and 1μm deep. According to the area of ​​the pattern, 100-250PA current and 30Kev energy deposition are set, argon gas is introduced to drive away oxygen impurities, and the deposition rate is controlled at 0.05-0.2μm / min. Atomic force microscope monitoring is used for feedback control. The irradiation strategy is customized for films of different thicknesses according to their characteristics. For films with a thickness of less than 100nm, the energy is reduced and the speed is increased for fine-tuning. For films with a thickness of ≥300nm, the irradiation time is increased and fine-tuned in multiple stages. The interconnection is planned by TSV process to improve the integration and electrical performance.

[0028] Compared with the prior art, the method and process for folding bits of a superconducting quantum chip processor have the following beneficial effects:

[0029] 1. The present invention realizes the folding processing of superconducting quantum bits by introducing focused ion beam technology, which greatly breaks through the limitations of traditional planar processing technology. Traditional superconducting quantum bit processing methods are mainly based on planar processing technology, and face many challenges in realizing the processing of complex three-dimensional structures. The present invention uses focused ion beam technology to accurately control the stress distribution of the film and realize highly controllable deformation in a set direction, thereby easily realizing the folding of superconducting quantum bits. It not only provides a new idea for the processing of superconducting quantum bits, but also effectively solves the problem that traditional technology is difficult to realize complex three-dimensional structure processing, and improves processing accuracy and repeatability.

[0030] 2. The present invention can fully utilize the three-dimensional scale space of the wafer through the folding of the film, thereby improving the integration of superconducting bits, which is of great significance to the development of the field of superconducting quantum computing. Traditional planar processing technology has limitations in the spatial utilization of wafers, resulting in limited integration of superconducting bits, which seriously restricts the large-scale development and application of superconducting quantum bits. The present invention, through folding processing, enables superconducting quantum bits to be arranged more closely on the wafer, thereby greatly improving the integration. At the same time, combined with mature semiconductor TSV technology, vertical electrical connection is achieved, further improving the performance and integration of superconducting quantum chips, and providing new ideas for the large-scale application of superconducting quantum technology.

[0031] Other advantages, objectives and features of the present invention will be set forth in part in the following description and, in part, will be apparent to those skilled in the art based on an examination of the following or may be taught from the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 A process framework diagram of a method for folding bits in a superconducting quantum chip processor;

[0034] Figure 2 A flow chart of the folded bit processing technology for a superconducting quantum chip processor. DETAILED DESCRIPTION

[0035] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the specific implementation mode, structure, characteristics and effects of the present invention are described in detail below in combination with the accompanying drawings and preferred embodiments.

[0036] Embodiment 1

[0037] First, engrave the SiO2 pattern, then deposit the Al film:

[0038] In a quantum physics laboratory at a certain university, a research team started to develop a new superconducting quantum chip processor, aiming to provide stable and efficient hardware support for quantum computing teaching and basic scientific research projects. They decided to adopt the process of first engraving SiO2 patterns and then depositing Al films. The specific operations are as follows:

[0039] Substrate pretreatment and initial etching of SiO2 graphics (S100): A 10-inch silicon wafer is selected as the substrate. The atomic force microscope is used to carefully scan the substrate surface, and the surface flatness is accurately detected to be good, with only very small fluctuations. The initial stress value is within the normal range. The SiO2 graphics are etched with the help of KrF excimer lithography technology. According to the bit transmission line width and coupling strength theory, the line width is set to 300nm. According to the electromagnetic shielding and crosstalk suppression model, the spacing is accurately determined to be 500nm. In combination with the subsequent deposition film thickness and etching process compatibility, it is set to 200nm. The graphics contour accuracy is strictly controlled at <±10nm to ensure that the graphics meet the superconducting bit functional layout and electrical interconnection requirements.

[0040] Dielectric layer deposition and performance enhancement (S200): The wafer is transferred to the PECVD equipment. In a low temperature environment of 90°C, 100sccm of SiH4 is used as the main gas source, 10sccm of N2O is added, and 200W of RF power is used to excite the plasma to start depositing the SiO2 film. With the help of an optical interferometer for real-time monitoring, the thickness uniformity deviation of the film is ensured to be maintained within ±5%, and the deposition rate is stabilized at 1nm / s. Finally, a 250nm thick SiO2 film is obtained. The temperature is then raised to 500°C at a heating rate of 8°C / min and annealed for 60min. The stress is successfully reduced to 30MPa, microscopic defects are eliminated, the high-temperature thermal budget is increased to 850°C, and the mechanical strength reaches a Knoop hardness of 10GPa.

[0041] Preparation of superconducting Josephson junction (S300): Enter the electron beam evaporation chamber, and before depositing the BE-Al film, degas treatment was performed at 180℃ for 45min to effectively drive away impurities. The deposition temperature was selected to be 100℃, the deposition rate was 0.2nm / s, the electron beam current was set to 20mA, and the acceleration voltage was set to 8kV. The thickness of the film was monitored in real time using a quartz crystal microbalance, and a 100nm thick BE-Al film was deposited. Then, the O2 flow rate was regulated to 10sccm by a mass flow controller, and the chamber pressure was stably controlled at 8×10 - 3 Torr, the oxidation time was set to 30s, a 10nm AlOx insulating layer was made, and then a 100nm thick TE-Al film was deposited. The photoresist was spin-coated at 4000rpm to form a 1.5μm thick film, and then at 300μC / cm 2 Electron beam exposure was used to transfer the designed pattern. After development, ion beam etching was used to etch the BE and TE layers with an etching energy of 400eV, a beam current of 20mA, and an angle of 10° to successfully form a Josephson junction.

[0042] Membrane suspended structure processing (S400): Use hydrofluoric acid HF solution to wet-etch the SiO2 film at a constant temperature of 22°C to achieve a suspended state. Determine the etching time based on the thickness of the SiO2 film and the graphic contour. Use the reaction kinetics model combined with an in-situ optical microscope to monitor the grayscale changes and morphological characteristics of the etching front in real time. Dynamically optimize the etching process within 60s, stabilize the etching rate at 20nm / s, and create a fan-shaped etching area with a fan radius of 100μm, a central angle of 45°, an accuracy of ±2°, and a suspension accuracy controlled within ±10μm.

[0043] FIB irradiation film folding (S500): Fix the treated sample on a 6-inch vacuum fixture on the FIB stage with a clamping force of 80N, and evacuate to <10 -6After 100 Pa, the electron beam (beam current is 3nA) and ion beam (beam current is 80pA) are started. After calibrating the size, energy and scanning accuracy of the beam spot according to the standard calibration procedure of the equipment, the stage is tilted 55°±1° and the WD is adjusted to 6mm±0.1mm to lock the processing area. The processing frame is drawn according to the design blueprint and the size is set. The irradiation is carried out with a current of 50PA±5PA and an energy of 30Kev. The SEM is used to collect images in real time to analyze the evolution of the stress-strain field of the film. The parameters are fine-tuned according to the strain rate of 0.01% / s of the Ta film deformation. The scanning rate is stepped adjusted at 1μm / s and the beam spot size is dynamically optimized at 10nm. The deformation rate is controlled to be 0.1μm / s and the directional accuracy is ±1° until the Ta film stands up and the irradiation is stopped.

[0044] Advanced FIB deposition function (S600): Move the platinum probe to the processing position, heat up to 350℃ at 15℃ / min, draw the deposition area, 5μm long, 4μm wide, 1μm deep, with an accuracy of ±0.3μm, set 180PA current and 30Kev energy to start deposition according to the area of ​​the pattern, introduce argon gas into the chamber before deposition to drive away oxygen impurities, and optimize the deposition rate based on the Pt deposition kinetics equation and the finite element simulation of the electric field distribution and accurately control it at 0.1μm / min. Use atomic force microscopy to monitor the surface morphology for feedback regulation, and use SEM with energy spectrometer to monitor the uniformity of platinum atomic deposition distribution and thickness accuracy in real time. According to the Pt crystal growth model and thin film nucleation theory, the microstructure is verified by high-resolution transmission electron microscopy, and the through-hole layout is pre-planned in combination with the TSV process to avoid interference at each stage of film folding, and vertical electrical interconnection is achieved by TSV to improve integration and performance.

[0045] In summary, this embodiment focuses on the research and development needs of quantum physics laboratories in universities, and demonstrates in detail the folding bit processing flow of a superconducting quantum chip processor that first engraves a SiO2 pattern and then deposits an Al film, highlighting the significant advantages of this process in basic scientific research and teaching scenarios. Starting from substrate pretreatment, with the help of advanced detection equipment and lithography technology, the key parameters of the SiO2 pattern are accurately controlled to lay a solid foundation for subsequent processes; in the dielectric layer deposition stage, the PECVD equipment is combined with strict monitoring methods to achieve the optimization of film thickness, stress and mechanical properties, which meets the laboratory's demand for long-term and stable operation of chips.

[0046] In the preparation of superconducting Josephson junctions, multiple parameters are finely controlled to ensure high-quality formation of the junction; wet etching of suspended structures and FIB irradiation and deposition processes are closely linked, and real-time monitoring feedback and dynamic adjustment are carried out throughout the entire process to ensure microscopic processing accuracy and macroscopic performance. The final product has excellent performance in bit transmission stability and coupling strength, which strongly proves that this process route can not only produce chip samples that meet the requirements of intuitive teaching demonstrations, but also provide reliable hardware support for basic quantum scientific research projects, helping universities to steadily move forward in academic exploration and talent training in the quantum field.

[0047] Embodiment 2:

[0048] Directly engrave Al film:

[0049] A quantum technology company received an order from a customer to customize a high-performance superconducting quantum chip processor. The customer required the chip to have high integration and fast computing speed. The company's R&D team decided to try the process of directly engraving the Al film, hoping to optimize the processing flow and shorten the construction period. The specific implementation steps are as follows:

[0050] Substrate selection and initial engraving of SiO2 patterns (S100): An 8-inch SiC wafer is selected as the substrate, and the surface morphology and initial stress value are quickly measured using an atomic force microscope and a stress tester. The SiO2 pattern is etched using KrF excimer lithography technology. The line width is precisely set to 200nm based on the bit transmission line width and coupling strength theory, and the spacing is precisely set to 400nm based on the electromagnetic shielding and crosstalk suppression model. The depth is determined to be 150nm based on the subsequent process, and the pattern contour accuracy is <±10nm, providing a suitable basic pattern architecture for the subsequent direct engraving of the Al film.

[0051] Dielectric layer deposition and quality improvement (S200): In the 85℃ low temperature range of the PECVD equipment, SiH4 with a flow rate of 80sccm was introduced as the main gas source, and 8sccm of N2O was used as the doping gas. The plasma was excited with a 150W RF power to deposit the SiO2 film. The film thickness uniformity deviation was maintained within ±5% with the optical interferometer for close monitoring. The deposition rate was stabilized at 0.8nm / s, and a 220nm thick SiO2 film was successfully deposited. Then, the temperature was raised to 450℃ at a heating rate of 6℃ / min for annealing for 45min. The stress was successfully reduced to 40MPa, micro defects were eliminated, the high-temperature thermal budget was improved, and the mechanical strength met the subsequent processing requirements.

[0052] Fine shaping of Josephson junction (S300): The wafer is quickly placed in the electron beam evaporation chamber to prepare the Al / AlOx / Al Josephson junction. Before depositing the BE-Al film, it is treated with Degas at 160℃ for 50 minutes to completely remove impurities. The deposition temperature is selected as room temperature, the deposition rate is 0.15nm / s, and a 98nm thick BE-Al film is deposited. The electron beam current is set to 15mA and the acceleration voltage is 6kV. The quartz crystal microbalance is used for full monitoring and the O2 flow rate is precisely controlled to 8sccm to oxidize and manufacture a 10nmAlOx insulating layer. Subsequently, a 99nm thick TE-Al film is deposited. The photoresist is spin-coated at 3500rpm to form a 1.2μm thick film. Electron beam exposure and development are immediately performed, and the BE and TE layers are etched with an ion beam. The etching energy is 350eV, the beam current is 15mA, and the angle is 8° to efficiently create a Josephson junction.

[0053] The ingenious creation of the suspended membrane structure (S400): Under a constant temperature of 23°C, the SiO2 membrane is wet-etched with hydrofluoric acid HF solution. Combined with the reaction kinetics model and in-situ optical microscope, the etching is monitored while etching, and the etching time is flexibly adjusted according to the thickness of the membrane and the pattern contour. The optimized etching is achieved within 45s, and the etching rate is maintained at 15nm / s. A fan-shaped etching area is produced with a fan radius of 80μm, a central angle of 35°, an accuracy of ±2°, and the suspension accuracy is stably controlled within ±10μm.

[0054] Three-dimensional folding of FIB irradiated film (S500): The sample is firmly fixed on the 6-inch vacuum fixture FIB stage with a clamping force of 60N, and the vacuum is evacuated to <10 -6 After 100 Pa, the electron beam (beam current is 2nA) and ion beam (beam current is 60pA) are started, the stage is tilted 55°±1°, and the WD is adjusted to 6mm±0.1mm to lock the processing area. The processing frame is drawn according to the design blueprint, and the irradiation parameters are accurately set. The SEM is used to collect images in real time, and the evolution of the stress-strain field of the thin film is deeply analyzed. The parameters are fine-tuned according to the strain rate of the Ta film of 0.008% / s, and the deformation rate is strictly controlled to 0.08μm / s and the direction accuracy is ±1° until the Ta film reaches the ideal bending shape.

[0055] Excellent advancement of FIB deposition performance (S600): Move the platinum probe to the processing position, heat up to 320℃ at 12℃ / min, draw the deposition area, 4μm long, 3μm wide, 1μm deep, with an accuracy of ±0.3μm, set 120PA current and 30Kev energy to start deposition according to the graphic area, introduce argon gas in advance to drive away oxygen impurities, and accurately control the deposition rate at 0.08μm / min. With the help of atomic force microscope, real-time monitoring and feedback control are carried out. For films of different thicknesses, exclusive irradiation strategies are customized according to their characteristics. When the thickness is less than 100nm, the energy is reduced to 20Kev and the speed is increased to 2μm / s for fine-tuning. When the thickness is ≥300nm, the irradiation time is increased by 20min. Four sections of irradiation are used, and the energy of each section is fine-tuned by ±5Kev. Combined with TSV process planning, efficient interconnection is achieved, which greatly improves the integration and electrical performance.

[0056] To sum up, in the scenario where quantum technology companies pursue efficient production and high-performance delivery, the superconducting quantum chip processor processing technology of direct Al film etching demonstrates great value. With SiC wafer as the substrate, the early etching of SiO2 pattern can closely meet the high-performance requirements of the chip, lock the key dimensional accuracy, and lay a good foundation for the subsequent direct Al etching; the dielectric layer deposition and annealing treatment are completed efficiently, and the ideal film layer quality and stress state are quickly achieved, which is in line with the company's production rhythm of shortening construction period and strictly controlling costs.

[0057] When preparing the Josephson junction, all steps are completed in one go, and precise parameter settings ensure the electrical performance of the junction. The suspended structure processing and FIB-related operations rely on real-time monitoring and targeted fine-tuning to keep the microstructure under control and meet the high integration requirements of the chip. Especially in the advanced FIB deposition stage, the irradiation strategy customized according to the film thickness is combined with the TSV process to comprehensively improve the electrical performance and integration effect. The finished product successfully passed the company's strict quality inspection, far exceeding customer expectations, injecting strong impetus for the company to expand the market and establish a brand image, and also accumulating valuable experience for the commercial mass production of quantum chips, helping the industry to move towards a new stage of efficient and high-quality development.

[0058] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for folding bits of a superconducting quantum chip processor, characterized in that: The specific steps of this processing method are: S100, substrate pretreatment and initial engraving of SiO2 patterns: select silicon, SiC, and GaN wafers of 12 inches or less as the base, use atomic force microscopes and stress testers to detect the surface morphology and initial stress value of the substrate, and use KrF excimer lithography technology to etch SiO2 patterns. The design rules are based on the functional layout of superconducting bits and the requirements of electrical interconnection. S200, dielectric layer deposition and performance enhancement: In the PECVD equipment, in the low temperature range of 80-100℃, SiH4 is used as the main gas source with a flow rate of 50-150sccm, a small amount of N2O is added with a flow rate of 5-15sccm, and 100-300W RF power is used to excite plasma to deposit SiO2 film. The film thickness is monitored in real time by means of an optical interferometer based on the principle of multi-beam interference to ensure that the film thickness uniformity deviation is within ±5% and the deposition rate is stable at 0.5-2nm / s. The temperature is raised to 400-600℃ at a rate of 5-10℃ / min, and annealed for 30-90min to reduce the stress to ≤50MPa, eliminate microscopic defects, increase the high temperature thermal budget to above 800℃, and achieve a mechanical strength of 8-12GPa of Knoop hardness; S300, preparation of superconducting Josephson junction: Al / AlOx / Al Josephson junction was prepared in an electron beam evaporation chamber. Before depositing the BE-Al film, the film was treated with Degas at 150-200℃ for 30-60min to drive away impurities. The deposition temperature was selected to be room temperature to 150℃, the deposition rate was 0.1-0.3nm / s, the electron beam current was set to 10-30mA, the acceleration voltage was set to 5-10kV, the film thickness was monitored in real time by a quartz crystal microbalance, and a 10nm AlOx insulating layer was produced by oxidation. The O2 flow rate was regulated by a mass flow controller to 5-15sccm, and the chamber pressure was stabilized by a capacitive thin film vacuum gauge to 5×10 -3 -1×10 -2 Torr, oxidation time 20-40s, continue to deposit TE-Al film, and then spin-coat photoresist at 200-400μC / cm 2 The design pattern is transferred by electron beam exposure. After development, the BE and TE layers are etched by ion beam with an etching energy of 300-500eV, a beam current of 10-30mA, and an angle of 5-15° to form a Josephson junction. S400, membrane suspended structure processing: use wet etching process to etch SiO2 film to achieve suspended state, etching temperature 20-25℃, etching time is determined according to SiO2 film thickness and pattern profile, with the help of reaction kinetics model combined with in-situ optical microscope to monitor the grayscale change and morphological characteristics of etching front in real time, dynamically optimize the etching process within 30-90s, and control the etching rate at 10-30nm / s to manufacture fan-shaped etching area, with fan radius 50-150μm, central angle 30-60°, accuracy ±2°, and suspension accuracy within ±10μm; S500, FIB irradiation film folding: Fix the treated sample on the FIB stage with a 6-inch vacuum fixture with a clamping force of 50-100N, and evacuate to <10 -6 After Pa, start the electron beam and ion beam, calibrate the beam spot size, energy and scanning accuracy according to the standard calibration procedure of the equipment, tilt the stage 55°±1°, adjust the WD to 6mm±0.1mm to lock the processing area, draw the processing frame according to the design blueprint and set the size, irradiate with a current of 50PA±5PA and an energy of 30Kev, use SEM to collect images in real time to analyze the evolution of the film stress-strain field, fine-tune the parameters according to the strain rate of Ta film deformation of 0.005-0.02% / s, adjust the scanning rate by 0.5-2μm / s, dynamically optimize the beam spot size of 5-15nm, control the deformation rate to 0.05-0.2μm / s, and the directional accuracy to ±1°, until the Ta film stands up or reaches a curved shape, stop irradiation; S600, advanced FIB deposition function: move the platinum probe to the processing position, heat up to 300-400℃ at 10-20℃ / min, draw the deposition area, 3-8μm long, 2-6μm wide, 1μm deep, with an accuracy of ±0.3μm, set 100-250PA current and 30Kev energy to start deposition according to the area of ​​the pattern, introduce argon gas into the chamber before deposition to drive away oxygen impurities, and the deposition rate is optimized and precisely controlled at 0.05-0.2μm / min based on the Pt deposition kinetics equation and finite element simulation of electric field distribution. Use atomic force microscopy to monitor the surface morphology for feedback regulation, and use SEM with energy spectrometer to monitor the uniformity of platinum atomic deposition distribution and thickness accuracy in real time. According to the Pt crystal growth model and thin film nucleation theory, the microstructure is verified by high-resolution transmission electron microscopy. The irradiation strategy is customized according to the material characteristics and thickness range of the film, and the through-hole layout is pre-planned in combination with the TSV process to avoid interference at each stage of film folding. Vertical electrical interconnection is achieved through TSV to improve integration and performance.

2. A superconducting quantum chip processor folding bit processing method according to claim 1, characterized in that: In the S100, the parameters of the line width, spacing, depth and pattern profile accuracy of the substrate pretreatment and the initial etching of the SiO2 pattern are set as follows: the line width is accurately calculated to be 100-500nm based on the bit transmission line width and coupling strength theory, the spacing is accurately calculated to be 200-800nm ​​based on the electromagnetic shielding and crosstalk suppression model, the depth is strictly determined to be 100-300nm based on the subsequent deposition film thickness and etching process compatibility, and the pattern profile accuracy is <±10nm.

3. A superconducting quantum chip processor folding bit processing method according to claim 1, characterized in that: In the S200, the thickness of the SiO2 film deposited in the dielectric layer deposition and performance enhancement is 200-300nm.

4. A superconducting quantum chip processor folding bit processing method according to claim 1, characterized in that: In the S300, in the preparation of the superconducting Josephson junction, the thickness of the BE-Al film is 95-105 nm, and the thickness of the TE-Al film is 98-102 nm.

5. A superconducting quantum chip processor folding bit processing method according to claim 1, characterized in that: In the S300, the rotation speed of the photoresist spin coating in the preparation of the superconducting Josephson junction is 3000-5000 rpm, and the thickness is 1-2 μm.

6. A superconducting quantum chip processor folding bit processing method according to claim 1, characterized in that: In the above S400, in the film layer suspended structure processing, a wet etching process is used to etch the lower SiO2 film, and the solution used is a hydrofluoric acid HF solution.

7. A superconducting quantum chip processor folding bit processing method according to claim 1, characterized in that: In the S500, the beam current of the electron beam in the FIB irradiation film layer folding is 1-5nA, and the beam current of the ion beam is 50-100pA.

8. A superconducting quantum chip processor folding bit processing method according to claim 1, characterized in that: In the S600, FIB deposition function advancement, the thin film material properties involved in the FIB deposition function advancement are: single layer includes Nb, Al, Ta, TiN; multi-layer includes Nb / AlOx / Nb, Al / AlOx / Al.

9. A superconducting quantum chip processor folding bit processing method according to claim 1, characterized in that: In the S600, when the FIB deposition function is advanced, when the thickness is less than 100nm, the energy is reduced to 15-25Kev and the speed is increased to 1-3μm / s for fine-tuning; when the thickness is ≥300nm, the irradiation time is increased by 10-30min, and multi-stage irradiation is divided into 3-5 stages, and the energy of each stage is fine-tuned by ±5Kev.

10. A superconducting quantum chip processor folding bit processing technology, characterized in that: The specific steps of this processing technology are: S100, substrate selection and initial engraving of SiO2 patterns: using 12-inch or smaller silicon, SiC, and GaN wafers as substrates, measuring the surface morphology and initial stress value by atomic force microscope and stress tester, etching SiO2 patterns by KrF excimer lithography, the line width is set to 100-500nm according to the bit transmission line width and coupling strength theory, the spacing is set to 200-800nm ​​according to the electromagnetic shielding and crosstalk suppression model, the depth is determined to be 100-300nm according to the subsequent process, and the pattern contour accuracy is <±10nm; S200, dielectric layer deposition and quality improvement: In the low temperature range of 80-100℃ of PECVD equipment, 50-150sccm SiH4 is used as the main gas source, 5-15sccm N2O is used as the doping gas, and 100-300W RF power is used to excite plasma to deposit SiO2 film. The optical interferometer monitors the uniformity of the film thickness to within ±5%, and the deposition rate is 0.5-2nm / s. After depositing a 200-300nm thick film, the temperature is raised to 400-600℃ at 5-10℃ / min for annealing for 30-90min to reduce stress to ≤50MPa, eliminate micro defects, and improve thermal budget and mechanical strength. S300, fine shaping of Josephson junction: Al / AlOx / Al Josephson junction is made in electron beam evaporation chamber, impurities are removed by degas treatment at 150-200℃ for 30-60min before BE-Al film is deposited, 95-105nm thick BE-Al film is deposited at a deposition temperature of room temperature to 150℃ and a deposition rate of 0.1-0.3nm / s, electron beam current is set at 10-30mA, acceleration voltage is 5-10kV and quartz crystal microbalance is used for monitoring, O2 flow is controlled at 5-15sccm to oxidize and make 10nm AlOx insulating layer, then 98-102nm thick TE-Al film is deposited, photoresist is spin-coated at 3000-5000rpm to form 1-2μm thick film, then electron beam exposure and development are performed, and BE and TE layers are etched by ion beam to form junction; S400, the ingenious creation of the suspended film structure: the SiO2 film is wet-etched with hydrofluoric acid HF solution at 20-25°C. The etching time is determined by the film thickness and pattern. The reaction kinetics model is combined with in-situ optical microscope monitoring. The etching is optimized for 30-90s, and the rate is 10-30nm / s to make a sector area with a radius of 50-150μm, a central angle of 30-60°±2°, and a suspension accuracy within ±10μm. S500, three-dimensional folding of FIB irradiated film: the sample is fixed on the 6-inch vacuum fixture FIB stage with a clamping force of 50-100N, and the vacuum is <10 -6 After Pa, start the 1-5nA beam electron beam and 50-100pA beam ion beam, tilt the stage 55°±1°, adjust the WD 6mm±0.1mm to lock the processing area, set the irradiation parameters according to the blueprint processing frame, SEM image analysis of the film stress-strain field evolution, fine-tune according to the Ta film strain rate 0.005-0.02% / s, control the deformation rate 0.05-0.2μm / s and the direction accuracy ±1° until the Ta film reaches the target shape; S600, an excellent advancement in FIB deposition performance: the platinum probe is moved to the processing position to draw the deposition area, which is 3-8μm long, 2-6μm wide and 1μm deep. According to the area of ​​the pattern, 100-250PA current and 30Kev energy deposition are set, argon gas is introduced to drive away oxygen impurities, and the deposition rate is controlled at 0.05-0.2μm / min. Atomic force microscope monitoring is used for feedback control. The irradiation strategy is customized for films of different thicknesses according to their characteristics. For films with a thickness of less than 100nm, the energy is reduced and the speed is increased for fine-tuning. For films with a thickness of ≥300nm, the irradiation time is increased and fine-tuned in multiple stages. The interconnection is planned by TSV process to improve the integration and electrical performance.

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