Memory repair system providing soft repair data and hard repair data

Abstract

A system for repairing a random access memory may include serial test interface logic, fuse sensing logic, a repair data register chain, and multiplexing logic. The repair data register chain may include serial interconnected data registers configured to shift data through the repair data register chain. Each data register of the repair data register chain may have a data output configured to be coupled to a repair information input of the random access memory. The multiplexing logic may be configured to provide a soft repair mode and a hard repair mode. When the soft repair mode is selected, the multiplexing logic may be configured to receive soft repair data provided by the serial test interface logic into the data register. When the hard repair mode is selected, the multiplexing logic may be configured to receive data provided by the fuse sensing logic into the data register.

Description

[0001] Related technical description

[0002] Memory devices, such as dynamic random access memory ("DRAM"), may be included in a wide variety of computing devices. In a computing device, the memory device may be included in or otherwise coupled to a chip that contains one or more processing systems. A system on a chip, or "SoC," is a chip that integrates many components to provide system-level functionality. For example, a SoC may include one or more types of processors, such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), a digital signal processor ("DSP"), and a neural processing unit ("NPU"). The SoC may include other processing subsystems, such as a transceiver or "modem" subsystem that provides wireless connectivity.

[0003] In a memory device, a memory array cell may have a manufacturing defect that prevents the cell from properly storing data. The memory device may be tested after manufacturing to reveal any such defects. Techniques have been developed for repairing a memory array having defective cells. A memory device may include spare rows or columns that may replace any defective rows or columns. A first type of repair using spare rows or columns may be referred to as a "soft repair." A second type of repair using spare rows or columns may be referred to as a "hard repair."

[0004] The soft repair method may use a serial test interface specified by the Joint Test Action Group ("JTAG"). Through the JTAG interface, repair information may be serially loaded into a chain of JTAG data registers, such as in a SoC or other chip to which a memory device is coupled or in which the memory device is integrated. The repair information stored in the JTAG data registers is thus used by the memory device to control the replacement of defective rows or columns of a memory array with spare rows or columns.

[0005] The hard repair method may use a programmable read-only memory ("PROM") to store repair information. A PROM cell may be referred to as a fuse. The PROM and associated repair logic (such as fuse sensing control logic and fuse sensing registers) may be included in a SoC or other chip to which a memory device is coupled or in which the memory device is integrated. The hard repair may be performed when the computing device is powered on or otherwise restarted in preparation for use. When the computing device is powered on or restarted, the fuse sensing control logic may serially load the repair information into the fuse sensing register (i.e., a trigger). The repair information thus stored in the fuse sensing register is accessed and used by the memory device to control the replacement of defective rows or columns of a storage array with spare rows or columns.

[0006] The SoC or similar chip may include both soft repair logic and hard repair logic. Multiplexing circuits may be included to couple the fuse sense registers or the JTAG data registers to the memory device. Such combined soft repair and hard repair logic may include thousands of JTAG data registers for soft repair and thousands of fuse sense registers for hard repair. Summary of the invention

[0007] Systems, methods and other examples for repairing random access memory are disclosed. An exemplary system for repairing random access memory may include serial test interface logic, fuse sensing logic, a repair data register chain and multiplexing logic. The repair data register chain may include a plurality of serially interconnected data registers configured to serially shift data through the repair data register chain. Each data register of the repair data register chain may have a data output configured to be coupled to a repair information input of the random access memory. The multiplexing logic may be configured to provide a soft repair mode and a hard repair mode. When the soft repair mode is selected, the multiplexing logic may be configured to receive the soft repair data provided by the serial test interface logic into the data register. When the hard repair mode is selected, the multiplexing logic may be configured to receive the data provided by the fuse sensing logic into the data register.

[0008] An exemplary method for repairing a random access memory may include receiving a mode selection signal indicating a soft repair mode or a hard repair mode. The method may also include reading soft repair data from a serial test interface logic into a repair data register chain via multiplexing logic in response to the mode selection signal indicating the soft repair mode. The method may also include reading hard repair data from a fuse sensing logic into a repair data register chain via multiplexing logic in response to the mode selection signal indicating the hard repair mode. The method may also include providing repair data from an output of a data register to a repair information input of the random access memory.

[0009] Another exemplary system for repairing a random access memory may include a component for receiving a mode selection signal indicating a soft repair mode or a hard repair mode. The system may also include a component for reading soft repair data from a serial test interface logic into a repair data register chain via a multiplexing logic in response to the mode selection signal indicating the soft repair mode. The system may also include a component for reading hard repair data from a fuse sensing logic into a repair data register chain via a multiplexing logic in response to the mode selection signal indicating the hard repair mode. The system may also include a component for providing repair data from an output of a data register to a repair information input of the random access memory.

[0010] An exemplary system on chip (SoC) may include a system for repairing a random access memory. The SoC may include fuse sensing logic, serial test interface logic, a repair data register chain, and multiplexing logic. The serial test interface logic may include JTAG logic. The repair data register chain may include a plurality of serially interconnected data registers configured to serially shift data through the repair data register chain. Each data register of the repair data register chain may have a data output configured to be coupled to a repair information input of the random access memory. The multiplexing logic may be configured to provide a soft repair mode and a hard repair mode. When the soft repair mode is selected, the multiplexing logic may be configured to receive the soft repair data provided by the serial test interface logic into the data register. When the hard repair mode is selected, the multiplexing logic may be configured to receive the data provided by the fuse sensing logic into the data register. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In the drawings, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations, such as "101A" or "101B", the letter character designation may distinguish between two similar parts or elements in the same figure. The letter character designation of a reference numeral may be omitted when it is intended that the reference numeral encompass all parts having the same reference numeral in all figures.

[0012] Figure 1 is a block diagram of a memory repair system according to an exemplary embodiment.

[0013] Figure 2 is a block diagram of another memory repair system according to an exemplary embodiment.

[0014] Figure 3A is a block diagram of a repair data register chain and associated logic according to an exemplary embodiment.

[0015] Figure 3B yes Figure 3A Continuation of the block diagram.

[0016] Figure 4 is a block diagram of control signal chain register logic according to an exemplary embodiment.

[0017] Figure 5 is a block diagram of a JTAG data register according to an exemplary embodiment.

[0018] Figure 6 is a flowchart illustrating a memory repair method according to an exemplary embodiment.

[0019] Figure 7is a flow chart illustrating a hard repair method according to an exemplary embodiment.

[0020] Figure 8 is a flow chart illustrating a soft repair method according to an exemplary embodiment.

[0021] Fig. 9 is a block diagram of a portable computing device according to an exemplary embodiment. DETAILED DESCRIPTION

[0022] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." The word "exemplary" may be used herein synonymously with "exemplary." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0023] like Figure 1 As shown, in an exemplary or exemplary embodiment, a memory repair system 100 for repairing a random access memory ("RAM") 102 may include a repair data register chain and multiplexing logic 104. The RAM 102 may be of any type that includes features for repairing its memory array by replacing spare rows or columns based on repair information that the RAM 102 may receive. The format of such repair information and the manner in which the RAM 102 may receive and use the repair information are well understood by those of ordinary skill in the art. Therefore, such aspects are not described herein. The RAM 102 may be, for example, a double data rate synchronous dynamic RAM ("DDR-SDRAM"). The repair data register chain and multiplexing logic 104 may be included in a system on a chip ("SoC") 106. Although in Figure 1 Not shown, SoC 106 may include numerous other components, such as processors and subsystems, interconnected by a data communication bus or the like.

[0024] The memory repair system 100 may also include fuse sensing logic 108. The fuse sensing logic 108 may be configured to read the state of fuses or cells of a read-only memory ("ROM") 110, which may be referred to as a fuse ROM. The fuse ROM 110 may be a programmable ROM ("PROM"). Since the fuse sensing logic 108 and the fuse ROM 110 are fully understood in the art, they will not be described in further detail herein. It may be noted that the fuse ROM 110 contains or stores repair information, and providing the repair information from the fuse ROM 110 to the repair information input of the RAM 102 may be referred to as a "hard repair".

[0025] The memory repair system 100 may also include a serial test interface logic 112. The serial test interface logic 112 may also be included in the SoC 106. Although in the illustrated embodiment, the RAM 102, the fuse sensing logic 108, and the fuse ROM 110 are shown as separate components coupled to the SoC 106 (i.e., outside the SoC 106), in other embodiments, one or more of such components may be included in such a SoC together with the serial test interface logic 112 and the repair data register chain and the multiplexing logic 104. The serial test interface logic 106 may be used not only to test the logic components of the SoC 106, but also to provide soft repair data or information to the RAM 102. Although not shown for clarity, the serial test interface logic 112 may be coupled to SoC pins, pads, etc., through which signals may be communicated between the serial test interface logic 112 and equipment external to the SoC 106. An example of the serial test interface logic 106 is logic according to the specifications published by the Joint Test Action Group ("JTAG"). Although such JTAG logic is well understood by those skilled in the art, it can be described as follows: Figure 2 Providing repair information from JTAG logic or other serial test interface logic 112 to the repair information input of RAM 102 may be referred to as "soft repair."

[0026] Soft repair can be performed at any time. For example, it can be performed on a computing device ( Figure 1 Soft repair may be performed during post-manufacturing testing of the SoC 106 or a portion thereof that includes the SoC 106 and the RAM 102. As will be appreciated by one of ordinary skill in the art, in the event that substantially the same repair information is expected to be used to perform a hard repair of the RAM 102, the soft repair may be employed to confirm the validity of the repair information. The soft repair information (i.e., row / column replacements) that is confirmed by the soft repair method to result in correct operation of the RAM 102 may then be translated into corresponding hard repair information.

[0027] For example, hard repair may be performed at the beginning or start-up of a normal operating mode or "mission mode" of a computing device (not shown) including SoC 106 (including system 100) therein. For example, during the startup (e.g., power-on, reset, etc.) process in a smartphone, hard repair information may be transferred from fuse ROM 110 to RAM 102 via the repair data register chain and multiplexing logic 104 and used to maintain RAM 102 in a repair state during the course of mission mode operation of the smartphone by a user.

[0028] Whether the repair data register chain and multiplexing logic 104 operates in a hard repair mode or a soft repair mode may be selectable (e.g., based on a control signal, as described below). The multiplexing feature of the repair data register chain and multiplexing logic 104 may be configured to select a data path based on whether the soft repair mode or the hard repair mode is selected. That is, such multiplexing feature may be configured to receive soft repair data provided by the serial test interface logic 112 into the repair data register chain via certain data paths when the soft repair mode is selected (described in further detail below), and to receive hard repair data provided by the fuse sensing logic 108 via other data paths when the hard repair mode is selected.

[0029] exist Figure 2 In the embodiment, the memory repair system 200 may include JTAG logic 202. The system 200 may be the system 100 ( Figure 1 ), and the JTAG logic 202 may be an example of a portion of the serial test interface logic 106 described above. As will be appreciated by one of ordinary skill in the art, the JTAG logic 202 may receive the following JTAG test signals via a test access port or “TAP”: a test data input (“TDI”) signal on a TDI signal input 204; a test clock (“TCK”) signal on a TCK signal input 206, a test mode select (“TMS”) signal on a TMS signal input 208, and a test reset (“TRST”) signal on a TRST signal input 210. The JTAG logic 202 may include a TAP controller 212 (e.g., a finite state machine), an instruction register 214, an instruction decoder 216, a bypass register 218, and a device ID register 220. The TAP controller 212 may control receiving data via the TDI signal path 204, loading various registers, and other functions. For example, the instruction register 214 may be loaded with instructions received via the TDI signal path 204. Instruction decoder 216 is configured to decode instructions in instruction register 214. As will be appreciated by one of ordinary skill in the art, data received serially via TDI signal path 204 may represent not only test data, but also instructions involved in controlling JTAG logic 202. Since TAP controller 212 and its use via JTAG logic 202 are well understood by one of ordinary skill in the art, such aspects will not be described in detail herein.

[0030] The system 200 may also include a repair data register chain and multiplexing logic 226, a control signal register chain 228, a boundary scan register chain 224, and any number of other JTAG data register chains (not shown but indicated by an ellipsis symbol ("..."). The boundary scan register chain 224 is not relevant to the solution described herein, but is shown for completeness because it is typically included in a system having such JTAG logic. The control signal register chain 228 may include a plurality of JTAG data registers ("JDR") 227. For example, the control signal register chain 228 may include eight JDRs 227, each JDR being configured to receive and store one of eight corresponding control bits "C0"-"C7". The control signal register chain 228 is further described below. The repair data register chain and multiplexing logic 226 and the control signal register chain 228 may receive TDI and TCK signals. The control signal register chain may provide at least two of the aforementioned control bits to the repair data register chain and multiplexing logic 226: a soft repair enable signal (which may be referred to hereinafter as mem_sr_en) and a soft repair done signal (which may be referred to hereinafter as mem_sr_done).

[0031] The JTAG logic 202 may also include repair data distribution logic 229. The repair data distribution logic 229 may be configured to provide repair data to the repair information input terminal ( Figure 2 The repair data distribution logic 229 may be configured to receive the repair data from the repair data register chain and multiplexing logic 226 and provide the repair data to the repair information input of the RAM in response to a repair_data_ready signal received from the repair data register chain and multiplexing logic 226.

[0032] JTAG logic 202 may also include a multiplexer ("MUX") 222 that selects from among its inputs based on the output of instruction decoder 216. One of the selectable inputs of MUX 222 may be coupled to an output of a repair data register chain and multiplexing logic 226. Repair data register chain and multiplexing logic 226 may be a repair data register chain and multiplexing logic 104 (described above). Figure 1). Yet another of the selectable inputs of MUX 222 may be coupled to an output of control signal register chain 228. Another of the selectable inputs of MUX 222 may be coupled to an output of boundary scan register chain 224. Still other of the selectable inputs of MUX 222 may be coupled to bypass register 218, device ID register 220, or other registers (not shown) of JTAG logic 202. The output of MUX 222 may be provided to an input of another MUX 230, which may be configured to select between the input and a second input coupled to instruction register 214. The output of MUX 230 may provide a test data output ("TDO") JTAG signal via a TAP. The TDO JTAG signal may be used in the context of memory repair system 200 to read back data from the registers referenced above for verification.

[0033] The JTAG logic 202 may also include instruction gating logic 232 configured to decode signals provided by the instruction decoder 216 as a result of decoding an instruction. The instruction gating logic 232 may provide a data shift signal (which may be referred to below as mem_sr_data_shift) to the repair data register chain and multiplexing logic 226 via signal path 234. The instruction gating logic 232 may also provide the following signals to the control signal register chain 228 via signal path 236: a control shift signal (which may be referred to below as mem_sr_ctrl_shift), a read or hold select signal (which may be referred to below as mem_sr_ctrl_bsen), and a control bit update signal (which may be referred to below as mem_sr_ctrl_update). The TAP controller 212 may provide JTAG signals, generally referred to as capture_DR, shift_DR, and update_DR, to the instruction gating logic 232 via signal path 235. The TAP controller 212 may provide a JTAG reset signal (which may be referred to hereinafter as jtag_reset) to the repair data register chain and multiplexing logic 226 and the control signal register chain 228 via signal path 237. The instruction gating logic 232 may be configured to generate the mem_sr_data_shift signal using the following operation: shift_DR & INST(mem_sr_data), where the and symbol ("&") represents a logical AND operation, and INST is a decode function of the instruction decoder 216, where the instruction is mem_sr_data. The instruction gating logic 232 may be configured to generate the mem_sr_ctrl_shift signal using the following operation: shift_DR & INST(mem_sr_ctrl). The instruction gating logic 232 may be configured to generate the mem_sr_ctrl_bsen signal using the following operation: (capture_DR|shift-DR) & INST(mem_sr_ctrl), where the vertical bar symbol ("|") represents a logical OR operation. The instruction gating logic 232 may be configured to generate the mem_sr_ctrl_update signal using the following operation: update_DR & INST(mem_sr_ctrl).

[0034] exist FIG. 3A to FIG. 3B , a repair data register chain and multiplexing logic 300 and a repair data distribution logic 303 are shown. The repair data register chain and multiplexing logic 300 may be the above-mentioned repair data register chain and multiplexing logic 104 ( Figure 1 ) or 226( Figure 2 ) example.

[0035] The repair data register chain and multiplexing logic 300 may include data registers (eg, D-type flip-flops) 302. The data registers 302 may be interconnected in series (ie, in a chain): a first register 302A ( Figure 3A ) may be coupled (e.g., via any number of intermediate multiplexing or other components, as described below) to a second register 302B ( Figure 3A ) data input terminal ("D"). The data output terminal of the second register 302B may be coupled to the third register 302C ( Figure 3A ) data input terminal. The data output terminal of the third register 302C can be coupled to the fourth register 302D ( Figure 3A ) data input terminal. The data output terminal of the fourth register 302D can be coupled to the fifth register 302E ( Figure 3B ) data input terminal. The data output terminal of the fifth register 302E can be coupled to the sixth register 302F ( Figure 3B ) data input terminal. The data output terminal of the sixth register 302F can be coupled to the seventh register 302G ( Figure 3B ) data input terminal. The data output terminal of the seventh register 302G can be coupled to the eighth register 302H ( Figure 3B ) is a data input terminal of the data register 302. This configuration enables data to be serially shifted through the data register 302, i.e., from the previous data register 302 in the chain to the next data register 302 in the chain. Whether the data is read into the register 302, shifted through the register 302, or held in the register 302 can be controlled by the multiplexing logic described below. Although in the illustrated embodiment, eight data registers 302 are included in the chain, in other embodiments, there may be more or less than eight such serially interconnected data registers. For example, there may be thousands of such serially interconnected (i.e., in the chain) data registers.

[0036] A clock signal may be provided to each data register 302 via signal path 304. The clock signal provided to the data register 302 may be provided by a clock MUX 306 ( Figure 3A ) from the TCK signal or the functional clock signal ("func_clk"). The functional clock signal can be connected to the SoC (in FIG. 3A to FIG. 3B 306). The clock MUX 306 may be responsive to the control signal register chain 228 (not shown) under which the functional logic of the SoC (not shown) operates. When the SoC is powered on or otherwise initialized, the functional clock signal not only begins to operate the SoC in task mode, but also operates the data register 302 based on the selection made by the clock MUX 306. The clock MUX 306 may be responsive to the control signal register chain 228 ( Figure 2) to select between its input terminals. The mem_sr_en signal acts as a mode selection signal that controls whether the hard repair mode or the soft repair mode is selected. When the SoC is powered on or otherwise initialized, the mem_sr_en signal is low, indicating the hard repair mode.

[0037] The repair data register chain and multiplexing logic 300 may include fuse sensing logic 308 ( Figure 3A ). The fuse sensing logic 308 may be the fuse sensing logic 108 ( Figure 1 ). For clarity, the fuse sensing logic 308 may be coupled to a fuse PROM in Figure 3A The output of the fuse sense logic 308 providing the hard repair data may be coupled to the data inputs of at least some of the data registers 302. The hard repair data provided by the fuse sense logic 308 may thus be read into the data registers 302, controlled by the multiplexing logic described below.

[0038] In the illustrated embodiment, and referring first to Figure 3A , a data input of the first register 302A may be coupled to a first output 310A of the fuse sensing logic 308 via a path through a portion of the multiplexing logic including MUX 312 and MUX 314. A data input of the second register 302B may be coupled to a second output 310B of the fuse sensing logic 308 via a path through a portion of the multiplexing logic including MUX 318 and MUX 320. A data input of the third register 302C may be coupled to a third output 310C of the fuse sensing logic 308 via a path through a portion of the multiplexing logic including MUX 324 and MUX 326. A data input of the fourth register 302D may be coupled to a fourth output 310D of the fuse sensing logic 308 via a path through a portion of the multiplexing logic including MUX 330 and MUX 332.

[0039] exist Figure 3B Continuing in FIG. 1 , the data input of the fifth register 302E may be coupled to the first register 302A ( FIG. 14 ) via a path through a portion of the multiplexing logic including MUX 336 and MUX 338. Figure 3A The data input of the sixth register 302F may be coupled to the second register 302B ( ) via a path through a portion of the multiplexing logic including MUX 342 and MUX 344. Figure 3A The data input of the seventh register 302G may be coupled to the third register 302C ( ) via a path through a portion of the multiplexing logic including MUX 348 and MUX 350. Figure 3A The data input of the eighth register 302H may be coupled to the fourth register 302D ( ) via a path through a portion of the multiplexing logic including MUX 354 and MUX 356. Figure 3A ) data output terminal.

[0040] Note that in the illustrated embodiment, the four outputs 310A-310D of the fuse sense logic 308 are coupled to the data inputs of the first set of four registers 302A-302D, and the outputs of the first set of four registers 302A-302D are coupled to the inputs of the second set of four registers 302E-302H. The registers 302 are coupled in groups of four in this manner because, in the illustrated embodiment, four bits of repair data are read from the fuse sense logic 308 at a time. Thus, the repair data read from the fuse sense logic 308 is shifted through the registers 302 in the same four-bit unit. Initially, in a first read operation, a first set of four bits may be read from the fuse sense logic 308 into the first set of registers 302A-302D. Next, in a second read operation, as the first set of four bits are shifted from the first set of registers 302A-302D into the second set of registers 302E-302H, a second set of four bits may be read from the fuse sense logic 308 into the first set of registers 302A-302D. These read operations may be repeated until all hard repair data has been read into all registers 302. Although in the illustrated embodiment, the four outputs 310A-310D of the fuse sense logic 308 are coupled to the data inputs of the four registers 302A-302D, in other embodiments, more outputs of such fuse sense logic may be coupled to more such data registers, such as, for example, the data inputs of registers 302E-302H. In other embodiments, the repair data may be read in units of any other number of bits, such as 16 bits at a time, 32 bits at a time, etc., and there will be a correspondingly larger number of registers.

[0041] MUX 312, 318, 324, 330, 336, 342, 348, and 354 may be controlled by the output of an AND gate 358. The input of AND gate 358 may be coupled to the read_fuse signal and the complement of the mem_sr_en signal. In hard repair mode, the mem_sr_en signal is low (i.e., has a value of "0"), thereby enabling the read_fuse signal to control MUX 312, 318, 324, 330, 336, 342, 348, and 354. MUX 314, 320, 326, 332, 338, 344, 350, and 356 may be controlled by the output of another AND gate 360. The input of AND gate 360 ​​may be coupled to the mem_sr_en signal and the mem_sr_data_shift signal. When mem_sr_en is low (indicating hard repair mode) and the read_fuse signal is high, MUX 312-332 couples the output terminals 310A-310D of the fuse sensing logic 308 to the input terminals of the first group of four registers 302A-302D, and MUX 336-356 couples the output terminals of the first group of four registers 302A-302D to the input terminals of the second group of four registers 302E-302H.

[0042] In hard repair mode, when the read_fuse signal goes low (indicating that the hard repair data has been read), MUX 312-356 couples the output of register 302 to its corresponding input. In this state, the data at the output of register 302 is clocked back into register 302 on each cycle of the functional clock signal, thereby retaining the data.

[0043] When all registers 302 are loaded with hard repair data in this manner, MUX 362 may assert the repair_data_ready signal. When mem_sr_en is low (indicating hard repair mode), MUX 362 may select the fuse_sense_done signal as the repair_data_ready signal. In hard repair mode, in response to such assertion of the repair_data_ready signal, the repair data distribution logic 303 may transfer data from the output of the register 302 to the repair information input of the RAM.

[0044] The control signal register chain 228 ( Figure 2 ) to select the soft repair mode. As described above, when mem_sr_en is high, MUX 306 selects the TCK signal to clock register 302. The mem_sr_data_shift signal can be asserted to prepare for shifting the soft repair data into register 302.

[0045] Additionally, when mem_sr_en is high and mem_sr_data_shift is high, the output of AND gate 360 ​​causes MUXs 314, 320, 326, 332, 338, 344, 350, and 356 to couple the TDI signal to the input of register 302. The TDI signal may provide soft repair data, which is clocked into register 302 by the TCK signal. When all of the soft repair data has been shifted into register 302, the soft repair data may be retained in register 302 by deasserting the mem_sr_data_shift signal. In soft repair mode, after all of the soft repair data has been shifted into register 302, the output of AND gate 358 is low because the mem_sr_en signal is high (and therefore the complement of mem_sr_en is low). Additionally, in soft repair mode, after all soft repair data has been shifted into register 302, the output of AND gate 360 ​​is low because mem_sr_data_shift is low. When the outputs of both AND gates 358 and 360 are low, MUX 312-356 couple the output of register 302 to the corresponding input of register 302. In this state, the data at the output of register 302 is clocked back into register 302 on each cycle of the TCK signal, thereby retaining the data.

[0046] When all registers 302 are loaded with soft repair data in this manner, MUX 362 may assert the repair_data_ready signal. When mem_sr_en is high (indicating soft repair mode), MUX 362 selects the mem_sr_done signal as the repair_data_ready signal. In response to such assertion of the repair_data_ready signal in the soft repair mode, the repair data distribution logic 303 may transfer data from the output of the register 302 to the repair information input of the RAM.

[0047] Thus, the data outputs of registers 302 collectively provide hard repair data to repair data distribution logic 303 when hard repair mode is selected, and collectively provide soft repair data to repair data distribution logic 303 when soft repair mode is selected. The multiplexing logic portion including MUXs 306 and 312-358 may operate based on whether hard repair mode or soft repair mode is selected.

[0048] like Figure 4As shown, the exemplary control signal register chain 228 may include eight JDRs 227: a first JDR 227A, a second JDR 227B, and so on to an eighth JDR 227H. For clarity, only three JDRs 227A, 227B, and 227H are shown, and the remaining four JDRs 227 are indicated by an omission ("...") symbol. In the illustrated embodiment, only two JDRs 227A and 227B are used, and the remaining six JDRs 227 may not be used. The first JDR 227A may be configured to store a first control bit C0 representing a mem_sr_en signal. The second JDR 227B may be configured to store a second control bit C1 representing a mem_sr_done signal. The eighth JDR 227H may be configured to store an eighth control bit C7, but it is not used in this example.

[0049] As will be understood by one of ordinary skill in the art, each JDR 227 may have the following inputs and outputs: a clock signal input ("clk"), a shift signal input ("shift"), a read or hold select signal input ("bsen"), an update signal input ("upt"), a reset signal input ("rst"), a primary data input ("pi"), a primary data output ("po"), a shift data input ("bsi"), and a shift data output ("bso"). In the control signal register chain 228, the shift data input of the first JDR 227A may be configured to receive the TDI signal, and the shift data input of each other JDR 227 in the chain may be coupled to the shift data output of the previous JDR 227 in the chain. The primary data output (C0 control bit) of the first JDR 227A may provide a mem_sr_en signal. The primary data output (C1 control bit) of the second JDR 227B may provide a mem_sr_done signal. The clock signal input terminal of each JDR 227 may be configured to receive a TCK signal. The shift signal input terminal of each JDR 227 may be configured to receive a mem_sr_ctrl_shift signal. The read / hold select signal input terminal of each JDR 227 may be configured to receive a mem_sr_ctrl_bsen signal. The update signal input terminal of each JDR 227 may be configured to receive a mem_sr_ctrl_update signal. The reset signal input terminal of each JDR 227 may be configured to receive a jtag_reset signal.

[0050] exist Figure 5 , an exemplary JDR 500 is shown. The JDR 500 may be a JDR 227 ( Figure 4) in each JDR. JDR 500 may include a first MUX 502, a second MUX 504, a flip-flop 506, and a latch 508. Two inputs of MUX 502 may be a main data input and a shift data input of JDR 500. A control input of MUX 502 may be a shift signal input of JDR 500. One input of MUX 504 may be coupled to an output of MUX 502. Another input of MUX 504 may be coupled to a Q output of flip-flop 506. A control input of MUX 506 may be a read / hold selection signal input of JDR 500. A D input of flip-flop 506 may be coupled to an output of MUX 504. A clock input of flip-flop 506 may be a clock signal input of JDR 500. A Q output of flip-flop 506 may also be coupled to a D input of latch 508 and may also be a shift data output of JDR 500. The Q output of latch 508 may be the primary data output of JDR 500. The latch control input G of latch 508 may be the update signal input of JDR 500. The reset input of latch 508 may be the reset signal input of JDR 500. It may be noted that a system according to the solution described herein includes only one set of data registers, such as register 302 (FIG. 3); such a system does not include a first set of registers for soft repair data and a second set of registers for hard repair data. In contrast, some conventional memory repair systems (not shown) may include both a chain of thousands of serially interconnected JTAG data registers for soft repair data and an array of thousands of fuse sense registers for hard repair. In contrast, the solution described herein effectively uses the same registers, such as register 302, for both hard repair and soft repair. Fewer registers and associated data paths (i.e., conductors) on a SoC or other chip may reduce chip area congestion and / or make chip area that would otherwise be occupied by such registers and associated data paths (i.e., conductors) available for other components, data paths, etc. Fewer registers on an SoC or other chip can also help reduce power consumption.

[0051] exist Figure 6 , a method 600 for repairing RAM is illustrated in flowchart form. As indicated by block 602, the method 600 may include receiving a mode selection signal indicating a soft repair mode or a hard repair mode. For example, setting a control bit of a control signal register chain may select the hard repair mode. Additionally or alternatively, the hard repair mode may be selected in response to a power-on reset of the system.

[0052] As indicated at block 604, method 600 may include reading hard repair data from the fuse sensing logic into the repair data register chain via multiplexing logic when the mode selection signal indicates the hard repair mode. For example, further in response to a power-on reset, the hard repair data may be read from the fuse sensing logic into the repair data register chain using a functional clock signal.

[0053] As indicated at block 606, method 600 may include reading soft repair data from JTAG logic or other serial test interface logic into a repair data register chain via multiplexing logic when the mode select signal indicates a soft repair mode. For example, setting a control bit of a control signal register chain may select the soft repair mode. The repair data bits may then be loaded into the repair data register chain using JTAG logic.

[0054] As indicated at block 608, method 600 may include providing repair data from the output of the data register to the repair information input of the RAM. The repair data may be hard repair data read into the repair data register chain as per block 604 or soft repair data read into the repair data register chain as per block 606.

[0055] exist Figure 7 For use Figure 2 and FIG. 3A to FIG. 3B A method 700 for performing a hard repair on a RAM of a system is illustrated in flowchart form. As indicated by block 702, a power-on reset may be performed. As a result of the power-on reset, various logic elements may be initialized as follows. All JTAG logic 202 ( Figure 2 ) can be in reset state. All JDR 227( Figure 2 and Figure 4 ) may be in a reset state. Therefore, the mode selection signals mem_sr_en and mem_sr_done may have a value of "0". When the fuse sensing logic and the repair data distribution logic 226 ( Figure 2 ) is in the reset state, the fuse_sense_done signal may have a value of "0" and all data to the memory repair input of the RAM may have a value of "0".

[0056] As indicated by block 704, in response to the signal referenced above having been initialized, fuse sense logic 308 ( Figure 3A ) may read the hard repair data from the fuse PROM. As indicated by block 706, the operation indicated by block 704 may be repeated until all the hard repair data has been read from the fuse PROM. When all the hard repair data has been read from the fuse PROM, the fuse_sense_done signal may have a value of "1". In response to the fuse_sense_done signal having a value of "1", the repair data distribution logic 303 may distribute the hard repair data to the RAM repair information input terminal.

[0057] Although block 708 may end the hard repair method 700, additional operations may be performed after the repair. For example, the memory system including the (repaired) RAM may begin mission mode operations, as indicated by block 710. Alternatively, a memory built-in self-test or "MBIST" may be performed on the (repaired) RAM, as indicated by block 712. Alternatively, a soft repair method may be performed on the RAM after the hard repair, as indicated by block 714. (Soft repair methods are described below with respect to Figure 8 As indicated in block 716, yet another alternative after hard repair of the RAM may be to use JTAG logic 202 ( Figure 2 ) to debug the PROM fuse. For example, after hard repair, it can be determined that the hard repair data is incorrect. Figure 2 2, the repair data register chain and multiplexing logic 226 may have a serial repair data output ("RDO") coupled to an input of MUX 222. Through this path, repair data values ​​(e.g., fuse values) may be shifted out of register 302 ( FIG. 3A to FIG. 3B ) and read from the TDO signal output of JTAG logic 202. The output of the last register 302H in the chain can provide an RDO path coupled to the input of MUX 222. A method similar to method 800 described below ( Figure 8 ) of the portion indicated by boxes 802-808.

[0058] exist Figure 8 For use Figure 2 and FIG. 3A to FIG. 3B A method 800 for performing soft repair on a RAM of a system is illustrated in flowchart form. As indicated by block 802, JTAG logic 202 ( Figure 2 ) can be used to issue a mem_sr_ctrl instruction. In response to the mem_sr_ctrl instruction, the instruction gating logic 232 ( Figure 2 ) can select the control signal register chain 228 ( Figure 2 ), that is, the mem_sr_ctrl_shift, mem_sr_ctrl_bsen, and mem_sr_ctrl_update signals may be enabled to control the control signal register chain 228 .

[0059] As indicated at block 804, in the control signal register chain 228 ( Figure 2 ) is in the selected or enabled state, the control bit can be shifted to the control signal register chain 228 ( Figure 2) into the JDR 227 of the TAP controller 212. Using the JTAG logic 202, the TAP controller 212 can assert the SHIFT_DR signal on the signal path 235 to prepare to shift the control bits into the JDR 227. In response to the assertion of the SHIFT_DR signal, the instruction gating logic 232 can set the mem_sr_ctrl_shift signal to "1" and set the mem_sr_ctrl_bsen_signal to "1". The control bits can be provided using the TDI and TCK signals. To enable the soft repair mode, a value of "1" can be shifted into the control bit C0 to set the mem_sr_en signal to "1". A value of "0" can be shifted into the control bit C1 to set the mem_sr_done signal to "0". When all control bits have been shifted into the JDR 227, the TAP controller 212 can de-assert the SHIFT_DR signal. In response to the deassertion of the SHIFT_DR signal, the instruction gating logic 232 may set the mem_sr_ctrl_shift signal to "0" and the mem_sr_ctrl_bsen_signal to "0". The TAP controller 212 may then assert the UPDATE_DR signal. In response to the UPDATE_DR signal, the instruction gating logic 232 may generate the mem_sr_ctrl_update signal. In response to the mem_sr_ctrl_update signal, the JDR 227 latches the value at its Q input.

[0060] As indicated by block 806, JTAG logic 202 ( Figure 2 ) can then be used to issue a mem_sr_data instruction. In response to the mem_sr_data instruction, the instruction gating logic 232 ( Figure 2 ) Optionally repair the data register chain and multiplexing logic 226 ( Figure 2 ), that is, mem_sr_data_shift can be enabled to control the repair data register chain and multiplexing logic 226.

[0061] As indicated at block 808, before repairing the data register chain and multiplexing logic 226 ( Figure 2 ) is in the selected or enabled state, the soft repair data can be shifted to register 302 ( FIG. 3A to FIG. 3B ). Using JTAG logic 202, TAP controller 212 ( Figure 2 ) may assert the SHIFT_DR signal on signal path 235 to prepare for shifting the soft repair data into register 302. In response to the assertion of the SHIFT_DR signal, instruction gating logic 232 may set the mem_sr_data_shift signal to "1".

[0062] Blocks 802-808 described above involve shifting the repair data into register 302 ( FIG. 3A to FIG. 3B ) for soft repair purposes. As described above, a similar method can be used to shift the repair data value (e.g., hard repair fuse value) from register 302 to JTAG logic 202 ( Figure 2 ), thus enabling the repair data value to be read via the TDO signal for purposes such as debugging fuse values.

[0063] The soft repair data bits may be provided using the TDI and TCK signals. As indicated by block 810, the operations of block 808 may continue until all of the soft repair data bits have been shifted into register 302. When all of the control bits have been shifted into register 302, TAP controller 212 may de-assert the SHIFT_DR signal. As indicated by block 812, in response to de-assertion of the SHIFT_DR signal, instruction gating logic 232 may set the mem_sr_data_shift signal to "0". In response to the mem_sr_data_shift signal having a value of "0", MUXs 314, 320, 326, 332, 338, 344, 350, and 356 retain or hold the contents of register 302, as described above.

[0064] As indicated by block 814, the soft repair data is loaded into register 302 ( FIG. 3A to FIG. 3B ) in the JTAG logic 202 ( Figure 2 ) can be used to issue another mem_sr_ctrl instruction. In response to the mem_sr_ctrl instruction, the instruction gating logic 232 ( Figure 2 ) can select the control signal register chain 228 again ( Figure 2 ).

[0065] As indicated by block 816, the control bit may be set again. The TAP controller 212 may assert the SHIFT_DR signal on the signal path 235 to prepare for shifting the control bit into the JDR 227. In response to the assertion of the SHIFT_DR signal, the instruction gating logic 232 may set the mem_sr_ctrl_shift signal to "1" and the mem_sr_ctrl_bsen_signal to "1". The control bits may be provided using the TDI and TCK signals. A value of "1" may be shifted into the control bit C0 to set the mem_sr_en signal to "1". A value of "1" may be shifted into the control bit C1 to set the mem_sr_done signal to "1", thereby indicating that the soft repair data has been loaded into the register 302 ( FIG. 3A to FIG. 3B). When all control bits have been shifted into JDR 227, TAP controller 212 may deassert the SHIFT_DR signal. In response to the deassertion of the SHIFT_DR signal, instruction gating logic 232 may set the mem_sr_ctrl_shift signal to "0" and the mem_sr_ctrl_bsen_signal to "0". TAP controller 212 may then assert the UPDATE_DR signal. In response to the UPDATE_DR signal, instruction gating logic 232 may generate a mem_sr_ctrl_update signal. In response to the mem_sr_ctrl_update signal, JDR 227 latches the value at its Q input.

[0066] As indicated by block 818, in response to the mem_sr_done signal having a value of "1", the repair data distribution logic 303 may distribute the soft repair data from the register 302 to the repair information input of the RAM. Although block 818 may end the hard repair method 800, additional operations may be performed after the repair. Blocks 820, 822, 824, and 826 indicate four examples of various alternative additional operations. Blocks 820-826 indicate the same operations as blocks 710-716 ( Figure 7 ) additional operations of the same type.

[0067] Fig. 9 An example of a portable computing device ("PCD") 900 is illustrated in which exemplary embodiments of systems, methods, computer-readable media, and other examples of memory repair may be provided. For example, PCD 900 may be a laptop or palmtop computer, a cellular or smartphone, a personal digital assistant, a navigation device, a smartbook, a portable game console, a satellite phone, etc. However, systems, methods, computer-readable media, and other examples of memory repair may be provided in any other type of computing device or component thereof. For clarity, the PCD 900 may be described in detail in the accompanying drawings. Fig. 9 Some data buses or interconnects, signal paths, etc. are not shown, and other data buses or interconnects, signal paths, etc. may be shown in a conceptual manner. However, it should be understood that the components of PCD 900 can be coupled via such interconnects or signal paths.

[0068] PCD 900 may include SoC 902. SoC 902 may include a central processing unit ("CPU") 904, a graphics processing unit ("GPU") 906, a digital signal processor ("DSP") 907, an analog signal processor 908, a modem / modem subsystem 954, or other processors. CPU 904 may include one or more CPU cores, such as a first CPU core 904A, a second CPU core 904B, and so on to an Nth CPU core 904N.

[0069] The PCD 900 may include a display controller 910 and a touch screen controller 912 coupled to the CPU 904. A touch screen display 914 external to the SoC 902 may be coupled to the display controller 910 and the touch screen controller 912. The PCD 900 may also include a video decoder 916 coupled to the CPU 904. A video amplifier 918 may be coupled to the video decoder 916 and the touch screen display 914. A video port 920 may be coupled to the video amplifier 918. A universal serial bus (“USB”) controller 922 may also be coupled to the CPU 904, and a USB port 924 may be coupled to the USB controller 922. A subscriber identity module (“SIM”) card 926 may also be coupled to the CPU 904.

[0070] One or more memories may be coupled to the CPU 904. The one or more memories may include both volatile memory and non-volatile memory. Examples of volatile memory include static RAM ("SRAM") 928 and dynamic RAM ("DRAM") 930 and 931. Such memories may be located external to the SoC 902 (such as DRAM 930) or internal to the SoC 902 (such as DRAM 931). A DRAM controller 932 coupled to the CPU 904 may control writing data to and reading data from the DRAMs 930 and 931. Either or both of the DRAMs 930 and 931 may be RAM 102 ( Figure 1 ) example.

[0071] SoC 902 may include a memory repair system 933 that may be coupled to CPU 904 and one or both of DRAMs 930 and 931. Memory repair system 933 may include the memory repair system 100 described above. Figure 1 ) or 200( Figure 2 ) part. Although Figure 1 , Figure 2In the embodiments illustrated in the for clarity, JTAG logic or other serial test interface logic is included in the memory repair system 100, 200, etc., but those of ordinary skill in the art understand that such serial test interface logic can be used for other purposes, such as testing various functionalities of the SoC 702. Therefore, such serial test interface logic can be a different subsystem from the memory repair system 933 and can be coupled to other SoC subsystems, other JTAG data registers, SoC boundary scan triggers (not shown), etc. More generally, as those of ordinary skill in the art understand, such serial test interface logic provides a way to pass test data to and from the SoC 902 (e.g., to and from test equipment (not shown) external to the SoC 902). The serial test interface logic can be used to test the SoC 902 before providing the SoC 902 in the PCD 900.

[0072] A stereo audio codec 934 may be coupled to the analog signal processor 908. In addition, an audio amplifier 936 may be coupled to the stereo audio codec 934. A first stereo speaker 938 and a second stereo speaker 940 may be coupled to the audio amplifier 936, respectively. In addition, a microphone amplifier 942 may be coupled to the stereo audio codec 934, and a microphone 944 may be coupled to the microphone amplifier 942. A frequency modulation ("FM") radio tuner 946 may be coupled to the stereo audio codec 934. An FM antenna 948 may be coupled to the FM radio tuner 946. In addition, a stereo headset 950 may be coupled to the stereo audio codec 934. Other devices that may be coupled to the CPU 904 include one or more digital (e.g., CCD or CMOS) cameras 952.

[0073] A modem or RF transceiver 954 may be coupled to the analog signal processor 908 and the CPU 904. An RF switch 956 may be coupled to the RF transceiver 954 and the RF antenna 958. In addition, a keypad 960, a mono headset 962 with a microphone, and a vibrator device 964 may be coupled to the analog signal processor 908.

[0074] SoC 902 may have one or more internal or on-chip thermal sensors 970A and may be coupled to one or more external or off-chip thermal sensors 970B. Analog-to-digital converter controller 972 may convert the voltage drop generated by thermal sensors 970A and 970B into a digital signal. Power supply 974 and power management integrated circuit ("PMIC") 976 may provide power to SoC 902 and other components.

[0075] Specific implementation examples are described in the following numbered clauses.

[0076] 1. A system for repairing a random access memory, comprising:

[0077] Serial test interface logic;

[0078] Fuse sensing logic;

[0079] A repair data register chain, the repair data register chain comprising a plurality of serially interconnected data registers configured to serially shift data through the repair data register chain, each data register of the repair data register chain having a data output terminal configured to be coupled to a repair information input terminal of the random access memory; and multiplexing logic, the multiplexing logic being configured to provide a soft repair mode and a hard repair mode, the multiplexing logic being configured to selectively receive soft repair data provided by the serial test interface logic into the data register when the soft repair mode is selected, or to selectively receive hard repair data provided by the fuse sensing logic into the data register when the hard repair mode is selected.

[0080] 2. The system of clause 1, wherein the serial test interface logic comprises a Joint Test Action Group (JTAG)

[0081] logic.

[0082] 3. A system according to clause 1 or 2, wherein the multiplexing logic includes a first plurality of multiplexers corresponding to the plurality of data registers, each of the first plurality of multiplexers having an output terminal coupled to a data input terminal of the corresponding data register, and each of the first plurality of multiplexers having a first input terminal configured to receive a portion of the hard repair data provided by the fuse sensing logic and a second input terminal configured to receive a portion of the soft repair data.

[0083] 4. A system as described in claim 3, wherein the second input of a first multiplexer in the first plurality of multiplexers is coupled to a serial data output of the serial test interface logic, and the second input of each other multiplexer in the first plurality of multiplexers is coupled to the data output of one of the data registers.

[0084] 5. The system of clause 4, further comprising a second plurality of multiplexers corresponding to the plurality of data registers, a first input of each of the second plurality of multiplexers coupled to the fuse sensing logic, a second input of each of the second plurality of multiplexers coupled to the data output of the corresponding data register, and an output of each of the second plurality of multiplexers coupled to the first input of a multiplexer in the first plurality of multiplexers.

[0085] 6. The system according to any one of clauses 1 to 5 further includes a clock multiplexer, which is configured to selectively couple a serial test interface clock signal to a clock input of each data register when the soft repair mode is selected, or to selectively couple a functional clock signal to a clock input of each data register when the hard repair mode is selected.

[0086] 7. A system according to any one of clauses 1 to 6, further comprising a control signal register chain, wherein the control signal register chain comprises a plurality of serially interconnected control signal registers configured to serially shift data through the control signal register chain, an input end of the control signal register chain being coupled to a serial data output end of the serial test interface logic, and an output end of each control signal register being coupled to a control input end of the multiplexing logic.

[0087] 8. The system of any one of clauses 1 to 7, wherein the serial test interface logic, the fuse sensing logic, the repair data register chain, and the multiplexing logic are included in a system on a chip (SoC).

[0088] 9. A system for repairing a random access memory, comprising:

[0089] means for receiving a mode selection signal indicating a soft repair mode or a hard repair mode;

[0090] means for reading soft repair data from serial test interface logic into a repair data register chain via multiplexing logic in response to the mode selection signal indicating the soft repair mode, the repair data register chain comprising a plurality of serially interconnected data registers;

[0091] for responding to the mode selection signal indicating the hard repair mode, via the multiplexing logic

[0092] Hard repair data is read from fuse sensing logic to components in the repair data register chain; and

[0093] Means for providing repair information from the output of the data register to the repair information input of the random access memory.

[0094] 10. The system of clause 9, wherein the serial test interface logic comprises Joint Test Action Group (JTAG) logic.

[0095] 11. A system according to clause 9 or 10, wherein:

[0096] The means for reading hard repair data comprises means for providing a portion of the hard repair data to a first input of each of a first plurality of multiplexers corresponding to the plurality of data registers;

[0097] and

[0098] The means for reading soft repair data includes means for providing a portion of the soft repair data to a second input of each multiplexer of the first plurality of multiplexers.

[0099] 12. The system of clause 11, wherein the means for providing the portion of the soft repair data comprises:

[0100] for coupling a serial data output of the serial test interface logic to the first plurality of multiplexers

[0101] a component of the second input terminal of the first multiplexer; and

[0102] Means for coupling an output of the data register to the second input of each other multiplexer of the first plurality of multiplexers.

[0103] 13. The system according to clause 12, further comprising:

[0104] for coupling a first input terminal of each multiplexer in a second plurality of multiplexers to the fuse inductor

[0105] a detection logic component, wherein the second plurality of multiplexers correspond to the plurality of data registers; and

[0106] Means for coupling a second input of each multiplexer of the second plurality of multiplexers to the output of a corresponding data register.

[0107] 14. A system according to any one of clauses 9 to 13, further comprising:

[0108] means for coupling a serial test interface clock signal to a clock input of each data register when said soft repair mode is selected; and

[0109] Means for coupling a functional clock signal to the clock input of each data register when the hard repair mode is selected.

[0110] 15. A system according to any one of clauses 9 to 14, further comprising:

[0111] means for serially transferring data from the serial test interface logic to a control signal register chain, the control signal register chain comprising a plurality of serially interconnected control signal registers; and

[0112] Means for coupling an output of the control signal register to a control input of the multiplexing logic.

[0113] 16. A method for repairing a random access memory, comprising:

[0114] receiving a mode selection signal indicating a soft repair mode or a hard repair mode;

[0115] In response to the mode selection signal indicating the soft repair mode, the soft repair data is read from the serial test interface logic into a repair data register chain via a multiplexing logic, the repair data register chain comprising a plurality of serial test interface logics.

[0116] Data registers interconnected in rows;

[0117] In response to the mode selection signal indicating the hard repair mode, the hard repair mode is selected via the multiplexing logic.

[0118] The repair data is read from the fuse sensing logic into the repair data register chain; and

[0119] Repair information is provided from an output of the data register to a repair information input of the random access memory.

[0120] 17. The method of clause 16, wherein the serial test interface logic comprises Joint Test Action Group (JTAG) logic.

[0121] 18. A method according to clause 16 or 17, wherein:

[0122] Reading the hard repair data includes providing a portion of the hard repair data to a first input of each of a first plurality of multiplexers corresponding to the plurality of data registers; and

[0123] Reading the soft repair data includes providing a portion of the soft repair data to a second input of each multiplexer in the first plurality of multiplexers.

[0124] 19. The method of clause 18, wherein providing the portion of the soft repair data comprises:

[0125] coupling a serial data output of the serial test interface logic to the second input of a first multiplexer of the first plurality of multiplexers; and

[0126] An output of the data register is coupled to the second input of each other multiplexer in the first plurality of multiplexers.

[0127] 20. The method according to clause 19, further comprising:

[0128] A first input terminal of each multiplexer in the second plurality of multiplexers is coupled to the fuse sensing logic

[0129] logic, the second plurality of multiplexers corresponding to the plurality of data registers; and

[0130] A second input of each multiplexer of the second plurality of multiplexers is coupled to the output of a corresponding data register.

[0131] 21. The method according to any one of clauses 16 to 20, further comprising:

[0132] When the soft repair mode is selected, the serial test interface clock signal is coupled to the clock of each data register.

[0133] input terminal; and

[0134] A functional clock signal is coupled to the clock input of each data register when the hard repair mode is selected.

[0135] 22. The method according to any one of clauses 16 to 21, further comprising:

[0136] The data is transferred serially from the serial test interface logic to the control signal register chain.

[0137] The signal register chain includes a plurality of serially interconnected control signal registers; and

[0138] An output of the control signal register is coupled to a control input of the multiplexing logic.

[0139] 23. The method of any of clauses 16 to 22, wherein the method is performed in a system on a chip (SoC).

[0140] 24. A system on chip (SoC) having a system for repairing a random access memory, comprising:

[0141] Fuse sensing logic on the SoC;

[0142] serial test interface logic on the SoC, the serial test interface logic comprising Joint Test Action Group (JTAG) logic;

[0143] A repair data register chain on the SoC, the repair data register chain comprising a plurality of serially interconnected data registers configured to serially shift data through the repair data register chain, each data register of the repair data register chain having a data register configured to be coupled to a repair information input terminal of the random access memory.

[0144] output terminal; and

[0145] A multiplexing logic on the SoC, the multiplexing logic being configured to provide a soft repair mode and a hard repair mode, the multiplexing logic being configured to selectively receive soft repair data provided by the serial test interface logic into the data register when the soft repair mode is selected, or to selectively receive hard repair data provided by the fuse sensing logic into the data register when the hard repair mode is selected.

[0146] 25. A system according to clause 24, wherein the multiplexing logic includes a first plurality of multiplexers corresponding to the plurality of data registers, each of the first plurality of multiplexers having an output terminal coupled to a data input terminal of a corresponding data register, each of the first plurality of multiplexers having a first input terminal configured to receive a portion of the hard repair data provided by the fuse sensing logic and a second input terminal configured to receive a portion of the soft repair data.

[0147] 26. A system according to clause 24 or 25, wherein the second input of a first multiplexer in the first plurality of multiplexers is coupled to a serial data output of the serial test interface logic, and the second input of each other multiplexer in the first plurality of multiplexers is coupled to the data output of one of the data registers.

[0148] 27. The system of clause 26, further comprising a second plurality of multiplexers corresponding to the plurality of data registers, a first input of each of the second plurality of multiplexers coupled to the fuse sensing logic, a second input of each of the second plurality of multiplexers coupled to the data output of the corresponding data register, and an output of each of the second plurality of multiplexers coupled to the first input of a multiplexer in the first plurality of multiplexers.

[0149] 28. The system according to any one of clauses 24 to 27 further includes a clock multiplexer, which is configured to selectively couple a serial test interface clock signal to a clock input of each data register when the soft repair mode is selected, or to selectively couple a functional clock signal to a clock input of each data register when the hard repair mode is selected.

[0150] 29. A system according to any one of clauses 24 to 28, further comprising a control signal register chain, the control signal register chain comprising a plurality of serially interconnected control signal registers configured to serially shift data through the control signal register chain, an input end of the control signal register chain coupled to a serial data output end of the serial test interface logic, and an output end of each control signal register coupled to a control input end of the multiplexing logic.

[0151] 30. The system of clause 29, wherein one of the control signal registers is configured to store a bit indicating whether the soft repair mode or the hard repair mode is selected.

[0152] Alternative embodiments will become apparent to those of ordinary skill in the art.Thus, while selected aspects have been illustrated and described in detail, it should be understood that various substitutions and changes may be made therein.

Claims

1. A system for repairing a random access memory, comprising: Serial test interface logic; Fuse sensing logic; a repair data register chain, the repair data register chain comprising a plurality of serially interconnected data registers configured to serially shift data through the repair data register chain, each data register of the repair data register chain having a data output configured to be coupled to a repair information input of the random access memory; and A multiplexing logic is configured to provide a soft repair mode and a hard repair mode, and the multiplexing logic is configured to selectively receive soft repair data provided by the serial test interface logic into the data register when the soft repair mode is selected, or to selectively receive hard repair data provided by the fuse sensing logic into the data register when the hard repair mode is selected.

2. The system of claim 1, wherein the serial test interface logic comprises Joint Test Action Group (JTAG) logic.

3. The system of claim 1 , wherein the multiplexing logic comprises a first plurality of multiplexers corresponding to the plurality of data registers, each multiplexer in the first plurality of multiplexers having an output coupled to a data input of a corresponding data register, each multiplexer in the first plurality of multiplexers having a first input configured to receive a portion of the hard repair data provided by the fuse sensing logic and a second input configured to receive a portion of the soft repair data.

4. The system of claim 3 , wherein the second input of a first multiplexer of the first plurality of multiplexers is coupled to a serial data output of the serial test interface logic, and the second input of each other multiplexer of the first plurality of multiplexers is coupled to the data output of one of the data registers.

5. The system of claim 4 , further comprising a second plurality of multiplexers corresponding to the plurality of data registers, a first input of each of the second plurality of multiplexers coupled to the fuse sensing logic, a second input of each of the second plurality of multiplexers coupled to the data output of the corresponding data register, and an output of each of the second plurality of multiplexers coupled to the first input of a multiplexer of the first plurality of multiplexers.

6. The system of claim 1 , further comprising a clock multiplexer configured to selectively couple a serial test interface clock signal to a clock input of each data register when the soft repair mode is selected, or to selectively couple a functional clock signal to a clock input of each data register when the hard repair mode is selected.

7. The system of claim 1 , further comprising a control signal register chain, the control signal register chain comprising a plurality of serially interconnected control signal registers configured to serially shift data through the control signal register chain, an input of the control signal register chain coupled to a serial data output of the serial test interface logic, an output of each control signal register coupled to a control input of the multiplexing logic.

8. The system of claim 1, wherein the serial test interface logic, the fuse sensing logic, the repair data register chain, and the multiplexing logic are included in a system on a chip (SoC).

9. A system for repairing a random access memory, comprising: means for receiving a mode selection signal indicating a soft repair mode or a hard repair mode; means for reading soft repair data from serial test interface logic into a repair data register chain via multiplexing logic in response to the mode selection signal indicating the soft repair mode, the repair data register chain comprising a plurality of serially interconnected data registers; means for reading hard repair data from fuse sensing logic into the repair data register chain via the multiplexing logic in response to the mode selection signal indicating the hard repair mode; and Means for providing repair information from the output of the data register to the repair information input of the random access memory.

10. The system of claim 9, wherein the serial test interface logic comprises Joint Test Action Group (JTAG) logic.

11. The system of claim 9, wherein: The means for reading hard repair data comprises means for providing a portion of the hard repair data to a first input of each of a first plurality of multiplexers corresponding to the plurality of data registers; and The means for reading soft repair data includes means for providing a portion of the soft repair data to a second input of each multiplexer of the first plurality of multiplexers.

12. The system of claim 11, wherein the means for providing the portion of the soft repair data comprises: means for coupling a serial data output of said serial test interface logic to said second input of a first multiplexer of said first plurality of multiplexers; and Means for coupling an output of the data register to the second input of each other multiplexer of the first plurality of multiplexers.

13. The system of claim 12, further comprising: means for coupling a first input of each multiplexer of a second plurality of multiplexers corresponding to the plurality of data registers to the fuse sensing logic; and Means for coupling a second input of each multiplexer of the second plurality of multiplexers to the output of a corresponding data register.

14. The system of claim 9, further comprising: means for coupling a serial test interface clock signal to a clock input of each data register when said soft repair mode is selected; and Means for coupling a functional clock signal to the clock input of each data register when the hard repair mode is selected.

15. The system of claim 9, further comprising: means for serially transferring data from the serial test interface logic to a control signal register chain, the control signal register chain comprising a plurality of serially interconnected control signal registers; and Means for coupling an output of the control signal register to a control input of the multiplexing logic.

16. A method for repairing a random access memory, comprising: receiving a mode selection signal indicating a soft repair mode or a hard repair mode; reading soft repair data from serial test interface logic into a repair data register chain via multiplexing logic in response to the mode selection signal indicating the soft repair mode, the repair data register chain comprising a plurality of serially interconnected data registers; reading hard repair data from fuse sensing logic into the repair data register chain via the multiplexing logic in response to the mode selection signal indicating the hard repair mode; as well as Repair information is provided from an output of the data register to a repair information input of the random access memory.

17. The method of claim 16, wherein the serial test interface logic comprises Joint Test Action Group (JTAG) logic.

18. The method of claim 16, wherein: Reading the hard repair data includes providing a portion of the hard repair data to a first input of each of a first plurality of multiplexers corresponding to the plurality of data registers; and Reading the soft repair data includes providing a portion of the soft repair data to a second input of each multiplexer in the first plurality of multiplexers.

19. The method of claim 18, wherein providing the portion of the soft repair data comprises: coupling a serial data output of the serial test interface logic to the second input of a first multiplexer of the first plurality of multiplexers; as well as An output of the data register is coupled to the second input of each other multiplexer in the first plurality of multiplexers.

20. The method according to claim 19, further comprising: coupling a first input of each multiplexer in a second plurality of multiplexers corresponding to the plurality of data registers to the fuse sensing logic; as well as A second input of each multiplexer of the second plurality of multiplexers is coupled to the output of a corresponding data register.

21. The method of claim 16, further comprising: coupling a serial test interface clock signal to a clock input terminal of each data register when the soft repair mode is selected; as well as A functional clock signal is coupled to the clock input of each data register when the hard repair mode is selected.

22. The method of claim 16, further comprising: passing data serially from the serial test interface logic to a control signal register chain, the control signal register chain comprising a plurality of serially interconnected control signal registers; as well as An output of the control signal register is coupled to a control input of the multiplexing logic.

23. The method of claim 16, wherein the method is performed in a system on a chip (SoC).

24. A system on chip (SoC) having a system for repairing a random access memory, comprising: Fuse sensing logic on the SoC; serial test interface logic on the SoC, the serial test interface logic comprising Joint Test Action Group (JTAG) logic; a repair data register chain on the SoC, the repair data register chain comprising a plurality of serially interconnected data registers configured to serially shift data through the repair data register chain, each data register of the repair data register chain having a data output terminal configured to be coupled to a repair information input terminal of the random access memory; as well as A multiplexing logic on the SoC, the multiplexing logic being configured to provide a soft repair mode and a hard repair mode, the multiplexing logic being configured to selectively receive soft repair data provided by the serial test interface logic into the data register when the soft repair mode is selected, or to selectively receive hard repair data provided by the fuse sensing logic into the data register when the hard repair mode is selected.

25. The system of claim 24, wherein the multiplexing logic comprises a first plurality of multiplexers corresponding to the plurality of data registers, each multiplexer in the first plurality of multiplexers having an output coupled to a data input of a corresponding data register, each multiplexer in the first plurality of multiplexers having a first input configured to receive a portion of the hard repair data provided by the fuse sensing logic and a second input configured to receive a portion of the soft repair data.

26. The system of claim 25, wherein the second input of a first multiplexer of the first plurality of multiplexers is coupled to a serial data output of the serial test interface logic, and the second input of each other multiplexer of the first plurality of multiplexers is coupled to the data output of one of the data registers.

27. The system of claim 26, further comprising a second plurality of multiplexers corresponding to the plurality of data registers, a first input of each of the second plurality of multiplexers coupled to the fuse sensing logic, a second input of each of the second plurality of multiplexers coupled to the data output of the corresponding data register, and an output of each of the second plurality of multiplexers coupled to the first input of a multiplexer of the first plurality of multiplexers.

28. The system of claim 24, further comprising a clock multiplexer configured to selectively couple a serial test interface clock signal to a clock input of each data register when the soft repair mode is selected, or to selectively couple a functional clock signal to a clock input of each data register when the hard repair mode is selected.

29. The system of claim 24, further comprising a control signal register chain comprising a plurality of serially interconnected control signal registers configured to serially shift data through the control signal register chain, an input of the control signal register chain coupled to a serial data output of the serial test interface logic, an output of each control signal register coupled to a control input of the multiplexing logic.

30. The system of claim 29, wherein one of the control signal registers is configured to store a bit indicating whether the soft repair mode or the hard repair mode is selected.

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