Buried trench capacitor

Abstract

A microelectronic device (100) is provided that includes a buried trench capacitor (170) under an electronic component (174) of the microelectronic device (100). In one embodiment, the buried trench capacitor (170) may be formed between a silicon oxide-covered p-type buried trench capacitor polysilicon region (126) and a buried trench capacitor deep n-type region (108) separated by a buried trench capacitor liner dielectric (124). In a second embodiment, the buried trench capacitor (170) may be formed from a buried trench capacitor polysilicon region (126) and a p-type silicon epitaxial region (106) separated by a buried trench capacitor liner dielectric (124). One terminal of the deep trench capacitor (170) is made through the substrate (102) via a deep trench substrate contact (134). A second terminal of the deep trench capacitor (170) is made via a well contact that in one embodiment connects to the capacitor (170) through a deep well region and in a second embodiment through a polysilicon layer.

Description

Technical Field

[0001] The present disclosure relates to the field of microelectronic devices. More particularly, but not exclusively, the present disclosure relates to buried trench capacitors in microelectronic devices. Background Art

[0002] Bypass capacitors have been used in conjunction with microelectronic devices such as switch mode power converters. In such devices, capacitor characteristics such as electromagnetic interference (EMI) are critical to performance. EMI has previously been improved by moving bypass capacitors from a separate chip to the same chip as the microelectronic device. Further improvements in integrating capacitors into microelectronic devices are needed. Summary of the invention

[0003] The present disclosure introduces a microelectronic device that includes a buried trench capacitor below the top surface of the microelectronic device. In one embodiment, the buried trench capacitor can be formed between a silicon oxide covered buried trench capacitor polysilicon region and a buried trench capacitor deep well region separated by a buried trench capacitor liner dielectric. In a second embodiment, the buried trench capacitor can be formed by a buried trench capacitor polysilicon region and a silicon epitaxial region separated by a buried trench liner dielectric. One terminal of the deep trench capacitor is made through the substrate via a deep trench substrate contact. The second terminal of the deep trench capacitor is made via a well contact, which passes through the deep well region in one embodiment and through the polysilicon layer in a second embodiment to connect to the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1A to Figure 1K A cross-section of a first embodiment of an example microelectronic device having a buried trench capacitor is depicted at successive stages of an example formation method.

[0005] FIG. 2A to FIG. 2I A cross-section of a second embodiment of an example microelectronic device having a buried trench capacitor is depicted at successive stages of an example formation method. DETAILED DESCRIPTION

[0006] The present disclosure is described with reference to the accompanying drawings. The figures are not drawn to scale and are provided only to illustrate the present disclosure. Several aspects of the present disclosure are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the present disclosure. The present disclosure is not limited by the described order of actions or events, because some actions may occur in different orders and / or may occur simultaneously with other actions or events. In addition, not all described actions or events are required to implement the methods according to the present disclosure.

[0007] In addition, although some of the embodiments described herein are shown in two-dimensional views of various regions with depth and width, it should be clearly understood that these regions are merely illustrative of portions of a device that is actually a three-dimensional structure. Therefore, these regions, when manufactured on an actual device, will have three dimensions, including length, width, and depth. Furthermore, although the present invention is described by embodiments with respect to active devices, these descriptions are not intended to limit the scope or applicability of the present invention. It is not intended to limit the active devices of the present invention to the physical structures described. These structures are included to demonstrate the utility and application of the present invention to the presently preferred embodiments.

[0008] It should be noted that terms such as top, bottom, front, back, over, above, below, and below may be used in the present disclosure. These terms should not be construed as limiting the position or orientation of structures or elements, but should be used to provide spatial relationships between structures or elements. Similarly, words such as "inwardly" and "outwardly" will refer to directions toward and away from, respectively, the geometric center of a device or area and designated parts thereof.

[0009] For purposes of this disclosure, the term "lateral" refers to directions parallel to the plane of the live top surface of the microelectronic device and the term "vertical" is understood to refer to directions perpendicular to the plane of the live top surface of the microelectronic device.

[0010] For purposes of this disclosure, the term “conductive” should be interpreted as “electrically conductive.” The term “conductive” refers to materials and structures that are capable of supporting a steady electrical current, ie, direct current (DC).

[0011] The microelectronic device is formed in and on a substrate having a semiconductor material. The microelectronic device includes buried capacitor cells below a top surface of the semiconductor material. The buried capacitor cells include a trench lining dielectric layer in each buried capacitor cell. The buried capacitor cells further include a conductive trench filling material on the trench lining dielectric layer in each buried capacitor cell.

[0012] The microelectronic device may have a deep trench adjacent to the array of buried capacitor cells, the deep trench providing contact to the substrate.For purposes of this disclosure, the term deep trench is a trench that is deeper in the semiconductor material than the field oxide.

[0013] The electrical component is above the buried trench capacitor array through which the buried capacitor is integrated. In one example, the electrical component is a transistor, such as a laterally diffused MOS transistor (LDMOS) transistor, a drain extended metal oxide semiconductor (DEMOS) transistor, a bipolar junction transistor, a junction field effect transistor, a gated bipolar, a gated unipolar semiconductor device, or an insulated gate bipolar transistor (IGBT). In other examples, as examples, the electronic component is a silicon controlled rectifier (SCR), a metal oxide semiconductor (MOS) triggered SCR, a MOS controlled gate fluid, a gated diode, an amplifier, or a Schottky diode. Placing the buried capacitor in a microelectronic device below or near the electrical component of the microelectronic device is advantageous because physically positioning the buried trench capacitor array below or near the electrical component can reduce electromagnetic interference (EMI) of the microelectronic device. In addition, physically positioning the buried trench capacitor array below or at least partially below the electrical component provides silicon area savings.

[0014] Figure 1A to Figure 1K is a cross-section of an example microelectronic device 100 depicted in successive stages of an example formation method containing a buried trench capacitor array 170 as part of an integrated buried capacitor 172 that provides a capacitance source to an electrical component 174 .

[0015] See also Figure 1A , microelectronic device 100 includes substrate 102 having semiconductor material 103, referred to herein as silicon 103. In an alternative version of this example, substrate 102 may include a dielectric material, such as silicon dioxide or sapphire, to provide a silicon-on-insulator substrate. In this example, substrate 102 may include base wafer 104, such as a silicon wafer. Base wafer 104 may have a first conductivity type, which is shown as p-type in this example. A doped first epitaxial layer 106 is formed on base wafer 104. First epitaxial layer 106 primarily includes silicon, and may consist essentially of silicon and a dopant, such as boron. First epitaxial layer 106 has a first epitaxial top surface 107. In this example, first epitaxial layer 106 may have a first conductivity type, i.e., p-type. As an example, first epitaxial layer 106 may be 5 microns to 15 microns thick.

[0016] The buried layer 110 may be formed in the first epitaxial layer 106. The buried layer 110 has a second conductivity type opposite to the first conductivity type. In this example, the second conductivity type is n-type. The buried layer 110 may be formed by implanting a dopant of the second conductivity type (e.g., phosphorus, arsenic, or antimony) into the first epitaxial layer 106. The buried layer 110 may have an average dopant density greater than twice the average dopant density of the first epitaxial layer 106. The base wafer 104 may be annealed after the buried layer is implanted.

[0017] See also Figure 1B , a pad oxide layer 112 may be formed on the first epitaxial top surface 107 of the first epitaxial layer 106. As an example, the pad oxide layer 112 may mainly include silicon dioxide, may be formed by a thermal oxidation process or a thermal chemical vapor deposition (CVD) process, and may have a thickness of 50 nanometers to 200 nanometers. A nitride cap layer 114 may be formed on the pad oxide layer 112. For example, the nitride cap layer 114 may mainly include silicon nitride, may be formed by a low pressure chemical vapor deposition (LPCVD) furnace process, and may have a thickness of 100 nanometers to 500 nanometers. A hard mask layer 116 may be formed on the nitride cap layer 114. The hard mask layer 116 may mainly include silicon dioxide, may be formed by a plasma enhanced chemical vapor deposition (PECVD) process, and may have a thickness of 1 micrometer to 3 micrometers, depending on Figure 1C The depth of the subsequently formed buried capacitor trench 122 is shown in FIG. The pad oxide layer 112 can provide stress relief between the first epitaxial layer 106 and the combination of the nitride cap layer 114 and the hard mask layer 116. The nitride cap layer 114 can provide a stop layer for subsequent etching and planarization processes. The hard mask layer 116 can be Figure 1C 1 and 12. The hard mask is provided during a subsequent buried capacitor etching process 120 discussed in 1 to form a buried capacitor trench 122. Next, a buried capacitor trench mask 118 can be formed on the hard mask layer 116, having a buried capacitor trench mask opening 119 that exposes the hard mask layer 116 in the area for the buried capacitor trench 122. The buried capacitor trench mask 118 can include a photoresist, and can optionally include an anti-reflective material, such as a bottom anti-reflective coating (BARC). The buried capacitor trench mask 118 can be formed by a photolithography process.

[0018] See also Figure 1C , a buried capacitor etching process 120 is performed to form buried capacitor trenches 122 in the first epitaxial layer 106. The buried capacitor trenches 122 are formed for each desired capacitor cell, which forms a capacitor cell array. The buried capacitor etching process 120 may include multiple steps. In one embodiment, a hard mask etch may be first performed to remove the Figure 1BThe hard mask layer 116 exposed by the buried capacitor trench mask 118 may be removed, and then silicon etching may be performed to remove the nitride cap layer 114, the pad oxide layer 112, and the first epitaxial layer 106 in the area exposed by the hard mask layer 116 to form a buried capacitor trench 122. The buried capacitor trench 122 extends from the first epitaxial top surface 107 into the first epitaxial layer 106 and may extend into the base wafer 204. During the silicon etching, the buried capacitor trench mask 118 may also be partially or completely removed, leaving the hard mask layer 116 to prevent areas outside the buried capacitor trench 122 from being etched. Figure 1C The buried capacitor etch process 120 is depicted when complete, and the buried capacitor trench mask 118 has been removed by a subsequent buried capacitor trench etch clean process (not specifically shown). The organic polymer in the buried capacitor trench mask 118 may be removed using an oxygen plasma, followed by a series of wet etching processes including an aqueous mixture of sulfuric acid and hydrogen peroxide, an aqueous mixture of ammonium hydroxide and hydrogen peroxide, and an aqueous mixture of hydrochloric acid and hydrogen peroxide.

[0019] The buried capacitor deep well 108 may be formed in the first epitaxial layer 106, extending beyond the bottom edge of the buried layer 110 along the edge of the buried capacitor trench 122. The buried capacitor deep well 108 may be formed by implanting a second conductivity type dopant, such as phosphorus, using an angled implant to implant the dopant beyond the buried layer 110 into the first epitaxial layer 106 along the edge of the buried capacitor trench 122, followed by a thermal drive to diffuse and activate the implanted dopant. The buried capacitor deep well 108 may have an average concentration of the second conductivity type dopant that is 2 to 10 times greater than the average concentration of the first conductivity type dopant in the first epitaxial layer 106 outside the buried capacitor deep well 108. The angled implant may provide an improved implant profile by implanting through the walls of the buried capacitor trench 122.

[0020] See also Figure 1D , a buried capacitor trench liner dielectric layer 124, referred to herein as a trench liner dielectric layer 124, is formed in the buried capacitor trench 122, thereby contacting the first epitaxial layer 106 and the base wafer 104 as well as the buried capacitor deep well 108 and the buried layer 110. The trench liner dielectric layer 124 may extend over the hard mask layer 116, the nitride cap layer 114, and the pad oxide layer 112. The trench liner dielectric layer 124 may include a single layer of silicon nitride compound or silicon dioxide compound, or may include multiple layers of silicon nitride compound, silicon dioxide compound, or other dielectric materials. After the formation of the trench liner dielectric layer 124, a trench liner dielectric layer etching process (not specifically shown) is used to form a trench liner gap 125 through the bottom of the trench liner dielectric layer 124, thereby exposing the base wafer 104.

[0021] See also Figure 1E , a trench filling material 126 is formed on the trench lining dielectric layer 124 in the buried capacitor trench 122. The trench filling material 126 is conductive. The trench filling material 126 mainly includes silicon and can be implemented as polycrystalline silicon (polysilicon), which is commonly referred to as polysilicon. Alternatively, the trench filling material 126 can be implemented as amorphous silicon or semi-amorphous silicon. The trench filling material 126 can have a first conductivity type, which is p-type in this example. The trench filling material 126 can have a 5×10 18 cm -3 and 1×10 20 cm -3 The average dopant concentration of 100% to provide a low equivalent resistance for the buried trench capacitor array 170. The trench fill material 126 may be formed by thermal decomposition of a silicon-containing reagent gas including a doped polysilicon reagent 127. The trench fill material 126 fills the buried capacitor trenches 122 and may extend outside the buried capacitor trenches 122.

[0022] See also Figure 1F , the trench filling material 126 and the trench lining dielectric layer 124 are removed from the outside of the buried capacitor trench 122. The trench filling material 126 and the trench lining dielectric layer 124 may be removed by a planarization process such as a chemical mechanical polishing (CMP) process 128, such as Figure 1F Alternatively, the trench filling material 126 and the trench lining dielectric layer 124 may be removed by an etch back process. The process of removing the trench filling material 126 and the trench lining dielectric layer 124 outside the buried capacitor trench 122 leaves the trench filling material 126 on the trench lining dielectric layer 124 in the buried capacitor trench 122. The process of removing the trench filling material 126 and the trench lining dielectric layer 124 may leave the nitride cap layer 114 and the pad oxide layer 112 on the first epitaxial top surface 107 of the first epitaxial layer 106. The nitride cap layer 114 may be Figure 1G The subsequent polysilicon oxidation process 129 shown in FIG. 1 provides a selective template layer.

[0023] See also Figure 1G The polysilicon oxidation process 129 is used to form a buried capacitor silicon dioxide cap 130 that provides a dielectric barrier over the trench fill material 126 of the buried trench capacitor array 170. The polysilicon oxidation process 129 may use oxygen or oxygen and steam at high temperature to oxidize the trench fill material 126 at the first epitaxial top surface 107 of the first epitaxial layer 106. The nitride cap layer 114 prevents oxidation in regions other than the trench fill material 126.

[0024] See also Figure 1H , removing the nitride cap layer 114 and the pad oxide layer 112. The nitride cap layer 114 may be removed by a wet etching process using an aqueous solution of phosphoric acid at 140° C. to 170° C. The pad oxide layer 112 may be removed by a wet etching process using an aqueous solution of buffered hydrofluoric acid. The pad oxide layer 112 removal process is optimized to remove the pad oxide layer 112 but not to remove an excessive amount of the buried capacitor silicon dioxide cap 130 to an extent that would affect the dielectric integrity of the buried capacitor silicon dioxide cap 130. After removing the pad oxide layer 112, the buried capacitor silicon dioxide cap 130 is continuous over the trench fill material 126.

[0025] See also Fig. 1I , an epitaxial silicon cap layer 132 is deposited on the buried capacitor silicon dioxide cap 130. The epitaxial silicon cap layer 132 has a first conductivity type, which is p-type in this example. As an example, the epitaxial silicon cap layer 132 may be 1 micron to 3 microns. The epitaxial silicon cap layer 132 may contain a concentration of 1×10 15 atoms / cm3 to 1×10 16 atoms / cm3 of a p-type dopant, such as boron.

[0026] See also Figure 1J , forming a top epitaxial silicon 136 layer doped with a first conductivity type (e.g., p-type) and an integrated deep trench 134. After the deposition of the epitaxial silicon cap layer 132, the top epitaxial silicon 136 layer is deposited. The top epitaxial silicon 136 layer has a top epitaxial silicon top surface 137. As an example, the top epitaxial silicon 136 layer may contain a concentration of 1×10 15 atoms / cm3 to 1×10 16 The top epitaxial silicon 136 layer may be formed by forming a p-type dopant such as boron at a concentration of 100 atoms / cm3. As an example, the thickness of the top epitaxial silicon 136 layer may be between 5 microns and 15 microns. After the formation of the top epitaxial silicon 136 layer, patterning and implantation steps are used to form a deep trench deep well region 138. The deep trench deep well region 138 has a second conductivity type (e.g., n-type). Alternatively, the deep trench deep well region 138 may be formed after the formation of the integrated deep trench 134.

[0027] The integrated deep trench 134 forms an electrical connection from the top epitaxial silicon top surface 137 of the microelectronic device 100 to the base wafer 104. The formation of the integrated deep trench 134 consists of an integrated deep trench hard mask layer formation step, a photolithography patterning step, a plasma etching step, and a cleaning step (not specifically shown), which form the integrated deep trench 134.

[0028] After the formation of the deep trench 140, a deep trench liner 142 is deposited. The deep trench liner 142 is a dielectric layer. As an example, the deep trench liner 142 may be 50A to 300A. The deep trench liner 142 may be a single layer or multiple layers of dielectric material, such as silicon nitride, silicon oxynitride, and silicon dioxide. After the deposition of the deep trench liner 142, a deep trench liner etch process is used to create a deep trench liner gap 145, which provides a conductive path between a subsequently deposited conductive deep trench polysilicon filler 146 and the base wafer 104. After the formation of the deep trench liner gap 145, a polysilicon deposition process is used to form a conductive deep trench polysilicon filler 146 on the deep trench liner 142. As an example, the conductive deep trench polysilicon filler 146 is p-type doped with a dopant such as boron. The conductive deep trench polysilicon filling 146 and the deep trench liner 142 outside the deep trench 140 are then removed by a CMP process (not specifically shown).

[0029] See also Figure 1K , showing the remaining process steps necessary to complete the formation of the integrated deep trench 134 and the formation of the electrical component 174 (CMOS transistor in this example). The buried capacitor array 170 or a portion of the buried capacitor array 170 may be below the electrical component 174. The well 150 is implanted to provide electrical contact with the deep trench deep well region 138 of the integrated deep trench 134, the integrated buried capacitor 172, and the buried trench capacitor array 170. The field oxide 148 is formed in a series of steps consisting of patterning, etching, field oxide fill steps, and CMP steps (none of which is specifically shown). The field oxide 148 provides isolation for the electrical component 174 and provides electrical isolation for the integrated deep trench 134. Figure 1K The remaining components of the CMOS transistor of the example device shown in 100 consist of a gate oxide 152 on the top epitaxial silicon top surface 137 and a gate electrode material 154 on the gate oxide 152, which forms a transistor gate electrode 156. The transistor includes a halo implant region 158 and a source / drain implant region 160. Sidewalls 162 are formed on the lateral surfaces of the gate electrode 157. A metal silicide 159 may be formed on the exposed silicon surface on the top epitaxial silicon top surface 137 of silicon. A pre-metal dielectric (PMD) 164 is formed over the top epitaxial silicon top surface 137 of the microelectronic device 100. Contacts 165 and metallization 166 are formed to provide electrical contact between a first buried trench capacitor terminal 176 of the integrated buried capacitor 172, a second buried trench capacitor terminal 178 of the integrated buried capacitor 172, and the electrical component 174.

[0030] First buried trench capacitor terminal 176 provides electrical connection through integrated deep trench 134, through substrate 102 to conductive buried capacitor trench fill material 126. Second buried trench capacitor terminal 178 provides electrical connection through well 150 and deep trench well region 138 to buried trench capacitor buried capacitor deep well 108.

[0031] The microelectronic device 100 can be considered to consist of three different regions. The first region is the buried trench capacitor array 170. The second region is the integrated buried capacitor 172 including the buried trench capacitor array 170 and the integrated deep trench 134. The third region is the electrical component 174, in this example a CMOS transistor.

[0032] FIG. 2A to FIG. 2I is a cross-section of an example microelectronic device 200 depicted in successive stages of an example formation method containing a buried trench capacitor array 270 as part of an integrated buried capacitor 272 that provides a capacitance source to an electrical component 274 .

[0033] See also Figure 2A , a microelectronic device 200 is formed in and on a substrate 202 having a semiconductor material 203, referred to herein as silicon 203. In this example, the substrate 202 may include a base wafer 204, such as a silicon wafer. In an alternative version of this example, the substrate 202 may include a dielectric material, such as silicon dioxide or sapphire, to provide a silicon-on-insulator substrate. The base wafer 204 may have a first conductivity type, which may be p-type in this example. A first epitaxial layer 206 is formed on the base wafer 204. The first epitaxial layer 206 primarily includes silicon and may consist essentially of silicon and a dopant, such as boron. The first epitaxial layer 206 has a first epitaxial top surface 207. In this example, the first epitaxial layer 206 may have a first conductivity type, i.e., p-type. As an example, the first epitaxial layer 206 may be 5 microns to 15 microns thick.

[0034] A buried layer 210 may be formed in the first epitaxial layer 206. The buried layer 210 has a second conductivity type opposite to the first conductivity type. In this example, the second conductivity type is n-type. The buried layer 210 may be formed by implanting a dopant of the second conductivity type (e.g., phosphorus, arsenic, or antimony) into the first epitaxial layer 206. The buried layer 210 may have an average dopant density greater than twice the average dopant density of the first epitaxial layer 206. The base wafer 204 may be annealed after the buried layer implantation.

[0035] See also Figure 2B, a pad oxide layer 212 may be formed on the first epitaxial top surface 207 of the first epitaxial layer 206. As an example, the pad oxide layer 212 may mainly include silicon dioxide, may be formed by a thermal oxidation process or a thermal chemical vapor deposition (CVD) process, and may have a thickness of 50 nanometers to 200 nanometers. A nitride cap layer 214 may be formed on the pad oxide layer 212. For example, the nitride cap layer 214 may mainly include silicon nitride, may be formed by a low pressure chemical vapor deposition (LPCVD) furnace process, and may have a thickness of 100 nanometers to 500 nanometers. A hard mask layer 216 may be formed on the nitride cap layer 214. The hard mask layer 216 may mainly include silicon dioxide, may be formed by a plasma enhanced chemical vapor deposition (PECVD) process, and may have a thickness of 1 micrometer to 3 micrometers, depending on Figure 1C The depth of the subsequently formed buried capacitor trench 222 is shown in FIG. The pad oxide layer 212 can provide stress relief between the first epitaxial layer 206 and the combination of the nitride cap layer 214 and the hard mask layer 216. The nitride cap layer 214 can provide a stop layer for subsequent etching and planarization processes. The hard mask layer 216 can be Figure 1C 2 to form the buried capacitor trench 122. Next, a buried capacitor trench mask 218 may be formed on the hard mask layer 216, having a buried capacitor trench mask opening 219 that exposes the hard mask layer 216 in the area for the buried capacitor trench 222. The buried capacitor trench mask 218 may include a photoresist, and may optionally include an anti-reflective material, such as a bottom anti-reflective coating (BARC). The buried capacitor trench mask 218 may be formed by a photolithography process.

[0036] See also Figure 2C , a buried capacitor etching process 220 is performed to form a buried capacitor trench 222 in the first epitaxial layer 206. The buried capacitor etching process 220 may include multiple steps. For example, in one embodiment, a hard mask etch may be first performed to remove the buried capacitor trench 222 formed by the first epitaxial layer 206. Figure 1B The hard mask layer 216 exposed by the buried capacitor trench mask 218 may be removed, and then silicon etching may be performed to remove the nitride cap layer 214, the pad oxide layer 212, and the first epitaxial layer 206 in the area exposed by the hard mask layer 216 to form a buried capacitor trench 222. The buried capacitor trench 222 extends from the first epitaxial top surface 207 into the first epitaxial layer 206 and may extend into the base wafer 204. During the silicon etching, the buried capacitor trench mask 218 may also be partially or completely removed, leaving the hard mask layer 216 to prevent areas outside the buried capacitor trench 222 from being etched. Figure 1CThe buried capacitor etch process 220 is depicted when complete, and the buried capacitor trench mask 218 has been removed by a subsequent buried capacitor trench etch clean process (not specifically shown). The organic polymer in the buried capacitor trench mask 218 may be removed using an oxygen plasma, followed by a series of wet etching processes including an aqueous mixture of sulfuric acid and hydrogen peroxide, an aqueous mixture of ammonium hydroxide and hydrogen peroxide, and an aqueous mixture of hydrochloric acid and hydrogen peroxide.

[0037] See also Figure 2D , a trench liner dielectric layer 224 is formed in the buried capacitor trench 222, thereby contacting the first epitaxial layer 206 and the base wafer 204. The trench liner dielectric layer 224 may extend over the hard mask layer 216, the nitride cap layer 214, and the pad oxide layer 212. The trench liner dielectric layer 224 may include a single layer of silicon nitride compound or silicon dioxide compound, or may include multiple layers of silicon nitride compound, silicon dioxide compound, or other dielectric materials.

[0038] See also Figure 2E , a conductive buried capacitor trench fill material 226 is formed in the buried capacitor trench 222 on the trench liner dielectric layer 224. The conductive buried capacitor trench fill material 226 mainly includes silicon and can be implemented as polycrystalline silicon (polysilicon), commonly referred to as polysilicon. Alternatively, the conductive buried capacitor trench fill material 226 can be implemented as amorphous silicon or semi-amorphous silicon. The conductive buried capacitor trench fill material 226 can have a second conductivity type, which is n-type in this example. The conductive buried capacitor trench fill material 226 can have a 5×10 18 cm -3 and 1×10 20 cm -3 The average dopant concentration of 200 μm / s is provided to provide a low equivalent resistance for the buried trench capacitor array 270. The conductive buried capacitor trench filling material 226 may be formed by thermal decomposition of a silicon-containing reagent gas including a doped polysilicon reagent 227. The conductive buried capacitor trench filling material 226 fills the buried capacitor trenches 222 and may extend outside the buried capacitor trenches 222.

[0039] See also Figure 2F , the conductive buried capacitor trench filling material 226 and the trench lining dielectric layer 224 are removed from the outside of the buried capacitor trench 222. The conductive buried capacitor trench filling material 226 and the trench lining dielectric layer 224 may be removed by a planarization process, such as a chemical mechanical polishing (CMP) process 228, as shown in FIG. Figure 1F. Alternatively, the conductive buried capacitor trench filling material 226 and the trench lining dielectric layer 224 may be removed by an etch-back process. The process of removing the conductive buried capacitor trench filling material 226 and the trench lining dielectric layer 224 outside the buried capacitor trench 222 leaves the conductive buried capacitor trench filling material 226 on the trench lining dielectric layer 224 in the buried capacitor trench 222. The process of removing the conductive buried capacitor trench filling material 226 and the trench lining dielectric layer 224 may leave the nitride capping layer 214 and the pad oxide layer 212 on the top surface 207 of the first epitaxial layer 206. The nitride capping layer 214 may provide a stop layer for the CMP process 228 or the etch-back process. The nitride capping layer 214 and the pad oxide layer 212 are then removed (not specifically shown). The nitride cap layer 214 may be removed by a wet etching process using an aqueous solution of phosphoric acid at 140° C. to 170° C. The pad oxide layer 212 may be removed by a wet etching process using an aqueous solution of buffered hydrofluoric acid.

[0040] See also Figure 2G , an n-type epitaxial silicon cap layer 232 is deposited on the first epitaxial top surface 207 and is in electrical contact with the conductive buried capacitor trench fill material 226. As an example, the n-type epitaxial silicon cap layer 232 may be 1 micron to 3 microns. The n-type epitaxial silicon cap layer 232 may contain a concentration of 1×10 15 atoms / cm3 to 1×10 16 atoms / cm3 of an n-type dopant such as arsenic or phosphorus.

[0041] See also Figure 2H , forming a top epitaxial silicon 236 layer with p-type doping and an integrated deep trench 234. As an example, the top epitaxial silicon 136 layer may contain a concentration of 1×10 15 atoms / cm3 to 1×10 16 The top epitaxial silicon 236 layer has a top epitaxial silicon top surface 237. As an example, the thickness of the top epitaxial silicon 236 layer can be between 5 microns and 15 microns. An electrical connection is formed from the top epitaxial silicon top surface 237 of the microelectronic device to the base wafer 204 through the integrated deep trench 234. The formation of the integrated deep trench 234 begins with a patterning and implantation step to form a deep trench deep n-type well 238, followed by a patterning and etching step to define a deep trench 240.

[0042] After the formation of the deep trench 240, a deep trench liner 242 is deposited. The deep trench liner 242 is a dielectric layer. As an example, the deep trench liner 242 may be 50A to 300A. The deep trench liner 242 may be a single layer or multiple layers of dielectric material, such as silicon nitride, silicon oxynitride, and silicon dioxide. After the deposition of the deep trench liner 242, a deep trench liner etch process is used to create a deep trench liner gap 245, which provides a conductive path between a subsequently deposited conductive deep trench polysilicon filler 246 and the base wafer 204. After the deep trench liner gap 245 is formed, a polysilicon deposition process is used to form a conductive deep trench polysilicon filler 246 on the deep trench liner 242. As an example, the conductive deep trench polysilicon filler 246 is n-type doped with a dopant such as phosphorus. The conductive deep trench polysilicon filling 246 and the deep trench liner 242 outside the deep trench 240 are then removed by a CMP process.

[0043] See also Fig.2I , showing the remaining process steps necessary to complete the formation of the integrated deep trench 234 and the formation of the electrical component 274 (CMOS transistor in this example). Well 250 is implanted to provide electrical contact with the deep n-type implant 238 of the integrated deep trench 234, with the integrated buried capacitor 272 and the buried trench capacitor array 270. Field oxide 248 is formed in a series of steps consisting of patterning, etching, field oxide fill steps and CMP steps. Field oxide 248 provides isolation for the electrical component 274 and provides electrical isolation for the integrated deep trench 234. Fig.2I The remaining components of the electrical component 274 of the example device shown in 200 consist of a gate oxide 252 on the top epitaxial silicon top surface 237 and a gate electrode material 254 (e.g., polysilicon) on the gate oxide 252, which forms a transistor gate electrode 256. The electrical component 274 includes a halo implant region 258 and a source / drain implant region 260. Sidewalls 262 are formed on the lateral surfaces of the transistor gate electrode 256. A metal silicide 259 may be formed on the exposed silicon surface on the top epitaxial silicon top surface 237 of silicon. A pre-metal dielectric (PMD) 264 is formed over the top epitaxial silicon top surface 237 of the microelectronic device 200. Contacts 265 and metallization 266 are formed to provide electrical contact between a first buried trench capacitor terminal 276 of the integrated buried capacitor 272, a second buried trench capacitor terminal 278 of the integrated buried capacitor 272, and the electrical component 274.

[0044] A first buried trench capacitor terminal 276 of the integrated buried capacitor 272 provides an electrical connection to the base wafer 204 through the integrated deep trench 234 and the substrate 202. A second buried trench capacitor terminal 278 of the integrated buried capacitor 272 provides an electrical connection to the conductive buried capacitor trench fill material 226 through the well 250 and the n-type epitaxial silicon cap layer 232.

[0045] The microelectronic device 200 can be considered to consist of three different regions. The first region is a buried trench capacitor array 270. The second region is an integrated buried capacitor 272 including the buried trench capacitor array 270 and the integrated deep trench 234. The third region is an electrical component 274, which in this example is a CMOS transistor, but as examples may be a laterally diffused MOS transistor (LDMOS) transistor, a drain extended metal oxide semiconductor (DEMOS) transistor, a bipolar junction transistor, a junction field effect transistor, a gated bipolar, a gated unipolar semiconductor device, an insulated gate bipolar transistor (IGBT), a silicon controlled rectifier (SCR), a metal oxide semiconductor (MOS) triggered SCR, a MOS controlled gate fluid, a gated diode, a resistor, an amplifier, and a Schottky diode.

[0046] See also Figure 3 , showing the highlighted Figure 1K 300, which includes a buried trench capacitor array 370, an integrated buried capacitor 372, and an electrical component 374 (a CMOS transistor in this example). All components are in silicon 303. Trench fill material 326, trench liner dielectric layer 324, and buried capacitor deep well 308 form buried trench capacitor array 370. Buried trench capacitor array 370 is below electrical component 374. It is advantageous to place buried trench capacitor array 370 below electrical component 374 to achieve area savings and reduce electromagnetic interference (EMI) of microelectronic device 300. Contacts 365 are shown, but metallization is not shown for clarity. The components of the deep trench consist of conductive deep trench polysilicon fill 346, deep trench liner 342, and deep trench deep well 338. Well 350 contacts deep well 338 to provide an electrical path to buried trench capacitor array 370. The electrical component 374 , in this example a CMOS transistor, consists of the gate electrode material 354 , source and drain regions 360 which are surrounded by the isolation region 348 .

[0047] Although various embodiments of the present disclosure have been described above, it should be understood that they are presented only as examples and not as limitations. Many changes may be made to the disclosed embodiments according to the disclosure herein without departing from the spirit or scope of the present disclosure. Therefore, the breadth and scope of the present invention should not be limited by any of the embodiments described above. Instead, the scope of the present disclosure should be defined according to the attached claims and their equivalents.

Claims

1. A microelectronic device comprising: a substrate wafer having a silicon layer; A first epitaxial layer on the base wafer, the first epitaxial layer having a first epitaxial layer top surface; a buried trench capacitor extending into the first epitaxial layer; as well as A second epitaxial layer is above the buried trench capacitor.

2. The microelectronic device of claim 1 , wherein the buried trench capacitor comprises: a buried trench capacitor array beneath the second epitaxial layer, the buried trench capacitor array comprising; a buried capacitor trench in the first epitaxial layer and in the base wafer; a buried capacitor well of a first conductivity type surrounding the buried capacitor trench; a trench liner dielectric in said buried capacitor trench; a trench liner gap extending through the trench liner dielectric to the base wafer; a trench fill material on the trench liner dielectric in the buried capacitor trench, the trench fill material being electrically conductive and having a second conductivity type opposite to the first conductivity type; as well as A buried trench capacitor silicon dioxide cap is on the trench fill material.

3. The microelectronic device of claim 2, wherein the buried trench capacitor further comprises: a first buried trench capacitor terminal contacting the base wafer; as well as The second buried trench capacitor terminal, It contacts the buried capacitor deep well around the buried capacitor trench.

4. The microelectronic device of claim 2, further comprising an epitaxial silicon cap layer of the second conductivity type on the buried trench capacitor silicon dioxide cap.

5. The microelectronic device of claim 2, further comprising a buried layer of the first conductivity type in the first epitaxial layer.

6. The microelectronic device of claim 2, further comprising an electrical component at a surface of the second epitaxial layer and extending at least partially over the buried trench capacitor array.

7. The microelectronic device of claim 2, further comprising an integrated deep trench containing a deep trench liner gap, the integrated deep trench providing an electrical connection between a first buried trench capacitor terminal and the trench fill material of the buried trench capacitor array.

8. The microelectronic device of claim 2, further comprising a deep trench n-type well providing an electrical connection between a second buried trench capacitor terminal and the buried capacitor wells of the buried trench capacitor array.

9. A microelectronic device comprising a buried trench capacitor, the microelectronic device comprising: a substrate wafer having a silicon layer; A first epitaxial layer on the base wafer, the first epitaxial layer having a first epitaxial layer top surface; as well as A buried trench capacitor having: A buried trench capacitor cell array, in the first epitaxial layer, each buried trench capacitor cell comprising; a buried capacitor trench in the first epitaxial layer and in the base wafer; a buried capacitor trench liner dielectric in said buried capacitor trench; an n-type conductive buried capacitor trench filling material on the buried capacitor trench lining dielectric; an n-type epitaxial silicon cap layer on top of the buried trench capacitor; a first buried trench capacitor terminal contacting the base wafer; a second buried trench capacitor terminal contacting the n-type epitaxial silicon cap layer; as well as A second p-type epitaxial layer is on the n-type epitaxial silicon cap layer.

10. The microelectronic device of claim 9, further comprising an electrical component extending at least partially over the array of buried trench capacitor cells.

11. The microelectronic device of claim 9, further comprising an integrated deep trench containing a deep trench liner gap, the integrated deep trench providing an electrical connection between a first buried trench capacitor terminal and the n-type conductive buried capacitor trench fill material of the buried trench capacitor.

12. The microelectronic device of claim 9, further comprising a deep trench n-type deep well providing an electrical connection between a second buried trench capacitor terminal and the n-type epitaxial silicon cap layer.

13. A method of forming a microelectronic device, comprising: forming a first epitaxial layer on a base wafer, the first epitaxial layer having a top surface; forming a buried trench capacitor extending into the first epitaxial layer; and A second epitaxial layer is formed over the buried trench capacitor.

14. The method of claim 13, wherein the buried trench capacitor comprises; forming a buried trench capacitor array below the second epitaxial layer, comprising; forming a buried capacitor trench in the first epitaxial layer and in the base wafer; forming a deep well of a first conductivity type around the buried capacitor trench; forming a trench liner dielectric in the buried capacitor trench; forming a trench liner gap through the trench liner dielectric to the base wafer; forming a trench fill material on the trench liner dielectric in the buried capacitor trench, the trench fill material being electrically conductive and having a second conductivity type; as well as A buried trench capacitor silicon dioxide cap is formed on the trench fill material.

15. The method of claim 14, wherein the buried trench capacitor comprises; forming a first buried trench capacitor terminal contacting the base wafer; and A second buried trench capacitor terminal is formed contacting the deep well around the buried trench capacitor.

16. The method of claim 13, wherein a p-type epitaxial silicon cap layer is formed on the buried trench capacitor silicon dioxide cap. The method of claim 13 , wherein an n-type buried layer is formed in the first epitaxial layer.

18. The method of claim 13, wherein an electrical component of the microelectronic device is in electrical contact in parallel with an array of buried trench capacitors.

19. The method of claim 13, wherein the integrated deep trench contains a deep trench liner gap that provides electrical connection between the first buried trench capacitor terminal and a trench fill material of the buried trench capacitor array.

20. The method of claim 13, wherein the deep trench n-type deep well provides electrical connection between the second buried trench capacitor terminal and the deep well of the buried trench capacitor array.

21. A method of forming a microelectronic device having a buried capacitor, comprising: forming a first epitaxial layer on a base wafer of a substrate; forming a buried trench capacitor array, comprising; forming a buried capacitor trench in the first epitaxial layer and in the base wafer; forming a buried capacitor trench liner dielectric on the buried capacitor trench; forming an n-type conductive buried capacitor trench filling material on the buried capacitor trench liner dielectric; as well as forming a second p-type epitaxial layer on the buried trench capacitor array; forming a first buried trench capacitor terminal contacting the base wafer; as well as A second buried trench capacitor terminal is formed contacting a deep well surrounding the buried capacitor trench.

22. The method of claim 21, wherein a deep trench n-type deep well provides electrical connection between a second buried trench capacitor terminal and the first epitaxial layer of the buried trench capacitor array.

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