Folding series switch

Abstract

A chip includes: a first active region; a first gate extending over the first active region in a first direction, where the first gate corresponds to a first transistor; and a second gate extending over the first active region in the first direction, where the second gate corresponds to a second transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to non-provisional patent application serial number 17 / 939,392 filed in the U.S. Patent Office on September 7, 2022, the entire contents of which are incorporated herein as if fully set forth below and for all applicable purposes. background Technical Field

[0004] Aspects of the present disclosure relate generally to chip layout, and more particularly to the layout of transistors on a chip. Background Art

[0005] A large number of transistors can be integrated on a chip (i.e., a die). In order to integrate transistors on a chip, a chip layout is generated to specify the geometry and placement of transistors on the chip. The chip layout can also specify metal wiring on the chip. The metal wiring can interconnect the transistors, couple the transistors to power rails and / or ground, etc. Summary of the invention

[0006] The following content presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or important elements of all implementations, nor is it intended to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

[0007] One aspect relates to a chip. The chip includes: a first active region; a first gate extending in a first direction over the first active region, wherein the first gate corresponds to a first transistor; and a second gate extending in the first direction over the first active region, wherein the second gate corresponds to a second transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A side view of an example of a chip including metal layers and vias according to certain aspects of the present disclosure is shown.

[0009] Figure 2A A side view of an example of a fin field effect transistor (FinFET) according to certain aspects of the present disclosure is shown.

[0010] Figure 2B A perspective view of a FinFET according to certain aspects of the present disclosure is shown.

[0011] Figure 3AA top view of an example of a multi-gate transistor according to certain aspects of the present disclosure is shown.

[0012] Figure 3B An example of an interconnector for a multi-gate transistor according to certain aspects of the present disclosure is shown.

[0013] Figure 4 An example of a circuit is shown to illustrate layout techniques in accordance with certain aspects of the present disclosure.

[0014] Figure 5 An example of a layout with source / drain sharing according to certain aspects of the present disclosure is shown.

[0015] Figure 6 shows a repetitive Figure 5 An example of an exemplary layout in .

[0016] Fig. 7A An example of a layout of a transistor with an odd number of gates according to certain aspects of the present disclosure is shown.

[0017] Figure 7B An odd number of gates prevents the Figure 7B An example of a layout that repeats horizontally.

[0018] Figure 8 shows an example of the effect of process variation on gate length according to certain aspects of the present disclosure;

[0019] Fig.9A Examples of fins according to certain aspects of the present disclosure are shown.

[0020] Fig. 9B Examples of source / drain contacts according to certain aspects of the present disclosure are shown.

[0021] Fig.10 Examples of gate interconnects according to certain aspects of the present disclosure are shown.

[0022] Fig.11 An example of a layout having a gate ratio of 2:6 between a first transistor and a second transistor in accordance with certain aspects of the present disclosure is shown.

[0023] Fig.12 An example of a layout having a gate ratio of 6:2 between a first transistor and a second transistor in accordance with certain aspects of the present disclosure is shown.

[0024] Fig.13 An example of a layout having a 4:4 gate ratio between a first transistor and a second transistor in accordance with certain aspects of the present disclosure is shown.

[0025] Fig.14 An example of a layout having a gate ratio of 4:6 between a first transistor and a second transistor in accordance with certain aspects of the present disclosure is shown.

[0026] Fig.15 An example of a layout having a gate ratio of 4:8 between a first transistor and a second transistor in accordance with certain aspects of the present disclosure is shown.

[0027] Fig.16 According to certain aspects of the present disclosure, Figure 4 The circuit in is used as an example for power switching. DETAILED DESCRIPTION

[0028] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. In order to provide a comprehensive understanding of the various concepts, the specific embodiments include specific details. However, it is apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, in order to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0029] Figure 1 1 shows a side view of an example of a chip 100 (ie, a die) according to certain aspects. The chip 100 may include a number of devices (eg, transistors) integrated on the chip 100. In this regard, Figure 1 An example of a transistor 110 integrated on a chip 100 is shown. Figure 1 One transistor 110 is shown in FIG. 1 , but it should be understood that chip 100 may include many transistors.

[0030] exist Figure 1 In the example shown, transistor 110 includes a gate 115, a first source / drain 120-1, and a second source / drain 120-2. As used herein, the term "source / drain" means a source, a drain, or both. Gate 115 is formed over a channel between first source / drain 120-1 and second source / drain 120-2. Transistor 110 may also include a thin gate oxide (not shown) between the gate and the channel. Gate 115 may be a polysilicon gate, a metal gate, or another type of gate. Figure 1 In the example shown, transistor 110 is depicted as a planar transistor. However, it should be understood that transistor 110 may be implemented using a fin field effect transistor (FinFET), as described below. Figure 2A and Figure 2B An example of the FinFET will be discussed.

[0031] The chip 100 may further include a first source / drain contact 130-1 formed on the first source / drain 120-1 and a second source / drain contact 130-2 formed on the second source / drain 120-2. The source / drain contacts 130-1 and 130-2 may be formed from a source / drain contact layer ( Figure 1 is marked as "MD" in the Figure 1 In the example of FIG. 1 , the source / drain contact layer is labeled “MD”, but it should be understood that the source / drain contact layer may also be labeled “CA” or another label.

[0032] The chip 100 may further include a gate contact 135 formed on the gate 115. The gate contact 135 may be formed by forming a gate contact layer ( Figure 1 is marked as "MP" in the Figure 1 The gate contact layer is labeled as “MP” in the example of FIG. 1 , but it should be understood that the gate contact layer may also be labeled with another label.

[0033] Chip 100 may also include a stack of metal layers 150. Metal layers 150 are patterned (e.g., using photolithography and etching) to provide metal wiring for transistor 110 and other transistors on chip 100. Metal wiring may be used, for example, to interconnect transistors on chip 100, couple transistors to power rails and / or ground, etc. Metal layers 150 may also be referred to as metallization layers or another term.

[0034] exist Figure 1 In the example in FIG. 1 , the bottom metal layer may be designated as metal layer M0 (also referred to as metal 0), the metal layer immediately above metal layer M0 may be designated as metal layer M1 (also referred to as metal 1), the metal layer immediately above metal layer M1 may be designated as metal layer M2 (also referred to as metal 2), the metal layer immediately above metal layer M2 may be designated as metal layer M3 (also referred to as metal 3), and so on. Although for ease of illustration, the bottom metal layer may be designated as metal layer M0 (also referred to as metal 0), the metal layer immediately above metal layer M0 may be designated as metal layer M1 (also referred to as metal 1), and so on. Figure 1 , it should be understood that chip 100 may include additional metal layers (e.g., five or more metal layers including metal layer M4, metal layer M5, etc.). It should be understood that the present disclosure is not limited to the nomenclature in which the bottom-most metal layer is designated as metal layer M0. For example, in another example, the bottom-most metal layer may be designated as metal layer M1 instead of metal layer M0.

[0035] Chip 100 also includes vias 160 that provide electrical coupling between metal layers 150 and between metal layer M0 and contacts 130-1, 130-2, and 135. In this example, vias VD provide electrical coupling between source / drain contacts 130-1 and 130-2 and metal layer M0, and vias VG provide electrical coupling between gate contact 135 and metal layer M0. Via V0 provides electrical coupling between metal layer M0 and metal layer M1, via V1 provides electrical coupling between metal layer M1 and metal layer M2, and via V2 provides electrical coupling between metal layer M2 and metal layer M3.

[0036] Figure 2A A side view of an example in which transistor 110 is implemented using a FinFET is shown and Figure 2B 1 and 2. In this example, transistor 110 includes a gate 115 and source / drain contacts 130-1 and 130-2 (in Figure 2B ) and fins 210-1 to 210-4 extending orthogonally. Figure 2B In the example shown in FIG. 1 , four fins 210 - 1 to 210 - 4 are shown, but it should be understood that the transistor 110 may include a different number of fins. In addition, although the fins 210 - 1 to 210 - 4 are shown as having a rectangular cross-section, it should be understood that the fins may have other cross-sectional shapes (e.g., a tapered cross-section). Note that in FIG. Figure 2B The metal layer 150, the via 160 and the gate contact 135 are not explicitly shown.

[0037] In this example, the gate 115 is formed on the first portion 215 of the fins 210-1 to 210-4. The gate 115 may wrap around three or more sides of each fin (e.g., the top side and two opposing sidewalls of each fin). In this example, the transistor 110 may also include a thin dielectric layer (not shown) interposed between the fins 210-1 to 210-4 and the gate 115. Figure 2A As shown, a gate contact 135 may be formed on the gate 115 , and a via VG may electrically couple the gate contact 135 to the metal layer M0 .

[0038] A portion of the fins 210-1 to 210-4 extending from a first side 222-1 of the gate 115 forms a first source / drain 120-1, and a portion of the fins 210-1 to 210-4 extending from a second side 222-2 of the gate 115 forms a second source / drain 120-2, wherein the first side 222-1 and the second side 222-2 are opposite sides of the gate 115. In this example, a first source / drain contact 130-1 is formed over the second portion 220-1 of the fins 210-1 to 210-4 on the first side 222-1 of the gate 115, and a second source / drain contact 130-2 is formed over the third portion 220-2 of the fins 210-1 to 210-4 on the second side 222-2 of the gate 115. Each of the source / drain contacts 130-1 to 130-2 may be made of a conductive material (eg, one or more metals). Figure 2A As shown, vias VD may electrically couple the source / drain contacts 130 - 1 to 130 - 2 to the metal layer M0 .

[0039] In certain aspects, transistor 110 may be a multi-gate transistor including multiple gates (also referred to as fingers).As used herein, a "multi-gate" transistor is a transistor including two or more gates. Figure 3A An example is shown in which the transistor 110 is implemented using a multi-gate transistor. In this example, the transistor 110 includes an active region 310 and a plurality of gates 115-1 to 115-4. The source / drain and channel of the transistor 110 are formed in the active region 310. For a FinFET process, the active region 310 includes a fin (e.g., Figure 3A ). The active region 310 may also be referred to as an active diffusion, an active area, an oxide diffusion (OD), or another term.

[0040] The gates 115-1 to 115-4 extend parallel to each other and are spaced apart from each other in a lateral direction 322. As used herein, a "lateral" direction is a direction parallel to the substrate of the chip 100 (ie, die). Figure 3A In the example of FIG. 1 , each of the gates 115-1 to 115-4 is elongated and extends over the active region 310 in a lateral direction 324, wherein the lateral direction 324 is perpendicular to the lateral direction 322. The portion of the active region 310 located below the gates 115-1 to 115-4 provides a channel for the transistor 110. Each of the gates 115-1 to 115-4 can be a polysilicon gate, a metal gate, or another type of gate. It should be understood that the transistor 110 is not limited to Figure 3A The number of gates shown is the same, and transistor 110 may have a different number of gates.

[0041] exist Figure 3A In the example of FIG. 1 , the active region 310 includes a first source / drain 330-1, a second source / drain 330-2, a third source / drain 330-3, a fourth source / drain 330-4, and a fifth source / drain 330-5, wherein the source / drains 330-1 to 330-5 are separated from each other by gates 115-1 to 115-4. Figure 3A Although not explicitly shown in FIG. 1 , it should be understood that source / drain contacts may be placed on each source / drain. For FinFET processes, the active region 310 includes fins (in Figure 3A ), wherein each fin is elongated and extends in a lateral direction 322 .

[0042] Figure 3B An example of a first interconnector 350 electrically coupling gates 115-1 to 115-4 to each other is shown. As used herein, an "interconnector" may be a structure that electrically couples two or more elements. The interconnector may include one or more contacts, one or more vias, and / or one or more metal lines formed by one or more of the metal layers 150. In this example, the first interconnector 350 may provide a gate terminal of the transistor 110.

[0043] exist Figure 3B In the example shown, the first interconnector 350 includes a metal line 352 and conductive paths 354-1 to 354-4. In this example, the metal line 352 extends on the gates 115-1 to 115-4 in the lateral direction 322. The metal line 352 can be formed from one of the metal layers 150 (e.g., using a photolithography process and an etching process). It should be understood that the width of the metal line 352 can be greater than Figure 3B Width shown.

[0044] Each of the conductive paths 354-1 to 354-4 may couple a corresponding one of the gates 115-1 to 115-4 to the metal line 352. Each of the conductive paths 354-1 to 354-4 may include a gate contact, one or more vias (e.g., vias VG), and / or one or more portions formed by one or more of the metal layers 150. Figure 3B , each of the conductive paths 354-1 to 354-4 is represented by an X. It should be understood that the first interconnector 350 is not limited to Figure 3B It should also be understood that the first interconnect 350 is not limited to Figure 3B Exemplary locations are shown, and the first interconnect 350 may be placed at various locations on the chip 100 (ie, die).

[0045] Figure 3BAlso shown is an example of a second interconnector 360 that electrically couples the first source / drain 330-1, the third source / drain 330-3, and the fifth source / drain 330-5 to each other. In this example, the second interconnector 360 includes a metal line 362 and conductive paths 364-1, 364-2, and 364-3. In this example, the metal line 362 extends in the lateral direction 322 and can be formed by one of the metal layers 150 (e.g., using a photolithography process and an etching process). It should be understood that the width of the metal line 362 can be greater than Figure 3B Width shown.

[0046] Each of the conductive paths 364-1, 364-2, and 364-3 may couple the metal line 362 to a corresponding one of the first source / drain 330-1, the third source / drain 330-3, and the fifth source / drain 330-5. Each of the conductive paths 364-1, 364-2, and 364-3 may include a source / drain contact, one or more vias (e.g., via VD), and / or one or more portions formed by one or more of the metal layers 150. Figure 3B In FIG. 1 , each of the conductive paths 364 - 1 , 364 - 2 and 364 - 3 is represented by an X. It should be understood that the second interconnector 360 is not limited to Figure 3B It should also be understood that the second interconnect 360 is not limited to Figure 3B Exemplary locations are shown, and the second interconnect 360 may be placed at various locations on the chip 100 (ie, die).

[0047] Figure 3B Also shown is an example of a third interconnector 370 that electrically couples the second source / drain 330-2 and the fourth source / drain 330-4 to each other. In this example, the third interconnector 370 includes a metal line 372 and conductive paths 374-1 and 374-2. In this example, the metal line 372 extends in the lateral direction 322 and can be formed by one of the metal layers 150 (e.g., using a photolithography process and an etching process). It should be understood that the width of the metal line 372 can be greater than Figure 3B Width shown.

[0048] Each of the conductive paths 374-1 and 374-2 may couple the metal line 362 to a respective one of the second source / drain 330-2 and the fourth source / drain 330-4. Each of the conductive paths 354-1 to 354-4 may include a source / drain contact, one or more vias (e.g., via VD), and / or one or more portions formed by one or more of the metal layers 150. Figure 3B , each of the conductive paths 374-1 and 374-2 is represented by an X. It should be understood that the third interconnector 370 is not limited to Figure 3B It should also be understood that the third interconnect 370 is not limited to Figure 3B The exemplary positions are shown, and the third interconnect 370 may be placed at various positions on the chip 100 (ie, die).

[0049] In certain aspects, the second interconnect 360 may provide a source terminal of the transistor 110 and the third interconnect 370 may provide a drain terminal of the transistor 110 , or vice versa.

[0050] As discussed above, chip 100 may include a large number of transistors. In order to integrate transistors on a chip, a chip layout is generated to specify the geometry and placement of transistors on the chip. The chip layout may also specify metal wiring on the chip. The metal wiring may interconnect transistors, couple transistors to power rails and / or ground, etc.

[0051] In previous chip layout methods, transistors were loosely organized by area with little consideration for sharing the source / drain between transistors. These layout methods cause large parasitic resistance between transistors, which degrades performance. The large resistance is caused by the metal wiring of the transistors, which increases over time as process nodes continue to scale down. Therefore, an area-efficient layout technique that reduces parasitic resistance is needed.

[0052] As discussed further below, aspects of the present disclosure provide area efficient layout techniques that use source / drain sharing between transistors to reduce wiring resistance between transistors.As used herein, "source / drain sharing" is when transistors share at least one source / drain.

[0053] It will be used below Figure 4 The exemplary circuit 410 shown in the circuit schematic diagram in FIG. 4 is used to describe layout techniques according to various aspects of the present disclosure. It should be understood that Figure 4 The circuit 410 in FIG. 4 is only used for the purpose of promoting a better understanding of the layout techniques according to various aspects of the present disclosure. Therefore, the layout techniques according to various aspects of the present disclosure are not limited to Figure 4 The exemplary circuit 410 is shown and may be broadly applicable to other circuits.

[0054] Figure 4 The exemplary circuit 410 shown may be part of a power multiplexer (e.g., an adaptive power multiplexer). The circuit 410 includes a first transistor A, a second transistor B, and a third transistor C. The first transistor A is located between a node X and a node Y, and the second transistor B and the third transistor C are each located between a node Y and a node Z. Note that a "node" may also be referred to as a "network" or another term. In Figure 4In the example of , the first transistor A is a p-type field effect transistor (PFET), the second transistor B is a PFET, and the third transistor C is an n-type field effect transistor (NFET). However, it should be understood that the present disclosure is not limited to this example.

[0055] In some aspects, the first transistor A and the second transistor B have the same transistor type (also referred to as channel type). This enables source / drain sharing between the first transistor A and the second transistor B, as discussed further below. Figure 4 In the example of , both the first transistor A and the second transistor B are p-type. However, it should be understood that in other embodiments, both the first transistor A and the second transistor B can be n-type. In this example, the third transistor C has a different transistor type (i.e., channel type) than the first transistor A and the second transistor B. For the example where the first transistor A and the second transistor B are p-type, the third transistor C is n-type.

[0056] exist Figure 4 In the example, the source terminal S of the first transistor A A is coupled to the node X, and the drain terminal D of the first transistor A A Coupled to node Y. The source terminal S of the second transistor B B is coupled to the node Y, and the drain terminal D of the second transistor B A Coupled to the node Z. The drain terminal D of the third transistor C C is coupled to the node Y, and the source terminal S of the third transistor C C Coupled to node Z.

[0057] In some aspects, each of the first transistor A, the second transistor B, and the third transistor C is implemented using a multi-gate transistor including respective gates (also referred to as fingers). Figure 4 The gate of the first transistor A is coupled to the gate terminal G of the first transistor A. A , the gate of the second transistor B is coupled to the gate terminal G of the second transistor B B , and the gate of the third transistor C is coupled to the gate terminal G of the third transistor C C .

[0058] Figure 5An exemplary layout 510 of the circuit 410 using layout techniques according to aspects of the present disclosure is shown. The layout 510 includes a first active region 512 and a second active region 530. Each active region may also be referred to as an oxide diffusion (OD) or another term. For FinFET processes, each of the active regions 512 and 530 may include a respective fin extending in a lateral direction 522 (in Figure 5 ). In this example, the first transistor A shares the first active region 512 with the second transistor B. As discussed further below, the first active region 512 provides source / drain sharing between the first transistor A and the second transistor B.

[0059] The layout 510 also includes first gates 515-1 and 515-2 and second gates 520-1 and 520-2. The first gates 515-1 and 515-2 correspond to the first transistor A, and the second gates 520-1 and 520-2 correspond to the second transistor B. Each of the gates 515-1, 515-2, 520-1, and 520-2 is elongated and extends over the first active region 512 in a lateral direction 524. The first gates 515-1 and 515-2 may be connected to the first active region 512 by a first gate interconnector (at Figure 5 ) and are coupled to each other, and the second gates 520-1 and 520-2 may be coupled to each other through a second gate interconnector (not shown in Figure 5 Examples of gate interconnectors are discussed further below.

[0060] exist Figure 5 In the example of FIG. 1 , the first active region 512 includes a first source / drain 525-1, a second source / drain 525-2, a third source / drain 525-3, a fourth source / drain 525-4, and a fifth source / drain 525-5, wherein the source / drain 525-1 and 525-5 are separated by gates 515-1, 515-2, 520-1, and 520-2, as shown in FIG. Figure 5 In other words, each of the gates 515-1, 515-2, 520-1, and 520-2 is located between a corresponding pair of source / drains in the source / drain 525-1 to 525-5.

[0061] exist Figure 5, the letter (i.e., Z, Y, or X) in each source / drain indicates which node the source / drain is coupled to. In this example, the first source / drain 525-1 and the fifth source / drain 525-5 are coupled to node Z (e.g., through an interconnector), the second source / drain 525-2 and the fourth source / drain 525-4 are coupled to node Y (e.g., through an interconnector), and the third source / drain 525-3 is coupled to node X (e.g., through an interconnector). However, it should be understood that the present disclosure is not limited to this example.

[0062] In this example, the second source / drain 525-2 is shared by the first transistor A and the second transistor B, wherein the second source / drain 525-2 is located between the first gate 515-1 and the second gate 520-1. The second source / drain 525-2 can serve as the drain of the first transistor A and as the source of the second transistor B. In addition, in this example, the fourth source / drain 525-4 is shared by the first transistor A and the second transistor B, wherein the fourth source / drain 525-4 is located between the first gate 515-2 and the second gate 520-2. The fourth source / drain 525-4 can serve as the drain of the first transistor A and as the source of the second transistor B. However, it should be understood that the present disclosure is not limited to this example.

[0063] Therefore, in this example, the second source / drain 525-2 and the fourth source / drain 525-4 provide source / drain sharing between the first transistor A and the second transistor B. The source / drain sharing between the first transistor A and the second transistor B can eliminate or reduce the need for metal wiring between the first transistor A and the second transistor B, which can eliminate or reduce the metal wiring resistance between the first transistor A and the second transistor B. This significantly reduces parasitic resistance compared to layout methods that do not use source / drain sharing.

[0064] exist Figure 5 In the example of FIG. 5 , the layout 510 also includes third gates 535-1 to 535-4 corresponding to the third transistor C. Each of the third gates 535-1 to 535-4 is elongated and extends over the second active region 530 in the lateral direction 524. The third gates 535-1 to 535-4 can be connected to the second active region 530 by a third gate interconnector (in Figure 5 ) are coupled to each other.

[0065] exist Figure 5 In the example of FIG. 5 , the second active region 530 includes source / drain electrodes 545-1 to 545-5 separated by third gate electrodes 535-1 and 535-5. In other words, each of the third gate electrodes 535-1 to 535-5 is located between a corresponding pair of source / drain electrodes in the source / drain electrodes 545-1 to 545-5. Figure 5In FIG. 1 , the letter in each source / drain (ie, Z or Y) indicates to which node the source / drain is coupled.

[0066] In some aspects, the source / drain 525-1 and 525-5 in the first active region 512 can be coupled to the source / drain 545-1 and 545-5 in the second active region 530 because the source / drain 525-1, 525-5, 545-1, and 545-5 are coupled to the node Z. In this regard, Figure 5 An example of a metal wiring 550-1 coupling source / drain 525-1 and 545-1 and a metal wiring 550-2 coupling source / drain 525-5 and 545-5 is shown. Metal wirings 550-1 and 550-2 may be part of an interconnector coupling source / drain 525-1, 525-5, 545-1, and 545-5 to each other. The interconnector may include source / drain contacts formed by one or more of metal layers 150, vias (e.g., vias VD), and / or one or more metal lines.

[0067] In some aspects, the source / drain 525-2 and 525-4 in the first active region 512 can be coupled to the source / drain 545-2 and 545-4 in the second active region 530 because the source / drain 525-2, 525-4, 545-2, and 545-4 are coupled to the node Y. In this regard, Figure 5 An example of a metal wiring 555-1 coupling source / drain 525-2 and 545-2 and a metal wiring 555-2 coupling source / drain 525-4 and 545-4 is shown. Metal wirings 555-1 and 555-2 may be part of an interconnector coupling source / drain 525-2, 525-4, 545-2, and 545-4 to each other. The interconnector may include source / drain contacts formed by one or more of metal layers 150, vias (e.g., vias VD), and / or one or more metal lines.

[0068] Figure 5 The exemplary layout 510 shown illustrates various layout features according to aspects of the present disclosure. For example, in some aspects, the number of first gates 515-1 and 515-2 is an even number and the number of second gates 520-1 and 520-2 is an even number (i.e., each of the first transistor A and the second transistor B has an even number of gates). Such features facilitate coupling the source / drain 525-1 and 525-5 on both sides of the first active region 512 to the same node (e.g., node Z). Coupling the source / drain 525-1 and 525-5 on both sides to the same node enables the layout 510 to be repeated in the lateral direction 522 to increase the size of transistors A and B. Figure 6 An example of this situation is illustrated in .

[0069] Figure 6 An example of a first layout 510-1 and a second layout 510-2 is shown, where each of the first layout 510-1 and the second layout 510-2 is a copy of the exemplary layout 510. Figure 6 As shown, both the source / drain 525-5 on the right side of the first layout 510-1 and the source / drain 525-1 on the left side of the second layout 510-2 are coupled to the node Z. This enables the first layout 510-1 to be combined with the second layout 510-2 to form Figure 6 6. Note that in this example, the source / drain 525-5 on the right side of the first layout 510-1 is combined with the source / drain 525-1 on the left side of the second layout 510-2 in the combined layout 610. It should be understood that the layouts 510 may be Figure 6 The illustrated approach is repeated any number of times to increase the size of transistors A and B.

[0070] Therefore, having an even number of first gates 515-1 and 515-2 and an even number of second gates 520-1 to 520-2 helps to couple the source / drain 525-1 and 525-5 on both sides of the first active area 512 to the same node (e.g., node Z), which enables repeating the layout 510 to increase the size of transistors A and B.

[0071] In contrast, Fig. 7A An example of a layout 710 is shown in which there is an odd number of gates (e.g., three) for the first transistor A. This causes the source / drain 715 on the left side to be coupled to a different node than the source / drain 720 on the right side (i.e., the source / drain 715 is coupled to node Z, while the source / drain 720 is coupled to node X). This prevents the layout 710 from repeating in the lateral direction 522 to form a combined layout. Figure 7B An example of this is illustrated in FIG. 7 , in which a first layout 710 - 1 and a second layout 710 - 2 are shown, each of which is a copy of the exemplary layout 710 . Fig. 7A As shown, the source / drain 720 on the right side of the first layout 710-1 and the source / drain 715 on the left side of the second layout 710-2 are coupled to different nodes, which prevents the layouts 710-1 and 710-2 from being coupled to each other in a manner similar to that shown in FIG. Figure 6 Combination of the illustrated methods.

[0072] exist Figure 5In the example in, the ratio of the number of gates of the first transistor A (i.e., the first gates 515-1 and 515-2) to the number of gates of the second transistor B (i.e., the second gates 520-1 and 520-2) is 2:2. However, it should be understood that the present disclosure is not limited to this example, and other ratios can be used. Examples of other ratios that can be used include the following: 2:6, 6:2, 4:4, 4:6, 4:8, etc. For one of these ratios, the number of gates of the first transistor A is an even number, and the number of gates of the second transistor B is an even number. Examples of other ratios that can be used are further discussed below according to certain aspects.

[0073] In some aspects, the number of gates of the third transistor C (i.e., the third gates 535-1 to 535-4) is equal to the sum of the number of gates of the first transistor A (i.e., the first gates 515-1 and 515-2) and the number of gates of the second transistor B (i.e., the second gates 520-1 to 520-2). In other words, the number of gates of the third transistor C is equal to the number of gates of the first transistor A plus the number of gates of the second transistor B. This feature helps to match the width of the first active region 512 with the width of the second active region 530 in the lateral direction 522, which helps to reduce the area on the chip 100 with dummy gates due to the mismatch between the widths of the active regions 512 and 530.

[0074] exist Figure 5 In the example of , the second gates 520-1 and 520-2 are interspersed on the first active region 512. As used herein, the second gates 520-1 and 520-2 are interspersed on the first active region 512 when both of the second gates 520-1 and 520-2 are separated by one or more intervening first gates 515-1 and 515-2. Figure 5 In the example shown, the second gates 520-1 and 520-2 are separated by the first gates 515-1 and 515-2. However, it should be understood that the present disclosure is not limited to this example.

[0075] In this example, spreading the second gates 520-1 and 520-2 helps reduce the mismatch between the first gates 515-1 and 515-2 and the second gates 520-1 and 520-2 due to process variations. This is because spreading the second gates 520-1 and 520-2 helps make the first gates 515-1 and 515-2 and the second gates 520-1 and 520-2 more equally affected by process variations. Figure 8An example of this is illustrated in , which shows an example of the effect of process variations on the length of gates 820-1 to 820-4. Note that in this example, the length of each of gates 820-1 to 820-4 (labeled "L") is in direction 815. In this example, gates 820-1 to 820-4 ideally have the same length. However, due to process variations during manufacturing, the lengths of gates 820-1 to 820-4 increase slightly in direction 815 (i.e., in Figure 8 ). Figure 8 In the example shown, due to process variations, gate 820-1 may have a length of L, gate 820-2 may have a length of 1.01L, gate 820-3 may have a length of 1.02L, and gate 820-4 may have a length of 1.03L. Note that for ease of illustration, Figure 8 The difference in lengths of the gates 820 - 1 to 820 - 4 is exaggerated in FIG.

[0076] for Figure 8 In the illustrated example, spreading the second gates 520-1 and 520-2 helps reduce the mismatch between the lengths of the first gates 515-1 and 515-2 and the second gates 520-1 and 520-2 caused by process variations. Assuming that the second gates 520-1 and 520-2 correspond to the gates 820-1 and 820-4 and the first gates 515-1 and 515-2 correspond to the gates 820-2 and 820-3, in this example, the average length of the second gates 520-1 to 520-2 is 1.015L and the average length of the first gates 515-1 to 515-2 is also 1.015L. Therefore, in this example, spreading the second gates 520-1 and 520-2 makes the average length of the second gates 520-1 and 520-2 match the average length of the first gates 515-1 and 515-2.

[0077] Therefore, the second gates 520-1 and 520-2 are dispersed to reduce the mismatch of the length of the gates 515-1, 515-2, 520-1 and 520-2 caused by process variations. It should be understood that the second gates 520-1 and 520-2 can also reduce the mismatch of the width of the gates 515-1, 515-2, 520-1 and 520-2 caused by process variations, wherein the width of each gate (marked as "W") is in the direction 818.

[0078] It should be understood that mismatch due to process variations can also be reduced by spreading the first gates 515-1 and 515-2 over the first active region 512. As used herein, the first gates 515-1 and 515-2 are spread over the first active region 512 when both of the first gates 515-1 and 515-2 are separated by one or more intervening second gates 520-1 and 520-2. Examples in which the first gates are spread are discussed below.

[0079] As discussed above, for FinFET processes, each of the active regions 512 and 530 includes a fin. In this regard, Fig.9A An example is shown in which the first active region 512 includes first fins 910-1 to 910-4 and the second active region 530 includes second fins 920-1 to 920-4. Note that for ease of illustration, Fig.9A Reference numerals of the source / drain electrodes 525-1 to 525-5 and 545-1 to 545-5 are not shown.

[0080] In this example, each of the first fins 910-1 to 910-4 is elongated and extends in the lateral direction 522. The first gates 515-1 and 515-2 and the second gates 520-1 and 520-2 are formed on the first fins 910-1 to 910-4. Each of the first fins 910-1 to 910-4 is continuous in the first active region 512. It should be understood that the present disclosure is not limited to Fig.9A The number of first fins 910 - 1 to 910 - 4 shown in the example.

[0081] In this example, each of the second fins 920-1 to 920-4 is elongated and extends in the lateral direction 522. The third gates 535-1 to 535-4 are formed on the second fins 920-1 to 920-4. Each of the second fins 920-1 to 920-4 is continuous in the second active region 530. It should be understood that the present disclosure is not limited to Fig.9A The number of second fins 920 - 1 to 920 - 4 shown in the example.

[0082] Fig. 9B An example of first source / drain contacts 930-1 to 930-5 formed on first fins 910-1 to 910-4 to provide contacts for source / drain 525-1 to 525-5, respectively, is shown. Fig. 9B ) may be coupled to the source / drain 525-1, 525-2, 525-4, and 525-5 through corresponding source / drain contacts 930-1, 930-2, 930-4, and 930-5.

[0083] Fig. 9B Also shown are examples of second source / drain contacts 935-1 to 935-5 formed over the second fins 920-1 to 920-4 to provide contacts for the source / drain 545-1 to 545-5, respectively. Fig. 9B ) may be coupled to source / drain 545-1, 545-2, 545-4, and 545-5 through corresponding source / drain contacts 935-1, 935-2, 935-4, and 935-5.

[0084] As discussed above, the first gates 515-1 and 515-2 may be coupled to each other via a first gate interconnector, the second gates 520-1 and 520-2 may be coupled to each other via a second gate interconnector, and the third gates 535-1 to 535-4 may be coupled to each other via a third gate interconnector. In this regard, Fig.10 Examples of a first gate interconnector 1010 , a second gate interconnector 1020 , and a third gate interconnector 1030 according to certain aspects are shown.

[0085] In this example, the first gate interconnector 1010 includes a metal line 1012 and conductive paths 1014-1 and 1014-2. In this example, the metal line 1012 extends on the first gates 515-1 and 515-2 in the lateral direction 522. The metal line 1012 can be formed from one of the metal layers 150 (e.g., using a photolithography process and an etching process). It should be understood that the width of the metal line 1012 can be greater than Fig.10 Each of the conductive paths 1014-1 and 1014-2 (indicated by X) can couple a corresponding one of the first gates 515-1 and 515-2 to the metal line 1012. Each of the conductive paths 1014-1 and 1014-2 can include a gate contact, one or more vias (e.g., vias VG), and / or one or more portions formed by one or more of the metal layers 150. It should be understood that the first gate interconnector 1010 is not limited to Fig.10 It should also be understood that the first gate interconnector 1010 is not limited to Fig.10 For example, in some embodiments, the first gate interconnector 1010 can be placed on the other side or at another location of the first active region 512 .

[0086] In this example, the second gate interconnector 1020 includes a metal line 1022 and conductive paths 1024-1 and 1024-2. In this example, the metal line 1022 extends on the second gates 520-1 and 520-2 in the lateral direction 522. The metal line 1022 can be formed from one of the metal layers 150 (e.g., using a photolithography process and an etching process). It should be understood that the width of the metal line 1022 can be greater than Fig.10 The conductive paths 1024-1 and 1024-2 (indicated by X) may each couple a corresponding one of the second gates 520-1 and 520-2 to the metal line 1022. Each of the conductive paths 1024-1 and 1024-2 may include a gate contact, one or more vias (e.g., vias VG), and / or one or more portions formed by one or more of the metal layers 150. It should be understood that the second gate interconnect 1020 is not limited to Fig.10 It should also be understood that the second gate interconnector 1020 is not limited to Fig.10 For example, in some embodiments, the second gate interconnector 1020 can be placed on the other side or at another location of the first active region 512 .

[0087] In this example, the third gate interconnector 1030 includes a metal line 1032 and conductive paths 1034-1 to 1034-4. In this example, the metal line 1032 extends on the third gates 535-1 to 535-4 in the lateral direction 522. The metal line 1032 can be formed from one of the metal layers 150 (e.g., using a photolithography process and an etching process). It should be understood that the width of the metal line 1032 can be greater than Fig.10 Each of the conductive paths 1034-1 to 1034-4 (indicated by X) can couple a corresponding one of the third gates 535-1 to 535-4 to the metal line 1032. Each of the conductive paths 1034-1 to 1034-4 can include a gate contact, one or more vias (e.g., vias VG), and / or one or more portions formed by one or more of the metal layers 150. It should be understood that the third gate interconnector 1030 is not limited to Fig.10 It should also be understood that the third gate interconnector 1030 is not limited to Fig.10 For example, in some embodiments, the third gate interconnector 1030 can be placed on the other side or at another location of the second active region 530 .

[0088] As described above, the ratio of the number of gates of the first transistor A to the number of gates of the second transistor B may be different. In this regard, Fig.11An example of a layout 1110 is shown in which the ratio is 2:6. In this example, the first gates 515-1 and 515-2 are placed between the second gates 520-1 to 520-3 and the second gates 520-4 to 540-6. The source / drain 525-4 between the first gate 515-1 and the second gate 520-3 is shared by the first transistor A and the second transistor B, and the source / drain 525-6 between the first gate 515-2 and the second gate 520-4 is shared by the first transistor A and the second transistor B. As discussed above, the source / drain sharing between the first transistor A and the second transistor B reduces the parasitic resistance.

[0089] In this example, the number of first gates 515-1 and 515-2 is an even number (i.e., two) and the number of second gates 520-1 to 520-6 is an even number (i.e., six). The source / drain 525-1 on the left side of the first active region 512 and the source / drain 525-9 on the right side of the active region 512 are coupled to the same node (i.e., node Z), which enables the layout 1110 to be repeated in the lateral direction 522 to form a larger layout. In addition, in this example, the number of third gates 535-1 to 535-8 (i.e., eight) is equal to the sum of the number of first gates 515-1 and 515-2 and the number of second gates 520-1 to 520-6. As described above, this helps prevent the generation of a region with a dummy gate due to a width mismatch between the first active region 512 and the second active region 530.

[0090] Fig.12 An example of a layout 1210 is shown in which the ratio is 6:2. In this example, the first gates 515-1 to 515-6 are placed between the second gates 520-1 and 520-2. The source / drain 525-2 between the first gate 515-1 and the second gate 520-1 is shared by the first transistor A and the second transistor B, and the source / drain 525-8 between the first gate 515-6 and the second gate 520-2 is shared by the first transistor A and the second transistor B.

[0091] In this example, the number of first gates 515-1 to 515-6 is an even number (i.e., six) and the number of second gates 520-1 and 520-2 is an even number (i.e., two). The source / drain 525-1 on the left side of the first active region 512 and the source / drain 525-9 on the right side of the active region 512 are coupled to the same node (i.e., node Z). In addition, in this example, the number of third gates 535-1 to 535-8 (i.e., eight) is equal to the sum of the number of first gates 515-1 and 515-2 and the number of second gates 520-1 to 520-6.

[0092] Fig.13An example of a layout 1310 is shown in which the ratio is 4: 4. In this example, first gates 515-1 to 515-4 and second gates 520-1 to 520-4 are spread over the first active region 512. The first gates 515-1 and 515-2 are located between the second gates 520-1 and 520-2, the second gates 520-2 and 520-3 are located between the first gates 515-2 and 515-3, and the first gates 515-3 and 515-4 are located between the second gates 520-3 and 520-4. The source / drain 525-2 between the first gate 515-1 and the second gate 520-1 is shared by the first transistor A and the second transistor B, the source / drain 525-4 between the first gate 515-2 and the second gate 520-2 is shared by the first transistor A and the second transistor B, the source / drain 525-6 between the first gate 515-3 and the second gate 520-3 is shared by the first transistor A and the second transistor B, and the source / drain 525-8 between the first gate 515-4 and the second gate 520-4 is shared by the first transistor A and the second transistor B.

[0093] In this example, the number of first gates 515-1 to 515-4 is an even number (i.e., four), and the number of second gates 520-1 to 520-4 is an even number (i.e., four). The source / drain 525-1 on the left side of the first active region 512 and the source / drain 525-9 on the right side of the active region 512 are coupled to the same node (i.e., node Z). In addition, in this example, the number of third gates 535-1 to 535-8 (i.e., eight) is equal to the sum of the number of first gates 515-1 to 515-4 and the number of second gates 520-1 to 520-4.

[0094] Fig.14An example of a layout 1410 is shown in which the ratio is 4:6. In this example, first gates 515-1 to 515-4 and second gates 520-1 to 520-6 are spread over the first active region 512. The first gates 515-1 and 515-2 are located between the second gates 520-2 and 520-3, the second gates 520-3 and 520-4 are located between the first gates 515-2 and 515-3, and the first gates 515-3 and 515-4 are located between the second gates 520-4 and 520-5. The source / drain 525-3 between the first gate 515-1 and the second gate 520-2 is shared by the first transistor A and the second transistor B, the source / drain 525-5 between the first gate 515-2 and the second gate 520-3 is shared by the first transistor A and the second transistor B, the source / drain 525-7 between the first gate 515-3 and the second gate 520-4 is shared by the first transistor A and the second transistor B, and the source / drain 525-9 between the first gate 515-4 and the second gate 520-5 is shared by the first transistor A and the second transistor B.

[0095] In this example, the number of first gates 515-1 to 515-4 is an even number (i.e., four), and the number of second gates 520-1 to 520-6 is an even number (i.e., six). The source / drain 525-1 on the left side of the first active region 512 and the source / drain 525-11 on the right side of the active region 512 are coupled to the same node (i.e., node Y). In addition, in this example, the number of third gates 535-1 to 535-10 (i.e., ten) is equal to the sum of the number of first gates 515-1 to 515-4 and the number of second gates 520-1 to 520-6.

[0096] Fig.15 An example of a layout 1510 in which the ratio is 4:8 is shown. In this example, the first gates 515-1 to 515-4 are located between the second gates 520-1 to 520-4 and the second gates 520-5 to 520-8. The source / drain 525-5 between the first gate 515-1 and the second gate 520-4 is shared by the first transistor A and the second transistor B, and the source / drain 525-9 between the first gate 515-4 and the second gate 520-5 is shared by the first transistor A and the second transistor B.

[0097] In this example, the number of first gates 515-1 to 515-4 is an even number (ie, four) and the number of second gates 520-1 to 520-8 is an even number (ie, eight). The source / drain 525-1 on the left side of the first active region 512 and the source / drain 525-13 on the right side of the active region 512 are coupled to the same node (ie, node Y). In addition, in this example, the number of third gates 535-1 to 535-12 (ie, twelve) is equal to the sum of the number of first gates 515-1 to 515-4 and the number of second gates 520-1 to 520-8.

[0098] In certain aspects, the exemplary circuit 410 can be used for power switching in the system 1605. In this regard, Fig.16 An example is shown where node X is coupled to a first power rail 1620 and node Z is coupled to a second power rail 1630. The first power rail 1620 provides a voltage supply vdd (e.g., from a power management integrated circuit (PMIC) or another voltage source). The second power rail 1630 can be coupled to a circuit that receives power (e.g., a processor, a logic component, a memory, etc.). Figure 5 In the illustrated exemplary layout 510, the first power rail 1620 is coupled to the source / drain 525-3 in the first active region 512 between two adjacent first gates 515-1 and 515-2. As used herein, two gates are adjacent when there is no intervening gate between them.

[0099] In this example, the system 1605 includes a control circuit 1610, a first switch 1635, and a second switch 640. The control circuit 1610 is coupled to the gate terminal G of the first transistor A. A To control the on / off state of the first transistor A. The first switch 1635 is coupled to the gate terminal G of the second transistor B. B The drain terminal D of the second transistor B B Between. For Figure 5 In the exemplary layout 510 shown, the first terminal of the first switch 1635 is coupled to the second gates 520-1 and 520-2, and the second terminal of the first switch 1635 is coupled to the source / drain 525-1 and 525-5. The second switch 1640 is coupled to the gate terminal G of the third transistor C. C and the drain terminal D of the third transistor C C Between. For Figure 5In the exemplary layout 510 shown, the first terminal of the second switch 1640 is coupled to the third gate 535-1 to 535-5 and the second terminal of the second switch 1640 is coupled to the source / drain 545-2 and 545-4. The second terminal of the second switch 1640 can also be coupled to the source / drain 525-2 and 525-4 (which are shared by transistors A and B) through metal wiring 555-1 and 555-2. Each of the switches 1635 and 1640 can be implemented using a corresponding transistor. The control circuit 1610 controls the on / off state of the switches 1635 and 1640.

[0100] The control circuit 1610 is configured to decouple the second power supply rail 1630 from the first power supply rail 1620 by turning off the first transistor A and turning off the switches 1635 and 1640. For example, the control circuit 1610 can decouple the second power supply rail 1630 from the first power supply rail 1620 when a circuit (not shown) coupled to the second power supply rail 1630 is powered off or when the circuit coupled to the second power supply rail 1630 is supplied by another supply voltage (e.g., a supply voltage different from vdd) through another power switch (not shown).

[0101] To power up the circuit coupled to the second supply rail 1630 with the supply voltage vdd, the control circuit 1610 is configured to turn on the first transistor A (e.g., by applying a low voltage to the gate terminal G of the first transistor A). A ) and turns on switches 1635 and 1640. When the first switch 1635 is turned on, the first switch 1635 connects the gate terminal G of the second transistor B to the B With the drain terminal D B The second switch 1640 is coupled together so that the second transistor B acts as a diode-connected transistor. Similarly, when the second switch 1640 is turned on, the gate terminal G of the third transistor C is connected to the diode. C With the drain terminal D C coupled together so that the third transistor C acts as a diode-connected transistor.

[0102] Thus, in this example, the first power supply rail 1620 is coupled to the second power supply rail 1630 through the first transistor A and the diode-connected transistors B and C. The diode-connected transistors B and C help prevent unintentional current from flowing from the second power supply rail 1630 to the first power supply rail 1620. By way of example, the second power supply rail 1630 may initially be at a higher potential than the first power supply rail 1620. This may occur, for example, when the second power supply rail 1630 switches to the supply voltage vdd from another supply voltage higher than vdd. In this example, the diode-connected transistors C and B prevent the initial higher potential at the second power supply rail 630 from causing current to flow from the second power supply rail 1630 to the first power supply rail 1620.

[0103] It should be understood that, in addition to Fig.16 In addition to the circuit 410 shown, the system 1605 may also include an additional power switch between the first power rail 1620 and the second power rail 1630. It should also be understood that the circuit 410 is not limited to use as a power switch and can be used in other applications. Fig.16 Example shown.

[0104] It should be understood that layout techniques according to aspects of the present disclosure may be used for FinFETs, planar transistors, gate-all-around (GAA) transistors, and other types of transistors.

[0105] Specific implementation examples are described in the following numbered clauses:

[0106] 1. A chip, comprising:

[0107] a first active region;

[0108] a first gate extending over the first active region in a first direction, wherein the first gate corresponds to a first transistor; and

[0109] A second gate extends over the first active region in the first direction, wherein the second gate corresponds to a second transistor.

[0110] 2. A chip according to clause 1, wherein:

[0111] The number of the first gates is an even number; and

[0112] The number of the second gates is an even number.

[0113] 3. The chip of clause 2, wherein a ratio of the number of the first gates to the number of the second gates is 2:2, 2:6, 6:2, 4:4, or 4:8.

[0114] 4. A chip according to any one of clauses 1 to 3, further comprising:

[0115] a first gate interconnector coupling the first gates to each other; and

[0116] A second gate interconnector couples the second gates to each other.

[0117] 5. The chip according to any one of clauses 1 to 4, wherein a first one of the first gates is separated from a second one of the first gates by one or more of the second gates.

[0118] 6. The chip of clause 5, wherein a first one of the second gates is separated from a second one of the second gates by one or more of the first gates.

[0119] 7. The chip according to any of clauses 1 to 4, wherein the first gate is spread over the first active area.

[0120] 8. The chip of clause 7, wherein the second gate is spread over the second active area.

[0121] 9. A chip according to any one of clauses 1 to 8, wherein:

[0122] The first active region includes fins extending in a second direction perpendicular to the first direction;

[0123] The first gate is formed on the fin; and

[0125] The second gate is formed on the fin.

[0126] 10. The chip according to any of clauses 1 to 9, wherein the first transistor and the second transistor share at least one source / drain in the first active region.

[0127] 11. A chip according to any of clauses 1 to 10, further comprising a switch having a first terminal and a second terminal, wherein the first terminal is coupled to the second gate and the second terminal is coupled to a first source / drain in the first active region.

[0128] 12. The chip of clause 11, further comprising a power supply rail coupled to a second source / drain in the first active region.

[0129] 13. The chip according to clause 12, wherein the second source / drain is located between adjacent ones of the first gates.

[0130] 14. A chip according to any one of clauses 1 to 13, further comprising:

[0131] a second active region; and

[0132] A third gate extends over the second active region in the first direction, wherein the third gate corresponds to a third transistor.

[0133] 15. The chip of clause 14, further comprising metal wirings, wherein each of the metal wirings couples a corresponding source / drain in the first active region to a corresponding source / drain in the second active region.

[0134] 16. The chip according to clause 14 or 15, wherein the number of the third gates is equal to the sum of the number of the first gates and the number of the second gates.

[0135] 17. A chip according to clause 16, wherein:

[0136] The number of the first gates is an even number; and

[0137] The number of the second gates is an even number.

[0138] 18. A chip according to any one of clauses 14 to 17, further comprising:

[0139] a first gate interconnector coupling the first gates to each other;

[0140] a second gate interconnector coupling the second gates to each other; and

[0141] A third gate interconnector couples the third gates to each other.

[0142] 19. A chip according to any one of clauses 14 to 18, wherein:

[0144] The first transistor and the second transistor have the same channel type; and

[0145] and

[0146] The third transistor has a different channel type from the first transistor and the second transistor.

[0147] 20. A chip according to clause 19, wherein:

[0148] The first transistor comprises a first p-type transistor;

[0149] The second transistor comprises a second p-type transistor; and

[0150] The third transistor includes an n-type transistor.

[0151] 21. A chip according to any one of clauses 14 to 19, wherein the first transistor and the second transistor share at least one source / drain in the first active region, and the chip further comprises a switch having a first terminal and a second terminal, wherein the first terminal is coupled to the third gate and the second terminal is coupled to the at least one source / drain in the first active region.

[0152] Within this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or superior to other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect electrical coupling between two structures.

[0153] Any reference to an element using designations such as "first," "second," etc. herein does not generally limit the number or order of those elements. Rather, these designations are used herein as a convenient method of distinguishing two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements can be used or that the first element must be located before the second element.

[0154] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but should be granted the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip, comprising: a first active region; a first gate extending over the first active region in a first direction, wherein the first gate corresponds to a first transistor; and A second gate extends over the first active region in the first direction, wherein the second gate corresponds to a second transistor.

2. The chip according to claim 1, wherein: The number of the first gates is an even number; and The number of the second gates is an even number. 3 . The chip according to claim 2 , wherein a ratio of the number of the first gates to the number of the second gates is 2:2, 2:6, 6:2, 4:4 or 4:

8.

4. The chip according to claim 1, further comprising: a first gate interconnector coupling the first gates to each other; and A second gate interconnector couples the second gates to each other. 5 . The chip according to claim 1 , wherein a first one of the first gates is separated from a second one of the first gates by one or more of the second gates. 6 . The chip according to claim 5 , wherein a first one of the second gates is separated from a second one of the second gates by one or more of the first gates. The chip according to claim 1 , wherein the first gate is spread over the first active area. The chip according to claim 7 , wherein the second gate is spread over the second active area.

9. The chip according to claim 1, wherein: The first active region includes fins extending in a second direction perpendicular to the first direction; The first gate is formed on the fin; and The second gate is formed on the fin. 10 . The chip according to claim 1 , wherein the first transistor and the second transistor share at least one source / drain in the first active region. 11 . The chip of claim 1 , further comprising a switch having a first terminal and a second terminal, wherein the first terminal is coupled to the second gate and the second terminal is coupled to the first source / drain. 12 . The chip of claim 11 , further comprising a power supply rail coupled to a second source / drain in the first active region. 13 . The chip according to claim 12 , wherein the second source / drain is located between adjacent ones of the first gates.

14. The chip according to claim 1, further comprising: a second active region; and A third gate extends over the second active region in the first direction, wherein the third gate corresponds to a third transistor. 15 . The chip of claim 14 , further comprising metal wirings, wherein each of the metal wirings couples a corresponding source / drain in the first active region to a corresponding source / drain in the second active region. 16 . The chip according to claim 14 , wherein the number of the third gates is equal to the sum of the number of the first gates and the number of the second gates.

17. The chip according to claim 16, wherein: The number of the first gates is an even number; and The number of the second gates is an even number.

18. The chip according to claim 14, further comprising: a first gate interconnector coupling the first gates to each other; a second gate interconnector coupling the second gates to each other; and A third gate interconnector couples the third gates to each other.

19. The chip according to claim 14, wherein: The first transistor and the second transistor have the same channel type; and The third transistor has a different channel type from the first transistor and the second transistor.

20. The chip according to claim 19, wherein: The first transistor comprises a first p-type transistor; The second transistor comprises a second p-type transistor; and The third transistor includes an n-type transistor.

21. The chip of claim 14, wherein the first transistor and the second transistor share at least one source / drain in the first active region, and the chip further comprises a switch having a first terminal and a second terminal, wherein the first terminal is coupled to the third gate and the second terminal is coupled to the at least one source / drain in the first active region.

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