Distributed optical fiber sonic sensor system based on multi-core heterogeneous data processing chip

Abstract

The invention discloses a distributed optical fiber sonic sensor system based on a multi-core heterogeneous data processing chip. The distributed optical fiber sonic sensor system adopts the multi-core heterogeneous data processing chip to demodulate and process signals detected by an optical fiber sonic sensor assembly; the multi-core heterogeneous data processing chip comprises an FPGA (Field Programmable Gate Array) and a non-FPGA second core structure; the number of the second core structures is more than one; the FPGA demodulates the received signals of the distributed optical fiber acoustic wave sensor assembly, and caches the signals through at least two channels; all the second core structures use the micro real-time operating system to sequentially carry out real-time uninterrupted data processing on the demodulation data of the channel cache. According to the structure, the problem that an existing distributed optical fiber acoustic sensor system is large in size is solved, and the technical problem that demodulation data cannot be displayed and processed in a real-time and uninterrupted mode without an upper computer in a traditional scheme is solved.

Description

Technical Field

[0001] The present invention relates to the field of sensor technology, and in particular to a distributed optical fiber acoustic wave sensor system based on a multi-core heterogeneous data processing chip. Background Art

[0002] In distributed fiber optic acoustic wave sensing systems, FPGA is usually used to accelerate data demodulation and upload it to the host computer for data display. However, based on the maturity of on-chip heterogeneous chip technology, the ARM+FPGA chip structure represented by the ZYNQ model can directly display the data demodulated by FPGA using ARM+peripherals, which can completely replace the host computer and realize the miniaturization of distributed fiber optic acoustic wave sensing systems.

[0003] However, in the ARM+FPGA chip structure represented by the ZYNQ model, ARM has no design improvements, but simply mentions that it can be used as a single-chip microcomputer to achieve system miniaturization. A small number of ARM-based developments are only used as data packets sent by the network port.

[0004] Since the amount of data demodulated by the distributed fiber optic acoustic wave sensor system is very large (1GB / s), it is not possible to completely replace the host computer with ARM in the existing technology.

[0005] In view of this, there is an urgent need for a multi-core heterogeneous data processing chip that can display and process the demodulated data in real time and without interruption, so as to realize the miniaturization of the distributed fiber optic acoustic wave sensing system. Summary of the invention

[0006] 1. Technical issues to be resolved

[0007] In view of the above-mentioned shortcomings and deficiencies of the prior art, the present invention provides a distributed fiber optic acoustic wave sensor system based on a multi-core heterogeneous data processing chip, which solves the problem of large size of the existing distributed fiber optic acoustic wave sensor system and the technical problem that the demodulated data cannot be displayed and processed in real time and without interruption without using a host computer in the traditional solution.

[0008] (II) Technical solution

[0009] In order to achieve the above object, the main technical solutions adopted by the present invention include:

[0010] In a first aspect, an embodiment of the present invention provides a distributed optical fiber acoustic wave sensor system based on a multi-core heterogeneous data processing chip, wherein the distributed optical fiber acoustic wave sensor system uses a multi-core heterogeneous data processing chip to demodulate and process a signal detected by an optical fiber acoustic wave sensor component;

[0011] The multi-core heterogeneous data processing chip includes: an FPGA and a non-FPGA second core structure; the number of the second core structure is more than one;

[0012] The FPGA demodulates the received signal of the distributed optical fiber acoustic wave sensor assembly and caches it through at least two channels;

[0013] All second core structures use a micro real-time operating system to sequentially process the demodulated data in the channel buffer in real time without interruption.

[0014] Optionally, the second core structure includes one or more of the following: an advanced reduced instruction set machine ARM, a reduced instruction set machine RISV, a microprocessor MIPS without internal interlocked pipeline stages, and a performance-optimized enhanced RISC performance computing PowerPC.

[0015] Optionally, the length of the signal demodulated in real time by the FPGA is L, and the number of data cached by each channel selector is N, then when the cached data in the first channel reaches N*L, the channel selector in the FPGA switches to the second channel for data caching; N and L are both natural numbers greater than 0;

[0016] Accordingly, the second core structure includes a first ARM and a second ARM;

[0017] The first ARM creates the same number of threads as the number of channels during initialization; each thread corresponds to one channel, and when the cached data of each thread in the corresponding channel reaches N*L, it reads N*L; it reads the cached data in each channel in turn and parses it;

[0018] The second ARM creates a processing thread during initialization to process the data parsed in the first ARM for display or network transmission.

[0019] Optionally, the length of the signal demodulated in real time by the FPGA is L, and the number of data cached by each channel selector is N, then when the cached data in the first channel reaches N*L, the channel selector in the FPGA switches to the second channel for data caching; N and L are both natural numbers greater than 0;

[0020] Accordingly, the second core structure includes, a first ARM;

[0021] The first ARM creates the same number of threads as the number of channels during initialization; each thread corresponds to one channel, and when the cached data of each thread in the corresponding channel reaches N*L, it reads N*L; it reads the cached data in each channel in turn and parses it;

[0022] The first ARM creates a processing thread during initialization to process the data parsed in the first ARM for display or network transmission.

[0023] Optionally, the length of the signal demodulated in real time by the FPGA is L, and the number of data cached by each channel selector is N, then when the cached data in the first channel reaches N*L, the channel selector in the FPGA switches to the second channel for data caching; N and L are both natural numbers greater than 0;

[0024] Accordingly, the second core structure includes a first ARM and a second ARM;

[0025] The first ARM creates a thread pool when initialized, and the thread pool includes at least one thread for parsing data.

[0026] The second ARM creates a thread pool for processing data when initialized, and the thread pool includes at least one thread for processing data.

[0027] Optionally, the processing threads created by the second ARM include: a data saving thread and a variance calculation thread;

[0028] The data saving thread is used to fetch the column vector from the first ARM for processing;

[0029] Alternatively, the variance calculation thread is used to fetch the column vector from the first ARM for processing.

[0030] Optionally, it also includes an HDMI display module, and the HDMI display module is connected to the FPGA;

[0031] The second ARM sends the processed data to be displayed to the FPGA, so that the FPGA sends the displayed data to the HDMI display module for display;

[0032] and / or,

[0033] It also includes: a network port connected to the last second core structure, which is used to forward the data processed by the second core structure to the network.

[0034] Optionally, the FPGA and the non-FPGA second core structure are integrated in a development board.

[0035] Optionally, the distributed optical fiber acoustic wave sensor system further comprises: a DDS signal source;

[0036] The output of the multi-core heterogeneous data processing chip is connected to a DDS signal source,

[0037] The multi-core heterogeneous data processing chip and the DDS signal source are integrated in one housing to form a miniaturized distributed optical fiber acoustic wave sensing system.

[0038] Optionally, the distributed optical fiber acoustic wave sensor system further comprises: a laser, an AOM, an EDFA, a coupler, an optical fiber, and a PDR connected in sequence;

[0039] The output of the PDR is connected to the multi-core heterogeneous data processing chip via the ADC of the circuit component.

[0040] (III) Beneficial effects

[0041] The beneficial effects of the present invention are as follows: the distributed fiber optic acoustic wave sensor system based on a multi-core heterogeneous data processing chip of the present invention adopts a multi-core heterogeneous data processing chip to replace a host computer, which can reduce the volume of the fiber optic acoustic wave sensor system and effectively reduce the cost. The above system solves the problem of the existing distributed fiber optic acoustic wave sensor system being bulky and the technical problem that the demodulated data cannot be displayed and processed in real time without interruption without adopting a host computer in the traditional solution.

[0042] If the second core structure in the multi-core heterogeneous data processing chip is ARM, the chip of the present application uses a two-channel data cache to realize pipe line data reading on the one hand; on the other hand, a micro real-time operating system is used on the ARM side to demodulate data and perform real-time display data processing / or data sticking and data caching without interruption, which is applied to the fiber optic acoustic wave sensing system, thereby truly realizing the miniaturization of the distributed fiber optic acoustic wave sensing system, completely abandoning the host computer in the sensing system of the prior art, and effectively reducing the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is an architecture diagram of a multi-core heterogeneous data processing chip in a distributed fiber optic acoustic wave sensor system provided in this application;

[0044] Figure 2 A schematic diagram of a portion of the structure of the FPGA in the multi-core heterogeneous data processing chip provided in this application;

[0045] Figure 3 An architectural diagram of a multi-core heterogeneous data processing chip provided in another embodiment of the present application;

[0046] Figure 4 An architectural diagram of a multi-core heterogeneous data processing chip provided in another embodiment of the present application;

[0047] Figure 5 A schematic diagram of displaying content of an HDMI display module provided in another embodiment of the present application;

[0048] Figure 6 An architectural diagram of a multi-core heterogeneous data processing chip provided in another embodiment of the present application;

[0049] Figure 7 A schematic diagram of a second core structure in a multi-core heterogeneous data processing chip provided in another embodiment of the present application;

[0050] Figure 8 A schematic diagram of the framework of the distributed optical fiber acoustic wave sensing system provided for this application;

[0051] Fig. 9 A schematic diagram of the electrical components of the distributed fiber optic acoustic wave sensor system provided by the present application;

[0052] Fig.10 This is a schematic diagram of the miniaturized distributed fiber optic acoustic wave sensor system of the present application. DETAILED DESCRIPTION

[0053] In order to better explain the present invention and facilitate understanding, the present invention is described in detail below through specific implementation modes in conjunction with the accompanying drawings.

[0054] The embodiment of the present invention provides a distributed optical fiber acoustic wave sensor system based on a multi-core heterogeneous data processing chip, such as Figure 8 As shown, the distributed fiber optic acoustic wave sensor system uses a multi-core heterogeneous data processing chip to demodulate and process the signals detected by the fiber optic acoustic wave sensor assembly;

[0055] The multi-core heterogeneous data processing chip includes: an FPGA and a non-FPGA second core structure; the number of the second core structure is more than one;

[0056] The FPGA demodulates the received data of the distributed optical fiber acoustic wave sensor system and caches the data through at least two channels;

[0057] All second core structures use a micro real-time operating system to sequentially process the demodulated data in real time without interruption.

[0058] The second core structure of this embodiment is not a host computer. It is used in the acoustic wave sensing system to replace the host computer. For example, the second core structure may include one or more of the following: advanced reduced instruction set machine ARM, reduced instruction set machine RISV, microprocessor MIPS without internal interlocking pipeline stages, performance optimization enhanced RISC performance computing PowerPC, etc.

[0059] The distributed fiber optic acoustic wave sensor system based on a multi-core heterogeneous data processing chip of this embodiment adopts a multi-core heterogeneous data processing chip to replace a host computer, which can reduce the size of the fiber optic acoustic wave sensor system and effectively reduce costs.

[0060] exist Figure 8 and Fig. 9In the distributed fiber optic acoustic wave sensor system, the optical components include: narrow line width laser (Laser), acousto-optic modulator (AOM), optical fiber amplifier (EDFA), fiber coupler, polarization controller (PC), polarization diversity receiving optical path (PDR), balanced photodetector (BPD); electrical components include: signal generator (DDS), radio frequency amplifier, ADC acquisition card and multi-core heterogeneous data processing chip. The relationship between optical components and electrical components is as follows: Figure 8 As shown, specifically, a laser, an AOM, an EDFA, a fiber coupler, and a PDR are connected in sequence; the output of the PDR is connected to the multi-core heterogeneous data processing chip via an ADC of a circuit component.

[0061] The signal generator in this embodiment is a miniaturized DDS signal source, which serves as the output of the modulation signal of the system, ensuring the miniaturization of the entire system. The DDS signal source in this embodiment replaces the large signal source used in traditional laboratories, and while generating a signal that meets the requirements, it greatly reduces the volume of the signal source.

[0062] exist Figure 8 In the system, the control of DDS signal source, laser and EDFA devices adopts serial port protocol, which can all be controlled by ARM2 core.

[0063] The distributed optical fiber acoustic wave sensor system of this embodiment solves the problem of large size of existing distributed optical fiber acoustic wave sensor systems and the technical problem that in traditional solutions, the demodulated data cannot be displayed and processed in real time without interruption without using a host computer.

[0064] To better understand the processing of multi-core heterogeneous data processing chips, Figures 1 to 7 Give an example.

[0065] In practical applications, such as Figures 1 to 4 As shown, the length of the signal demodulated by the FPGA in real time is L, and the number of data cached by each channel selector is N. When the cached data in the first channel reaches N*L, the channel selector in the FPGA switches to the second channel for data caching; N is a natural number greater than or equal to 100; L is a natural number greater than 0;

[0066] Accordingly, the second core structure includes a first ARM and a second ARM;

[0067] The first ARM creates the same number of threads as the number of channels during initialization; each thread corresponds to one channel, and when the cached data of each thread in the corresponding channel reaches N*L, it reads N*L; it reads the cached data in each channel in turn and parses it;

[0068] The second ARM creates a processing thread during initialization to process the data parsed in the first ARM for display or network transmission.

[0069] It is understandable that if Figure 2 As shown, the length of each signal demodulated in the FPGA is L. At the beginning, the channel selector selects address 1. When the number of stored data reaches 300 and the data point is 300*L, the data at address 1 is full, an address 1 interrupt is issued, and the channel selector switches to address 2; the demodulated data continues to be input, and the real data is stored in address 2. When the number of data reaches 300, the data at address 2 is full, an address 2 interrupt is issued, and the channel selector switches to address 1, and so on.

[0070] During the initialization process of ARM1, two threads event_1 and event_2 (both belong to the data analysis thread data_anay_thread) are created to receive the two address interrupts in the first step. When the interrupt is activated, the corresponding thread will be activated to fetch 300*L data from the corresponding DDR address. Because the interrupt signals of the addresses are triggered sequentially, event_1 and event_2 will also be triggered sequentially, and the data in the DDR will also be read out sequentially.

[0071] like Figure 3 As shown, 300 pieces of data need to be parsed at the ARM1 end. Whenever L length data is parsed, it is sent to the ARM2 end to perform data packet sticking for network transmission or further sent to the HDMI display module for data display, as shown in FIG. Figure 5 shown.

[0072] Alternatively, in the previous step, the array is traversed and its column vector y_data is taken out, whose length is 300. It is sent to the post-processing thread math_process_thread in the ARM2 end for some post-processing algorithms. After the calculation is completed, it is also sent to the ARM2 end for data display or gluing. The display effect is as follows Figure 5 shown.

[0073] That is to say, Figure 5 As shown, the multi-core heterogeneous data processing chip of this embodiment further includes an HDMI display module, and the HDMI display module is connected to the FPGA;

[0074] The second ARM sends the processed data to be displayed to the FPGA, so that the FPGA sends the displayed data to the HDMI display module for display;

[0075] Furthermore, the multi-core heterogeneous data processing chip of this embodiment also includes a network port connected to the last second core structure, which is used to forward the data processed by the second core structure through a network.

[0076] In actual development, FPGA and non-FPGA second core structures are integrated in the development board.

[0077] In addition, the number of threads in the above embodiment is created as needed and is not limited to two threads. The drawings illustrate the creation of two threads by way of example.

[0078] In another embodiment, if the length of the signal demodulated in real time by the FPGA is L, and the number of data cached by each channel selector is N, when the cached data in the first channel reaches N*L, the channel selector in the FPGA switches to the second channel for data caching;

[0079] Accordingly, the second core structure includes, a first ARM;

[0080] The first ARM creates the same number of threads as the number of channels during initialization; each thread corresponds to one channel, and when the cached data of each thread in the corresponding channel reaches N*L, it reads N*L; it reads the cached data in each channel in turn and parses it;

[0081] The first ARM creates a processing thread during initialization to process the data parsed in the first ARM for display or network transmission.

[0082] In the specific implementation process, Figure 6 and Figure 7 As shown, the length of the signal demodulated by the FPGA in real time is L, and the number of data cached by each channel selector is N. When the cached data in the first channel reaches N*L, the channel selector in the FPGA switches to the second channel for data caching;

[0083] Accordingly, the second core structure includes a first ARM and a second ARM;

[0084] The first ARM creates a thread pool when initialized, and the thread pool includes at least one thread for parsing data.

[0085] The second ARM creates a thread pool for processing data when initialized, and the thread pool includes at least one thread for processing data.

[0086] It can be understood that the processing threads created by the second ARM include: a data saving thread and a variance calculation thread;

[0087] The data saving thread is used to fetch the column vector from the first ARM for processing;

[0088] Alternatively, the variance calculation thread is used to fetch the column vector from the first ARM for processing.

[0089] In this embodiment, the analysis solution in the ARM1 end can be that the data of the two channels are analyzed in the same main thread, and then the data is used. In addition, the analysis solution in the ARM1 end can be: design a thread pool, design a thread for each of the two channels to perform data analysis, and design a thread for each of the other functions to work, such as Figure 6 shown.

[0090] Figure 6 and Figure 7 The work of the thread pool shown can be placed in the same microcontroller as needed. For chips or development boards with multiple ARM cores, different cores can also be used to perform tasks collaboratively to achieve related processing of results.

[0091] Above Figures 1 to 7 In the embodiments of the present invention, the second core structure in the multi-core heterogeneous data processing chip is explained by taking ARM as an example. In practical applications, other core structures can also be used. This embodiment is selected according to actual needs. When ARM is used as the second core structure, the chip uses two-channel data cache on the one hand to realize pipe line data reading; on the other hand, a micro real-time operating system is used on the ARM side to demodulate data and perform real-time display data processing / or data sticking and data caching in real time without interruption, which is applied to the fiber optic acoustic wave sensing system, thereby truly realizing the miniaturization of the distributed fiber optic acoustic wave sensing system, completely abandoning the host computer in the sensing system of the prior art, and effectively reducing the cost.

[0092] like Figure 8 , Fig. 9 As shown, an embodiment of the present invention further provides a distributed optical fiber acoustic wave sensor system, comprising the multi-core heterogeneous data processing chip described in any of the above embodiments,

[0093] The non-FPGA second core structure in the distributed optical fiber acoustic wave sensor system realizes the function of the host computer.

[0094] In this embodiment, based on the multi-threaded data reading framework of pipe line, a micro real-time operating system is used in ARM to perform data reading, and two data stream processing frameworks are provided.

[0095] In addition, the FPGA-side data demodulation + ARM-side dual / multi-core processing architecture fully utilizes the advantages of multi-core heterogeneity to complete multiple functions. The sensor data can be sent directly to the PS side through interrupts or DMA, received and some post-processing algorithms are performed in ARM1 (micro real-time operating system), and data splicing is performed in ARM2 (li nux / micro real-time operating system) and sent to HDMI (display module) or network port. It can replace the host computer of the existing sensor system and further realize the miniaturization of the DAS system, such as Fig.10 shown.

[0096] The system of this embodiment solves the problem of large size of existing distributed optical fiber acoustic wave sensor systems and the technical problem that in traditional solutions, the demodulated data cannot be displayed and processed in real time without interruption without using a host computer.

[0097] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0098] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions.

[0099] It should be noted that in the claims, any reference numerals placed between brackets shall not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention may be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In the claims enumerating several means, several of these means may be embodied by the same hardware. The use of the words first, second, third, etc., is for convenience of expression only and does not indicate any order. These words may be understood as part of the component name.

[0100] In addition, it should be noted that, in the description of this specification, the description of the terms "one embodiment", "some embodiments", "embodiment", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0101] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments after knowing the basic creative concept. Therefore, the claims should be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0102] Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention should also include these modifications and variations.

Claims

1. A distributed fiber optic acoustic wave sensor system based on a multi-core heterogeneous data processing chip, characterized in that: The distributed fiber optic acoustic wave sensor system uses a multi-core heterogeneous data processing chip to demodulate and process the signals detected by the fiber optic acoustic wave sensor assembly; The multi-core heterogeneous data processing chip includes: an FPGA and a non-FPGA second core structure; the number of the second core structure is more than one; The FPGA demodulates the received signal of the distributed optical fiber acoustic wave sensor assembly and caches it through at least two channels; All second core structures use a micro real-time operating system to sequentially process the demodulated data in the channel buffer in real time without interruption.

2. The distributed optical fiber acoustic wave sensor system according to claim 1, characterized in that: The second core structure includes one or more of the following: an advanced reduced instruction set machine ARM, a reduced instruction set machine RISV, a microprocessor MIPS without internal interlocked pipeline stages, and a performance-optimized enhanced RISC performance computing PowerPC.

3. The distributed optical fiber acoustic wave sensor system according to claim 1, characterized in that: The length of the signal demodulated in real time by the FPGA is L, and the number of data cached by each channel selector is N. When the cached data in the first channel reaches N*L, the channel selector in the FPGA switches to the second channel for data caching; N and L are both natural numbers greater than 0; Accordingly, the second core structure includes a first ARM and a second ARM; The first ARM creates the same number of threads as the number of channels during initialization; each thread corresponds to one channel, and when the cached data of each thread in the corresponding channel reaches N*L, it reads N*L; it reads the cached data in each channel in turn and parses it; The second ARM creates a processing thread during initialization to process the data parsed in the first ARM for display or network transmission.

4. The distributed optical fiber acoustic wave sensor system according to claim 1, characterized in that: The length of the signal demodulated in real time by the FPGA is L, and the number of data cached by each channel selector is N. When the cached data in the first channel reaches N*L, the channel selector in the FPGA switches to the second channel for data caching; N and L are both natural numbers greater than 0; Accordingly, the second core structure includes, a first ARM; The first ARM creates the same number of threads as the number of channels during initialization; each thread corresponds to one channel, and when the cached data of each thread in the corresponding channel reaches N*L, it reads N*L; it reads the cached data in each channel in turn and parses it; The first ARM creates a processing thread during initialization to process the data parsed in the first ARM for display or network transmission.

5. The distributed optical fiber acoustic wave sensor system according to claim 1, characterized in that: The length of the signal demodulated in real time by the FPGA is L, and the number of data cached by each channel selector is N. When the cached data in the first channel reaches N*L, the channel selector in the FPGA switches to the second channel for data caching; N and L are both natural numbers greater than 0; Accordingly, the second core structure includes a first ARM and a second ARM; The first ARM creates a thread pool when initialized, and the thread pool includes at least one thread for parsing data; The second ARM creates a thread pool for processing data when initialized, and the thread pool includes at least one thread for processing data.

6. The distributed optical fiber acoustic wave sensor system according to claim 3, characterized in that: The processing threads created by the second ARM include: a data saving thread and a variance calculation thread; The data saving thread is used to fetch the column vector from the first ARM for processing; Alternatively, the variance calculation thread is used to fetch the column vector from the first ARM for processing.

7. The distributed optical fiber acoustic wave sensor system according to claim 1, characterized in that: Also included is an HDMI display module, the HDMI display module is connected to the FPGA; The second ARM sends the processed data to be displayed to the FPGA, so that the FPGA sends the displayed data to the HDMI display module for display; and / or, It also includes: a network port connected to the last second core structure, which is used to forward the data processed by the second core structure to the network.

8. The distributed optical fiber acoustic wave sensor system according to claim 1, characterized in that: The FPGA and the non-FPGA second core structure are integrated in a development board.

9. The distributed optical fiber acoustic wave sensor system according to claim 1, characterized in that: The distributed optical fiber acoustic wave sensor system further includes: a DDS signal source; The output of the multi-core heterogeneous data processing chip is connected to a DDS signal source, The multi-core heterogeneous data processing chip and the DDS signal source are integrated in one housing to form a miniaturized distributed optical fiber acoustic wave sensing system.

10. The distributed optical fiber acoustic wave sensor system according to claim 1, characterized in that: The distributed optical fiber acoustic wave sensor system also includes: a laser, an AOM, an EDFA, a coupler, an optical fiber, and a PDR connected in sequence; The output of the PDR is connected to the multi-core heterogeneous data processing chip via the ADC of the circuit component.

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