POR circuit compatible with low working voltage

Abstract

The invention discloses a POR circuit compatible with a low working voltage, and the circuit comprises a delay unit which is used for generating a following voltage which lags behind the change of a VIO voltage in the power-on process of the VIO voltage; the delay unit comprises a first branch, a second branch and a third branch; the first branch comprises a first PMOS tube, a first NMOS tube and a second resistor which are sequentially connected in series; the second branch comprises a first resistor and a second NMOS tube which are connected in series; and the third branch comprises a second PMOS tube and a capacitor unit which are connected in series. The POR circuit of the MIPI RFFE chip is optimized, compatible work of VIO = 1.8 V and 1.2 V is achieved, effective reset signals can be normally provided under the low VIO voltage, and the hard reset function is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency front-end chips, and in particular to a POR circuit compatible with low operating voltage. Background Art

[0002] With the rapid development of mobile communication technology, modern mobile products such as mobile phones and mobile computers are becoming lighter and thinner. In addition to RF transceivers, these modern mobile communication devices also widely use RF front-end (RFFE) devices such as power amplifiers, low noise amplifiers, filters, switches, power management modules, and antenna tuners. Most of these RF front-end devices are controlled and configured in working mode by the main controller through a digital bus.

[0003] In order to unify industry specifications, many standardization organizations have developed communication standards suitable for mobile devices. Among them, the most eye-catching and widely used is the RF front-end control interface developed by the Mobile Industry Processor Interface (MIPI) Alliance. The MIPI RFFE interface is a simple interface for RF systems that can be integrated with a smaller number of logic devices to reduce cost investment. The MIPI RFFE interface uses three signal lines, of which SCLK is the bus clock signal line, SDATA is the bus data signal line, and VIO is the bus voltage reference / power line. This interface can achieve high-speed data transmission and is simple and easy to use. It is currently widely used in RF front-end devices in the mobile industry.

[0004] Figure 1 The internal block diagram of the MIPI controlled RF front-end chip is shown. The RFFE Digital Core module includes a POR (Power on reset) circuit module. The POR circuit module performs a hard reset operation on the RFFE Digital Core module during the VIO power-on period to prevent the RFFE Digital Core module from outputting an error signal after VIO is stable.

[0005] The specific implementation is as follows Figure 2 T VIO-R Time period (corresponding to Figure 3 The POR module needs to output a low level, and the voltage of the inflection point M1 needs to be higher than 1V. This ensures that the RFFE Digital Core powered by VIO can work normally, receives a reset signal of 0, that is, a valid reset signal, and operates normally to control the internal circuit.

[0006] A POR circuit in the prior art can refer to the patent document with publication number CN109738830B. Figure 4 As shown, the POR circuit includes a current generating unit 100, a capacitor unit C1, a comparator 200 and a charge discharge unit 300; the PMOS tubes in the figure are marked with MP1 to MP7; the current generating unit 100 is used to generate an intermediate current I1 related to the size of VIO to charge the capacitor unit C1 after VIO reaches a preset voltage value (the sum of the threshold voltages of MP3 and MP4), so that the follower voltage Vdelay at the circuit node B rises with a lag as VIO rises; the comparator 200 is used to compare the sizes of VIO and Vdelay after VIO reaches another preset voltage (the threshold voltage of MP6), and output a 0 voltage as a valid reset signal when Vdelay is less than VIO, and output a VIO voltage when Vdelay is close to VIO; the charge discharge unit 300 is used to Figure 3 The M5-M0 dotted line segment stage discharges the charge stored in the capacitor unit C1, so that the POR circuit can work normally when VIO is powered on next time.

[0007] And as Figure 5 As shown, according to the evolution of the VIO voltage level specified in the MIPI protocol, the VIO voltage is compatible from 1.8V to 1.8V and 1.2V to meet the requirements of low voltage and low power consumption. The delay unit 100 requires the VIO rated operating voltage to be higher than the sum of the threshold voltages of MP3 and MP4 for normal operation, while MP3 and MP4 use 1.8V or 2.5V PMOS tubes, and the threshold voltage of the two-stage tubes is greater than 1.2V, resulting in the MP4 tube being unable to conduct under certain process corners under the condition of VIO = 1.2V operating voltage, and the current generating unit 100 cannot work normally, resulting in an abnormal POR circuit.

[0008] Therefore, how to design a POR circuit structure that is compatible with a lower VIO voltage and can generate an intermediate current I1 when VIO = 1.2 V and 1.8 V to enable the POR circuit to work normally is an urgent problem to be solved. Summary of the invention

[0009] In view of this, an object of the present invention is to design a circuit structure of a current generating unit that is compatible with the working states of VIO=1.2V and 1.8V and realizes the normal function of the POR circuit.

[0010] To achieve the above object, the present invention provides a POR circuit compatible with a low operating voltage, comprising a delay unit, wherein the delay unit is used to generate a follow-up voltage that lags behind the change of the VIO voltage during the power-on process of the VIO voltage;

[0011] The delay unit includes a first branch, a second branch and a third branch; the first to third branches are connected between the VIO terminal and the ground terminal;

[0012] The first branch includes a first PMOS transistor, a first NMOS transistor and a second resistor connected in series in sequence, the source of the first PMOS transistor is electrically connected to the VIO terminal, the drain of the first PMOS transistor is electrically connected to the drain of the first NMOS transistor, one end of the second resistor is electrically connected to the first NMOS transistor, and the other end of the second resistor is grounded;

[0013] The second branch includes a first resistor and a second NMOS transistor connected in series; the drain of the second NMOS transistor is electrically connected to the VIO terminal through the first resistor, and the source of the second NMOS transistor is grounded;

[0014] The third branch includes a second PMOS tube and a capacitor unit connected in series; the source of the second PMOS tube is electrically connected to the VIO terminal; one end of the capacitor unit is electrically connected to the drain of the second PMOS tube, and the other end of the capacitor unit is grounded;

[0015] The gate of the first NMOS tube is electrically connected to the drain of the second NMOS tube; the gate of the second NMOS tube is electrically connected to the source of the first NMOS tube; the gate of the first PMOS tube and the gate of the second PMOS tube are electrically connected to the drain of the first PMOS tube;

[0016] The drain voltage of the second PMOS tube is the follower voltage generated by the delay unit.

[0017] Preferably, the POR circuit further includes a comparator and a charge discharge unit, wherein the comparator is electrically connected to the delay unit, and the comparator is electrically connected to the VIO terminal. The comparator is used to compare the follower voltage and the VIO voltage, and to generate a valid reset signal after the VIO terminal is powered on. The charge discharge unit is used to discharge the charge stored in the capacitor unit during the VIO voltage drop phase.

[0018] Preferably, the POR circuit further includes a fourth branch and a fifth branch, wherein the fourth branch includes a third PMOS transistor, a third NMOS transistor and a third resistor connected in series in sequence; and the fifth branch includes a fourth PMOS transistor and a fourth NMOS transistor connected in series;

[0019] The source of the third PMOS tube is electrically connected to the VIO terminal, the drain of the third PMOS tube is electrically connected to the drain of the third NMOS tube, one end of the third resistor is electrically connected to the source of the third NMOS tube, and the other end of the third resistor is grounded; the gate of the third PMOS tube and the gate of the third NMOS tube are electrically connected to the drain of the second PMOS tube;

[0020] The source of the fourth PMOS tube is electrically connected to the VIO terminal; the source of the fourth NMOS tube is grounded; the drain of the fourth PMOS tube and the drain of the fourth NMOS tube are electrically connected to the output terminal of the POR circuit; the gate of the fourth PMOS tube and the gate of the fourth NMOS tube are electrically connected to the drain of the third PMOS tube.

[0021] Preferably, the POR circuit further includes a fifth PMOS tube, the fifth PMOS tube is connected in parallel with the second PMOS tube, and a gate of the fifth PMOS tube is electrically connected to the VIO terminal.

[0022] Preferably, the POR circuit is used for a radio frequency front-end chip whose VIO voltage is compatible with 1.8V and 1.2V.

[0023] The beneficial effects of the present invention are:

[0024] The POR circuit of the MIPI RFFE chip has been optimized to achieve compatible operation with VIO=1.8V and 1.2V. It can provide a valid reset signal normally at a lower VIO voltage to realize the hard reset function. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 This is a schematic diagram of the structure of the RF front-end chip that supports the MIPI protocol;

[0027] Figure 2 It is a schematic diagram of the conversion between the effective state and the invalid state of the VIO voltage;

[0028] Figure 3 It is a schematic diagram of the relationship between the reset signal reset and the VIO voltage when the VIO voltage state is switched;

[0029] Figure 4 A POR circuit diagram in the prior art;

[0030] Figure 5 This is the parameter table of the power supply requirements for VIO voltage of the MIPI protocol;

[0031] Figure 6 is a circuit diagram of a delay unit according to an embodiment of the present invention;

[0032] Figure 7 A POR circuit diagram of an embodiment of the present invention;

[0033] Figure 8 This is a diagram of power-on simulation results of an embodiment of the present invention when VIO=1.2V;

[0034] Fig. 9 1 is a diagram of power-on simulation results of an embodiment of the present invention when VIO=1.8V. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] Figure 6 The circuit diagram of the delay unit of the embodiment of the present invention is shown. The delay unit includes a first branch, a second branch and a third branch. The first to third branches are respectively connected between the VIO terminal and the ground terminal. The first branch includes a first PMOS tube MP1, a first NMOS tube MN1 and a second resistor R2 connected in series in sequence, the source of the first PMOS tube MP1 is electrically connected to the VIO terminal, the first PMOS tube MP1 and the first NMOS tube MN1 are electrically connected to the drain, one end of the second resistor R2 is electrically connected to the source of the first NMOS tube MN1, and the other end of the second resistor R2 is grounded; the second branch includes a first resistor R1 and a second NMOS tube MN2 connected in series, the drain of the second NMOS tube is electrically connected to the VIO terminal through the first resistor R1, and the source of the second NMOS tube MN2 is grounded; the third branch includes a second PMOS tube MP2 and a capacitor unit C1, the source of the second PMOS tube is electrically connected to the VIO terminal, and the two ends of the capacitor unit C1 are respectively electrically connected to the drain and the ground terminal of the second PMOS tube MP2. The gate of the first NMOS tube MN1 is electrically connected to the drain of the second NMOS tube; the gate of the second NMOS tube MN2 is electrically connected to the source of the first NMOS tube; the gates of the first PMOS tube MP1 and the second PMOS tube MP2 are electrically connected to the drain of the first PMOS tube, and the second PMOS tube is used to mirror the current of the first PMOS tube as the intermediate current I1 and charge the capacitor unit C1, that is, the second PMOS tube MP2 of the first branch, the second branch and the third branch acts as the current generating unit 100, and the drain terminal voltage of the second PMOS tube MP2 follows the voltage Vdelay.

[0037] Figure 7The circuit diagram of the POR circuit after replacing the prior art with the delay unit of the embodiment of the present invention is shown. On the basis of including the delay unit, the POR circuit also includes a fourth branch, a fifth branch and a charge discharge unit 300; the fourth branch and the fifth branch are respectively connected between the VIO terminal and the ground terminal. The fourth branch includes a comparator 200, and the comparator 200 includes a third PMOS tube MP3, a third NMOS tube MN3 and a third resistor R3 connected in series in sequence. The source of the third PMOS tube MP3 is electrically connected to the VIO terminal, the third PMOS tube MP3 and the third NMOS tube MN3 are electrically connected to the common drain, one end of the third resistor R3 is electrically connected to the drain of the third NMOS tube, and the other end of the third resistor R3 is grounded. The gates of the third PMOS tube and the third NMOS tube are electrically connected to the drain of the second PMOS tube MP2, and receive the follower voltage Vdelay and compare it with VIO; the fifth branch The circuit includes a fourth PMOS tube MP4 and a fourth NMOS tube MN4 connected in series, the source of the fourth PMOS tube is electrically connected to the VIO terminal, the drain of the fourth PMOS tube and the drain of the fourth NMOS tube are electrically connected to the output terminal of the POR circuit, the drain of the fourth NMOS tube is grounded, the gates of the fourth PMOS tube and the fourth NMOS tube are electrically connected to the drain of the third PMOS tube MP3, and the fifth branch is used for signal shaping; the charge discharge unit 300 includes a fifth PMOS tube MP5, the fifth PMOS tube and the second PMOS tube MP2 are connected in parallel, and the gate of the fifth PMOS tube is electrically connected to the VIO terminal.

[0038] During operation, when VIO is 1.2V, the V gs The sum is V gs_MN1 +V gs_MN2 >1.2V, the second NMOS tube MN2 cannot be turned on and is in the off state; the current of the first branch is (VIO-V gs_MN1 ) / R2, that is, when VIO>V gs_MN1 When the current flows through the first PMOS tube MP1, the third branch generates an intermediate current I1 through the mirror, which charges the capacitor unit C1 to generate a delayed follow-up voltage Vdelay. The simulation results are as follows: Figure 8 shown. Figure 8 The upper, middle and lower (pink, green and red) curves respectively represent the relationship between the VIO voltage, the following voltage Vdelay and the POR circuit output signal reset over time during the VIO power-on process. As can be seen from the figure, since the following voltage Vdelay signal has a hysteresis relative to the VIO signal, the POR circuit outputs a valid reset signal reset = 0 within a short time window after VIO is powered on, realizing the hard reset function.

[0039] When VIO is 1.8V, V gs The sum is V gs_MN1 +V gs_MN2 <1.8V, the first NMOS tube MN1 and the second NMOS tube MN2 are turned on at the same time; at this time, the current flowing through the first PMOS tube MP1 is V gs_MN2 / R2 determines that the third branch generates an intermediate current I1 through a mirror image, charging C1 to generate a hysteresis following voltage Vdelay. The simulation results are as follows Fig. 9 As shown in the figure, the upper, middle and lower (pink, green and red) curves respectively represent the relationship between the VIO voltage, the follower voltage Vdelay and the POR circuit output signal reset over time during the VIO power-on process. Compared with the working condition of VIO = 1.2V, when VIO is higher, the second NMOS tube MN2 plays the role of negative feedback clamping current, thereby generating sufficient delay time for judgment.

[0040] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A POR circuit compatible with low operating voltage, characterized in that: A delay unit is included, wherein the delay unit is used to generate a follow-up voltage that lags behind the change of the VIO voltage during the power-on process of the VIO voltage; The delay unit includes a first branch, a second branch and a third branch; the first to third branches are connected between the VIO terminal and the ground terminal; The first branch includes a first PMOS transistor, a first NMOS transistor and a second resistor connected in series in sequence, the source of the first PMOS transistor is electrically connected to the VIO terminal, the drain of the first PMOS transistor is electrically connected to the drain of the first NMOS transistor, one end of the second resistor is electrically connected to the first NMOS transistor, and the other end of the second resistor is grounded; The second branch includes a first resistor and a second NMOS transistor connected in series; the drain of the second NMOS transistor is electrically connected to the VIO terminal through the first resistor, and the source of the second NMOS transistor is grounded; The third branch includes a second PMOS tube and a capacitor unit connected in series; the source of the second PMOS tube is electrically connected to the VIO terminal; one end of the capacitor unit is electrically connected to the drain of the second PMOS tube, and the other end of the capacitor unit is grounded; The gate of the first NMOS tube is electrically connected to the drain of the second NMOS tube; the gate of the second NMOS tube is electrically connected to the source of the first NMOS tube; the gate of the first PMOS tube and the gate of the second PMOS tube are electrically connected to the drain of the first PMOS tube; The drain voltage of the second PMOS tube is the follower voltage generated by the delay unit.

2. The POR circuit according to claim 1, characterized in that: It also includes a comparator and a charge discharge unit, the comparator is electrically connected to the delay unit, the comparator is electrically connected to the VIO terminal, the comparator is used to compare the follower voltage and the VIO voltage, and generate a valid reset signal after the VIO terminal is powered on, and the charge discharge unit is used to discharge the charge stored in the capacitor unit during the VIO voltage drop stage.

3. The POR circuit according to claim 1, characterized in that: It also includes a fourth branch and a fifth branch, wherein the fourth branch includes a third PMOS tube, a third NMOS tube and a third resistor connected in series in sequence; and the fifth branch includes a fourth PMOS tube and a fourth NMOS tube connected in series; The source of the third PMOS tube is electrically connected to the VIO terminal, the drain of the third PMOS tube is electrically connected to the drain of the third NMOS tube, one end of the third resistor is electrically connected to the source of the third NMOS tube, and the other end of the third resistor is grounded; the gate of the third PMOS tube and the gate of the third NMOS tube are electrically connected to the drain of the second PMOS tube; The source of the fourth PMOS tube is electrically connected to the VIO terminal; the source of the fourth NMOS tube is grounded; the drain of the fourth PMOS tube and the drain of the fourth NMOS tube are electrically connected to the output terminal of the POR circuit; the gate of the fourth PMOS tube and the gate of the fourth NMOS tube are electrically connected to the drain of the third PMOS tube.

4. The POR circuit according to claim 3, characterized in that: The fifth PMOS tube is also included. The fifth PMOS tube is connected in parallel with the second PMOS tube, and a gate of the fifth PMOS tube is electrically connected to the VIO terminal.

5. The POR circuit according to claim 1, characterized in that: The POR circuit is used for a radio frequency front-end chip whose VIO voltage is compatible with 1.8V and 1.2V.

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