Storage device read-write method and device, equipment, storage medium and program product

Abstract

The invention relates to the technical field of computers, and discloses a storage device read-write method and device, equipment, a storage medium and a program product.The method comprises the steps that in response to a processing instruction for a target submission queue at the front end in the storage device, the target submission queue is mapped into a first submission queue and a second submission queue at the rear end in the storage device, the target submission queue comprises at least one of a read command and a write command; reading the read command in the first submission queue by using the first data transmission channel, and writing the read read command into a read buffer area; reading the write command in the second submission queue by using a second data transmission channel, and writing the read write command into a write buffer area; processing the read command in the read buffer area to execute a read operation; and processing the write command in the write buffer area to execute write operation. According to the method and the device, the problem of queue head blockage caused by read-write speed limitation of the storage equipment can be solved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a storage device reading and writing method, apparatus, device, storage medium and program product. Background Art

[0002] In the related art, storage devices are often limited in read and write speed to improve data security, optimize system performance, facilitate storage resource management, and control storage costs. However, in the process of limiting the read and write speed of storage devices, it is difficult for the backend of the storage device to know whether the next operation to be processed is a read operation or a write operation. Therefore, if the write operation is limited, the read operation in the queue will be blocked, and vice versa, resulting in head-of-line blocking. Summary of the invention

[0003] In view of this, the present disclosure provides a storage device reading and writing method, apparatus, device, storage medium and program product to solve the problem of head-of-line blocking caused by limiting the reading and writing speed of the storage device.

[0004] In a first aspect, the present disclosure provides a storage device reading and writing method, the method comprising:

[0005] In response to a processing instruction for a target submission queue of a front end in the storage device, mapping the target submission queue into a first submission queue and a second submission queue of a back end in the storage device, the target submission queue including at least one of a read command and a write command;

[0006] Reading the read commands in the first submission queue using the first data transmission channel, and writing the read read commands into the read buffer;

[0007] Using a second data transmission channel to read the write command in the second submission queue, and writing the read write command into a write buffer;

[0008] Processing the read command in the read buffer to perform a read operation;

[0009] The write command in the write buffer is processed to perform a write operation.

[0010] In a second aspect, the present disclosure provides a storage device reading and writing device, the device comprising:

[0011] a queue mapping module, for mapping the target submission queue into a first submission queue and a second submission queue in a back end of the storage device in response to a processing instruction for the target submission queue in the front end of the storage device, the target submission queue including at least one of a read command and a write command;

[0012] A read command writing module, configured to read the read commands in the first submission queue by using the first data transmission channel, and write the read read commands into the read buffer;

[0013] A write command writing module, used for reading the write commands in the second submission queue by using the second data transmission channel, and writing the read write commands into the write buffer;

[0014] A read command processing module, used for processing the read command in the read buffer to perform a read operation;

[0015] The write command processing module is used to process the write command in the write buffer to perform a write operation.

[0016] In a third aspect, the present disclosure provides an electronic device, comprising: a memory and a processor, the memory and the processor are communicatively connected to each other, computer instructions are stored in the memory, and the processor executes the storage device reading and writing method of the first aspect by executing the computer instructions.

[0017] In a fourth aspect, the present disclosure provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the storage device reading and writing method of the first aspect.

[0018] In a fifth aspect, the present disclosure provides a computer program product, including computer instructions, and the computer instructions are used to enable a computer to execute the storage device reading and writing method of the first aspect.

[0019] The storage device read and write method provided by the embodiment of the present disclosure uses the first data transmission channel and the second data transmission channel to map the target submission queue at the front end of the storage device into the first submission queue and the second submission queue at the back end to process the read command and the write command respectively. Therefore, the read speed limit scenario and the write speed limit scenario do not affect each other, and can effectively solve the problem of head-of-queue blocking in the storage device speed limit scenario. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the specific embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 is a flowchart of a first storage device reading and writing method according to an embodiment of the present disclosure;

[0022] Figure 2is a schematic diagram of a read / write speed limiting method of a related technology according to an embodiment of the present disclosure;

[0023] Figure 3 is a schematic diagram of a buffer zone of a related technology according to an embodiment of the present disclosure;

[0024] Figure 4 is a schematic diagram of another related technology read / write speed limiting method according to an embodiment of the present disclosure;

[0025] Figure 5 is a schematic diagram of a buffer zone of another related technology according to an embodiment of the present disclosure;

[0026] Figure 6 is a schematic diagram of a read / write speed limiting method of a related technology according to an embodiment of the present disclosure;

[0027] Figure 7 is a flowchart of a second storage device reading and writing method according to an embodiment of the present disclosure;

[0028] Figure 8 is a schematic diagram of a target submission queue according to an embodiment of the present disclosure;

[0029] Fig. 9 is a schematic diagram of command writing and processing of a read buffer and a write buffer according to an embodiment of the present disclosure;

[0030] Fig.10 is a schematic diagram of a third storage device reading and writing method according to an embodiment of the present disclosure;

[0031] Fig.11 is a flowchart of a fourth storage device reading and writing method according to an embodiment of the present disclosure;

[0032] Fig.12 is a flowchart of a fifth storage device reading and writing method according to an embodiment of the present disclosure;

[0033] Fig.13 is a structural block diagram of a storage device reading and writing apparatus according to an embodiment of the present disclosure;

[0034] Fig.14 is a structural block diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0036] It is understandable that before using the technical solutions disclosed in the embodiments of the present disclosure, the types, scope of use, usage scenarios, etc. of the personal information involved in the present disclosure should be informed to the user and the user's authorization should be obtained in an appropriate manner in accordance with relevant laws and regulations.

[0037] For example, in response to receiving an active request from a user, a prompt message is sent to the user to clearly prompt the user that the operation requested to be performed will require obtaining and using the user's personal information. Thus, the user can autonomously choose whether to provide personal information to software or hardware such as an electronic device, application, server, or storage medium that performs the operation of the technical solution of the present disclosure according to the prompt message.

[0038] As an optional but non-limiting implementation, in response to receiving an active request from the user, the prompt information may be sent to the user in the form of a pop-up window, in which the prompt information may be presented in text form. In addition, the pop-up window may also carry a selection control for the user to choose "agree" or "disagree" to provide personal information to the electronic device.

[0039] It is understandable that the above notification and the process of obtaining user authorization are merely illustrative and do not constitute a limitation on the implementation of the present disclosure. Other methods that meet the relevant laws and regulations may also be applied to the implementation of the present disclosure.

[0040] It is understandable that the data involved in this technical solution (including but not limited to the data itself, the acquisition or use of the data) shall comply with the requirements of relevant laws, regulations and relevant provisions.

[0041] In the storage scenario, limiting the read and write speed of storage devices has the following advantages: First, it improves data security. Limiting the write speed of storage devices can prevent data from being written too quickly, thereby reducing the risk of data loss and damage. At the same time, it can prevent malware or hacker attacks from obtaining sensitive information by quickly reading large amounts of data. Second, it optimizes system performance. Limiting the write speed of storage devices can prevent performance degradation caused by too fast data writing during high concurrent writes. Limiting the read speed of storage devices can ensure the stability and responsiveness of the system during large concurrent reads. Third, it facilitates the management of storage resources. Limiting the read and write speed of storage devices can help manage storage resources and prevent a certain application or user from overusing storage resources, thereby affecting the performance of other applications or users. Fourth, it controls storage costs. Limiting the read and write speed of storage devices can help control storage costs, reduce the amount of data transmitted and the load on storage devices, thereby reducing storage costs.

[0042] It can be seen that limiting the read and write speed of storage devices can improve data security, optimize system performance, facilitate the management of storage resources, and control storage costs.

[0043] In the related art, there are mainly two read and write speed limit schemes. The first one is that all the input and output (IO) commands obtained by the back end from the front end are placed in a shared buffer (buf). Since the write command and the read command share a buffer, if the current queue (queue) exit is waiting for the write command, and the write operation is restricted at this time, the queue will be in a waiting state. The read command in the queue will be intercepted, and the head of the line blocking will be generated for the read command, thereby causing a large jitter for the speed limit of the read operation. The second one is to divide the buffer of the cache command into two parts, and the read command and the write command occupy a storage space respectively. Assume that the storage space corresponding to the write command is full, and the storage space corresponding to the read command is empty. However, since it is still unknown whether the next operation type on the front end (host) side is a read command or a write command, back pressure congestion will occur at this time. When the write operation processes a part of the data to release the waterline, it can continue to read new commands and it may be the turn to process the read operation. It can be seen that the second read and write speed limit scheme still has the problem of head of line blocking.

[0044] It can be seen that the method of limiting the reading and writing speed of storage devices in the related art is prone to head-of-line blocking problems.

[0045] In view of this, according to an embodiment of the present disclosure, a storage device reading and writing method embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0046] In this embodiment, a first storage device reading and writing method is provided, which can be used for the back end of the above storage device. Figure 1 is a flowchart of a first storage device reading and writing method according to an embodiment of the present disclosure, such as Figure 1 As shown, the process includes the following steps:

[0047] Step S101, in response to a processing instruction for a target submission queue in a front end of a storage device, mapping the target submission queue into a first submission queue and a second submission queue in a back end of the storage device, wherein the target submission queue includes at least one of a read command and a write command.

[0048] Specifically, the input / output (IO) commands of the Non-Volatile Memory Host Controller Interface Specification (NVME) protocol are stored in the target submission queue (SQ) at the front end of the storage device. The target submission queue is a ring based on head and tail pointers, and both read and write commands are stored in the target submission queue.

[0049] It should be noted that the first submission queue, the second submission queue and the target submission queue are the same.

[0050] Step S102: read the read commands in the first submission queue using the first data transmission channel, and write the read read commands into the read buffer.

[0051] Specifically, the first data transmission channel is a direct memory access (DMA) channel.

[0052] Specifically, the first data transmission channel reads the command in the first submission queue and determines the type of the read command. If the read command is a read command, the read command is written into the read buffer.

[0053] Step S103: read the write commands in the second submission queue using the second data transmission channel, and write the read write commands into the write buffer.

[0054] Specifically, the second data transmission channel is a direct memory access (DMA) channel.

[0055] Specifically, the second data transmission channel reads the command in the second submission queue and determines the type of the read command. If the read command is a write command, the read write command is written into the write buffer.

[0056] It can be understood that the first data transmission channel and the second data transmission channel can be used to read the first submission queue and the second submission queue respectively, so that the command pointed to by the current head pointer of the submission queue corresponding to each data transmission channel will not be blocked due to read and write speed limits or insufficient storage space in the buffer.

[0057] Step S104: Process the read command in the read buffer to perform a read operation.

[0058] Specifically, the read command is read in the read buffer using the first data transmission channel to perform a read operation.

[0059] Step S105: Process the write command in the write buffer to perform a write operation.

[0060] Specifically, the write command is read in the write buffer using the second data transmission channel to perform the write operation.

[0061] The storage device read and write method provided in this embodiment uses the first data transmission channel and the second data transmission channel to map the target submission queue at the front end of the storage device into the first submission queue and the second submission queue at the back end to process the read command and the write command respectively. Therefore, the read speed limit scenario and the write speed limit scenario do not affect each other, and can effectively solve the problem of head-of-queue blocking in the storage device speed limit scenario.

[0062] For ease of understanding, Figure 2 As shown, Figure 2 It is a schematic diagram of the read and write speed limit method in the first related technology. In the first related technology, all the input and output obtained by the back end from the front end are placed in a shared buffer. The Quality of Service (QoS) reads commands from the shared buffer and determines the type of command to perform corresponding operations. For example, based on the read command, data is read from the cloud disk or local disk, based on the write command, data of the storage device is read and written to the cloud disk or local disk, and after the command is processed, the processing completion information is written to the completion queue (Completion Queue, CQ) of the front end, so that the front end releases the storage unit of the completed command in the submission queue. Since the write command and the read command share a buffer, if the current queue (queue) exit of the shared buffer is waiting for the write command, and the write operation is restricted at this time, the queue will be in a waiting state. The read command in the queue will be intercepted, and the head of the line blocking will occur for the read command, thereby causing greater jitter for the speed limit of the read operation. For example Figure 3As shown in the figure, assume that the shared buffer queues read command 0, read command 1, write command 0, read command 2, write command 1, etc. If the command before write command 0 is processed, write command 0 is waiting in the queue at the exit. At this time, read command 2 needs to wait for write command 0 to be processed before it can be processed. If the write operation is restricted at this time, it will cause head-of-line blocking.

[0063] As for the second related art read and write speed limit method, such as Figure 4 As shown, the second related technology divides the buffer of cache commands into a read buffer and a write buffer, and the read commands and write commands are written to the corresponding buffers respectively. Assume that the write buffer is full and the read buffer is empty. However, since it is unknown whether the next operation type on the front end is a read command or a write command, back pressure congestion will occur at this time. When the write operation processes a part of the data to release the waterline, new commands can be read and the read operation can be processed. For example Figure 5 As shown, the read buffer stores read commands 0 to read commands n, and there are free units. At this time, the write buffer is full. Since the back end does not know whether the next command obtained from the front end is a read command or a write command, back pressure blocking will occur. It is necessary to wait for the write buffer to release some space before continuing to read new commands and it may be the turn to process the read operation.

[0064] From the above analysis, it can be seen that for the first related technology, the back end of the storage device does not know the command type pointed to by the current head pointer before fetching the command of the front end submission queue. If it only processes a read command or a write command in a conventional way, it will inevitably encounter the head of line blocking problem. For the second related technology, if conventional single-channel processing is adopted, it is necessary to move all the descriptors of the entire front end submission queue to the back end for storage in order to completely solve the head of line blocking problem, which is obviously unrealistic.

[0065] Compared with the two related technologies, Figure 6 As shown, in the storage device read and write method disclosed in the present invention, the back end of the storage device maps the target submission queue of the front end into the first submission queue and the second submission queue to process the read command and the write command respectively, thereby avoiding the limitation brought by one submission queue corresponding to one data transmission channel. At the same time, since the two data transmission channels can read the target submission queue at the same time, the queue of the head pointer of the submission queue corresponding to each data transmission channel will not be blocked by the head of the queue due to the read and write speed limit or insufficient storage space of the read and write buffer.

[0066] In this embodiment, a second storage device reading and writing method is provided, which can be used for the back end of the above storage device. Figure 7 is a flow chart of a second storage device reading and writing method according to an embodiment of the present disclosure, such as Figure 7 As shown, the process includes the following steps:

[0067] Step S701, in response to a processing instruction for a target submission queue at the front end of the storage device, the target submission queue is mapped to a first submission queue and a second submission queue at the back end of the storage device, wherein the target submission queue includes at least one of a read command and a write command. Please refer to the above step S101, which will not be described in detail here.

[0068] Step S702: read the read commands in the first submission queue using the first data transmission channel, and write the read commands into the read buffer.

[0069] Specifically, the above step S702 includes:

[0070] Step S7021, obtaining a first head pointer and a first tail pointer of a first submission queue.

[0071] Specifically, a first head pointer and a first tail pointer of a first submission queue are obtained by using a first data transmission channel.

[0072] Step S7022: If the first head pointer is different from the first tail pointer, the read command in the first submission queue is read using the first data transmission channel, and the read command is written into the read buffer.

[0073] It can be understood that if the first head pointer is different from the first tail pointer, it indicates that there are unread commands in the first submission queue. Therefore, when the first head pointer is different from the first tail pointer, the first data transmission channel is used to continue reading the read commands in the first submission queue, and the read commands are written to the read buffer. If the first head pointer is the same as the first tail pointer, it indicates that all commands in the first submission queue have been read, and the reading of the read commands in the first submission queue is stopped at this time.

[0074] Step S703: read the write commands in the second submission queue using the second data transmission channel, and write the read write commands into the write buffer.

[0075] Specifically, the above step S703 includes:

[0076] Step S7031, obtaining a second head pointer and a second tail pointer of the second submission queue.

[0077] Specifically, the second data transmission channel is used to obtain the second head pointer and the second tail pointer of the second submission queue.

[0078] Step S7032: If the second head pointer is different from the second tail pointer, the write command in the second submission queue is read using the second data transmission channel, and the read write command is written into the write buffer.

[0079] It can be understood that if the second head pointer is different from the second tail pointer, it indicates that there are unread commands in the second submission queue. Therefore, when the second head pointer is different from the second tail pointer, the second data transmission channel is used to continue reading the write commands in the second submission queue, and the read write commands are written to the write buffer. If the second head pointer is the same as the second tail pointer, it indicates that all commands in the second submission queue have been read, and the reading of the write commands in the second submission queue is stopped at this time.

[0080] Step S704: Process the read command in the read buffer to perform a read operation. Please refer to the above step S104, which will not be described in detail here.

[0081] Step S705: Process the write command in the write buffer to perform a write operation. Please refer to the above step S105, which will not be described in detail here.

[0082] In the storage device read and write method provided in this embodiment, if the first head pointer and the first tail pointer of the first submission queue are different, the first data transmission channel is used to read the read command in the first submission queue. Therefore, the state of the first submission queue can be accurately determined by using the first head pointer and the first tail pointer. If the second head pointer and the second tail pointer are different, the write command in the second submission queue is read by using the second data transmission channel. Therefore, the state of the second submission queue can be accurately determined by using the second head pointer and the second tail pointer to avoid data reading errors or program logic errors in the first submission queue and the second submission queue.

[0083] In some optional implementations, the step S7022 of reading the read command in the first submission queue by using the first data transmission channel and writing the read read command to the read buffer includes:

[0084] Step a1: read the first target command in the first submission queue by using the first data transmission channel, and update the first head pointer.

[0085] It should be noted that the queue follows the data structure of the "first in, first out" principle. In actual operation, the first data transmission channel starts reading the first target command in the first submission queue from the position pointed to by the first head pointer. Whenever a first target command is read, the first head pointer is updated to point to the position of the next first target command.

[0086] Step a2: if the first target command is a read command, write the first target command into the read buffer.

[0087] Specifically, the first target command is type-judged using the first data transmission channel, and if the first target command is a read command, the first target command is written into the read buffer, and if the first target command is a write command, the first target command is discarded.

[0088] The storage device reading and writing method provided in this embodiment uses the first data transmission channel to read the first target command in the first submission queue. If the first target command is a read command, the first target command is written to the read buffer. Therefore, the commands written to the read buffer can be filtered to avoid head-of-line blocking when processing the commands in the read buffer. At the same time, storage resources can be saved.

[0089] In some optional implementations, the step S7032 of reading the write command in the second submission queue by using the second data transmission channel and writing the read write command to the write buffer includes:

[0090] Step b1, read the second target command in the second submission queue by using the second data transmission channel, and update the second head pointer.

[0091] Specifically, the second data transmission channel starts reading the second target commands in the second submission queue from the position pointed to by the second head pointer, and each time a second target command is read, the second head pointer is updated to point to the position of the next second target command.

[0092] Step b2: If the second target command is a write command, write the second target command into the write buffer.

[0093] Specifically, the second target command is judged by using the second data transmission channel, and if the second target command is a write command, the second target command is written into the write buffer, and if the second target command is a read command, the second target command is discarded.

[0094] The storage device reading and writing method provided in this embodiment uses the second data transmission channel to read the second target command in the second submission queue. If the second target command is a write command, the second target command is written to the write buffer. Therefore, the commands written to the write buffer can be filtered to avoid head-of-line blocking when processing the commands in the write buffer. At the same time, storage resources can be saved.

[0095] For example, Figure 8As shown, it is assumed that 13 commands are filled in the target submission queue, which are read commands 0-9, write command 0, write command 1, and read command 10. The next unit of read command 10 is an idle unit. The head pointer of the target submission queue points to read command 0, and the tail pointer of the target submission queue points to the next idle unit of read command 10. The first submission queue and the second submission queue mapped by the target submission queue are the same as the target submission queue. Assuming that there are a small number of emergencies in the processing of read commands at this time, the processing in the relevant technology will block the processing of subsequent write commands. Assuming that the first data transmission channel reads 8 commands for the first time, all 8 commands are read commands, and the read read commands are cached in the corresponding read buffer waiting for scheduling. The state of the first head pointer of the first data transmission channel is updated to point to read command 8. Assuming that the front end no longer issues new commands at this time, the first tail pointer remains unchanged. If the front end issues a new command, the first tail pointer is updated to point to the next unit of the last command in the first submission queue. Since the first head pointer is different from the first tail pointer at this time, it shows that there are still commands to be processed, so the second command read of the first submission queue is initiated, and the remaining 5 commands are read. Among them, 3 read commands and 2 write commands are read. The 3 read commands are written to the read buffer, and the 2 write commands are discarded. At the same time, the first head pointer is updated to the next unit of the last command, that is, the first head pointer is the same as the first tail pointer, which means that there are no pending commands in the first submission queue, waiting for new command notification.

[0096] Similarly, the second data transmission channel reads 8 commands for the first time, and all 8 commands are read commands. Since the second data transmission channel processes write commands, all 8 read commands are discarded. The local second head pointer state of the second data transmission channel is updated to point to read command 8. Assuming that the front end no longer issues new commands at this time, the second tail pointer remains unchanged. If the front end issues a new command, the second tail pointer is updated to point to the next unit of the last command in the second submission queue. Since the second head pointer is different from the second tail pointer at this time, it shows that there are still commands to be processed, so the second command reading of the second submission queue is initiated, and the remaining 5 commands are read. Among them, 3 read commands and 2 write commands are read. The 3 read commands are discarded, and the 2 write commands are written to the write buffer. At the same time, the second head pointer is updated to the next unit of the last command, that is, the second head pointer is the same as the second tail pointer, which means that there are no pending commands in the second submission queue, waiting for new command notification.

[0097] It is understandable that in actual operation, the first data transmission channel and the second data transmission channel are affected by factors such as the waterline back pressure of the corresponding buffer and the consumption of the speed limit token. The commands of the first data transmission channel and the second data transmission channel to read the submission queue are not synchronized. Therefore, it is necessary to wait for the head and tail pointers of the first data transmission channel and the second data transmission channel to be aligned, that is, the first head pointer is the same as the first tail pointer, and the second head pointer is the same as the second tail pointer, before judging that both submission queues at the back end are empty. When the life cycle of the submission queue stops, the emptying judgment is made based on the fact that both submission queues at the back end are empty.

[0098] It should be noted that the first data transmission channel and the second data transmission channel are executed in parallel. After the first data transmission channel and the second data transmission channel process the corresponding commands, they will feed back the command completion information to the front end and write it into the completion queue of the front end. The release of the target submission queue of the front end depends on the completion status of the completion queue. Therefore, the update and release of the target submission queue of the front end are unified for the first data transmission channel and the second data transmission channel.

[0099] It is worth noting that in the storage device reading and writing method disclosed in the present invention, since the dual-channel direct memory access interface (i.e., the first data transmission channel and the second data transmission channel) is opened, the read command and the write command each occupy a direct memory access interface, and the first data transmission channel and the second data transmission channel both carry the command normally. Since the first and second data transmission channels do not know the type of command to be read before reading the corresponding submission queue, only after reading the command can the unnecessary commands be filtered out according to the properties of the current data transmission channel (also known as dma chn properties), and the remaining commands are stored in the corresponding buffer. Therefore, when the token bucket speed limit is performed at the exit of the read buffer and the write buffer, there will be no head-of-line blocking at the exit of the read buffer and the write buffer, and independent speed limit for reading and writing can be accurately performed.

[0100] For example, Fig. 9 As shown, after reading the command, the first data transmission channel determines the type of the command. If it is a read command, it is stored in the read buffer, for example, read command 0 to read command n are stored in the read buffer. If it is a write command, the command is discarded. Then, the read command in the read buffer is processed. Similarly, after reading the command, the second data transmission channel determines the type of the command. If it is a write command, it is stored in the write buffer, for example, write command 0 to write command m are stored in the write buffer. If it is a read command, the command is discarded. Then, the write command in the write buffer is processed.

[0101] In this embodiment, a third storage device reading and writing method is provided, which can be used for the back end of the above storage device. Fig.10is a flow chart of a second storage device reading and writing method according to an embodiment of the present disclosure, such as Fig.10 As shown, the process includes the following steps:

[0102] Step S1001, in response to a processing instruction for a target submission queue at the front end of a storage device, the target submission queue is mapped to a first submission queue and a second submission queue at the back end of the storage device, wherein the target submission queue includes at least one of a read command and a write command. Please refer to the above step S101, which will not be described in detail here.

[0103] Step S1002: read the read commands in the first submission queue using the first data transmission channel, and write the read commands into the read buffer. Please refer to the above step S702, which will not be described in detail here.

[0104] Step S1003: read the write command in the second submission queue using the second data transmission channel, and write the read write command into the write buffer. Please refer to the above step S703, which will not be described in detail here.

[0105] Step S1004: Process the read command in the read buffer to perform a read operation. Please refer to the above step S104, which will not be described in detail here.

[0106] Step S1005: Process the write command in the write buffer to perform a write operation. Please refer to the above step S105, which will not be described in detail here.

[0107] Step S1006: if the read buffer reaches a first preset storage threshold, back pressure is applied to the reading of the read commands in the first submission queue.

[0108] Optionally, the first preset storage threshold is the number of storage units in the read buffer, or is the maximum storage capacity of the read buffer, and the first preset storage threshold may be adjusted according to actual conditions.

[0109] Step S1007: if the write buffer reaches the second preset storage threshold, back pressure is applied to the reading of write commands in the second submission queue.

[0110] Optionally, the second preset storage threshold is the number of storage units in the write buffer, or is the maximum storage capacity of the write buffer, and the second preset storage threshold may be adjusted according to actual conditions.

[0111] In the storage device read and write method provided by this embodiment, if the read buffer reaches the first preset storage threshold, back pressure is applied to the reading of the read command in the first submission queue. Therefore, the reading of the read command in the first submission queue can be paused or slowed down. If the write buffer reaches the second preset storage threshold, back pressure is applied to the reading of the write command in the second submission queue. Therefore, the reading of the write command in the second submission queue can be paused or slowed down to avoid data loss or system crash.

[0112] In this embodiment, a fourth storage device reading and writing method is provided, which can be used for the back end of the above storage device. Fig.11 is a flowchart of a third storage device reading and writing method according to an embodiment of the present disclosure, such as Fig.11 As shown, the process includes the following steps:

[0113] Step S1101, in response to a processing instruction for a target submission queue at the front end of the storage device, the target submission queue is mapped to a first submission queue and a second submission queue at the back end of the storage device, wherein the target submission queue includes at least one of a read command and a write command. Please refer to the above step S101, which will not be described in detail here.

[0114] Step S1102: read the read command in the first submission queue using the first data transmission channel, and write the read command into the read buffer. Please refer to the above step S702, which will not be described in detail here.

[0115] Step S1103: read the write command in the second submission queue using the second data transmission channel, and write the read write command into the write buffer. Please refer to the above step S703, which will not be described in detail here.

[0116] Step S1104, processing the read command in the read buffer to perform a read operation. Please refer to the above step S104, which will not be described in detail here.

[0117] Step S1105, processing the write command in the write buffer to perform a write operation. Please refer to the above step S105, which will not be described in detail here.

[0118] Step S1106 , in response to the speed limit instruction for the read buffer, the processing of the read commands in the read buffer is speed limited.

[0119] Specifically, the first data transmission channel limits the speed of processing the read commands in the read buffer in response to the speed limit instruction for the read buffer.

[0120] Step S1107 , in response to the speed limit instruction for the write buffer, speed limit is imposed on the processing of the write commands in the write buffer.

[0121] Specifically, the second data transmission channel limits the speed of processing the write commands in the write buffer in response to the speed limit instruction for the write buffer.

[0122] The storage device read and write method provided in this embodiment, in response to the speed limit instruction for the read buffer, limits the speed of the processing of the read command in the read buffer. Therefore, the data transmission rate at the exit of the read buffer can be limited, so as to avoid excessive consumption of system resources due to too fast data transmission, and also avoid system crash or instability caused by the processing of a large number of read commands, thereby improving the stability and reliability of the read command processing. In response to the speed limit instruction for the write buffer, the processing of the write command in the write buffer is limited. Therefore, the data transmission rate at the exit of the write buffer can be limited, so as to avoid excessive consumption of system resources due to too fast data transmission, and also avoid system crash or instability caused by the processing of a large number of write commands, thereby improving the stability and reliability of the write command processing.

[0123] For example, Fig.12 , open two sets of direct memory access channels in the computer bus interface standard (Peripheral Component Interconnect Express, PCle for short), namely the first data transmission channel for processing read commands and the second data transmission channel for processing write commands. The front-end driver sends a notification of the message passing mechanism, and simultaneously updates the two tail pointer states of the first data transmission channel and the second data transmission channel to obtain the first head pointer and the first tail pointer of the first submission queue. Then, the first data transmission channel and the second data transmission channel each maintain the corresponding head pointer and tail pointer states, and respectively initiate a read request of the target submission queue to the front end. Among them, the first data transmission channel reads the first target command of the first submission queue mapped by the target submission queue, and the second data transmission channel reads the second target command of the second submission queue mapped by the target submission queue.

[0124] Furthermore, the first data transmission channel determines whether the first head pointer is different from the first tail pointer. If they are the same, it continues to return to determine whether the first head pointer is different from the first tail pointer. If they are different, it is determined whether the read buffer is not full. If it is full, the read request of the first data transmission channel is back-pressured. If it is not full, the first data transmission channel reads the first target command of the first submission queue mapped by the target submission queue. It is determined whether the first target command is a read command. If it is not a read command, the first target command is discarded and the first head pointer is updated, that is, the first head pointer jumps plus 1. If it is a read command, the first target command is written into the read buffer and the first head pointer is updated, that is, the first head pointer jumps plus 1. It is determined whether the processing of the read command in the read buffer is speed-limited. If it is speed-limited, the processing of the read command in the read buffer is speed-limited. If it is not speed-limited, it is re-determined whether the processing of the read command in the read buffer is speed-limited, that is, input output / byte (also known as IO / Byte) speed limit.

[0125] Similarly, the second data transmission channel determines whether the second head pointer is different from the second tail pointer. If they are the same, it continues to return to determine whether the second head pointer is different from the second tail pointer. If they are different, it is determined whether the write buffer is not full. If it is full, the read request of the second data transmission channel is back-pressured. If it is not full, the second data transmission channel reads the second target command of the second submission queue mapped by the target submission queue. Determine whether the second target command is a write command. If it is not a write command, discard the second target command. Update the second head pointer, that is, the second head pointer jumps plus 1. If it is a write command, write the second target command to the write buffer, and update the second head pointer, that is, the second head pointer jumps plus 1. Determine whether to limit the speed of the processing of the write command in the write buffer. If it is limited, the processing of the write command in the write buffer is limited. If not limited, re-determine whether to limit the speed of the processing of the write command in the write buffer, that is, input and output / byte speed limit.

[0126] It can be understood that the first data transmission channel and the second data transmission channel perform back pressure on the commands of the read submission queue according to the empty and full status of the corresponding buffers. At this time, the read commands and the write commands are completely isolated, and there will be no head-of-line blocking problem.

[0127] As a specific application example, a target program is installed on the back end of a storage device, and the target program is used to read and write the storage device. In the target program, the storage device read and write method disclosed in the present invention can be used in the back end by virtualizing the target submission queue of the front end into a first submission queue and a second submission queue at the back end, so as to be used for processing read commands and write commands respectively. At the same time, command type filtering is performed on the data transmission channel corresponding to the read command and the write command. Therefore, the head of line blocking problem of the two key points of the front-end and back-end interaction part of the storage device and the internal storage buffer can be effectively solved, and the read and write decoupling is realized and storage resources are saved. At the same time, under the condition of solving the head of line blocking problem, it can also ensure that the number of bits per second (Bits Per Second, referred to as bps) and the number of input / output operations per second (Input / Output Operations Per Second, referred to as iops) are both jitter-free. Compared with the read and write speed limit scheme in the related art, the number of cached read commands and write commands is consistent, and no additional storage resources are added.

[0128] In the present embodiment, a storage device reading and writing device is also provided, and the device is used to implement the above-mentioned embodiment and preferred implementation mode, and the description has been made no further. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceived.

[0129] This embodiment provides a storage device reading and writing device, such as Fig.13 As shown, including:

[0130] A queue mapping module 1301, for responding to a processing instruction for a target submission queue at a front end of a storage device, mapping the target submission queue to a first submission queue and a second submission queue at a back end of the storage device, wherein the target submission queue includes at least one of a read command and a write command;

[0131] A read command writing module 1302 is used to read the read commands in the first submission queue by using the first data transmission channel, and write the read commands into the read buffer;

[0132] A write command writing module 1303 is used to read the write command in the second submission queue by using the second data transmission channel, and write the read write command into the write buffer;

[0133] A read command processing module 1304 is used to process the read command in the read buffer to perform a read operation;

[0134] The write command processing module 1305 is used to process the write command in the write buffer to perform a write operation.

[0135] In some optional implementations, the read command writing module 1302 includes:

[0136] A first pointer acquisition unit, used to acquire a first head pointer and a first tail pointer of a first submission queue;

[0137] The read command processing unit is used for reading the read command in the first submission queue by using the first data transmission channel if the first head pointer is different from the first tail pointer, and writing the read command into the read buffer.

[0138] In some optional implementations, the first pointer acquiring unit includes:

[0139] A first command reading subunit is used to read a first target command in a first submission queue by using a first data transmission channel, and update a first head pointer;

[0140] The read command processing subunit is configured to write the first target command into the read buffer if the first target command is a read command.

[0141] In some optional implementations, the write command writing module 1303 includes:

[0142] A second pointer acquisition unit, used to acquire a second head pointer and a second tail pointer of a second submission queue;

[0143] The write command processing unit is configured to read the write command in the second submission queue by using the second data transmission channel if the second head pointer is different from the second tail pointer, and write the read write command into the write buffer.

[0144] In some optional implementations, the second pointer acquiring unit includes:

[0145] A second command reading subunit is used to read a second target command in the second submission queue by using a second data transmission channel, and update a second head pointer;

[0146] The write command processing subunit is configured to write the second target command into the write buffer if the second target command is a write command.

[0147] In some optional implementations, the storage device reading and writing apparatus of the present disclosure further includes:

[0148] A first back pressure module, configured to perform back pressure on the reading of the read commands in the first submission queue if the read buffer reaches a first preset storage threshold;

[0149] The second back pressure module is used to perform back pressure on the reading of the write command in the second submission queue if the write buffer reaches a second preset storage threshold.

[0150] In some optional implementations, the storage device reading and writing apparatus of the present disclosure further includes:

[0151] A first speed limiting module, configured to limit the speed of processing the read command in the read buffer in response to a speed limiting instruction for the read buffer;

[0152] The second speed limiting module is used to limit the speed of processing the write command in the write buffer in response to the speed limiting instruction for the write buffer.

[0153] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0154] The storage device reading and writing device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0155] The present disclosure also provides an electronic device having the above Fig.13 The storage device reading and writing device shown.

[0156] See also Fig.14 , Fig.14 is a structural block diagram of an electronic device provided by an optional embodiment of the present disclosure, such as Fig.14 As shown, the electronic device includes: one or more processors 1401, memory 1402, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the electronic device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple electronic devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig.14 A processor 1401 is taken as an example.

[0157] The processor 1401 may be a central processing unit, a network processor or a combination thereof. The processor 1401 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable logic gate array, a general purpose array logic or any combination thereof.

[0158] The memory 1402 stores instructions executable by at least one processor 1401 , so that the at least one processor 1401 executes the method shown in the above embodiment.

[0159] The memory 1402 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the electronic device, etc. In addition, the memory 1402 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 1402 may optionally include a memory remotely arranged relative to the processor 1401, and these remote memories may be connected to the electronic device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0160] The memory 1402 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 1402 may also include a combination of the above types of memory.

[0161] The electronic device also includes an input device 1403 and an output device 1404. The processor 1401, the memory 1402, the input device 1403 and the output device 1404 may be connected via a bus or other means. Fig.14 The example of connecting through bus is taken in the following.

[0162] The input device 1403 can receive input digital or character information, and generate key signal input related to the user settings and function control of the electronic device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator rod, one or more mouse buttons, a trackball, a joystick, etc. The output device 1404 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0163] The embodiments of the present disclosure also provide a computer-readable storage medium. The above-mentioned method according to the embodiments of the present disclosure can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium and downloaded through a network, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0164] A part of the present disclosure may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present disclosure through the operation of the computer. Those skilled in the art should understand that the existence of computer program instructions in computer-readable media includes, but is not limited to, source files, executable files, installation package files, etc., and accordingly, the way in which computer program instructions are executed by a computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to the computer.

[0165] Although the embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A storage device reading and writing method, characterized in that: The method comprises: In response to a processing instruction for a target submission queue of a front end in the storage device, mapping the target submission queue into a first submission queue and a second submission queue of a back end in the storage device, the target submission queue including at least one of a read command and a write command; Using a first data transmission channel to read the read commands in the first submission queue, and writing the read read commands into a read buffer; Using a second data transmission channel to read the write command in the second submission queue, and writing the read write command into a write buffer; Processing the read command in the read buffer to perform a read operation; The write command in the write buffer is processed to perform a write operation.

2. The method according to claim 1, characterized in that: The method of reading the read command in the first submission queue by using the first data transmission channel and writing the read read command into the read buffer includes: Obtain a first head pointer and a first tail pointer of the first submission queue; If the first head pointer is different from the first tail pointer, the read command in the first submission queue is read using the first data transmission channel, and the read command is written into the read buffer.

3. The method according to claim 2, characterized in that The step of reading the read command in the first submission queue by using the first data transmission channel and writing the read read command into the read buffer includes: Using the first data transmission channel, reading the first target command in the first submission queue, and updating the first head pointer; If the first target command is a read command, the first target command is written into the read buffer.

4. The method according to claim 1, characterized in that: The method of reading the write command in the second submission queue by using the second data transmission channel and writing the read write command into the write buffer includes: Get the second head pointer and the second tail pointer of the second submission queue; If the second head pointer is different from the second tail pointer, the write command in the second submission queue is read using the second data transmission channel, and the read write command is written into the write buffer.

5. The method according to claim 4, characterized in that The using the second data transmission channel to read the write command in the second submission queue and writing the read write command into the write buffer includes: Using the second data transmission channel, reading the second target command in the second submission queue, and updating the second head pointer; If the second target command is a write command, the second target command is written into the write buffer.

6. The method according to claim 1, characterized in that The method further comprises: If the read buffer reaches a first preset storage threshold, back pressure is applied to the reading of the read commands in the first submission queue; If the write buffer reaches a second preset storage threshold, back pressure is applied to the reading of write commands in the second submission queue.

7. The method according to claim 1, characterized in that The method further comprises: In response to a speed limit instruction for the read buffer, speed limit the processing of read commands in the read buffer; In response to the speed limit instruction for the write buffer, the processing of the write command in the write buffer is speed limited.

8. A storage device reading and writing device, characterized in that: The device comprises: a queue mapping module, for mapping the target submission queue into a first submission queue and a second submission queue in a back end of the storage device in response to a processing instruction for the target submission queue in the front end of the storage device, the target submission queue including at least one of a read command and a write command; A read command writing module, used for reading the read commands in the first submission queue by using the first data transmission channel, and writing the read read commands into the read buffer; A write command writing module, used for reading the write commands in the second submission queue by using the second data transmission channel, and writing the read write commands into the write buffer; A read command processing module, used for processing the read command in the read buffer to perform a read operation; The write command processing module is used to process the write command in the write buffer to perform a write operation.

9. An electronic device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the storage device reading and writing method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the storage device reading and writing method according to any one of claims 1 to 7.

11. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to enable a computer to execute the storage device reading and writing method according to any one of claims 1 to 7.

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