Memory management method and memory controller

Abstract

The present disclosure provides a memory management method and a memory controller thereof. The method comprises: obtaining a first voltage value of a first data read operation; setting the first voltage value and a first read parameter to an integrated read module; obtaining a second voltage value of a second data read operation in parallel while the integrated read module performs the first data read operation; and setting the second voltage value and a second read parameter to the integrated read module to perform the second data read operation in response to completion of the first data read operation. The present disclosure significantly improves the data read efficiency of the storage device in the error handling process by integrating the read steps and implementing parallel processing.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of memory, in particular to a memory management method and a memory controller thereof. BACKGROUND

[0002] In modern storage technology, the NAND Flash has been widely used in storage devices such as SSD. During the operation of the storage device, data read errors may occur, and the error handling mechanism is needed to ensure the correct reading of data.

[0003] In the traditional error handling process, firmware needs to perform special processing on the error data, and an important step is to adjust the read voltage of the NAND Flash to ensure that the correct data can be read. However, this process involves multiple steps, including setting the voltage value, checking whether the set voltage value is correct, reading the original data on the NAND Flash, and transmitting the data. These steps are not only cumbersome to operate, but also occupy a lot of time during execution, thereby affecting the overall read-write performance of the storage device. SUMMARY

[0004] The present disclosure provides a memory management method and a memory controller thereof to solve the technical problem of long time consumption in the error handling process of the prior art.

[0005] One or more embodiments of the present disclosure provide a memory management method suitable for a storage device configured with a NAND Flash module. The method comprises: obtaining a first voltage value corresponding to a first data read operation of first data; setting the first voltage value and a first read parameter corresponding to the first data to an integrated read module, so as to execute the first data read operation via the integrated read module; obtaining a second voltage value corresponding to a second data read operation of second data in parallel when executing the first data read operation; and in response to completion of the first data read operation, setting the second voltage value and a second read parameter corresponding to the second data to the integrated read module, so as to execute the second data read operation via the integrated read module.

[0006] In one or more embodiments of the present disclosure, the first read parameter comprises one or more of: a target physical address of the first data in the NAND Flash module; a first data length of the first data; physical page size information of the first data; a read mode identifier of the first data; an error detection parameter of the first data; and metadata of the first data.

[0007] In one or more embodiments of the present application, wherein the method further comprises: if the first data read operation fails, obtaining another first voltage value for re-reading the first data, wherein the another first voltage value is different from the first voltage value; and setting the another first voltage value and the first read parameters to the integrated read module to re-execute the first data read operation via the integrated read module.

[0008] In one or more embodiments of the present application, wherein during the execution of the first data read operation: if the first data read operation fails, the execution of the second data read operation is suspended until the first data read operation is confirmed to be successfully completed.

[0009] In one or more embodiments of the present application, wherein the method further comprises: storing the first voltage value used in each execution of the first data read operation and the corresponding first read result; and determining an optimal voltage value for reading the first data based on the first voltage value and the first read result.

[0010] In one or more embodiments of the present application, wherein determining the optimal voltage value comprises: recording a plurality of first voltage values and a plurality of corresponding first read error bit numbers; and taking a specific first voltage value corresponding to the least first read error bit number as the optimal voltage value.

[0011] In one or more embodiments of the present application, wherein the integrated read module executing the first data read operation comprises: sending a read command sequence to the rewritable non-volatile memory module based on the first voltage value and the first read parameters; and obtaining the read first data from the rewritable non-volatile memory module.

[0012] In one or more embodiments of the present application, wherein the integrated read module comprises: a parameter configuration module for storing the first voltage value and the first read parameters; a command generation module for generating a read command sequence for the rewritable non-volatile memory module according to the first voltage value and the first read parameters; an execution module for sending the read command sequence to the rewritable non-volatile memory module and receiving the read first data; and a status feedback module for storing the execution status information of the first data read operation.

[0013] In one or more embodiments of the present application, wherein the rewritable non-volatile memory module comprises a plurality of storage planes, each of the storage planes has a corresponding register group and a command queue; and the integrated read module is configured to perform parallel parameter setting for the read operation of the second data located in different storage planes when executing the first data read operation.

[0014] In one or more embodiments of the present application, the method further comprises: determining whether the first data and the second data are located in different storage planes; and in response to the first data and the second data being located in different storage planes, triggering execution of the second data read operation before the first data read operation is completed.

[0015] One or more embodiments of the present application provide a memory controller for controlling a storage device configured with a rewritable non-volatile memory module. The memory controller comprises a memory interface control circuit electrically connected to the rewritable non-volatile memory module; and a processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to a connection interface circuit of the storage device to be electrically connected to a host system. Wherein, the processor is configured to: obtain a first voltage value corresponding to a first data read operation of first data; set the first voltage value and a first read parameter corresponding to the first data to an integrated read module to execute the first data read operation via the integrated read module; obtain a second voltage value corresponding to a second data read operation of second data in parallel when the integrated read module executes the first data read operation; and in response to the first data read operation being completed, set the second voltage value and a second read parameter corresponding to the second data to the integrated read module to execute the second data read operation via the integrated read module.

[0016] Based on the above, the memory management method provided by the present disclosure effectively reduces the time for executing redundant codes by the firmware by integrating the conventional multiple read steps into a unified interface. At the same time, by calculating the voltage value required for the next read operation in parallel while executing the current data read operation, the parallel processing of the data read process is realized, the data read efficiency in the error processing flow is optimized, and thus the working efficiency of the storage device is enhanced. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 Block schematic diagram of a host system and a storage device shown in accordance with embodiments of the present application;

[0019] Figure 2 Flowchart of a memory management method shown in accordance with one embodiment of the present disclosure;

[0020] Figure 3A timing diagram of multiple data read operations according to an embodiment of the present disclosure;

[0021] Figure 4 A sequence diagram of data read operations between a processor, an integrated read module and a rewritable non-volatile memory module according to an embodiment of the present disclosure;

[0022] Figure 5 A timing diagram of multiple data read operations according to an embodiment of the present disclosure;

[0023] Figure 6 A timing diagram of multiple data read operations according to another embodiment of the present disclosure;

[0024] Figure 7 A timing diagram of multiple data read operations according to yet another embodiment of the present disclosure.

[0025] BRIEF DESCRIPTION OF DRAWINGS

[0026] 10: host system

[0027] 20: storage device

[0028] 110: processor (second processor)

[0029] 120: host memory

[0030] 130: data transfer interface circuit

[0031] 210: memory controller

[0032] 211: processor (first processor)

[0033] 212: data management circuit

[0034] 213: memory interface control circuit

[0035] 214: buffer memory

[0036] 220: rewritable non-volatile memory module

[0037] 230: connection interface circuit

[0038] S210-S240: step 300: integrated read module

[0039] 310: parameter configuration module

[0040] 320: command generation module

[0041] 330: execution module

[0042] 340: status feedback module

[0043] S401-S406, S410-S413, S420-S423: steps

[0044] A41: arrow

[0045] CV1, CV1.1: step of acquiring a first read voltage

[0046] SR1, SR1.1: step of setting a first read operation

[0047] TR1, TR1.1: performing a first read operation

[0048] CV2: step of acquiring a second read voltage

[0049] SR2: step of setting a second read operation

[0050] TR2: performing a second read operation

[0051] CV3: step of acquiring a third read voltage

[0052] SR3: step of setting a third read operation

[0053] TR3: performing a third read operation

[0054] T1, T2, T3: time point

[0055] TR1.2: performing another first read operation

[0056] CV1.2: step of acquiring another first read voltage

[0057] SR1.2: step of setting another first read operation

[0058] CV1.2: step of acquiring another first read voltage in advance

[0059] TR2: performing a second read operation DETAILED DESCRIPTION

[0060] Reference will now be made in detail to exemplary embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the different drawings and the description to refer to the same or like parts.

[0061] Figure 1 A block diagram of a host system and a storage device according to embodiments of the present application is shown. Please refer to Figure 1The host system 10 is, for example, a personal computer, a notebook computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor) and a host memory 120, and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled to (also referred to as electrically connected to) the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other by a system bus. In this embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 can be disposed on a host board of the host system 10.

[0062] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also referred to as a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0063] In this embodiment, the host system 10 is electrically connected to the storage device 20 through the data transfer interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transfer interface circuit 130.

[0064] In the present embodiment, the number of data transfer interface circuits 130 can be one or more. Through the data transfer interface circuits 130, the host board can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a Near Field Communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy memory storage device (e.g., iBeacon), or the like memory storage device based on various wireless communication technologies. In addition, the host board can also be electrically connected to various I / O devices such as a Global Positioning System (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, and the like via a system bus.

[0065] In the present embodiment, the data transfer interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In addition, data transfer between the data transfer interface circuit 130 and the connection interface circuit 230 is performed using the Non-Volatile Memory express (NVMe) communication protocol.

[0066] In addition, in another embodiment, the connection interface circuit 230 can be packaged in a chip with the memory controller 210, or the connection interface circuit 230 can be disposed outside a chip containing the memory controller 210.

[0067] In the present embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in the present embodiment, the host memory 120 can be a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), or the like. However, it must be understood that the present application is not limited thereto, and the host memory 120 can also be other suitable memories.

[0068] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in a hardware type or a firmware type and perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 220 according to instructions of the host system 10.

[0069] In more detail, the processor 211 in the memory controller 210 is a hardware with computing capability, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with a plurality of control instructions / program codes, and when the storage device 20 is in operation, the control instructions / program codes are executed to perform operations such as writing, reading and erasing data. In addition, in the present embodiment, the control instructions / program codes can also be executed to perform data reading operations to implement the memory management method for error handling procedures provided by the present application. The control instructions / program codes corresponding to the memory management method can also be implemented as circuit units in hardware form to implement the memory management method provided by the present application.

[0070] It is worth mentioning that, in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a micro-processor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar circuit components, and the present application is not limited thereto.

[0071] In the present embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the components of the memory controller 210 can also be considered as operations performed by the memory controller 210.

[0072] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used to accept the indication of the processor 211 to perform data transmission. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written into the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., a write operation is performed according to a write instruction from the host system 10). For another example, data is read from one or more physical units of the rewritable non-volatile memory module 220 (the data can be read from one or more storage units of one or more physical units) via the memory interface control circuit 213, and the read data is written into the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

[0073] The memory interface control circuit 213 is used to accept the indication of the processor 211 to perform a write (also referred to as programming) operation, a read operation, or an erase operation on the rewritable non-volatile memory module 220 in cooperation with the data management circuit 212.

[0074] In addition, the data to be written into the rewritable non-volatile memory module 220 is converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 transmits a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, the instruction sequence can include a write instruction sequence to instruct writing data, a read instruction sequence to instruct reading data, an erase instruction sequence to instruct erasing data, and corresponding instruction sequences to instruct various memory operations. The instruction sequence can include one or more signals, or data on a bus. The signal or data can include an instruction code or a program code. For example, in the read instruction sequence, an identification code of the read, a memory address, a physical address, and the like are included.

[0075] In addition, the memory controller 210 establishes a logical to physical address mapping table and a physical to logical address mapping table to record the mapping relationship between the logical address of a logical unit (e.g., a logical block, a logical page) configured to the rewritable non-volatile memory module 220 and the physical address of a physical unit (e.g., a physical erase unit / physical block, a physical page). In other words, the memory controller 210 can find the physical unit mapped by a logical unit (e.g., find the physical page mapped by a logical page; find the physical address mapped by a logical address) through the logical to physical address mapping table (also referred to as a logical to physical mapping table), and the memory controller 210 can find the logical unit mapped by a physical unit (e.g., find the logical page mapped by a physical page; find the logical address mapped by a physical address) through the physical to logical address mapping table (also referred to as a physical to logical mapping table).

[0076] In an embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data (e.g., various mapping tables, voltage adjustment level lists, read voltage lists, read results) used to manage the storage device 20, so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 216.

[0077] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (the memory interface control circuit 213) and is used to store user data sent by the host system 10.

[0078] In the present embodiment, each memory die (chip) of the rewritable non-volatile memory module 220 has a plurality of planes, and each plane has a plurality of physical blocks. Each physical block includes a plurality of physical programming units (also referred to as physical pages). Each physical page has a plurality of memory cells (also referred to as physical bytes or bytes), each of which corresponds to a physical address. The physical address is used to record the physical location of the data stored in the memory cell. It should be noted that the present application is not limited to the size of each physical page and logical page. The size of each byte is 8 bits, which is used to store 8-bit data.

[0079] Figure 2A flowchart of a memory management method according to one embodiment of the present disclosure.

[0080] In one embodiment, referring to Figure 2 In step S210, the memory controller 210 obtains a first voltage value corresponding to a first data read operation of the first data.

[0081] Specifically, when the storage device 20 needs to read data, the memory controller 210 first determines a first voltage value required for reading the first data. The first voltage value can be obtained by an algorithm calculation, which is used to ensure correct reading of data from the rewritable non-volatile memory module 220.

[0082] Then, in step S220, the memory controller 210 sets the first voltage value and a first read parameter corresponding to the first data to the integrated read module, so as to execute the first data read operation on the rewritable non-volatile memory module 220 via the integrated read module.

[0083] The first read parameter can include a target physical address of the first data in the rewritable non-volatile memory module 220, a first data length of the first data, physical page size information of the first data, a read mode identifier of the first data, an error detection parameter of the first data, and metadata of the first data.

[0084] In one embodiment, the memory controller 210 can flexibly configure the specific content of the first read parameter according to different application scenarios and read requirements.

[0085] Specifically, the target physical address is used to accurately locate the storage position of the first data in the rewritable non-volatile memory module 220, so as to ensure that the read operation can access the correct data area. The first data length parameter indicates the size of the data to be read, so that the memory controller 210 can accurately allocate the cache space required for the read operation. The physical page size information reflects the physical storage characteristics of the rewritable non-volatile memory module 220, which helps the memory controller 210 to optimize the read strategy of the data. The read mode identifier is used to indicate the specific mode of the current read operation, such as whether error checking is required or whether it is a continuous read mode, etc. The error detection parameter contains the verification information used to ensure data integrity, so that the memory controller 210 can timely discover and handle possible data errors. In addition, the metadata can also contain auxiliary information such as the timestamp of the data and the access authority, which has corresponding effects on various data management and read control.

[0086] Next, in step S230, when the integrated read module performs the first data read operation, the memory controller 210 obtains, in parallel, a second voltage value for a second data read operation of corresponding second data.

[0087] In this way, through this parallel processing mechanism, the memory controller 210 has started preparing the voltage value needed for the next read operation while performing the current read operation, thereby improving the data read efficiency.

[0088] In an embodiment, the memory controller 210 triggering the integrated read module to perform the first data read operation can be based on various conditions. For example, when the host system 10 sends a read request, the memory controller 210 checks the priority and urgency of the request. If it is a high-priority request, the memory controller 210 will immediately trigger the integrated read module to perform the read operation. In addition, when the memory controller 210 detects that the data in the rewritable non-volatile memory module 220 can be at risk of bit flipping, it will also actively trigger the read operation to ensure the integrity of the data. Alternatively, when performing maintenance tasks such as data verification, the memory controller 210 can also need to trigger the integrated read module to perform the read operation. It is worth mentioning that after receiving the trigger signal, the integrated read module will first verify whether the set parameters are valid to ensure that the read operation can proceed normally.

[0089] Then, in step S240, in response to the completion of the first data read operation, the memory controller 210 sets the second voltage value and the second read parameters corresponding to the second data to the integrated read module to perform the second data read operation on the rewritable non-volatile memory module 220 via the integrated read module.

[0090] It is worth mentioning that in this embodiment, the memory controller 210 significantly reduces the time for the firmware to execute redundant code by integrating the conventional multiple read steps into a unified interface and using a parallel processing mechanism. In addition, since the necessary parameters for the second data read operation are prepared during the execution of the first data read operation, the second data read operation can be started immediately after the completion of the first data read operation, further optimizing the overall read process.

[0091] In addition, in a specific implementation of this embodiment, the memory controller 210 can decide whether to continue performing the second data read operation by monitoring the execution status of the first data read operation. If the first data read operation fails, the memory controller 210 can need to re-execute the first data read operation using a different voltage value, at which time the execution of the second data read operation can be suspended.

[0092] In one embodiment, the memory controller 210 monitors the execution status of each operation in real time when performing a read operation via the consolidated read module. If the memory controller 210 detects that the first data read operation fails, the memory controller 210 will immediately initiate a data recovery mechanism.

[0093] In particular, the memory controller 210 first obtains another first voltage value for re-reading the first data according to a pre-defined voltage adjustment algorithm. This another first voltage value is different from the first voltage value used previously, and is usually adjusted appropriately according to the failure cause to improve the likelihood of a successful read.

[0094] In more detail, after obtaining the another first voltage value, the memory controller 210 sets this voltage value to the consolidated read module together with the original first read parameters. These first read parameters include information such as the target physical address, which remains unchanged because the read target is still the same first data. Subsequently, the memory controller 210 re-executes the first data read operation via the consolidated read module.

[0095] It is worth mentioning that in one embodiment, the memory controller 210 manages the execution status of the second data read operation simultaneously during this re-reading process. Since the failure of the first data read operation can imply a potential data integrity issue, the memory controller 210 will suspend the execution of the second data read operation.

[0096] In this way, through the above suspension mechanism, the memory controller continues to confirm that the first data read operation is successfully completed before starting to execute the read operation of the second data, to ensure the reliability and accuracy of data reading. Only after confirming that the first data has been successfully read, the memory controller 210 will resume the execution of the second data read operation. This strategy not only effectively prevents the spread of errors, but also ensures the orderly progress of data read operations.

[0097] In some embodiments, the memory controller 210 can set a maximum number of retries to avoid falling into an infinite retry loop in some extreme cases. In addition, the voltage value used each time can follow a specific adjustment pattern, such as stepwise increase or decrease, to improve the efficiency of retries.

[0098] Figure 3 A schematic diagram of a consolidated read module according to one embodiment of the present disclosure.

[0099] In one embodiment, please refer to Figure 3 The consolidated read module 300 is configured to execute data read instructions issued by the memory controller 210. The consolidated read module 300 includes a parameter configuration module 310, a command generation module 320, an execution module 330, and a status feedback module 340.

[0100] In one embodiment, the parameter configuration module 310 is configured to store various read parameters received from the memory controller 210. These parameters include the first voltage value and the first read parameters, which can include target physical address, data length, physical page size information, read mode identification, error detection parameters, and metadata, etc. The parameter configuration module 310 manages and stores these parameters uniformly, providing necessary configuration information for subsequent read operations.

[0101] In one embodiment, the command generation module 320 generates read command sequences for the rewritable non-volatile memory module 220 based on the parameter information stored in the parameter configuration module 310. These command sequences include complete read operation instructions, such as commands to set read voltage values, commands to perform data read, and commands for data transmission, etc. The command generation module 320 ensures that the generated command sequences comply with the communication protocol requirements of the rewritable non-volatile memory module 220.

[0102] In one embodiment, the execution module 330 is responsible for sending the read command sequences generated by the command generation module 320 to the rewritable non-volatile memory module 220, and receiving data returned from the rewritable non-volatile memory module 220. The execution module 330 manages the entire data transmission process, ensuring the correct execution of commands and reliable transmission of data.

[0103] In one embodiment, the status feedback module 340 is configured to store the execution status information of the read operation, including whether the operation is successfully completed, whether an error occurs, and other status information. These status information are fed back to the memory controller 210 in a timely manner, allowing it to understand the execution of the read operation in a timely manner and take appropriate handling measures when necessary.

[0104] In another embodiment, the memory controller 210 can take appropriate handling measures according to different execution states fed back by the status feedback module 340. Specifically, when the status feedback module 340 feeds back that the first data read operation fails, the memory controller 210 can take the following handling measures: first, the memory controller 210 analyzes the failure reason, such as checking whether the data read error is caused by an inappropriate read voltage value. If it is confirmed that it is a voltage value problem, the memory controller 210 selects another voltage value from the voltage adjustment gear list in the buffer memory 214 and re-executes the read operation through the integration read module 300.

[0105] In more detail, if the status feedback module 340 reports consecutive multiple read failures using different voltage values, the memory controller 210 can initiate a more complex error recovery mechanism. For example, the memory controller 210 can record all the attempted voltage values and their corresponding read results, and analyze the data to find the optimal read voltage value. Meanwhile, the memory controller 210 can also update the voltage adjustment table in the buffer memory 214, adding the newly discovered valid voltage value to the table to optimize future read operations.

[0106] In addition, when the status feedback module 340 reports frequent read errors in a certain storage area, the memory controller 210 can record this information in the buffer memory 214 for evaluating the reliability of the storage area (e.g., error frequency). If the error frequency exceeds a preset threshold, the memory controller 210 can actively initiate a data migration operation to transfer the data stored in the area to a more reliable storage area, thereby preventing possible data loss.

[0107] It is worth mentioning that the memory controller 210 will also optimize the parallel processing strategy according to the report of the status feedback module 340. For example, when it is found that certain types of read errors occur regularly, the memory controller 210 can adjust the scheduling strategy of parallel read operations to avoid performing parallel operations in these error-prone situations, thereby improving the overall read reliability.

[0108] It is worth mentioning that the modular design of the integrated read module 300 not only improves the maintainability of the code, but also realizes the standardized processing of read operations. By integrating multiple read steps into a unified interface, the operation process of the memory controller 210 is simplified, and the efficiency of data reading is improved. In addition, this design also supports parallel processing mechanism, allowing the preparation of parameters for the next read operation while the current read operation is being performed.

[0109] In some embodiments, the various sub-modules of the integrated read module 300 communicate through standardized internal interfaces, making it easier to upgrade and maintain the modules. For example, when it is necessary to support new read modes or optimize certain types of read operations, only the corresponding sub-modules need to be modified, without affecting the normal work of other modules.

[0110] In another embodiment, the integrated read module 300 achieves efficient data read operations through the cooperation of various components of the storage device 20.

[0111] In particular, the parameter configuration module 310 obtains the required parameters from the buffer memory 214 after receiving the read instruction from the memory controller 210. For example, when a data read operation requiring error handling is to be performed, the parameter configuration module 310 first reads the voltage adjustment level list from the buffer memory 214 to determine the appropriate read voltage value. Meanwhile, the parameter configuration module 310 also obtains the physical address information of the target data from the logical-to-physical address mapping table of the memory controller 210 to ensure accurate positioning of the data to be read.

[0112] In some embodiments, the command generation module 320 generates command sequences in compliance with the communication protocol of the rewritable non-volatile memory module 220 in cooperation with the memory interface control circuit 213 based on the information provided by the parameter configuration module 310. For example, when the read voltage value needs to be adjusted, the command generation module 320 generates a complete sequence including a voltage setting command, a voltage verification command, and a data read command. These command sequences are format-converted by the memory interface control circuit 213 to ensure that the rewritable non-volatile memory module 220 can correctly identify and execute them.

[0113] In some embodiments, during the data transmission phase, the execution module 330 coordinates the data transmission process through the data management circuit 212. After the execution module 330 sends the read command sequence, the data management circuit 212 is responsible for managing the data flow read from the rewritable non-volatile memory module 220. For example, in the error handling process, if the same data needs to be read multiple times using different voltage values, the execution module 330 cooperates with the data management circuit 212 to temporarily store the data read each time in the buffer memory 214 for subsequent data comparison and analysis.

[0114] In some embodiments, the status feedback module 340 maintains real-time status communication with the processor 211. After the execution module 330 completes a read operation, the status feedback module 340 records the execution result in the read result list of the buffer memory 214. The processor 211 can determine whether the read operation needs to be adjusted for re-execution by checking this status information in a timely manner. For example, if the status feedback module 340 reports a failed read operation, the processor 211 immediately obtains a new voltage value from the buffer memory 214 and initiates a new round of read operation through the parameter configuration module 310.

[0115] It is worth mentioning that the modular design allows the integrated read module 300 to fully utilize the functions of the various components of the storage device 20, while simplifying the operation process through a unified interface. For example, when processing an error handling request, the processor 211 only needs to send a read instruction to the integrated read module 300, and subsequent parameter acquisition, command generation, data transmission, and other complex operations will be completed by the various sub-modules of the integrated read module 300 in coordination, greatly reducing the burden on the processor 211.

[0116] Figure 4 A sequence diagram of a data read operation between a processor, an integrated read module, and a rewritable non-volatile memory module according to one embodiment of the present disclosure.

[0117] In one embodiment, referring to Figure 4 , the figure shows the interaction timing between the processor 211, the integrated read module 300, and the rewritable non-volatile memory module 220 when performing a data read operation.

[0118] Specifically, in step S401, the processor 211 first acquires a first voltage value for a first data read operation. Then, in step S402, the processor 211 sets the first voltage value and the first read parameters to the integrated read module 300 to perform the first data read operation (S410). While performing the first data read operation, the processor 211 acquires a second voltage value for a second data read operation in step S403 in parallel, embodying the parallel processing mechanism of the present disclosure.

[0119] In another embodiment, the processor 211 employs a specific processing mechanism to optimize data read operations when performing steps S402 and S403. Specifically, in step S402, the processor 211 first acquires configuration information of the first read parameters from the buffer memory 214. These configuration information includes the target physical address of the first data in the rewritable non-volatile memory module 220, the length of the first data, page size information, read mode identification, error detection parameters, and metadata, etc. The processor 211 transmits these parameters to the parameter configuration module 310 of the integrated read module 300 together with the acquired first voltage value for unified configuration. At the same time, the processor 211 will mark the status of these parameters in the buffer memory 214 to track the execution of the read operation subsequently.

[0120] Upon execution of step S403, the processor 211 will immediately initiate the calculation process of the second voltage value without waiting for the completion of the first data read operation. More specifically, the processor 211 will determine the appropriate voltage value for the second data read operation according to the pre-set voltage adjustment algorithm in combination with the voltage adjustment profile list stored in the buffer memory 214. This parallel processing mechanism allows the processor 211 to make full use of the execution time of the first data read operation to prepare the key parameters (e.g. the second voltage value) in advance for the second data read operation.

[0121] Subsequently, upon receiving the settings from the processor 211, the integrated read module 300 triggers and executes the first data read operation S410. Then in step S411, the integrated read module 300 generates and sends the first read command sequence to the rewritable non-volatile memory module 220. The rewritable non-volatile memory module 220 performs the corresponding read operation and returns the first data in step S412. Upon receiving the data, the integrated read module 300 transmits the first data to the processor 211 in step S413.

[0122] In another embodiment, the integrated read module 300 performs steps S411 to S413 by the collaborative work of its internal functional modules. Specifically, in step S411, the command generation module 320 first generates the complete first read command sequence according to the first voltage value and the first read parameters stored in the parameter configuration module 310. This command sequence contains multiple specific operation instructions such as the command to set the voltage value, the command to verify the voltage value, the command to read the data, etc. Subsequently, the execution module 330 sends these command sequences to the rewritable non-volatile memory module 220 according to a specific timing. In step S412, upon completion of the data read by the rewritable non-volatile memory module 220, the execution module 330 is responsible for receiving the returned first data. The execution module 330 will perform a preliminary integrity verification on the received data to ensure that no error has occurred during the data transmission. Meanwhile, the status feedback module 340 will record the status information of the data reception in real time for the reference of the processor 211.

[0123] In step S413, the execution module 330 transmits the verified first data to the processor 211, while the status feedback module 340 can generate a detailed operation status report containing the complete execution of the read operation, the data transmission status, and any abnormal situation that may occur. These information are transmitted to the processor 211 together, allowing it to understand the execution result of the read operation in time and decide the subsequent operation.

[0124] In another embodiment, the validation of the first data by the execution module 330 includes multiple levels. Specifically, the execution module 330 first checks the integrity of the data, such as ensuring that the data has not been corrupted or lost during transmission by using checksum or other mechanisms. In addition, the execution module 330 also verifies that the format of the data is as expected, such as whether the data length is correct, the data structure is complete, etc. If any abnormality is found, the execution module 330 immediately reports the error status to the processor 211 through the status feedback module 340.

[0125] Next, in step S404, the processor 211 determines whether the first data read operation is successfully completed.

[0126] If the first data read operation is successfully completed, the processor 211 then sets the second voltage value and the second read parameters to the integrated read module 300 in step S405 to perform the second data read operation. The integrated read module 300 then initiates the second data read operation in step S420 and generates and sends the second read command sequence to the rewritable non-volatile memory module 220 in step S421. After performing the read operation, the rewritable non-volatile memory module 220 returns the second data through step S422, and the integrated read module 300 then transmits the second data to the processor 211 in step S423. Finally, in step S406, the processor 211 determines whether the second data read operation is successfully completed.

[0127] In another embodiment, the memory controller 210 implements a complete voltage value optimization mechanism. Specifically, when the memory controller 210 performs multiple read operations for the first data, the processor 211 stores the first voltage value used each time and its corresponding read result in the buffer memory 214. These read results include detailed data correctness information, such as the number of error bits detected in each read operation.

[0128] More specifically, the processor 211 establishes a voltage value performance table to record each attempted first voltage value and its corresponding number of read error bits. For example, when using voltage value VI, 50 error bits are detected, when using voltage value V2, 30 error bits are detected, and when using voltage value V3, 20 error bits are detected. The processor 211 determines the voltage value that produces the least number of error bits as the optimal voltage value by analyzing these data.

[0129] In practical applications, the processor 211 can perform multiple rounds of testing to ensure the reliability of the results. For example, multiple read operations can be performed for each voltage value to reduce the impact of incidental factors by taking the average number of error bits. In addition, the processor 211 also stores the determined optimal voltage value in the buffer memory 214 to form a voltage optimization database. This database not only records the specific voltage value, but also contains corresponding usage scenario information, such as the storage area where the data is located, the temperature conditions during reading, etc., to provide a reference for subsequent read operations.

[0130] It is worth mentioning that the memory controller 210 also considers the stability of the read operation when determining the optimal voltage value. Specifically, if a certain voltage value produces the fewest error bits in a certain read operation, but the results of multiple tests fluctuate greatly, the processor 211 can choose a voltage value that performs more stably overall as the optimal voltage value. This strategy ensures that the read operation can maintain high reliability under different conditions.

[0131] In some embodiments, the processor 211 can periodically update the voltage optimization database to adapt to changes in the performance of the storage device during use. For example, when it is found that the optimal voltage value for a certain storage area begins to deviate from the historical record, a new round of voltage value optimization process can be triggered.

[0132] In some embodiments, the processor 211 can dynamically adjust the parameters of the second data read operation according to the execution status of the first data read operation. For example, if it is found that the first data read operation has a higher success rate at a certain specific voltage value, the processor 211 can adjust the second voltage value accordingly to improve the success rate of the second data read operation.

[0133] In another embodiment, please refer to Figure 4 As shown by arrow A41, the processor 211 further performs an iterative data read process. Specifically, when the processor 211 determines in step S404 that the first data read operation is not successfully completed, the processor 211 starts the iterative read mechanism. In this case, the processor 211 re-executes step S401 to obtain another first voltage value, and sets the voltage value and the first read parameters to the integrated read module 300 again through step S402 to attempt to read the first data again. This iterative process can continue until the first data is successfully read or the pre-set retry limit is reached.

[0134] In more detail, the processor 211 can select the other first voltage value based on different strategies. For example, the processor 211 can calculate the new voltage value according to a pre-set voltage adjustment algorithm based on the result of the previous read operation. Alternatively, the processor 211 can select the next voltage value to be tried from a pre-stored sequence of voltage values in the buffer memory 214. This iterative read mechanism ensures that there is still a chance to successfully read the data by adjusting the voltage value in case of a first read failure.

[0135] However, in yet another embodiment, even if the first data read operation has been successfully completed, the processor 211 can still continue to perform additional read operations under certain conditions. For example, when the processor 211 detects that the number of error bits in the current read result is close to the upper limit of the acceptable range, the processor 211 can choose to perform additional read attempts using another voltage value even if the data can already be successfully corrected in order to obtain a better quality read result. This optimization mechanism is particularly suitable for application scenarios where the data reliability requirement is high.

[0136] It is worth mentioning that when performing these additional read operations, the processor 211 weighs the relationship between the read quality improvement and the time overhead. For example, if the number of error bits in the current read result is already low, or the system is in a high load state, the processor 211 can choose to skip the additional read attempts and directly proceed to the read operation of the next data. This flexible strategy enables the memory controller 210 to strike a good balance between read performance and data reliability.

[0137] Figure 5 A timing diagram of multiple data read operations according to an embodiment of the present disclosure is shown.

[0138] In an embodiment, please refer to Figure 5 which shows a timing flow of the memory controller 210 performing multiple data read operations.

[0139] For example, at time point T1, the memory controller 210 first performs step CV1: obtaining a first read voltage (also referred to as a first voltage value) corresponding to the first data. Subsequently, in step SR1, a first read operation corresponding to the first data is set based on the first read voltage. Then, the memory controller 210 triggers and performs the first read operation TR1. It is worth noting that during the execution of the first read operation TR1, the memory controller 210 starts to perform step CV2: obtaining a second read voltage (also referred to as a second voltage value) corresponding to the second data, and in step SR2, a second read operation corresponding to the second data is set based on the second read voltage, embodying the parallel processing mechanism of the present disclosure.

[0140] In more detail, when time point T2 is reached, the first read operation TR1 is completed, and the memory controller 210 immediately triggers and performs the second read operation TR2. At the same time, the memory controller 210 performs the step CV3 of obtaining the third read voltage (also referred to as the third voltage value) corresponding to the third data, and sets the third read operation for the third data based on the third read voltage in step SR3. This design ensures that at any time, the subsequent read operation can be performed in succession to the previous read operation (because the corresponding necessary parameters are ready).

[0141] When time point T3 is reached, the second read operation TR2 is completed, and the memory controller 210 immediately triggers and performs the third read operation TR3. This continuous operation mode exhibits a pipelined data reading process, in which the preparation and execution of each read operation form an efficient overlapping execution mode.

[0142] It is worth mentioning that Figure 5 The timing arrangement in FIG. 7 shows an ideal case in which each read operation is successfully completed. This parallel processing mechanism significantly improves the data reading efficiency, because the voltage value and related parameters required for the next read operation are always ready before the current read operation is completed. For example, during the time period T1 to T2, the memory controller 210 completes steps CV2 and SR2 while performing the first read operation TR1, thereby ensuring that the second read operation TR2 can be immediately started at time T2.

[0143] However, in the case where the previous read operation is not successfully completed, the memory management method provided by the present disclosure also has a corresponding execution flow, please see Figure 6 、 Figure 7 for the description of the corresponding embodiments.

[0144] Figure 6 A timing diagram of multiple data read operations according to yet another embodiment of the present disclosure.

[0145] In another embodiment, please refer to Figure 6 , which shows the processing flow when the first data read operation fails. In this case, the memory controller 210 takes specific measures to ensure reliable reading of data.

[0146] For example, at time point T1, the memory controller 210 first performs the step of acquiring a first read voltage (as step CV1.1), and then sets a first read operation based on the first read voltage in step SR1.1. Subsequently, the memory controller 210 triggers and performs another first read operation TR1.1. Notably, during the execution of the another first read operation TR1.1, the memory controller 210 starts to perform the step of acquiring a second read voltage CV2, and sets a second read operation based on the second read voltage in step SR2, embodying the parallel processing mechanism of the present disclosure.

[0147] Then, at time point T2, when the another first read operation TR1.1 is completed, the memory controller 210 detects that the operation is not successfully completed. In this case, although the memory controller 210 has already prepared for the second data read operation through steps CV2 and SR2, the memory controller 210 will prioritize the reading of the first data. Therefore, the memory controller 210 will immediately perform the step of acquiring another first read voltage CV1.2, and set another first read operation based on the another first read voltage in step SR1.2.

[0148] This prioritization mechanism is embodied in that the memory controller 210 temporarily suspends the originally planned second data read operation, and instead performs another reading attempt TR1.2 for the first data. This design ensures that a new read operation will not be started recklessly before the current data read problem is resolved. Notably, although the preparation work (CV2 and SR2) for the second data read operation has been completed, its execution will be delayed until it is confirmed that the first data can be successfully read.

[0149] In addition, at time point T3, the memory controller 210 will decide the subsequent operation according to the execution result of TR1.2. If the another first read operation TR1.2 still fails, the memory controller 210 can continue to try new voltage values; and if TR1.2 is successfully completed, the previously prepared second data read operation TR2 can be started.

[0150] It is worth mentioning that, Figure 6 The timing arrangement in FIG. 1 reflects the flexibility and reliability of the present disclosure in handling read failure cases. By timely adjusting the read strategy and ensuring that the current data read problem is resolved, the memory controller 210 can maintain the efficiency of the read operation as much as possible while ensuring data reliability. This mechanism is particularly suitable for application scenarios with high requirements for data integrity, such as data recovery operations when error handling is performed.

[0151] Figure 7Timing diagram of multiple data read operations as shown in accordance with yet another embodiment of the present disclosure.

[0152] In another embodiment, referring to Figure 7 , the data read flow with a preventive preparation mechanism is shown. This embodiment particularly emphasizes that during the execution of the first data read operation, another set of read parameters that can be needed is prepared in advance, further optimizing the time efficiency of the read operation.

[0153] Specifically, at time point T1, the memory controller 210 first performs the step of acquiring the first read voltage CV1.1 and sets the first read operation based on the voltage in step SR1.1. Subsequently, during the execution of another first read operation TR1.1, the memory controller 210 not only performs the steps of acquiring the second read voltage CV2 and the corresponding setting step SR2, but also performs the steps of acquiring another first read voltage CV1.2 and the corresponding setting step SR1.2 in advance.

[0154] In more detail, the advantage of this preventive preparation mechanism is that when time point T2 is reached, if the execution of another first read operation TR1.1 fails, the memory controller 210 can immediately perform another first data read operation TR1.2 using the already prepared another set of first read parameters without additional parameter preparation time. Compared with the embodiment shown in Figure 6 , this preventive preparation mechanism further reduces the response time in the case of read failure. That is, in the example of Figure 7 , it can be seen that each read operation can be performed consecutively and immediately.

[0155] At time point T3, if another first read operation TR1.2 is successfully completed, the memory controller 210 can directly start to perform the second data read operation TR2 that has been prepared in advance. This mechanism ensures that even in the case of multiple attempts to read the first data, the subsequent read operation can be started in time, thus maintaining the overall read efficiency.

[0156] It is worth mentioning that this preventive preparation mechanism is particularly suitable for error handling scenarios. Since different read voltages can need to be tried multiple times during the error handling process, preparing the next set of parameters that can be needed in advance can significantly reduce the delay time between each retry. This scheme not only improves the response speed of a single read operation, but also improves the overall data read efficiency.

[0157] In some embodiments, the memory controller 210 can optimize the parameter selection for the preventive preparation based on historical data and error pattern analysis. For example, if the historical data shows that certain voltage value combinations are more likely to result in successful read, the memory controller 210 can prioritize the preparation of parameters corresponding to these voltage value pairs.

[0158] In another embodiment, the memory controller 210 (e.g., the integrated read module 300) improves the data read efficiency by rationally utilizing the multi-plane structure of the rewritable non-volatile memory module 220. Specifically, the rewritable non-volatile memory module 220 includes multiple storage planes, each of which is equipped with an independent register set and a command queue.

[0159] Specifically, when multiple data needs to be read, the integrated read module 300 first checks the physical location distribution of these data in the rewritable non-volatile memory module 220. For example, when the integrated read module 300 prepares to perform a first data read operation, it simultaneously queries the storage location information of a second data. If it is confirmed that the first data and the second data are located in different storage planes, the memory controller 210 can make full use of the relevant processing resources (e.g., register sets and command queues) of each storage plane to optimize the read process.

[0160] In more detail, in an embodiment, such parallel parameter setting includes, for example:

[0161] (1) Register set configuration: The integrated read module 300 can simultaneously write the respective required parameters to the register sets of different storage planes. For example, when the first data read operation is using the register set of the first storage plane, the integrated read module 300 can parallelly write the voltage value, address information, and other parameters of the second data read operation to the register set of the second storage plane.

[0162] (2) Command queue management: The integrated read module 300 can load the command sequence of the second data read operation into the command queue of the second storage plane in advance without interfering with the command queue currently being executed by the first storage plane. These command sequences include, for example: commands for setting read voltage values, commands for setting target addresses, commands for preloading data buffers, and commands for triggering read operations.

[0163] (3) Resource allocation: The integrated read module 300 allocates independent system resources for the parallel operation of different storage planes, including, for example: respective data buffer spaces, independent state monitoring registers, separate data transmission channels, and dedicated error detection resources.

[0164] For example, after confirming that the multiple data to be read are distributed in different planes, the consolidated read module 300 can employ a further parallel processing strategy. While a first data read operation is being performed, the consolidated read module 300 can simultaneously set up parameters for a second data read operation. Since the different storage planes have independent register sets and command queues, this parallel parameter setting does not interfere with the ongoing first data read operation. For example, while the first data read operation is using the hardware resources of the first storage plane, the consolidated read module 300 can simultaneously use the register set of the second storage plane to prepare the read parameters for the second data.

[0165] It is worth mentioning that the independent hardware resources of the different storage planes ensure that the two read operations do not interfere with each other. If the memory controller 210 determines that the second data is located in a different storage plane from the first data, it can even trigger the execution of the second data read operation before the first data read operation is completed. For example, during the operation of the first data read operation and after obtaining the second voltage corresponding to the second data read operation, the second data read operation can be directly executed without waiting for the completion of the first data read operation, thereby achieving parallel read operations and significantly improving the overall read efficiency. Assuming that another first voltage is obtained during the execution of the second data read operation, when the first data read operation is completed, another first data read operation can also be directly executed based on the other first voltage using the hardware resources of the first storage plane.

[0166] In addition, the memory controller 210 also dynamically manages the resource usage of each storage plane. When it detects that a read operation is about to be completed, the memory controller 210 plans the next read operation that will use that storage plane in advance, to ensure that the hardware resources of the storage plane are fully utilized. This dynamic scheduling mechanism based on storage planes not only improves the overall read efficiency, but also improves the utilization of hardware resources.

[0167] In practical applications, the memory controller 210 can maintain a storage plane status table to record the usage status, queue length, and other information of each storage plane in real time, in order to better schedule read operations. In addition, it can also consider allocating frequently accessed data to different storage planes when writing data, based on factors such as data read frequency and importance, to create more efficient operations for subsequent parallel reading.

[0168] The embodiment also provides a computer program product comprising computer readable code or a non-volatile computer readable storage medium carrying computer readable code, which, when executed in a processor, causes the processor to perform the steps of the above-mentioned storage device testing method. The computer program product can be implemented by hardware, firmware, software or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium. In another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK) or the like.

[0169] Based on the above, the memory management method and the memory controller provided by one or more embodiments of the present disclosure improve the data read efficiency, especially for the read operation in the error handling process, by using the innovative integrated read module and the corresponding parallel processing mechanism. Specifically, the present disclosure effectively reduces the time overhead required for pure serial processing by overlapping the execution process of the first data read operation with the parameter preparation process of the second data read operation. In addition, the present disclosure encapsulates the conventional multiple read steps into a unified interface using the integrated read module, simplifies the operation process of the processor 211, and also improves the maintainability of the code.

[0170] Furthermore, the present disclosure also provides a flexible error handling mechanism. When the first data read operation fails, the system can quickly switch to another set of read parameters prepared in advance, greatly reducing the response time of the retry process. At the same time, the present disclosure makes full use of the multi-plane architecture of the rewritable non-volatile memory module, and realizes true parallel data read under appropriate conditions by judging the storage plane where the data is located, further improving the overall performance.

[0171] In particular, it is worth mentioning that the present disclosure coordinates the operation of each functional unit through the integrated read module, maximizes the performance of the hardware resources of the storage device while ensuring the reliability of data read, and also reduces the processing burden of the processor itself. This design not only improves the data read speed in the error handling process, but also provides a new technical idea for the performance integration and optimization of the storage device, which has important practical value.

[0172] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the above embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory management method applicable to a storage device equipped with a rewritable non-volatile memory module, characterized in that, The method includes: Obtain the first voltage value corresponding to the first data read operation of the first data; The first voltage value and the corresponding first reading parameter of the first data are set to the integrated reading module, so that the first data reading operation can be performed via the integrated reading module. The integrated reading module includes: The parameter configuration module is used to store the first voltage value and the first read parameter; The command generation module is used to generate a read command sequence for the rewritable non-volatile memory module based on the first voltage value and the first read parameters. An execution module is configured to send the read command sequence to the rewritable non-volatile memory module and receive the read first data to perform the first read operation; and The status feedback module is used to store the execution status information of the first data reading operation; While performing the first data read operation, the second voltage value corresponding to the second data read operation is acquired in parallel; and Determine whether the first data and the second data are located in different storage planes; If the first data and the second data are located on different storage planes, before the first data reading operation is completed, the second voltage value and the second reading parameter corresponding to the second data are set to the integrated reading module so that the second data reading operation can be performed via the integrated reading module; If the first data and the second data are located on the same storage plane, in response to the completion of the first data read operation, the second voltage value and the second read parameter corresponding to the second data are set to the integrated read module so as to perform the second data read operation via the integrated read module.

2. The memory management method according to claim 1, characterized in that, The first read parameter includes one or more of the following: The first data is located at the target physical address of the rewritable non-volatile memory module. The first data length of the first data; The physical page size information of the first data; The read mode identifier of the first data; Error detection parameters for the first data; as well as The metadata of the first data.

3. The memory management method according to claim 1, characterized in that, The method further includes: If the first data read operation fails, obtain another first voltage value for rereading the first data, wherein the other first voltage value is different from the first voltage value; and The other first voltage value and the first reading parameter are set to the integrated reading module so that the first data reading operation is re-executed via the integrated reading module.

4. The memory management method according to claim 1 or 3, characterized in that, During the execution of the first data read operation: If the first data read operation fails, the second data read operation is paused until the first data read operation is confirmed to have been successfully completed.

5. The memory management method according to claim 1, characterized in that, The method further includes: Store the first voltage value and the corresponding first read result used in each execution of the first data read operation; and Based on the first voltage value and the first reading result, the optimal voltage value for reading the first data is determined.

6. The memory management method according to claim 5, characterized in that, Determining the optimal voltage value includes: Record multiple first voltage values ​​and the corresponding number of first read error bits; and The optimal voltage value is the specific first voltage value that corresponds to the minimum number of first read error bits.

7. The memory management method according to claim 1, characterized in that: The rewritable non-volatile memory module includes multiple storage planes, each of which has a corresponding register set and command queue; as well as The integrated reading module is configured to perform parallel parameter settings for the reading operations of the second data located on different storage planes when performing the first data reading operation.

8. A memory controller for controlling a storage device configured with a rewritable non-volatile memory module, characterized in that, The memory controller includes: A memory interface control circuit is provided for electrical connection to the rewritable non-volatile memory module; and The processor is electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to the connection interface circuit of the storage device for electrical connection to the host system. The processor is configured to: Obtain the first voltage value corresponding to the first data read operation of the first data; The first voltage value and the corresponding first reading parameter of the first data are set to the integrated reading module, so as to perform the first data reading operation via the integrated reading module, wherein the integrated reading module includes: The parameter configuration module is used to store the first voltage value and the first read parameter; The command generation module is used to generate a read command sequence for the rewritable non-volatile memory module based on the first voltage value and the first read parameters. An execution module is configured to send the read command sequence to the rewritable non-volatile memory module and receive the read first data to perform the first read operation; and The status feedback module is used to store the execution status information of the first data reading operation; While performing the first data read operation, the second voltage value corresponding to the second data read operation is acquired in parallel; and Determine whether the first data and the second data are located in different storage planes; If the first data and the second data are located on different storage planes, before the first data reading operation is completed, the second voltage value and the second reading parameter corresponding to the second data are set to the integrated reading module so that the second data reading operation can be performed via the integrated reading module; If the first data and the second data are located on the same storage plane, in response to the completion of the first data read operation, the second voltage value and the second read parameter corresponding to the second data are set to the integrated read module so as to perform the second data read operation via the integrated read module.

9. The memory controller according to claim 8, characterized in that, The first read parameter includes one or more of the following: The first data is located at the target physical address of the rewritable non-volatile memory module. The first data length of the first data; The physical page size information of the first data; The read mode identifier of the first data; Error detection parameters for the first data; as well as The metadata of the first data.

10. The memory controller according to claim 8, characterized in that, The processor is also configured to: If the first data read operation fails, another first voltage value is obtained for rereading the first data, wherein the other first voltage value is different from the first voltage value; as well as The other first voltage value and the first reading parameter are set to the integrated reading module so that the first data reading operation is re-executed via the integrated reading module.

11. The memory controller according to claim 8 or 10, characterized in that, The processor is also configured to: If the first data read operation fails during the execution of the first data read operation, the execution of the second data read operation is paused until the first data read operation is confirmed to have been successfully completed.

12. The memory controller according to claim 8, characterized in that, The processor is also configured to: Store the first voltage value and the corresponding first read result used in each execution of the first data read operation; as well as Based on the first voltage value and the first reading result, the optimal voltage value for reading the first data is determined.

13. The memory controller according to claim 12, characterized in that, Determining the optimal voltage value includes: Record multiple first voltage values ​​and the corresponding number of first read error bits; and The optimal voltage value is the specific first voltage value that corresponds to the minimum number of first read error bits.

14. The memory controller according to claim 8, characterized in that: The rewritable non-volatile memory module includes multiple storage planes, each of which has a corresponding register set and command queue; as well as The integrated reading module is configured to perform parallel parameter settings for the reading operations of the second data located on different storage planes when performing the first data reading operation.

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