Command distribution method and device, computer equipment, storage medium and program product

Abstract

The invention relates to the technical field of storage, and discloses a command distribution method and device, computer equipment, a storage medium and a program product, and the method comprises the steps: obtaining a target total command and the storage position information of the target total command; determining at least one sub-command corresponding to the target total command according to a target initial address, a target data length, a preset stripe size and the storage position information in the target total command; determining first stripe identification information of the first sub-command according to a sub-start address and a stripe size included in the first sub-command; obtaining a target corresponding relation table of the serial number and the distribution index value of the hardware calculation accelerator; according to the first stripe identification information, a preset allocation algorithm and a target corresponding relation table, determining a target hardware calculation accelerator in a plurality of pre-constructed hardware calculation accelerators; the first sub-command is assigned to the target hardware computing accelerator. The command processing efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a command distribution method, device, computer equipment, storage medium and program product. Background Art

[0002] In data center server systems, in order to improve hard disk read and write performance, storage scalability, and data security, server manufacturers use Redundant Array of Independent Disks (RAID) controllers to manage hard disks.

[0003] Generally, you can use the operating system to build RAID through software, or you can integrate the RAID controller board in the server to build RAID through hardware. For the latter, the RAID controller is integrated on the RAID controller board, and the RAID controller is integrated with a hardware computing accelerator (Raid Acceleration Cluster, RAC) specifically used for RAID business. In order to further improve the system command reading and writing performance, multiple copies of such RAC can be copied inside the RAID controller, and each RAC can process commands in parallel, thereby increasing command throughput and improving overall performance.

[0004] However, since different commands can operate on the same stripe, if these commands are assigned to different RACs for processing, the stripe will generally be locked to avoid data inconsistency. For example, if both command 1 and command 2 are to process stripe 1, command 1 is assigned to RAC1, and command 2 is assigned to RAC2, then when RAC1 processes command 1, it will lock the mutex on stripe 1, and release the mutex after processing command 1, and RAC2 can process stripe 1. This results in underutilization of RAC hardware resources, which in turn leads to low command processing efficiency. Summary of the invention

[0005] In view of this, the present invention provides a command distribution method, apparatus, computer equipment, storage medium and program product to solve the problem of low command processing efficiency.

[0006] In a first aspect, the present invention provides a command distribution method, the method comprising:

[0007] Obtaining a target total command, wherein the target total command includes a target start address and a target data length;

[0008] Get the storage location information of the target general command;

[0009] Determine at least one sub-command corresponding to the target general command according to the target start address, the target data length, the preset stripe size, and the storage location information, wherein each sub-command includes a sub-start address and a sub-data length;

[0010] Determine first stripe identification information of the first subcommand according to the sub-start address and the stripe size included in the first subcommand, wherein the first subcommand is any one of the at least one subcommand;

[0011] Obtain a target correspondence table of hardware computing accelerator numbers and allocation index values;

[0012] Determine a target hardware computing accelerator from among a plurality of pre-built hardware computing accelerators according to the first stripe identification information, the preset allocation algorithm, and the target correspondence table;

[0013] The first subcommand is assigned to the target hardware computing accelerator, so that the target hardware computing accelerator processes the first subcommand to obtain a return result corresponding to the first subcommand.

[0014] The command distribution method provided by the present invention has the following advantages:

[0015] First, this solution can first obtain the general command and its storage location information. Then, according to the starting address, data length, storage location information and stripe size in the general command, the general command can be processed to obtain at least one sub-command. Each sub-command can have its own sub-starting address and sub-data length. Further, the stripe identification information of the sub-command can be determined according to the sub-starting address and the stripe size. Finally, according to the stripe identification information, the preset allocation algorithm, and the target correspondence table of the number and allocation index value of the hardware computing accelerator, the hardware computing accelerator corresponding to the sub-command is determined, so that the hardware computing accelerator can process the sub-command. Through the above-mentioned processing method, each general command can be divided into one or more sub-commands, and each sub-command can be assigned to the corresponding hardware computing accelerator according to its corresponding stripe identification information. In this way, sub-commands with the same stripe identification information can be assigned to the same hardware computing accelerator, without the need to perform stripe locking operations, making full use of hardware resources, and improving command processing efficiency.

[0016] In an optional implementation, at least one sub-command corresponding to the target general command is determined according to the target start address, the target data length, the preset stripe size, and the storage location information, including:

[0017] Determine at least one sub-starting address and a sub-data length corresponding to each sub-starting address according to the target starting address, the target data length and the stripe size;

[0018] According to the size of each sub-starting address, determine the order of each sub-starting address;

[0019] A sub-command corresponding to each sub-starting address is generated according to the storage location information of the target general command, each sub-starting address, the sub-data length corresponding to each sub-starting address, and the order of each sub-starting address.

[0020] Specifically, the sub-command obtained based on the storage location information of the target general command, each sub-starting address, the order of each sub-starting address, and the sub-data length corresponding to each sub-starting address not only adds its own information but also retains the original target general command information, thereby ensuring the consistency of command processing.

[0021] In an optional implementation, determining at least one sub-starting address and a sub-data length corresponding to each starting address according to the target starting address, the target data length and the stripe size includes:

[0022] Determine the target stripe offset according to the target start address and stripe size;

[0023] In the first processing round, the target start address is determined as the first sub-start address;

[0024] Determine the first sub-data length corresponding to the first sub-start address according to the stripe size and the target stripe offset;

[0025] Determine whether the first sub-data length is less than the target data length;

[0026] When it is determined that the first sub-data length is equal to the target data length, the processing is terminated to obtain a sub-start address and a sub-data length.

[0027] Specifically, through the division method of this solution, it can be ensured that each sub-command corresponds to only one stripe.

[0028] In an optional embodiment, the method further includes:

[0029] When it is determined that the length of the first sub-data is less than the target data length, entering the next processing round corresponding to the first processing round;

[0030] In a current processing round that is not the first processing round, determining a sub-starting address of the current processing round according to a sub-starting address and a sub-data length corresponding to a previous processing round corresponding to the current processing round;

[0031] Determine the remaining data length according to the sub-data lengths and target data lengths respectively corresponding to all processing rounds before the current processing round;

[0032] Determine whether the remaining data length is greater than the stripe size;

[0033] When the remaining data length is greater than the stripe size, the stripe size is determined as the sub-data length of the current processing round, and the next processing round is entered.

[0034] Specifically, through the division method of this solution, it can be ensured that each sub-command corresponds to only one stripe.

[0035] In an optional embodiment, when it is determined that the remaining data length is less than or equal to the stripe size, the remaining data length is determined as the sub-data length of the current processing round, and the processing is terminated to obtain multiple sub-starting addresses and the sub-data length corresponding to each of the multiple sub-starting addresses.

[0036] Specifically, through the division method of this solution, it can be ensured that each sub-command corresponds to only one stripe.

[0037] In an optional implementation manner, the target general command also includes split indication information, and the split indication information includes multiple bits;

[0038] After generating a sub-command corresponding to each sub-starting address according to the storage location information of the target general command, each sub-starting address, the sub-data length corresponding to each sub-starting address, and the order of each sub-starting address, the method further includes:

[0039] According to the order of each sub-starting address, a bit corresponding to the order of each sub-starting address is determined from a plurality of bits;

[0040] The bits corresponding to the order of each sub-start address are all set to a first preset value, where the first preset value is used to indicate that the first sub-command is not processed by any hardware computing accelerator.

[0041] Specifically, by splitting the instruction information, it is easy to understand the execution progress of the target general command, so that after completing the processing of each sub-command corresponding to the target general command, the processing result of the target general command can be fed back in time.

[0042] In an optional implementation, determining a target hardware computing accelerator from a plurality of pre-built hardware computing accelerators according to the first stripe identification information, a preset allocation algorithm, and a target correspondence table includes:

[0043] Determine a target allocation index value according to the first stripe identification information and a preset allocation algorithm;

[0044] Determine whether there is a number of a hardware computing accelerator corresponding to the target allocation index value in the target correspondence table;

[0045] When it is determined that there is a target number corresponding to the target allocation index value in the target correspondence table, the hardware computing accelerator corresponding to the target number is determined as the target hardware computing accelerator.

[0046] Specifically, the preset allocation algorithm can quickly determine the target hardware computing accelerator, avoiding traversing all possible hardware computing accelerators and improving processing efficiency. Since the stripe identification information and the preset allocation algorithm are used, it is ensured that each task allocation is based on certain rules, reducing the uncertainty caused by random selection.

[0047] In an optional implementation, when it is determined that there is no target number corresponding to the target allocation index value in the target correspondence table, the method further includes:

[0048] Obtaining the number of uncompleted subcommands of each hardware computing accelerator among multiple hardware computing accelerators;

[0049] The target hardware computing accelerator is determined according to the number of uncompleted subcommands of each hardware computing accelerator.

[0050] Specifically, the load size of the hardware computing accelerator can be determined by the number of unfinished subcommands of the hardware computing accelerator. According to the load size of the hardware computing accelerator, a suitable target hardware computing accelerator can be selected to improve the processing efficiency of the subcommands, that is, the processing efficiency of the total command can be improved.

[0051] In an optional implementation, determining the target hardware computing accelerator according to the number of uncompleted subcommands of each hardware computing accelerator includes:

[0052] Determine, according to the number of uncompleted subcommands of each hardware computing accelerator, a hardware computing accelerator having the least number of uncompleted subcommands;

[0053] When the hardware computing accelerator with the least number of subcommands is one, directly determining the hardware computing accelerator with the least number of subcommands as the target hardware computing accelerator;

[0054] or,

[0055] When there are multiple hardware computing accelerators with the least number of subcommands, the hardware computing accelerator with the smallest number is selected from the multiple hardware computing accelerators with the least number of subcommands as the target hardware computing accelerator.

[0056] Specifically, by selecting the hardware computing accelerator with the least number of sub-commands as the target hardware computing accelerator, it is possible to achieve load balancing of different hardware computing accelerators and improve the data processing efficiency of the sub-commands.

[0057] In an optional embodiment, the method further includes:

[0058] After the target hardware computing accelerator has processed the first subcommand, the storage location information of the target total command and the order of the first sub-start address are extracted from the first subcommand;

[0059] Determine the target general command according to the storage location information of the target general command;

[0060] According to the sequence of the first sub-starting addresses, determining a first bit corresponding to the sequence of the first sub-starting addresses from among a plurality of bits of the target general command;

[0061] The first bit is set to a second preset value, wherein the second preset value is used to indicate that the first subcommand has been processed by the target hardware computing accelerator.

[0062] Specifically, by setting a specific bit to mark the processing status of a subcommand, it can be ensured that which subcommands have been processed can be accurately known, thereby preventing repeated processing or missing processing.

[0063] In an optional implementation, assigning the first subcommand to the target hardware computing accelerator includes:

[0064] The first subcommand is added to the end of the target queue corresponding to the target hardware computing accelerator, so that when the target hardware computing accelerator determines the processing order of the first subcommand according to the order of each subcommand in the target queue, it processes the first subcommand and obtains a return result corresponding to the first subcommand.

[0065] Specifically, by adding subcommands to the queue in sequence, it is ensured that the subcommands are processed in the order in which they enter the queue, so that the logical order of task processing can be maintained and data processing errors can be avoided.

[0066] In an optional implementation, obtaining the target total command includes:

[0067] Get the target host command sent by the host;

[0068] Get the preset total command data structure;

[0069] According to the general command data structure, the target host command is converted to obtain the target general command.

[0070] Specifically, through the preset general command data structure, target host commands in different formats can be uniformly converted into a consistent format, thereby simplifying subsequent processing steps and improving system compatibility and interoperability.

[0071] In an optional implementation, after setting the first bit to the second preset value, the method further includes:

[0072] Determining whether the value of each of the multiple bits of the target general command is a second preset value;

[0073] When it is determined that the value of each of the multiple bits in the split indication information of the target general command is the second preset value, obtaining the return results respectively corresponding to at least one sub-command corresponding to the target general command;

[0074] Determine a total return result corresponding to the target general command according to the return results respectively corresponding to at least one subcommand corresponding to the target general command;

[0075] Feedback the total return result to the host.

[0076] Specifically, by checking whether all bits of the target total command have been set to the second preset value, it can be ensured that all subcommands have been processed. This can prevent the problem of incomplete results due to a subcommand not being processed. After all subcommands have been processed, the results are summarized to ensure the consistency and accuracy of the final results and avoid problems caused by unsynchronized or incorrect summaries of intermediate results. Once it is confirmed that all subcommands have been processed, the results are immediately summarized and fed back to the host side to ensure the timeliness of task feedback.

[0077] In an optional implementation, the target allocation index value is determined according to the first stripe identification information and a preset allocation algorithm, using the following expression:

[0078] Hash Key = StripeID%K

[0079] Among them, Hash Key is the target allocation indicator value, StripeID is the first strip identification information, and K is the third preset value.

[0080] Specifically, the modulo operation can ensure that different stripes are evenly mapped to a fixed range (0 to K-1). This ensures the consistency of the allocation index value, that is, the same stripe identification information will always be allocated to the same hardware computing accelerator. In addition, the modulo operation is particularly simple and fast, and only requires one division operation and remainder operation to complete, with high computational efficiency. By adjusting the value of K, the allocation strategy can be easily adjusted. For example, if you need to increase or decrease the number of target nodes or disks, you only need to adjust the value of K accordingly, which can flexibly allocate resources.

[0081] In an optional implementation, after determining the target hardware computing accelerator according to the number of uncompleted subcommands of each hardware computing accelerator, the method further includes:

[0082] Get the target hardware computing accelerator number;

[0083] The target correspondence table is updated according to the target allocation index value and the serial number of the target hardware computing accelerator.

[0084] Specifically, the dynamic update mechanism can reduce management costs and eliminate the need for technical personnel to perform real-time management.

[0085] In an optional implementation, the first stripe identification information of the first subcommand is determined according to the sub-start address and the stripe size included in the first subcommand, using the following expression:

[0086] StripeID=ZSLBA%Stripe_Length

[0087] Among them, StripeID is the first stripe identification information, ZSLBA is the sub-start address included in the first sub-command, and Stripe_Length is the stripe size.

[0088] In a second aspect, the present invention provides a command distribution device, the device comprising:

[0089] An acquisition module is used to acquire a target general command; acquire storage location information of the target general command, wherein the target general command includes a target start address and a target data length;

[0090] a determination module, configured to determine at least one subcommand corresponding to a target general command according to a target start address, a target data length, a preset stripe size, and storage location information, wherein each subcommand includes a sub-start address and a sub-data length; and to determine first stripe identification information of a first subcommand according to the sub-start address and the stripe size included in a first subcommand, wherein the first subcommand is any one of the at least one subcommand;

[0091] The acquisition module is also used to obtain a target correspondence table between the serial number of the hardware computing accelerator and the allocation index value;

[0092] The determination module is further used to determine a target hardware computing accelerator from a plurality of pre-built hardware computing accelerators according to the first stripe identification information, the preset allocation algorithm and the target correspondence table;

[0093] The allocation module is used to allocate the first subcommand to the target hardware computing accelerator, so that the target hardware computing accelerator processes the first subcommand to obtain a return result corresponding to the first subcommand.

[0094] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the command allocation method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0095] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the command allocation method of the first aspect or any corresponding embodiment thereof.

[0096] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the command allocation method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0097] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0098] Figure 1 is a schematic diagram of the architecture of a RAID controller according to an embodiment of the present invention;

[0099] Figure 2 is a flow chart of a command distribution method according to an embodiment of the present invention;

[0100] Figure 3 is a schematic diagram of a general command data structure and a sub-command data structure according to an embodiment of the present invention;

[0101] Figure 4 is a schematic diagram of IO splitting according to an embodiment of the present invention;

[0102] Figure 5 is a hash representation according to an embodiment of the present invention;

[0103] Figure 6 is another IO splitting schematic diagram according to an embodiment of the present invention;

[0104] Figure 7 is a schematic diagram of IO allocation according to an embodiment of the present invention;

[0105] Figure 8 is a schematic diagram of analyzing the IO processing duration according to an embodiment of the present invention;

[0106] Fig. 9 is a structural block diagram of a command distribution device according to an embodiment of the present invention;

[0107] Fig.10 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0108] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0109] The special terms involved in the present invention are explained below.

[0110] Raw IO: refers to a method of performing raw read and write operations on storage devices, that is, directly accessing data blocks on storage devices without going through the intermediate layer of the operating system or file system.

[0111] Redundant Array of Independent Disks (RAID) technology: creates a fail-safe mechanism for data loss by combining two or more hard disk drives (HDD) or solid state drives (SSD) into a coordinated storage unit or array. Common RAID types include RAID0, RAID1, RAID5, and RAID6.

[0112] RAID5: The main feature is the use of parity checking to protect data while allowing parallel access to multiple disks to increase read and write speeds.

[0113] Stripe: It is a concept in RAID. RAID technology divides data into stripes. One stripe spans all data disks, and each disk stores a part of the stripe.

[0114] The present invention provides a RAID controller, such as Figure 1 As shown, the RAID controller may include an IO receiver, a load balancer, multiple hardware computing accelerators (Raid Acceleration Cluster, RAC), an IO responder, and other hardware components. Figure 1 The number of RACs in is 2.

[0115] The command (IO) receiver is used to receive the host IO (for example, Figure 1 IO-1, IO-2, IO-3, IO-4), and convert the host IO into RAW IO according to the preset total command data structure.

[0116] The load balancer may include a RAW IO splitter, a memory, a subcommand distributor, and a plurality of RAC IO recyclers. The RAW IO splitter may be used to split the RAW IO to obtain at least one RAC IO (e.g., Figure 1 ', IO-1', IO-2', IO-3', IO-4' in it). The memory can be used to store the target correspondence table of RAW IO, the number of hardware computing accelerators and the allocation index value, and multiple RAC IO queues. The sub-command distributor can be configured with a preset allocation algorithm. The sub-command distributor is used to submit the RAC IO to the corresponding RAC IO queue according to the RAC IO, the preset allocation algorithm and the target correspondence table. The number of RAC IO recyclers can be the same as the number of RACs, and there is a one-to-one correspondence, that is, one RAC IO recycler is used to recycle the IO processed by the corresponding RAC. "Recycling" means releasing the resources occupied by the corresponding IO. The RAC IO queue can be a first-in-first-out queue. The number of RAC IO queues can be the same as the number of RACs, and there is a one-to-one correspondence, that is, one RAC IO queue is used to store the sub-commands allocated to the corresponding RAC. RAC may include an IO calculator, an IO reader / writer, an IO terminator, and an IO counter, etc., which are used to read subcommands from the corresponding RAC IO queue and process the subcommands to obtain the return results corresponding to the RAC IO. The IO responder is used to respond to the host IO according to the return results of the subcommands. Other hardware components may be memory management, interrupt management, bus, etc.

[0117] The embodiment of the present invention provides a command allocation method, which splits the target total command and then allocates the RAC to fully utilize the hardware resources and improve the command processing efficiency.

[0118] According to an embodiment of the present invention, a command allocation method embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0119] In this embodiment, a command allocation method is provided, which can be executed by a computer device. For example, the computer device can be the above-mentioned RAID controller, that is, the various hardware components included in the RAID controller cooperate with each other to complete the command allocation method, or it can be other devices with computing capabilities. The following describes the process of the command allocation method with the RAID controller as the execution subject.

[0120] Figure 2 is a flow chart of a command distribution method according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0121] Step S201, obtaining the target general command.

[0122] The target general command may be generated according to a received host command, such as the above-mentioned RAW IO, or may be a command automatically generated by the IO receiver according to a preset business processing logic.

[0123] Specifically, when the target general command is generated according to the received host command, the specific generation process may be as follows:

[0124] Step 1: Get the target host command sent by the host.

[0125] Step 2: Get the preset total command data structure.

[0126] Step three, according to the general command data structure, convert the target host command to obtain the target general command.

[0127] The target host command may be the host IO mentioned above. The total command data structure includes split indication information, a start address, a data length, and an operation type. The split indication information may include multiple bits, and the number of bits may be the same as the maximum number of sub-commands that the total command can be split into. The start address may specifically be a start logical block address (SLBA). The operation type may be a write operation or a write operation. For example, the total command data structure may be as follows: Figure 3 As shown in IO-1 and IO-2, the "split_bitmap" is the split indication information.

[0128] Specifically, when the IO receiver in the RAID controller receives the target host command sent by the host side, it can obtain the preset total command data structure and parse the target host command to parse out the split indication information, target starting address, target data length, and operation type, and re-combine this information according to the preset total command data structure to obtain the target total command.

[0129] Step S202, obtaining storage location information of the target general command.

[0130] The storage location information may be a pointer, which is used to indicate the storage location of the target general command in the memory.

[0131] Specifically, after acquiring the target general command, the IO receiver may transmit the target general command to the RAW IO splitter, and the RAW IO splitter processes the target general command and stores it in the memory.

[0132] Step S203: determining at least one sub-command corresponding to the target general command according to the target start address, the target data length, the preset stripe size, and the storage location information.

[0133] The subcommand may be the above-mentioned RAC IO.

[0134] Since the target total command may be a command for cross-stripe operation or a command for non-cross-stripe operation, the target total command may be processed to divide it into sub-commands that do not require cross-stripe operation. Accordingly, the specific steps of the RAW IO splitter processing the target total command may be as follows:

[0135] Step 1: Determine at least one sub-starting address and a sub-data length corresponding to each sub-starting address according to the target starting address, the target data length and the stripe size.

[0136] Step 1: Determine the target stripe offset according to the target start address and stripe size.

[0137] Step 2: In the first processing round, the target start address is determined as the first sub-start address.

[0138] Step 3: Determine the first sub-data length corresponding to the first sub-start address according to the stripe size and the target stripe offset.

[0139] Step 4, determine whether the length of the first sub-data is smaller than the target data length.

[0140] Step 5: When it is determined that the first sub-data length is equal to the target data length, the processing is terminated to obtain a sub-start address and a sub-data length.

[0141] Step 6: When it is determined that the length of the first sub-data is smaller than the target data length, enter the next processing round corresponding to the first processing round.

[0142] Step 7: In a current processing round that is not the first processing round, determine the sub-starting address of the current processing round according to the sub-starting address and sub-data length corresponding to the previous processing round corresponding to the current processing round.

[0143] Step 8: Determine the remaining data length according to the sub-data lengths and target data lengths corresponding to all processing rounds before the current processing round.

[0144] Step 9, determine whether the remaining data length is greater than the stripe size.

[0145] Step 10: When the remaining data length is greater than the stripe size, the stripe size is determined as the sub-data length of the current processing round, and the next processing round is entered.

[0146] Step 11, when it is determined that the remaining data length is less than or equal to the stripe size, the remaining data length is determined as the sub-data length of the current processing round, and the processing is terminated to obtain multiple sub-starting addresses and the sub-data length corresponding to each of the multiple sub-starting addresses.

[0147] Specifically, the RAW IO splitter can use the following expression to determine the target stripe offset:

[0148] O=MSLBA Mod Stripe_Length

[0149] Among them, O is the target stripe offset, MSLBA is the target start address, Stripe_Length is the stripe size, and Mod is the modulo operation.

[0150] When determining the first sub-command, the RAW IO splitter can determine the target start address as the sub-start address corresponding to the first sub-command (i.e., the first sub-start address), and determine the remaining data length obtained by subtracting the target stripe offset from the stripe size as the sub-data length corresponding to the first sub-command (i.e., the first sub-data length). Then, the RAW IO splitter can determine whether the sub-data length is equal to the target data length. If so, no splitting is required, that is, the target total command corresponds to only one sub-command, i.e., itself. If not, it means that the target total command needs to be split, and the RAW IO splitter can enter the next processing round to determine the sub-start address and sub-data length of the next sub-command.

[0151] The RAW IO splitter can determine the sum of the first sub-start address and the first sub-data length as the second sub-start address. In addition, the target data length can be subtracted from the first sub-data length to obtain the remaining data length. At this time, it can be determined whether the remaining data length is greater than the stripe size. If so, it means that it needs to be split again, and the stripe size can be determined as the second sub-data length. If not, it means that the second sub-command is the last sub-command in the target total command, and the remaining data length can be determined as the second sub-data length.

[0152] By analogy, at least one sub-start address and at least one sub-data length corresponding to the target general command can be obtained.

[0153] Step 2: Determine the order of each sub-starting address according to the size of each sub-starting address.

[0154] Specifically, the RAW IO splitter may sort each sub-starting address from large to small according to the sub-starting address.

[0155] Step three, generating a sub-command corresponding to each sub-starting address according to the storage location information of the target general command, each sub-starting address, the sub-data length corresponding to each sub-starting address, and the order of each sub-starting address.

[0156] Specifically, the RAW IO splitter can process the storage location information of the target general command, each sub-starting address, the sub-data length corresponding to each sub-starting address, and the sorting of each sub-starting address according to a preset sub-command data structure to obtain at least one sub-command corresponding to the target general command.

[0157] In some optional implementations, the RAW IO splitter may also obtain the operation type of the target general command and use the operation type as information in the subcommand. For example, the subcommand data structure may be as follows: Figure 3 As shown, "parent_addr" is the storage location information of the target total command, and "split_bit_pos" is the order of the sub-start addresses.

[0158] exist Figure 3 In the example, IO-1 is split into two sub-commands, namely IO-1-1 and IO-1-2, while IO-2 is not split. Figure 4 As shown, after processing IO1, IO-1-1 operates on stripe 0, IO-1-2 operates on stripe 1, and IO-2 is not split and only operates on stripe 1.

[0159] In some optional implementations, after step 1 in step S203, the RAW IO splitter can also determine the bit corresponding to the sorting of each sub-starting address from the plurality of bits according to the sorting of each sub-starting address. The bit corresponding to the sorting of each sub-starting address is set to a first preset value. The default value of each bit can be a second preset value. The first preset value can be 0, and the second preset value can be 1.

[0160] In this way, by setting a specific bit to mark the processing status of the subcommand, it can be ensured that which subcommands have been processed can be accurately known, thereby preventing repeated processing or missing processing.

[0161] Step S204: Determine first stripe identification information of the first subcommand according to the sub-start address and stripe size included in the first subcommand.

[0162] The first subcommand is any subcommand of the at least one subcommand.

[0163] Specifically, the sub-command distributor may calculate the identification information of the stripe where the data operated by the first sub-command is located, that is, the first stripe identification information, according to the sub-start address and the stripe size included in the first sub-command.

[0164] For example, the following expression can be used to calculate the first band identification information:

[0165] StripeID=ZSLBA%Stripe_Length

[0166] Among them, StripeID is the first stripe identification information, ZSLBA is the sub-start address included in the first sub-command, and Stripe_Length is the stripe size.

[0167] Step S205: obtaining a target correspondence table of hardware computing accelerator numbers and allocation index values.

[0168] The target correspondence table may be a hash table. For example, the hash table may be as follows: Figure 5 shown.

[0169] Specifically, the sub-command distributor may read the target correspondence table from the memory.

[0170] Step S206: determining a target hardware computing accelerator from a plurality of pre-built hardware computing accelerators according to the first stripe identification information, the preset allocation algorithm and the target correspondence table.

[0171] Among them, the preset allocation algorithm is a hash algorithm.

[0172] Specifically, after determining the first stripe identification information and obtaining the target correspondence table, the subcommand distributor determines the target hardware computing accelerator from among the multiple hardware computing accelerators of the RAID controller according to the following steps:

[0173] Step 1: Determine the target allocation index value according to the first stripe identification information and a preset allocation algorithm.

[0174] For example, step 1 can be expressed as follows:

[0175] Hash Key = StripeID%K

[0176] The preset allocation algorithm may be a hash algorithm. Hash Key is the target allocation index value, StripeID is the first stripe identification information, and K is a third preset value. For example, K may be 128, which may be the same as the length of the target correspondence table.

[0177] Step 2: Determine whether there is a target number corresponding to the target allocation index value in the target correspondence table.

[0178] Step three: when it is determined that there is a target number corresponding to the target allocation index value in the target correspondence table, the hardware computing accelerator corresponding to the target number is determined as the target hardware computing accelerator.

[0179] Step 4: When it is determined that there is no target number corresponding to the target allocation index value in the target correspondence table, the number of uncompleted subcommands of each hardware computing accelerator is obtained.

[0180] Step 5: Determine the target hardware computing accelerator according to the number of uncompleted subcommands of each hardware computing accelerator.

[0181] Step 1: Determine the hardware computing accelerator with the least number of uncompleted subcommands according to the number of uncompleted subcommands of each hardware computing accelerator.

[0182] Step 2: When there is only one hardware computing accelerator with the least number of subcommands, directly determine the hardware computing accelerator with the least number of subcommands as the target hardware computing accelerator.

[0183] Step 3: When there are multiple hardware computing accelerators with the least number of subcommands, select the hardware computing accelerator with the smallest number from the multiple hardware computing accelerators with the least number of subcommands as the target hardware computing accelerator.

[0184] Specifically, the subcommand distributor may first calculate the target allocation index value based on the first strip identification information and the preset allocation algorithm. Further, it may determine whether there is a target number bound to the target allocation index value in the target correspondence table. If so, the hardware computing accelerator with the target number may be directly determined based on the target number. If not, the number of unfinished subcommands of each hardware computing accelerator may be obtained, and the hardware computing accelerator with the least number of subcommands may be determined therefrom. If there is only one hardware computing accelerator with the least number of subcommands, the hardware computing accelerator with the least number of subcommands may be determined as the target hardware computing accelerator. If there are multiple hardware computing accelerators with the least number of subcommands, the hardware computing accelerator with the smallest number may be selected from the hardware computing accelerator with the least number of subcommands as the target hardware computing accelerator.

[0185] In this way, the data processing efficiency of the first subcommand can be improved by selecting the hardware computing accelerator with the least number of subcommands as the target hardware computing accelerator.

[0186] In some optional implementations, after step 5, the subcommand distributor may also obtain the serial number of the target hardware computing accelerator, and update the target correspondence table according to the target allocation index value and the serial number of the target hardware computing accelerator.

[0187] Specifically, the subcommand distributor may bind the target allocation index value to the serial number of the target hardware computing accelerator.

[0188] In the related art, a method of pre-determining the correspondence between the type of stripe identification information and the number of the target hardware computing accelerator may be adopted. For example, when the stripe identification information of the command is an odd number, it is assigned to the first hardware computing accelerator, and when the stripe identification information of the command is an even number, it is assigned to the second hardware computing accelerator. However, there may be a situation where there are more commands with even stripe identification information, resulting in a large load on a certain hardware computing accelerator, an unbalanced load, and the problem that hardware resources are not fully utilized.

[0189] This solution does not need to create a complete correspondence table in advance, but can improve the target correspondence table according to the actual hardware computing accelerator processing sub-command situation, which is more in line with the actual situation, can ensure load balancing, and fully utilize hardware resources.

[0190] Step S207: distribute the first subcommand to the target hardware computing accelerator.

[0191] Specifically, the RAID controller can add the first subcommand to the end of the target queue corresponding to the target hardware computing accelerator, so that when the target hardware computing accelerator determines the processing order of the first subcommand according to the order of each subcommand in the target queue, it processes the first subcommand and obtains a return result corresponding to the first subcommand. The target queue can be a queue corresponding to the target hardware computing accelerator in the above-mentioned multiple RAC IO queues. When the operation type included in the first subcommand is a read operation, the return result can include the read data, and when the operation type included in the first subcommand is a write operation, the return result can include success indication information or failure indication information.

[0192] After the target hardware computing accelerator processes the first subcommand, the storage location information of the target general command and the order of the first sub-starting address can be extracted from the first subcommand. The target general command is determined according to the storage location information of the target general command. According to the order of the first sub-starting address, a first bit corresponding to the order of the first sub-starting address is determined from a plurality of bits of the target general command. The first bit is set to a second preset value.

[0193] The first preset value is used to indicate that the first subcommand has not been processed by any hardware computing accelerator, and the second preset value is used to indicate that the first subcommand has been processed by the target hardware computing accelerator.

[0194] In some optional embodiments, after setting the first bit to the second preset value, the IO responder may also determine whether the value of each of the multiple bits of the target general command is the second preset value. When it is determined that the value of each of the multiple bits in the split indication information of the target general command is the second preset value, the return result corresponding to at least one sub-command corresponding to the target general command is obtained. According to the return result corresponding to at least one sub-command corresponding to the target general command, the total return result corresponding to the target general command is determined. The total return result is fed back to the host end.

[0195] Specifically, after the target hardware computing accelerator processes the first subcommand, the first subcommand can be sent to the RAC IO recycler, which reclaims the storage resources and computing resources occupied by the RAC, and sends the first subcommand and the return result of the first subcommand to the IO responder. The IO responder determines the target total command in the memory according to the memory location information, and further, according to the sorting of the sub-start addresses included in the first subcommand, modifies the bit corresponding to the sorting in the target total command to a second preset value. When the IO responder determines that the value of each bit in the target total command is the second preset value, it can be determined that the target total command is completed, and the total return result can be formed according to the return result of each subcommand corresponding to the target total command and sent to the host side.

[0196] In this way, once it is confirmed that all subcommands have been processed, the results are immediately summarized and fed back to the host, ensuring the timeliness of task feedback.

[0197] The command allocation method provided in this embodiment, first, this scheme can first obtain the general command and its storage location information. Then, according to the starting address, data length, storage location information and stripe size in the general command, the general command can be processed to obtain at least one sub-command. Each sub-command can have its own sub-starting address and sub-data length. Further, the stripe identification information of the sub-command can be determined according to the sub-starting address and the stripe size. Finally, according to the stripe identification information, the preset allocation algorithm, and the target correspondence table of the number of the hardware computing accelerator and the allocation index value, the hardware computing accelerator corresponding to the sub-command is determined, so that the hardware computing accelerator can process the sub-command. Through the above-mentioned processing method, each general command can be divided into one or more sub-commands, and each sub-command can be allocated to the corresponding hardware computing accelerator according to its corresponding stripe identification information. In this way, sub-commands with the same stripe identification information can be allocated to the same hardware computing accelerator, without the need to perform a stripe locking operation, making full use of hardware resources, and improving command processing efficiency.

[0198] The following is a specific example to illustrate the process of the above command allocation method. Figure 6 As shown, the distribution of 4 IOs in stripes is shown, IO-1 and IO-3 are on stripe 0, IO-2 is on stripe 1, and IO4 is on stripe 129.

[0199] For each IO, the process of allocating hardware computing accelerators can be as follows:

[0200] IO-1: Calculate the allocation index value = 0. At this time, the allocation index value has not been bound. Then query the number of unfinished subcommands of each hardware computing accelerator. Here, the number of unfinished subcommands of RAC0 and RAC1 is 0. Then bind the allocation index value to RAC0, and RAC IO will be submitted to RAC0.

[0201] IO-2: Calculate the allocation index value = 1. At this time, the allocation index value has not been bound. Then query the number of unfinished subcommands of RAC. At this time, the number of unfinished subcommands of RAC0 = 1, and the number of unfinished subcommands of RAC1 = 0. It can be considered that the load of RAC0 is greater than that of RAC1. Therefore, the allocation index value = 1 is bound to RAC1, and then IO-2 is submitted to RAC1.

[0202] IO-3: The calculated allocation index value = 0. At this time, the allocation index value has been bound to RAC0, and the RAC IO is submitted to RAC0.

[0203] IO-4: the calculated allocation index value = 1, at this time the allocation index value has been bound to RAC1, and the RAC IO is submitted to RAC1.

[0204] After the load balancing algorithm is used, the two RACs process two IOs respectively. IO-1 and IO-3 are submitted to RAC0 for execution, and IO-2 and IO-4 are submitted to RAC1 for execution, thus achieving load balancing. The RAC binding relationship in the final hash table is as follows: Figure 7 shown.

[0205] like Figure 8 As shown in the figure, the subcommand distributor can continuously submit IO to the RAC IO queue, that is, after the subcommand distributor processes one RAC IO, it will immediately process the next RAC IO. Refer to the time dimension effect diagram in the figure below. After the subcommand distributor processes IO-1, it immediately processes IO-2. It can be seen that although IO-1 and IO-2 are not executed on the RAC at the same time, they can also achieve parallel effects. In addition, since the processing speed of the subcommand distributor is much faster than that of the RAC, the startup timing difference of IO-1 and IO-2 on the RAC module is relatively small. In the figure below, IO-1 and IO-3 are executed on RAC0 one after another. Since RAC supports pipelines, that is, one IO processing may involve multiple stages. When RAC finishes the first stage of IO-1 processing, it can simultaneously execute the second stage of IO-1 processing and the first stage of IO-3 processing. Therefore, IO-1 and IO-3 can also be regarded as parallel execution. In this way, the overall IO processing efficiency is relatively high.

[0206] In this embodiment, a command distribution device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0207] This embodiment provides a command distribution device, such as Fig. 9 As shown, including:

[0208] The acquisition module 901 is used to acquire a target general command; acquire storage location information of the target general command, wherein the target general command includes a target start address and a target data length;

[0209] A determination module 902 is used to determine at least one subcommand corresponding to the target general command according to the target start address, the target data length, the preset stripe size, and the storage location information, wherein each subcommand includes a sub-start address and a sub-data length; determine first stripe identification information of a first subcommand according to the sub-start address and the stripe size included in the first subcommand, wherein the first subcommand is any one of the at least one subcommand;

[0210] The acquisition module 901 is further used to obtain a target correspondence table between the serial number of the hardware computing accelerator and the allocation index value;

[0211] The determination module 902 is further configured to determine a target hardware computing accelerator from among a plurality of pre-built hardware computing accelerators according to the first stripe identification information, the preset allocation algorithm and the target correspondence table;

[0212] The allocation module 903 is used to allocate the first subcommand to the target hardware computing accelerator, so that the target hardware computing accelerator processes the first subcommand to obtain a return result corresponding to the first subcommand.

[0213] In some optional implementations, the determination module 902 is specifically configured to:

[0214] Determine at least one sub-starting address and a sub-data length corresponding to each sub-starting address according to the target starting address, the target data length and the stripe size;

[0215] According to the size of each sub-starting address, determine the order of each sub-starting address;

[0216] A sub-command corresponding to each sub-starting address is generated according to the storage location information of the target general command, each sub-starting address, the sub-data length corresponding to each sub-starting address, and the order of each sub-starting address.

[0217] In some optional implementations, the determination module 902 is specifically configured to:

[0218] Determine the target stripe offset according to the target start address and stripe size;

[0219] In the first processing round, the target start address is determined as the first sub-start address;

[0220] Determine the first sub-data length corresponding to the first sub-start address according to the stripe size and the target stripe offset;

[0221] Determine whether the first sub-data length is less than the target data length;

[0222] When it is determined that the first sub-data length is equal to the target data length, the processing is terminated to obtain a sub-start address and a sub-data length.

[0223] In some optional implementations, the determination module 902 is further configured to:

[0224] When it is determined that the length of the first sub-data is less than the target data length, entering the next processing round corresponding to the first processing round;

[0225] In a current processing round that is not the first processing round, determining a sub-starting address of the current processing round according to a sub-starting address and a sub-data length corresponding to a previous processing round corresponding to the current processing round;

[0226] Determine the remaining data length according to the sub-data lengths and target data lengths respectively corresponding to all processing rounds before the current processing round;

[0227] Determine whether the remaining data length is greater than the stripe size;

[0228] When the remaining data length is greater than the stripe size, the stripe size is determined as the sub-data length of the current processing round, and the next processing round is entered.

[0229] In some optional implementations, the determination module 902 is further configured to:

[0230] When it is determined that the remaining data length is less than or equal to the stripe size, the remaining data length is determined as the sub-data length of the current processing round, and the processing is terminated to obtain multiple sub-starting addresses and the sub-data length corresponding to each of the multiple sub-starting addresses.

[0231] In some optional implementations, the target general command also includes split indication information, and the split indication information includes multiple bits;

[0232] The determination module 902 is further used for:

[0233] According to the order of each sub-starting address, a bit corresponding to the order of each sub-starting address is determined from a plurality of bits;

[0234] The bits corresponding to the order of each sub-start address are all set to a first preset value, where the first preset value is used to indicate that the first sub-command is not processed by any hardware computing accelerator.

[0235] In some optional implementations, the determination module 902 is specifically configured to:

[0236] Determine a target allocation index value according to the first stripe identification information and a preset allocation algorithm;

[0237] Determine whether there is a target number corresponding to the target allocation index value in the target correspondence table;

[0238] When it is determined that there is a target number corresponding to the target allocation index value in the target correspondence table, the hardware computing accelerator corresponding to the target number is determined as the target hardware computing accelerator.

[0239] In some optional implementations, the determination module 902 is further configured to:

[0240] When it is determined that there is no target number corresponding to the target allocation index value in the target correspondence table, obtaining the number of uncompleted subcommands of each of the multiple hardware computing accelerators;

[0241] The target hardware computing accelerator is determined according to the number of uncompleted subcommands of each hardware computing accelerator.

[0242] In some optional implementations, the determination module 902 is specifically configured to:

[0243] Determine, according to the number of uncompleted subcommands of each hardware computing accelerator, a hardware computing accelerator having the least number of uncompleted subcommands;

[0244] When the hardware computing accelerator with the least number of subcommands is one, directly determining the hardware computing accelerator with the least number of subcommands as the target hardware computing accelerator;

[0245] or,

[0246] When there are multiple hardware computing accelerators with the least number of subcommands, the hardware computing accelerator with the smallest number is selected from the multiple hardware computing accelerators with the least number of subcommands as the target hardware computing accelerator.

[0247] In some optional implementations, the device further includes a setting module 904;

[0248] The setting module 904 is used to:

[0249] After the target hardware computing accelerator has processed the first subcommand, the storage location information of the target total command and the order of the first sub-start address are extracted from the first subcommand;

[0250] Determine the target general command according to the storage location information of the target general command;

[0251] According to the sequence of the first sub-starting addresses, determining a first bit corresponding to the sequence of the first sub-starting addresses from among a plurality of bits of the target general command;

[0252] The first bit is set to a second preset value, wherein the second preset value is used to indicate that the first subcommand has been processed by the target hardware computing accelerator.

[0253] In some optional implementations, the allocation module 903 is used to:

[0254] The first subcommand is added to the end of the target queue corresponding to the target hardware computing accelerator, so that when the target hardware computing accelerator determines the processing order of the first subcommand according to the order of each subcommand in the target queue, it processes the first subcommand and obtains a return result corresponding to the first subcommand.

[0255] In some optional implementations, the acquisition module 901 is specifically configured to:

[0256] Get the target host command sent by the host;

[0257] Get the preset total command data structure;

[0258] According to the general command data structure, the target host command is converted to obtain the target general command.

[0259] In some optional embodiments, the device further includes a feedback module 905;

[0260] The feedback module 905 is used to:

[0261] Determining whether the value of each of the multiple bits of the target general command is a second preset value;

[0262] When it is determined that the value of each of the multiple bits in the split indication information of the target general command is the second preset value, obtaining the return results respectively corresponding to at least one sub-command corresponding to the target general command;

[0263] Determine a total return result corresponding to the target general command according to the return results respectively corresponding to at least one subcommand corresponding to the target general command;

[0264] Feedback the total return result to the host.

[0265] In some optional implementations, the target allocation index value is determined according to the first stripe identification information and a preset allocation algorithm, using the following expression:

[0266] Hash Key = StripeID%K

[0267] Among them, Hash Key is the target allocation indicator value, StripeID is the first strip identification information, and K is the third preset value.

[0268] In some optional implementations, the apparatus further includes an updating module 906;

[0269] The updating module 906 is specifically used for:

[0270] Get the target hardware computing accelerator number;

[0271] The target correspondence table is updated according to the target allocation index value and the serial number of the target hardware computing accelerator.

[0272] In some optional implementations, the first stripe identification information of the first subcommand is determined according to the sub-start address and the stripe size included in the first subcommand, using the following expression:

[0273] StripeID=ZSLBA%Stripe_Length

[0274] Among them, StripeID is the first stripe identification information, ZSLBA is the sub-start address included in the first sub-command, and Stripe_Length is the stripe size.

[0275] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0276] The command distribution device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0277] The embodiment of the present invention also provides a computer device having the above Fig. 9 The command distribution device shown.

[0278] See also Fig.10 , Fig.10 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig.10 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig.10 A processor 10 is taken as an example.

[0279] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware integrated circuit. The hardware integrated circuit may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable logic gate array, a general purpose array logic or any combination thereof.

[0280] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0281] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0282] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0283] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0284] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0285] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0286] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A command distribution method, characterized in that: The method comprises: Obtaining a target general command, wherein the target general command includes a target start address and a target data length; Obtaining storage location information of the target general command; Determine at least one sub-command corresponding to the target general command according to the target start address, the target data length and the preset stripe size, and the storage location information, wherein each of the sub-commands includes a sub-start address and a sub-data length; Determine first stripe identification information of the first subcommand according to the sub-start address and the stripe size included in the first subcommand, wherein the first subcommand is any one of the at least one subcommand; Obtain a target correspondence table of hardware computing accelerator numbers and allocation index values; Determining a target hardware computing accelerator from a plurality of pre-built hardware computing accelerators according to the first stripe identification information, the preset allocation algorithm and the target correspondence table; The first subcommand is distributed to the target hardware computing accelerator, so that the target hardware computing accelerator processes the first subcommand to obtain a return result corresponding to the first subcommand.

2. The method according to claim 1, characterized in that The determining, according to the target start address, the target data length and the preset stripe size, and the storage location information, at least one sub-command corresponding to the target general command comprises: Determine at least one sub-starting address and a sub-data length corresponding to each of the sub-starting addresses according to the target starting address, the target data length and the stripe size; Determining the order of each of the sub-starting addresses according to the size of each of the sub-starting addresses; A sub-command corresponding to each sub-starting address is generated according to the storage location information of the target general command, each sub-starting address, the sub-data length corresponding to each sub-starting address, and the order of each sub-starting address.

3. The method according to claim 2, characterized in that The step of determining at least one sub-starting address and a sub-data length corresponding to each of the sub-starting addresses according to the target starting address, the target data length and the stripe size comprises: Determine a target stripe offset according to the target start address and the stripe size; In a first processing round, the target start address is determined as the first sub-start address; Determine, according to the stripe size and the target stripe offset, a first sub-data length corresponding to the first sub-start address; Determine whether the first sub-data length is less than the target data length; When it is determined that the first sub-data length is equal to the target data length, the processing is terminated to obtain a sub-start address and a sub-data length.

4. The method according to claim 3, characterized in that The method further comprises: When it is determined that the length of the first sub-data is less than the target data length, entering a next processing round corresponding to the first processing round; In a current processing round that is not the first processing round, determining a sub-starting address of the current processing round according to a sub-starting address and a sub-data length corresponding to a previous processing round corresponding to the current processing round; Determine the remaining data length according to the sub-data lengths respectively corresponding to all processing rounds before the current processing round and the target data length; Determining whether the remaining data length is greater than the stripe size; When the remaining data length is greater than the stripe size, the stripe size is determined as the sub-data length of the current processing round, and the next processing round is entered.

5. The method according to claim 4, characterized in that The method further comprises: When it is determined that the remaining data length is less than or equal to the stripe size, the remaining data length is determined as the sub-data length of the current processing round, and the processing is terminated to obtain multiple sub-starting addresses and the sub-data length corresponding to each of the multiple sub-starting addresses.

6. The method according to any one of claims 2 to 5, characterized in that: The target general command also includes split indication information, and the split indication information includes multiple bits; After generating a sub-command corresponding to each sub-starting address according to the storage location information of the target general command, each sub-starting address, the sub-data length corresponding to each sub-starting address, and the sorting of each sub-starting address, the method further includes: According to the order of each of the sub-starting addresses, determining a bit corresponding to the order of each of the sub-starting addresses from the plurality of bits; The bits corresponding to the order of each of the sub-start addresses are set to a first preset value, where the first preset value is used to indicate that the first sub-command is not processed by any hardware computing accelerator.

7. The method according to any one of claims 1 to 5, characterized in that: The step of determining a target hardware computing accelerator from a plurality of pre-built hardware computing accelerators according to the first stripe identification information, the preset allocation algorithm, and the target correspondence table includes: Determining a target allocation index value according to the first stripe identification information and the preset allocation algorithm; Determine whether there is a target number corresponding to the target allocation index value in the target correspondence table; When it is determined that there is a target number corresponding to the target allocation index value in the target correspondence table, the hardware computing accelerator corresponding to the target number is determined as the target hardware computing accelerator.

8. The method according to claim 7, characterized in that When it is determined that there is no target number corresponding to the target allocation index value in the target correspondence table, the method further includes: Obtaining the number of uncompleted subcommands of each of the hardware computing accelerators; The target hardware computing accelerator is determined according to the number of uncompleted subcommands of each of the hardware computing accelerators.

9. The method according to claim 8, characterized in that The step of determining the target hardware computing accelerator according to the number of uncompleted subcommands of each of the hardware computing accelerators comprises: Determine, according to the number of uncompleted subcommands of each of the hardware computing accelerators, a hardware computing accelerator having the least number of uncompleted subcommands; When the hardware computing accelerator with the least number of subcommands is one, directly determining the hardware computing accelerator with the least number of subcommands as the target hardware computing accelerator; or, When there are multiple hardware computing accelerators with the least number of subcommands, the hardware computing accelerator with the smallest number is selected from the multiple hardware computing accelerators with the least number of subcommands as the target hardware computing accelerator.

10. The method according to claim 6, characterized in that The method further comprises: After the target hardware computing accelerator has processed the first subcommand, extracting the storage location information of the target general command and the order of the first sub-start address from the first subcommand; Determining the target general command according to the storage location information of the target general command; According to the sequence of the first sub-starting addresses, determining a first bit corresponding to the sequence of the first sub-starting addresses from among the multiple bits of the target general command; The first bit is set to a second preset value, wherein the second preset value is used to indicate that the first subcommand has been processed by the target hardware computing accelerator.

11. The method according to any one of claims 1 to 5, characterized in that: The allocating the first subcommand to the target hardware computing accelerator comprises: The first subcommand is added to the end of the target queue corresponding to the target hardware computing accelerator, so that when the target hardware computing accelerator determines the processing order of the first subcommand according to the order of each subcommand in the target queue, the first subcommand is processed to obtain a return result corresponding to the first subcommand.

12. The method according to claim 10, characterized in that The acquisition target total command includes: Get the target host command sent by the host; Get the preset total command data structure; The target host command is converted according to the general command data structure to obtain the target general command.

13. The method according to claim 12, characterized in that After setting the first bit to a second preset value, the method further includes: Determine whether the value of each of the multiple bits of the target general command is the second preset value; When it is determined that the value of each of the multiple bits in the split indication information of the target general command is the second preset value, obtaining return results respectively corresponding to at least one sub-command corresponding to the target general command; Determine a total return result corresponding to the target general command according to the return results respectively corresponding to at least one subcommand corresponding to the target general command; The total return result is fed back to the host end.

14. The method according to claim 7, characterized in that The target allocation index value is determined according to the first stripe identification information and the preset allocation algorithm, using the following expression: Hash Key = StripeID%K Among them, Hash Key is the target allocation indicator value, StripeID is the first stripe identification information, and K is a third preset value.

15. The method according to claim 8, characterized in that After determining the target hardware computing accelerator according to the number of uncompleted subcommands of each of the hardware computing accelerators, the method further includes: Obtaining the serial number of the target hardware computing accelerator; The target correspondence table is updated according to the target allocation index value and the serial number of the target hardware computing accelerator.

16. The method according to any one of claims 1 to 5, characterized in that: The first stripe identification information of the first subcommand is determined according to the sub-start address and the stripe size included in the first subcommand, using the following expression: StripeID=ZSLBA%Stripe_Length Among them, StripeID is the first stripe identification information, ZSLBA is the sub-start address included in the first subcommand, and Stripe_Length is the stripe size.

17. A command distribution device, characterized in that: The device comprises: An acquisition module is used to acquire a target general command; acquire storage location information of the target general command, wherein the target general command includes a target start address and a target data length; a determination module, configured to determine at least one subcommand corresponding to the target general command according to the target start address, the target data length and the preset stripe size, and the storage location information, wherein each of the subcommands includes a sub-start address and a sub-data length; determine first stripe identification information of the first subcommand according to the sub-start address and the stripe size included in the first subcommand, wherein the first subcommand is any one of the at least one subcommand; The acquisition module is further used to obtain a target correspondence table between the serial number of the hardware computing accelerator and the allocation index value; The determination module is further configured to determine a target hardware computing accelerator from a plurality of pre-built hardware computing accelerators according to the first stripe identification information, a preset allocation algorithm and the target correspondence table; The allocation module is used to allocate the first subcommand to the target hardware computing accelerator, so that the target hardware computing accelerator processes the first subcommand to obtain a return result corresponding to the first subcommand.

18. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the command allocation method according to any one of claims 1 to 16 by executing the computer instructions.

19. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the command distribution method according to any one of claims 1 to 16.

20. A computer program product, characterized in that The method comprises computer instructions for causing a computer to execute the command distribution method according to any one of claims 1 to 16.

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