Floating point multiplication and addition operation method and device, electronic equipment and storage medium

Abstract

The invention relates to a floating point multiplication and addition operation method and device, electronic equipment and a storage medium. Comprising the following steps: uniformly converting data types of a first operand, a second operand and a third operand into a preset data type, and analyzing a boundary result and a boundary mark signal corresponding to the boundary result when the new first operand, the new second operand and the new third operand are operated according to a preset multiplication and addition operation sequence; calculating original multiply-add tail values of the new first operand, the new second operand and the new third operand based on a preset multiply-add operation sequence; and based on a preset floating-point number format and the boundary mark signal, carrying out normalization processing on the original multiply-add tail value to obtain a final floating-point result, and generating a corresponding floating-point abnormal signal. Therefore, the problems that the chip design verification process is more complex and the area overhead is increased due to the fact that different operation devices need to be designed according to different operation modes in an existing method are solved, and the operation frequency is improved.

Description

Technical Field

[0001] The present application relates to the field of floating-point number operation technology, and in particular to a floating-point multiplication and addition operation method, device, electronic device and storage medium. Background Art

[0002] Floating-point operations refer to mathematical operations between floating-point numbers. They are important functions that modern chips such as CPU (Central Processing Unit), GPU (Graphics Processing Unit) and NPU (Neural-network Processing Unit) need to have. The floating-point operations will affect the area, frequency and power consumption of the processor. Compared with integer operations, floating-point operations are more complicated, and they need to consider issues such as numerical precision, rounding error and overflow.

[0003] In the related art, operations of various modes and precisions generally require the design of different operation devices; for example, a floating-point addition module is specially designed to calculate the addition and subtraction of floating-point numbers, a floating-point multiplication module is specially designed to calculate the multiplication of floating-point numbers, and then a floating-point multiplication-addition module is specially designed to complete the multiplication-addition operation.

[0004] However, this method designs multiple computing devices to perform floating-point operations, which makes the chip design verification process more complicated and increases the area overhead, which needs to be solved urgently. Summary of the invention

[0005] The present application provides a floating-point multiplication and addition method, device, electronic device and storage medium to solve the problem that the existing method needs to design different operation devices according to different operation modes, which makes the chip design and verification process more complicated and increases the area overhead, so as to improve the operation frequency.

[0006] To achieve the above object, the first embodiment of the present application proposes a floating-point multiplication and addition method, comprising the following steps:

[0007] Get the first operand, the second operand, and the third operand;

[0008] uniformly converting the data types of the first operand, the second operand and the third operand into preset data types respectively to obtain a new first operand, a new second operand and a new third operand, and analyzing boundary conditions when the new first operand, the new second operand and the new third operand are operated according to a preset multiplication and addition operation sequence, wherein the boundary conditions include a boundary result and a boundary flag signal corresponding to the boundary result;

[0009] Based on the preset multiplication-addition operation order, calculating the original multiplication-addition mantissa values ​​of the new first operand, the new second operand, and the new third operand;

[0010] Based on the preset floating-point number format and the boundary flag signal, the original multiplication-addition mantissa value is normalized to obtain a final floating-point result, and a corresponding floating-point exception signal is generated.

[0011] According to an embodiment of the present application, the analyzing the boundary conditions when the new first operand, the new second operand, and the new third operand are operated according to a preset multiplication-addition operation order includes:

[0012] Determine in parallel whether the new first operand, the new second operand, and the new third operand are preset special cases to obtain a determination result, wherein the preset special cases include infinity, non-numeric value, and zero;

[0013] According to the judgment result and the preset multiplication and addition operation sequence, a corresponding boundary result is calculated, and a boundary mark signal corresponding to the boundary result is output.

[0014] According to one embodiment of the present application, when analyzing the boundary conditions when the new first operand, the new second operand, and the new third operand are operated according to the preset multiplication-addition operation order, it also includes:

[0015] Selecting the new first operand, the new second operand and the new third operand according to a preset multiplication-addition operation order;

[0016] When the current operation is an addition operation, setting the new third operand to a floating point number having a value of a first preset value;

[0017] When the current operation is a multiplication operation, the new first operand is set to a floating point number whose value is a second preset value.

[0018] According to an embodiment of the present application, the calculating, based on the preset multiplication-addition operation order, the original multiplication-addition mantissa values ​​of the new first operand, the new second operand, and the new third operand includes:

[0019] Based on the preset multiplication and addition operation order, calculate the product of the mantissa of the new second operand and the new third operand to obtain two partial products;

[0020] Determining, based on the new first operand exponent and the sum of the exponents of the two partial products, a multiplication-addition reference exponent value that needs to be aligned before performing an addition operation;

[0021] Based on the multiplication-addition reference exponent value, performing a shift operation on the new first operand and the two partial products to obtain an aligned first operand and two aligned partial products;

[0022] The aligned first operand and the two aligned partial products are combined and added to obtain the original multiplication-addition mantissa value.

[0023] According to an embodiment of the present application, the normalization processing of the original multiplication-addition mantissa value based on the preset floating-point number format and the boundary flag signal to obtain the final floating-point result and generate the corresponding floating-point exception signal includes:

[0024] Performing a leading zero detection on the original multiplication-addition mantissa value and shifting it left to eliminate the leading zero, obtaining a processed multiplication-addition mantissa value, and recording the number of left shifts to eliminate the leading zeros;

[0025] According to the sign bit of the processed multiplication-addition mantissa value, a negation operation and a rounding operation are performed on the processed multiplication-addition mantissa value to obtain a floating-point mantissa that satisfies the preset floating-point number format;

[0026] Subtract the number of left shifts from the multiplication-addition reference exponent value to obtain a floating-point exponent that satisfies the preset floating-point number format;

[0027] Based on the boundary flag signal, the floating-point mantissa and the floating-point exponent, the final floating-point result is obtained, and the corresponding floating-point exception signal is generated.

[0028] According to the floating-point multiplication and addition method proposed in the embodiment of the present application, by uniformly converting the data types of the first operand, the second operand and the third operand into preset data types, and analyzing the boundary conditions when the new first operand, the new second operand and the new third operand are operated according to the preset multiplication and addition operation order, a boundary result and a boundary flag signal corresponding to the boundary result can be obtained; based on the preset multiplication and addition operation order, the original multiplication and addition mantissa values ​​of the new first operand, the new second operand and the new third operand are calculated; based on the preset floating-point number format and the boundary flag signal, the original multiplication and addition mantissa values ​​are normalized to obtain the final floating-point result, and a corresponding floating-point exception signal is generated. Thus, the problem that the existing method needs to design different operation devices according to different operation modes, which makes the chip design verification process more complicated and the area overhead increased, is solved to improve the operation frequency.

[0029] To achieve the above-mentioned purpose, a second embodiment of the present application provides a floating-point multiplication and addition operation device, comprising:

[0030] An acquisition module, used for acquiring a first operand, a second operand and a third operand;

[0031] an analysis module, configured to uniformly convert the data types of the first operand, the second operand, and the third operand into preset data types respectively, obtain a new first operand, a new second operand, and a new third operand, and analyze boundary conditions when the new first operand, the new second operand, and the new third operand are operated in a preset multiplication-addition operation sequence, to obtain a boundary result and a boundary flag signal corresponding to the boundary result;

[0032] A calculation module, configured to calculate original multiplication-addition mantissa values ​​of the new first operand, the new second operand, and the new third operand based on the preset multiplication-addition operation order;

[0033] The processing module is used to perform normalization processing on the original multiplication and addition mantissa value based on a preset floating-point number format and the boundary mark signal to obtain a final floating-point result and generate a corresponding floating-point exception signal.

[0034] According to one embodiment of the present application, the analysis module is specifically used for:

[0035] Determine in parallel whether the new first operand, the new second operand, and the new third operand are preset special cases, and obtain a determination result, wherein the preset special cases include infinity, non-numeric value, and zero;

[0036] According to the judgment result and the preset multiplication and addition operation sequence, a corresponding boundary result is calculated, and a boundary mark signal corresponding to the boundary result is output.

[0037] According to one embodiment of the present application, when analyzing the boundary situation when the new first operand, the new second operand, and the new third operand are operated according to the preset multiplication and addition operation order, the analysis module is further used to:

[0038] Selecting the new first operand, the new second operand and the new third operand according to a preset multiplication-addition operation order;

[0039] When the current operation is an addition operation, setting the new third operand to a floating point number having a value of a first preset value;

[0040] When the current operation is a multiplication operation, the new first operand is set to a floating point number whose value is a second preset value.

[0041] According to one embodiment of the present application, the computing module is specifically used for:

[0042] Based on the preset multiplication and addition operation order, calculate the product of the mantissa of the new second operand and the new third operand to obtain two partial products;

[0043] Determining, based on the new first operand exponent and the sum of the exponents of the two partial products, a multiplication-addition reference exponent value that needs to be aligned before performing an addition operation;

[0044] Based on the multiplication-addition reference exponent value, performing a shift operation on the new first operand and the two partial products to obtain an aligned first operand and two aligned partial products;

[0045] The aligned first operand and the two aligned partial products are combined and added to obtain the original multiplication-addition mantissa value.

[0046] According to one embodiment of the present application, the processing module is specifically used to:

[0047] Performing a leading zero detection on the original multiplication-addition mantissa value and shifting it left to eliminate the leading zero, obtaining a processed multiplication-addition mantissa value, and recording the number of left shifts to eliminate the leading zeros;

[0048] According to the sign bit of the processed multiplication-addition mantissa value, a negation operation and a rounding operation are performed on the processed multiplication-addition mantissa value to obtain a floating-point mantissa that satisfies the preset floating-point number format;

[0049] Subtract the number of left shifts from the multiplication-addition reference exponent value to obtain a floating-point exponent that satisfies the preset floating-point number format;

[0050] Based on the boundary flag signal, the floating-point mantissa and the floating-point exponent, the final floating-point result is obtained, and the corresponding floating-point exception signal is generated.

[0051] According to the floating-point multiplication and addition operation device proposed in the embodiment of the present application, by uniformly converting the data types of the first operand, the second operand and the third operand into preset data types, and analyzing the boundary conditions when the new first operand, the new second operand and the new third operand are operated according to the preset multiplication and addition operation sequence, a boundary result and a boundary flag signal corresponding to the boundary result can be obtained; based on the preset multiplication and addition operation sequence, the original multiplication and addition mantissa values ​​of the new first operand, the new second operand and the new third operand are calculated; based on the preset floating-point number format and the boundary flag signal, the original multiplication and addition mantissa values ​​are normalized to obtain the final floating-point result, and a corresponding floating-point exception signal is generated. Thus, the problem that the existing method needs to design different operation devices according to different operation modes, which makes the chip design verification process more complicated and the area overhead increased, is solved to improve the operation frequency.

[0052] To achieve the above objectives, the third aspect of the present application proposes an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the floating-point multiplication and addition method as described in the above embodiments.

[0053] To achieve the above objectives, the fourth aspect of the present application proposes a computer-readable storage medium on which a computer program is stored. The program is executed by a processor to implement the floating-point multiplication and addition method as described in the above embodiments.

[0054] To achieve the above objectives, the fifth aspect of the present application proposes a computer program product, which includes a computer program. When the computer program is executed by a processor, it is used to implement the floating-point multiplication and addition method described in the above embodiments.

[0055] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0057] Figure 1 A flowchart of a floating-point multiplication and addition method provided according to an embodiment of the present application;

[0058] Figure 2 A schematic diagram of the structure of a floating-point multiplication-addition operation system according to an embodiment of the present application;

[0059] Figure 3 A flowchart of another floating-point multiplication and addition method provided according to an embodiment of the present application;

[0060] Figure 4 A three-stage pipeline implementation according to an embodiment of the present application;

[0061] Figure 5 An implementation method of a five-stage pipeline according to an embodiment of the present application;

[0062] Figure 6 It is a block diagram of a floating-point multiplication-addition operation device provided according to an embodiment of the present application;

[0063] Figure 7 It is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0064] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0065] The following describes a floating-point multiplication and addition method, device, electronic device, and storage medium proposed according to an embodiment of the present application with reference to the accompanying drawings.

[0066] Figure 1 It is a flowchart of a floating-point multiplication and addition method according to an embodiment of the present application.

[0067] Before introducing the floating-point multiplication and addition method proposed in the embodiment of the present application, the relevant technical background is first introduced.

[0068] A floating point number is a data type used to represent real numbers. It consists of a sign bit (indicating the positive or negative value of a number), an exponent (indicating the position of the decimal point), and a mantissa (indicating the number of significant digits after the decimal point). In computers, floating point numbers are usually represented in scientific notation. For example, the decimal number 3.14 can be represented as 0.314×10 1 , when using binary floating point representation in a computer (that is, the base is 2), first convert 3.14 into binary form to get 1.10010010000111111011011 (this is an infinite repeating decimal, but it will be truncated to a finite number of digits in the computer), and then express it in scientific notation, that is, +2 1 ×1.10010010000111111011011, where the sign bit is 0 (because 3.14 is a positive number), the exponent part is 1, and the mantissa part is 1.10010010000111111011011. When representing floating-point numbers in a computer, the mantissa part usually adopts a standardized representation form, namely the normalized form. This form requires that there must be a non-zero digit before the decimal point, in this example it is a non-zero digit 1. This 1 is implicit and will not be explicitly represented in the storage, thus saving one bit of storage space. Floating-point operations mainly include basic operations such as addition, subtraction, multiplication, and division, as well as some advanced operations such as square roots and trigonometric functions.

[0069] When performing floating-point operations, the data types involved may include single-precision floating point numbers fp32 (float point32, 32-bit floating point format), double-precision floating point numbers fp64 (float point 64, 64-bit floating point format), half-precision floating point numbers fp16 (float point 16, 16-bit floating point format), and brain floating point numbers bf16 (brain float point 16, a special 16-bit floating point format) specifically used for neural network machine learning and other data types.

[0070] In the design of floating-point modules, it is necessary to support operations of floating-point numbers with multiple precisions. In the prior art, for different data types, such as single-precision floating-point multiplication and double-precision floating-point multiplication, the multiplication implementation logic is often designed separately. This practice leads to logical redundancy, which in turn affects the maximum operating frequency that the chip can achieve. In addition, many operations also involve other precision requirements. For example, when two double-precision floating-point numbers are multiplied, the required result is a single-precision floating-point number. According to the prior art, the product of the double-precision floating-point number is first calculated, and then the product is input into the data format conversion module, through which the data format conversion from double precision to single precision is realized. This process requires more clock cycles to obtain the final operation result.

[0071] Since there are a large number of boundary cases or extreme cases in floating-point operations, existing designs generally perform classified operations for different situations. For example, floating-point addition requires evaluating whether the exponent difference exceeds a reasonable range (i.e., whether the exponent difference is greater than the mantissa length) or is too close (i.e., whether the exponent difference is less than 1); floating-point multiplication requires analyzing whether the multiplier and multiplicand are denormalized numbers, and in-depth analysis of factors such as the number of leading zeros in the mantissa of the denormalized number. This series of complex bypass designs results in certain limitations on the area and frequency of the computing device.

[0072] It is precisely based on the above-mentioned problems that the embodiment of the present application proposes a floating-point multiplication and addition method, which converts the addition, multiplication and multiplication and addition combined operations of different data types into unified standard double-precision floating-point multiplication and addition operations, and shares a main operation path; at the same time, for extreme situations that may occur in different operations, its bypass design can also share the same judgment logic, and only needs to judge whether the output result is a non-number or infinity. In other cases, the correct results can be obtained through the main operation path, thereby effectively reducing the delay of the operation path and reducing its occupied area.

[0073] The floating-point multiplication and addition operation method will be explained in detail below.

[0074] For example, Figure 1 As shown, the floating-point multiplication and addition operation method comprises the following steps:

[0075] In step S101 , a first operand, a second operand, and a third operand are obtained.

[0076] Among them, operands refer to the data or values ​​involved in the calculation process.

[0077] It can be understood that when performing a multiplication and addition operation, three operands need to be input to perform a mixed multiplication and addition operation in the form of ±(A±B*C) and output the operation result.

[0078] In step S102, the data types of the first operand, the second operand, and the third operand are uniformly converted into preset data types to obtain a new first operand, a new second operand, and a new third operand, and the boundary conditions of the new first operand, the new second operand, and the new third operand when they are operated in a preset multiplication and addition order are analyzed to obtain a boundary result and a boundary flag signal corresponding to the boundary result.

[0079] Among them, the preset data type can be fp64, fp32, etc.

[0080] Specifically, when performing floating-point operations, in order to ensure the uniformity and accuracy of the operations, it is necessary to convert floating-point operands of different formats into a unified, maximum supported data format. That is, if the maximum supported data format is fp64, then before performing the operation, other operand formats (such as fp32 or fp16) need to be converted to fp64 format.

[0081] For example, when the maximum supported data format is fp64, its exponent length is 11 and its mantissa length is 1+52. When the input operand is in fp32 format, its exponent length is 8 and its mantissa length is 1+23. In order to convert fp32 format to fp64 format, 3 zeros need to be added in front of the exponent part of fp32 to meet the exponent digit requirement of fp64. Similarly, 29 zeros need to be added after the mantissa part of fp32 to meet the mantissa digit requirement of fp64. This conversion ensures that all operands have the same format and precision when performing floating-point operations, thereby avoiding operation errors or precision loss caused by inconsistent formats.

[0082] Furthermore, after the operation sequence is clarified, the boundary conditions that may occur after the operation of the operands are identified and analyzed to obtain boundary results and boundary flag signals corresponding to the boundary results. Boundary conditions include but are not limited to infinity, non-numeric values, zero, and specific combinations of operands. Through in-depth analysis of these boundary conditions, the performance of the operation results under these extreme conditions can be predicted.

[0083] Next, how to obtain the boundary result and the boundary flag signal corresponding to the boundary result is described in detail.

[0084] As a possible implementation method, in some embodiments, the boundary conditions when a new first operand, a new second operand, and a new third operand are operated in a preset order of multiplication and addition are analyzed to obtain a boundary result and a boundary flag signal corresponding to the boundary result, including: judging in parallel whether the new first operand, the new second operand, and the new third operand are preset special cases to obtain a judgment result, wherein the preset special cases include infinity, non-numeric value, and zero; calculating the corresponding boundary result according to the judgment result and the preset order of multiplication and addition, and outputting a boundary flag signal corresponding to the boundary result.

[0085] Specifically, in the process of performing multiplication and addition operations, firstly, the data type of the new operand is combined to determine whether the input new operand is a special value such as infinity, non-numeric value or 0. Then, according to the judgment result and the order of multiplication and addition operations, the corresponding boundary result is calculated. This boundary result refers to the infinity or non-numeric situation that may occur in the operation under specific circumstances. In order to ensure the accuracy and reliability of the operation, a boundary mark signal (flag) corresponding to the boundary result can be output, that is, an infinity signal or a non-numeric signal. This signal will be used to indicate whether the operation result has reached a certain boundary value (such as infinity or non-numeric value), thereby providing important reference information for subsequent processing.

[0086] For example, when one operand is infinite and the other is zero, according to the multiplication rules, the result is a non-number; if both operands are infinite but have different signs, the result of their addition is also a non-number; if there is no non-number among the operands but one is infinite, then the result is still infinite, and so on.

[0087] It should be noted that the result of 0 does not require any boundary case processing and can be calculated using the normal operation path. Non-numbers can be divided into two types: QNaN (Quiet Not a Number, a non-number that does not trigger a floating point exception signal) and SNaN (Signaling Not a Number, a non-number that triggers an abnormal floating point signal). QNaN will not trigger an exception signal during operation, while SNaN will trigger an exception signal during operation. When processing these special values, it is necessary to decide whether to pull the corresponding invalid flag high based on their type. For example, SNaN will pull the corresponding invalid flag high.

[0088] Furthermore, in some embodiments, when analyzing the boundary conditions when a new first operand, a new second operand, and a new third operand are operated in a preset multiplication and addition order, it also includes: selecting the new first operand, the new second operand, and the new third operand in the preset multiplication and addition order; when the current operation is an addition operation, setting the new third operand to a floating-point number having a first preset value; and when the current operation is a multiplication operation, setting the new first operand to a floating-point number having a second preset value.

[0089] Specifically, the three new operands are matched and selected in the order of the preset multiplication and addition operation (i.e., A+B*C). If the operation is addition (i.e., A+B), the new third operand C is set to floating point 1, which is specifically manifested as: the sign bit is set to 0, the exponent part uses a floating point shift offset, the integer bit of the mantissa part is set to 1, and the decimal places are all set to 0; if the operation is multiplication (i.e., B*C), the new first operand A is set to floating point 0, that is, its sign bit, exponent, and mantissa are all 0.

[0090] In this way, addition and multiplication operation requests can be processed through a unified operation process, thereby simplifying the design complexity of the operation process and improving the operation efficiency.

[0091] In step S103, original multiplication-addition mantissa values ​​of a new first operand, a new second operand, and a new third operand are calculated based on a preset multiplication-addition operation order.

[0092] That is, according to the operation rule of A+B*C, the original multiplication and addition mantissa value based on the three new operands is calculated. First, the new second operand B and the new third operand C are multiplied, that is, the value of B multiplied by C is calculated; then, the obtained product result is added to the new first operand A, that is, the value of A plus the product just obtained is calculated; finally, the original multiplication and addition mantissa value is obtained.

[0093] How to calculate the original multiplication-addition mantissa values ​​of the new first operand, the new second operand, and the new third operand based on the preset multiplication-addition operation order will be described in detail below.

[0094] As a possible implementation method, in some embodiments, based on a preset multiplication and addition operation order, the original multiplication and addition mantissa values ​​of the new first operand, the new second operand, and the new third operand are calculated, including: based on the preset multiplication and addition operation order, calculating the product of the mantissas of the new second operand and the new third operand to obtain two partial products; based on the new first operand exponent and the sum of the exponents of the two partial products, determining the multiplication and addition reference exponent value that needs to be aligned before the addition operation; based on the multiplication and addition reference exponent value, shifting the new first operand and the two partial products to obtain an aligned first operand and the aligned two partial products; merging and adding the aligned first operand and the aligned two partial products to obtain the original multiplication and addition mantissa value.

[0095] Specifically, based on the preset multiplication and addition operation order (A+B*C), the product of the mantissa part of the new second operand and the new third operand (i.e., B*C) can be calculated first, and two partial products can be output. This part can use Booth coding technology and Wallace tree arrangement compression method to convert the originally complex multiplication operation into the summation process of two partial products. Next, a reference exponent value can be determined according to the exponent of the new first operand and the sum of the exponents of the two partial products, that is, the exponent of the first operand is compared with the sum of the exponents of the two partial products, and the maximum exponent is selected as the multiplication and addition reference exponent value. At the same time, the distance that the mantissa of the new first operand A needs to be shifted is calculated according to the multiplication and addition reference exponent value, thereby obtaining the aligned first operand and the aligned two partial products. Finally, the aligned first operand and the aligned two partial products are compressed into two operands by CSA (carry save adder), and then merged and added to obtain the final original multiplication and addition mantissa value (which may be positive or negative).

[0096] In step S104, based on the preset floating-point number format and boundary flag signal, the original multiplication-addition mantissa value is normalized to obtain a final floating-point result, and a corresponding floating-point exception signal is generated.

[0097] That is, when processing floating-point operations, operations can be performed according to a preset floating-point format and a boundary flag signal. The preset floating-point format usually includes an exponent and a mantissa, while the boundary flag signal is used to indicate special situations that may occur during the operation, such as an infinity signal and a non-numeric signal. By normalizing the mantissa value of the original multiplication and addition operation, it can be ensured that the result meets the preset floating-point format requirements. Normalization processing includes adjusting the mantissa to a standard range, usually by shifting the mantissa left or right until the most significant digit appears in a specific position. In this process, the adjustment of the exponent also needs to be considered to maintain the correctness of the value. Finally, through this normalization processing, a floating-point result that meets the standard can be obtained. At the same time, a corresponding floating-point exception signal can also be generated to indicate whether any abnormal situation occurs during the operation. These exception signals can be used for subsequent error handling or debugging to ensure the accuracy and reliability of floating-point operations.

[0098] The following describes in detail how to perform normalization processing on the original multiplication and addition mantissa value based on the preset floating-point number format and boundary flag signal to obtain the final floating-point result and generate the corresponding floating-point exception signal.

[0099] As a possible implementation method, in some embodiments, based on a preset floating-point format and a boundary flag signal, the original multiplication-addition mantissa value is normalized to obtain a final floating-point result, and a corresponding floating-point exception signal is generated, including: performing a leading zero detection on the original multiplication-addition mantissa value and left-shifting to eliminate the leading zeros to obtain a processed multiplication-addition mantissa value, and recording the number of left shifts to eliminate the leading zeros; according to the sign bit of the processed multiplication-addition mantissa value, negating and rounding the processed multiplication-addition mantissa value to obtain a floating-point mantissa that meets the preset floating-point format; subtracting the number of left shifts from the multiplication-addition reference exponent value to obtain a floating-point exponent that meets the preset floating-point format; based on the boundary flag signal, the floating-point mantissa and the floating-point exponent, the final floating-point result is obtained, and a corresponding floating-point exception signal is generated.

[0100] Specifically, the leading zero detection is performed on the original multiplication and addition mantissa value, and each bit of the mantissa value is scanned to determine whether there are consecutive zero values ​​at the front of the value. Once the leading zero is detected, the mantissa value can be left-shifted to eliminate these useless zero values. In the process of left shifting, the number of left shifts to eliminate the leading zeros can be recorded, and this value will be used in subsequent calculations.

[0101] It should be noted that the leading zero detection function has been carefully designed and optimized to ensure that after the shift operation, the value of the exponent part will only reach the exponent value corresponding to the denormalized number. This design is intended to avoid the exponent part from having too low a value, thereby ensuring the correctness of the value and the stability of the calculation.

[0102] Next, for the multiplication and addition mantissa value that has eliminated the leading zero, the sign bit of the mantissa value can be checked to determine whether it is positive or negative. According to the result of the sign bit, the mantissa value can be negated. That is, if the sign bit of the mantissa value is negative, then the mantissa value can be negated, that is, all the bits of the mantissa value are negated (0 becomes 1, 1 becomes 0). After the negation operation, an addition operation is required to ensure that the result after negation is correct. On the other hand, the mantissa value also needs to be rounded, and the rounding operation usually involves rounding the low bit of the mantissa or other rounding rules. After the rounding operation, an addition operation is also required to ensure that the result after rounding is correct. In order to reduce the overhead of the addition operation, the two steps of negation and addition and rounding and addition can be combined. In this way, the steps that originally required two addition operations can be combined into one, thereby effectively reducing the consumption of computing resources. At the same time, the multiplication and addition reference exponent value can also be processed, that is, the reference exponent value is subtracted from the previously recorded left shift number, and a floating-point exponent value that conforms to the preset floating-point number format can be obtained.

[0103] In addition, in floating-point operations, if the multiplication, addition, or rounding operation of the mantissa causes a carry in the mantissa, the mantissa and exponent also need to be adjusted in order to maintain the normalized representation of the floating-point number. Since the mantissas that meet the normalization requirements are all in the range of [1,2), when the mantissas of two floating-point numbers that meet [1,2) are multiplied, the result of the operation may be in the range of [2,4). At this time, the result of the operation does not meet the normalization requirements. Therefore, the mantissa of the operation result can be shifted right by one position (equivalent to division by 2) to meet the normalization requirements. In order to keep the value of the floating-point number unchanged, the exponent can be increased by 1 simultaneously; when performing floating-point addition operations, similar to multiplication operations, when the mantissas of two floating-point numbers that meet [1,2) are added, the result of the operation in the range of [2,4) does not meet the normalization requirements. It is also necessary to shift the mantissa of the operation result right by one position and increase the exponent by 1 accordingly; if the rounding operation causes a carry in one position of the mantissa, the mantissa can also be shifted right by one position and the exponent can be increased by 1 to keep the value of the floating-point number unchanged.

[0104] For example, suppose the mantissa of a floating point number is 0.00010010000 (in binary), where the number of leading zeros is 4. If this mantissa is shifted left by 4 places to eliminate the leading zeros, the result is 1.0010000 (after the left shift). However, the left shift operation will change the magnitude of the value, so the reference exponent needs to be adjusted to keep the value unchanged. Assuming the original reference exponent is 3 (indicating the number of digits after the decimal point), after the left shift of 4 places, the reference exponent should be subtracted by 4, that is, the new reference exponent becomes -1 to reflect that the decimal point has actually moved to the middle of the value.

[0105] It is understandable that in the normal operation process, the result of the multiplication and addition operation may exceed the predetermined range, which is called overflow. The overflow signal will be determined in step S104 according to the value of the reference exponent. If the reference exponent after rounding and shifting is greater than the maximum exponent corresponding to the output floating-point data type, it is judged as overflow. Overflow needs to select a legal output result according to different rounding modes. For example, if the overflow signal is pulled high and the rounding mode is RNE (Round to Nearest Ties to Even, the default rounding mode of the IEEE 754 standard), the output result is positive or negative infinity according to whether the sign bit is positive or negative. If the overflow signal is pulled high and the rounding mode is RDN (Round Down), when the sign bit is positive, the output result is the positive maximum value, and when the sign bit is negative, the output result is negative infinity. The opposite is true when the rounding mode is RUP (Round Up).

[0106] In order to avoid this situation from affecting the operation result, the overflow signal, infinity signal and non-numeric signal can be combined, and the final legal output result can be selected according to the different data types of the output result. In addition, it is also possible to decide whether to pull the corresponding exception flag (i.e., floating-point exception signal) high according to whether rounding operation is performed, whether the exponent is zero, and the existence of overflow signal and non-numeric signal. Finally, the floating-point exception signal will be output together with the operation result to ensure the correctness and integrity of the operation result.

[0107] To facilitate those skilled in the art to further understand the floating-point multiplication and addition method proposed in the embodiment of the present application, Figure 2 to Figure 5 For further explanation.

[0108] like Figure 2 As shown, Figure 2 The invention relates to a floating-point multiplication-addition operation system involved in the floating-point multiplication-addition operation method. The embodiment of the present application proposes a floating-point multiplication-addition operation system based on the fp64 format, and an operation device compatible with a variety of formats and operation requirements, which can realize multiplication-addition fusion operations such as ±(A±B*C) type. The system combines the multiplication device and the addition device in the prior art to form a unified multiplication-addition operation device. The system includes an operand selection module, a boundary case processing module, a multiplication compression module, an exponent comparison module, a front shift module, a mantissa addition module, a mantissa processing module and an output selection module, wherein the mantissa processing module includes a leading zero detection module, a rear shift module, an exponent subtraction module and a negation and rounding module.

[0109] It can be understood that in the embodiment of the present application, according to the order of operations, the floating-point multiplication and addition operation method can be divided into three parts: pre-processing, intermediate operation and post-processing. The specific implementation process is as follows: Figure 3 As shown:

[0110] Step S301, receiving the input of the previous module, obtaining the operand, when performing addition or multiplication operation on the input operand, only the valid bits of the first operand and the second operand are pulled high (activated), when performing multiplication and addition operation, the valid bits of the first operand, the second operand and the third operand are all pulled high (activated).

[0111] Step S302, pre-processing: integrating inputs of different operations and different data types into a consistent standard input signal required for double-precision floating-point multiplication and addition operations, and simultaneously performing boundary condition analysis.

[0112] That is, the operand selection module is used to normalize the inputs of different operations and different data types into 64-bit floating-point numbers; the boundary case processing module is used to judge special cases such as infinity, non-number and zero of the operands in parallel, and calculate the possible boundary results, and output the corresponding flag signals (infinity signal and non-numeric signal).

[0113] Step S303, intermediate operation: calculating the original multiplication-addition mantissa value, wherein the exponent part and the mantissa part of the floating point number can be calculated separately in parallel.

[0114] That is, the mantissa multiplication is simplified into the form of partial products by using the multiplication compression module; the multiplication-addition reference exponent value that needs to be aligned before the partial products are added is determined by using the exponent comparison module; the addition operand is shifted and aligned by using the forward shift module; and the original multiplication-addition mantissa value is calculated by using the mantissa addition module.

[0115] Step S304, post-processing: according to the different data types of the output results, the original multiplication-addition mantissa value and the multiplication-addition reference exponent value are normalized and converted into floating-point numbers that comply with the IEEE-754 standard as the output results.

[0116] That is, the leading zero detection module first performs leading zero detection on the original multiplication and addition mantissa value; the post-shift module, the exponential subtraction module, and the negation and rounding module can perform post-shift operations on the mantissa as needed, and round the mantissa to obtain a floating-point mantissa and floating-point exponent that meet the specifications. According to the overflow signal, the infinity signal, the non-numeric signal and the floating-point exponent, the output is selected to obtain the final correct floating-point result and the floating-point exception signal flag (a flag used to indicate an abnormal situation).

[0117] based on Figure 2 The floating-point multiplication and addition operation system shown can be split into modular designs and implemented in pipelines of different stages. For example, in a microcontroller MCU (Microcontroller Unit) with low frequency requirements, all modules can be implemented in the same pipeline stage.

[0118] For example, a conventional 3-stage pipeline implementation can be Figure 4 As shown, the operand selection module, boundary case processing module, multiplication compression module, exponent comparison module and forward shift module are used as the 1st-level pipeline; the mantissa addition module and leading zero detection module are used as the 2nd-level pipeline, and the remaining modules such as backward shift and rounding are used as the 3rd-level pipeline.

[0119] If the chip has a higher frequency requirement, it can also be split into a 5-stage pipeline implementation. Figure 5 The 5-stage pipeline is shown below. The operand selection module and the boundary case processing module are used as the 1st stage pipeline; the multiplication compression module, the exponent comparison module and the forward shift module are used as the 2nd stage pipeline; the mantissa addition module is used as the 3rd stage pipeline; the leading zero detection module, the backward shift module and the exponent subtraction module are used as the 4th stage pipeline; the negation and rounding module and the output selection module are used as the 5th stage pipeline.

[0120] It should be noted that the floating-point multiplication and addition operation system pipeline implementation methods of the present application are diverse, including but not limited to 2-stage pipeline and 4-stage pipeline division modes, and the pipeline implementation plans are not limited to the examples, and examples will not be given one by one here.

[0121] By adopting a pipeline design with detachable modules, the computing system is split into multiple modules with independent functions. By adding registers between the interfaces of each module, the computing device can be flexibly implemented as a pipeline structure of 1 to 5 levels to meet the specific needs of chips with different frequencies.

[0122] In summary, the floating-point multiplication and addition operation method proposed in the embodiment of the present application has the following advantages:

[0123] (1) This application is fully compatible with all requirements for floating-point instructions in the IEEE-754 standard and the RISC-V instruction set standard, covering all rounding modes, denormalized numbers, and exception flags.

[0124] (2) The present application can simultaneously support floating-point addition and subtraction and floating-point multiplication operation requests, and is compatible with operands and output data in multiple data formats. Compared with a computing device that only supports a single maximum data format (e.g., fp64) and a single multiplication and addition operation, the compatibility function of the present application does not have an adverse impact on its critical path, only adds a small amount of combinational logic, and only slightly increases the area compared to a single-function computing device.

[0125] (3) The present application can integrate and process a variety of extreme situations, significantly simplifying the judgment process of floating-point boundary conditions. Specifically, only three boundary conditions, namely non-number, infinity and overflow, need to be processed, and accurate results can be directly obtained through the main operation path for the remaining conditions. This design makes the bypass structure simpler, thereby increasing the maximum operating frequency that the computing device can achieve.

[0126] According to the floating-point multiplication and addition method proposed in the embodiment of the present application, by uniformly converting the data types of the first operand, the second operand and the third operand into preset data types, and analyzing the boundary conditions when the new first operand, the new second operand and the new third operand are operated according to the preset multiplication and addition operation sequence, a boundary result and a boundary flag signal corresponding to the boundary result can be obtained; based on the preset multiplication and addition operation sequence, the original multiplication and addition mantissa values ​​of the new first operand, the new second operand and the new third operand are calculated; based on the preset floating-point number format and the boundary flag signal, the original multiplication and addition mantissa values ​​are normalized to obtain the final floating-point result, and a corresponding floating-point exception signal is generated. Thus, the problem that the existing method needs to design different operation devices according to different operation modes, which makes the chip design verification process more complicated and the area overhead increased, is solved to improve the operation frequency.

[0127] Next, a floating-point multiplication-addition operation device according to an embodiment of the present application will be described with reference to the accompanying drawings.

[0128] Figure 6 It is a block diagram of a floating-point multiplication-addition operation device according to an embodiment of the present application.

[0129] like Figure 6 As shown, the floating-point multiplication-addition operation device 10 includes: an acquisition module 100 , an analysis module 200 , a calculation module 300 and a processing module 400 .

[0130] Wherein, the acquisition module 100 is used to acquire the first operand, the second operand and the third operand;

[0131] The analysis module 200 is used to uniformly convert the data types of the first operand, the second operand and the third operand into preset data types respectively, obtain a new first operand, a new second operand and a new third operand, and analyze the boundary conditions when the new first operand, the new second operand and the new third operand are operated according to the preset multiplication and addition operation sequence, and obtain a boundary result and a boundary flag signal corresponding to the boundary result;

[0132] The calculation module 300 is used to calculate the original multiplication-addition mantissa values ​​of the new first operand, the new second operand and the new third operand based on a preset multiplication-addition operation order;

[0133] The processing module 400 is used to perform normalization processing on the original multiplication and addition mantissa value based on a preset floating-point number format and a boundary flag signal to obtain a final floating-point result and generate a corresponding floating-point exception signal.

[0134] Furthermore, in some embodiments, the analysis module 200 is specifically configured to:

[0135] Determine in parallel whether the new first operand, the new second operand, and the new third operand are preset special cases to obtain a determination result, wherein the preset special cases include infinity, non-numeric value, and zero;

[0136] According to the judgment result and the preset multiplication and addition operation sequence, the corresponding boundary result is calculated and a boundary mark signal corresponding to the boundary result is output.

[0137] Further, in some embodiments, when analyzing the boundary conditions when the new first operand, the new second operand, and the new third operand are operated according to the preset multiplication and addition operation order, the analysis module 200 is further used to:

[0138] Selecting a new first operand, a new second operand, and a new third operand according to a preset multiplication-addition operation order;

[0139] When the current operation is an addition operation, setting the new third operand to a floating point number whose value is a first preset value;

[0140] When the current operation is a multiplication operation, the new first operand is set to a floating point number whose value is a second preset value.

[0141] Furthermore, in some embodiments, the calculation module 300 is specifically configured to:

[0142] Based on a preset multiplication-addition operation order, calculate the product of the mantissa of the new second operand and the new third operand to obtain two partial products;

[0143] Determining a multiply-add reference exponent value that needs to be aligned before performing an addition operation based on a new first operand exponent and a sum of the exponents of the two partial products;

[0144] Based on the multiply-add reference exponent value, a shift operation is performed on the new first operand and the two partial products to obtain an aligned first operand and the two aligned partial products;

[0145] The aligned first operand and the two aligned partial products are combined and added to obtain the original multiply-add mantissa value.

[0146] Furthermore, in some embodiments, the processing module 400 is specifically configured to:

[0147] Perform leading zero detection on the original multiplication and addition mantissa value and shift it left to eliminate the leading zero, obtain the processed multiplication and addition mantissa value, and record the number of left shifts to eliminate the leading zero;

[0148] According to the sign bit of the processed multiplication-addition mantissa value, the processed multiplication-addition mantissa value is inverted and rounded to obtain a floating-point mantissa that satisfies a preset floating-point number format;

[0149] Subtract the number of left shifts from the multiplication and addition reference exponent value to obtain a floating-point exponent that satisfies a preset floating-point number format;

[0150] Based on the boundary flag signal, the floating-point mantissa and the floating-point exponent, the final floating-point result is obtained, and a corresponding floating-point exception signal is generated.

[0151] It should be noted that the above explanation of the floating-point multiplication and addition method embodiment is also applicable to the floating-point multiplication and addition device of this embodiment, and will not be repeated here.

[0152] According to the floating-point multiplication and addition operation device proposed in the embodiment of the present application, by uniformly converting the data types of the first operand, the second operand and the third operand into preset data types, and analyzing the boundary conditions when the new first operand, the new second operand and the new third operand are operated according to the preset multiplication and addition operation sequence, a boundary result and a boundary flag signal corresponding to the boundary result can be obtained; based on the preset multiplication and addition operation sequence, the original multiplication and addition mantissa values ​​of the new first operand, the new second operand and the new third operand are calculated; based on the preset floating-point number format and the boundary flag signal, the original multiplication and addition mantissa values ​​are normalized to obtain the final floating-point result, and a corresponding floating-point exception signal is generated. Thus, the problem that the existing method needs to design different operation devices according to different operation modes, which makes the chip design verification process more complicated and the area overhead increased, is solved to improve the operation frequency.

[0153] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0154] A memory 701 , a processor 702 , and a computer program stored in the memory 701 and executable on the processor 702 .

[0155] When the processor 702 executes the program, the floating-point multiplication and addition operation method provided in the above embodiment is implemented.

[0156] Furthermore, the electronic device further comprises:

[0157] The communication interface 703 is used for communication between the memory 701 and the processor 702 .

[0158] The memory 701 is used to store computer programs that can be executed on the processor 702 .

[0159] The memory 701 may include a high-speed RAM (Random Access Memory) memory, and may also include a non-volatile memory, such as at least one disk memory.

[0160] If the memory 701, the processor 702 and the communication interface 703 are implemented independently, the communication interface 703, the memory 701 and the processor 702 can be connected to each other through a bus and communicate with each other. The bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 7 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0161] Optionally, in a specific implementation, if the memory 701, the processor 702 and the communication interface 703 are integrated on a chip, the memory 701, the processor 702 and the communication interface 703 can communicate with each other through an internal interface.

[0162] The processor 702 may be a CPU (Central Processing Unit), or an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present application.

[0163] An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the above floating-point multiplication and addition method is implemented.

[0164] An embodiment of the present application also provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the program implements the above floating-point multiplication and addition method.

[0165] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0166] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0167] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A floating-point multiplication and addition method, characterized in that: The following steps are involved: Get the first operand, the second operand, and the third operand; uniformly converting the data types of the first operand, the second operand and the third operand into preset data types respectively to obtain a new first operand, a new second operand and a new third operand, and analyzing boundary conditions when the new first operand, the new second operand and the new third operand are operated according to a preset multiplication and addition operation sequence to obtain a boundary result and a boundary flag signal corresponding to the boundary result; Based on the preset multiplication-addition operation order, calculating the original multiplication-addition mantissa values ​​of the new first operand, the new second operand, and the new third operand; Based on the preset floating-point number format and the boundary flag signal, the original multiplication-addition mantissa value is normalized to obtain a final floating-point result, and a corresponding floating-point exception signal is generated.

2. The method according to claim 1, characterized in that The step of analyzing the boundary conditions when the new first operand, the new second operand, and the new third operand are operated according to a preset multiplication-addition operation sequence to obtain a boundary result and a boundary flag signal corresponding to the boundary result includes: Determine in parallel whether the new first operand, the new second operand, and the new third operand are preset special cases to obtain a determination result, wherein the preset special cases include infinity, non-numeric value, and zero; According to the judgment result and the preset multiplication and addition operation sequence, a corresponding boundary result is calculated, and a boundary mark signal corresponding to the boundary result is output.

3. The method according to claim 2, characterized in that When analyzing the boundary conditions when the new first operand, the new second operand, and the new third operand are operated according to the preset multiplication and addition operation sequence, the method further includes: Selecting the new first operand, the new second operand and the new third operand according to a preset multiplication-addition operation order; When the current operation is an addition operation, setting the new third operand to a floating point number having a value of a first preset value; When the current operation is a multiplication operation, the new first operand is set to a floating point number whose value is a second preset value.

4. The method according to claim 1, characterized in that: The calculating, based on the preset multiplication-addition operation order, the original multiplication-addition mantissa values ​​of the new first operand, the new second operand, and the new third operand comprises: Based on the preset multiplication and addition operation order, calculate the product of the mantissa of the new second operand and the new third operand to obtain two partial products; Determining, based on the new first operand exponent and the sum of the exponents of the two partial products, a multiplication-addition reference exponent value that needs to be aligned before performing an addition operation; Based on the multiplication-addition reference exponent value, performing a shift operation on the new first operand and the two partial products to obtain an aligned first operand and two aligned partial products; The aligned first operand and the two aligned partial products are combined and added to obtain the original multiplication-addition mantissa value.

5. The method according to claim 1, characterized in that The method of normalizing the original multiplication-addition mantissa value based on the preset floating-point number format and the boundary flag signal to obtain a final floating-point result and generating a corresponding floating-point exception signal includes: Performing a leading zero detection on the original multiplication-addition mantissa value and shifting it left to eliminate the leading zero, obtaining a processed multiplication-addition mantissa value, and recording the number of left shifts to eliminate the leading zeros; According to the sign bit of the processed multiplication-addition mantissa value, a negation operation and a rounding operation are performed on the processed multiplication-addition mantissa value to obtain a floating-point mantissa that satisfies the preset floating-point number format; Subtract the number of left shifts from the multiplication-addition reference exponent value to obtain a floating-point exponent that satisfies the preset floating-point number format; Based on the boundary flag signal, the floating-point mantissa and the floating-point exponent, the final floating-point result is obtained, and the corresponding floating-point exception signal is generated.

6. A floating-point multiplication and addition device, characterized in that: include: An acquisition module, used for acquiring a first operand, a second operand and a third operand; an analysis module, configured to uniformly convert the data types of the first operand, the second operand, and the third operand into preset data types respectively, obtain a new first operand, a new second operand, and a new third operand, and analyze boundary conditions when the new first operand, the new second operand, and the new third operand are operated in a preset multiplication-addition operation sequence, to obtain a boundary result and a boundary flag signal corresponding to the boundary result; A calculation module, configured to calculate original multiplication-addition mantissa values ​​of the new first operand, the new second operand, and the new third operand based on the preset multiplication-addition operation order; The processing module is used to perform normalization processing on the original multiplication and addition mantissa value based on a preset floating-point number format and the boundary mark signal to obtain a final floating-point result and generate a corresponding floating-point exception signal.

7. The device according to claim 6, characterized in that The analysis module is specifically used for: Determine in parallel whether the new first operand, the new second operand, and the new third operand are preset special cases to obtain a determination result, wherein the preset special cases include infinity, non-numeric value, and zero; According to the judgment result and the preset multiplication and addition operation sequence, a corresponding boundary result is calculated, and a boundary mark signal corresponding to the boundary result is output.

8. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the floating-point multiplication and addition method according to any one of claims 1 to 5.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the floating-point multiplication and addition method as described in any one of claims 1 to 5.

10. A computer program product, characterized in that It comprises a computer program, which, when executed by a processor, is used to implement the floating-point multiplication and addition method according to any one of claims 1 to 5.

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