An invalid instruction generation method and device, electronic equipment and storage medium

Abstract

Embodiments of the present application provide a kind of invalid instruction generation method, device, electronic equipment and storage medium, involve computer technical field, in the method, first instruction coding format is selected from the instruction coding format set corresponding to the preset instruction set architecture;First random code with the fixed bit section total length of first instruction coding format is equal in length;In the case where the first random code is inconsistent with each preset fixed code corresponding to the first instruction coding format, the invalid instruction corresponding to the preset instruction set architecture is generated based on the first random code.The invalid instruction corresponding to the preset instruction architecture can be directly generated in a random manner, which does not comply with the instruction coding format, which helps to improve the efficiency of generating the invalid instruction of the preset instruction set architecture.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an invalid instruction generation method, apparatus, electronic device and storage medium. Background Technology

[0002] Currently, with the continuous development of computer technology, the design of the Central Processing Unit (CPU) is becoming increasingly complex. Typically, an instruction generator is used to randomly generate some instructions to test the CPU. These instructions include valid instructions that conform to the CPU's instruction set architecture, as well as invalid instructions that do not conform to the CPU's instruction set architecture definition.

[0003] In related technologies, a common approach is to first generate valid instructions that conform to a certain instruction type based on the instruction set architecture's definition requirements, and then modify these valid instructions to generate invalid instructions that differ from the valid instructions. However, generating invalid instructions in this way is inefficient. Summary of the Invention

[0004] This invention provides an invalid instruction generation method, apparatus, electronic device, and storage medium, which can improve the efficiency of generating invalid instructions.

[0005] To address the above problems, this invention discloses an invalid instruction generation method, the method comprising:

[0006] Select the first instruction encoding format from the set of instruction encoding formats corresponding to the preset instruction set architecture;

[0007] Generate a first random code whose encoding length is equal to the total length of the fixed bit segments of the first instruction encoding format;

[0008] When the first random encoding is inconsistent with each of the preset fixed encodings corresponding to the first instruction encoding format, an invalid instruction corresponding to the preset instruction set architecture is generated based on the first random encoding; wherein, the invalid instruction is used to test the central processing unit.

[0009] Optionally, generating invalid instructions corresponding to the preset instruction set architecture based on the first random encoding includes:

[0010] Based on the first random encoding, generate a pending instruction corresponding to the first instruction encoding format;

[0011] If the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture, the pending instruction is determined as an invalid instruction corresponding to the preset instruction set architecture; wherein, the other instruction encoding formats refer to instruction encoding formats other than the first instruction encoding format in the preset instruction set architecture.

[0012] Optionally, the method further includes:

[0013] Based on the fixed bit range information corresponding to other instruction encoding formats in the instruction encoding format set, extract the first fixed bit segment codes corresponding to the other instruction encoding formats from the pending instruction;

[0014] Based on the bit segment order corresponding to each first fixed bit segment code, the first fixed bit segment codes are concatenated to obtain the code to be compared;

[0015] If the code to be compared is inconsistent with each of the preset fixed codes corresponding to the other instruction encoding formats, it is determined that the instruction to be compared does not match the other instruction encoding formats corresponding to the preset instruction set architecture.

[0016] Optionally, generating the pending instruction corresponding to the first instruction encoding format based on the first random encoding includes:

[0017] Generate a second random code corresponding to the variable bit segment of the first instruction encoding format;

[0018] By concatenating the first random code and the second random code, a pending instruction corresponding to the first instruction encoding format is obtained.

[0019] Optionally, the step of concatenating the first random code and the second random code to obtain the pending instruction corresponding to the first instruction encoding format includes:

[0020] Based on the fixed bit range information of the first instruction encoding format, the first random code is segmented to obtain the second fixed bit segment code corresponding to each fixed bit segment of the first instruction encoding format.

[0021] Based on the bit order corresponding to the second random code and each second fixed bit segment code, the second random code and each second fixed bit segment code are concatenated to obtain the pending instruction corresponding to the first instruction encoding format.

[0022] Optionally, after generating invalid instructions corresponding to the preset instruction set architecture based on the first random encoding, the method further includes:

[0023] The first random code corresponding to the invalid instruction is determined as a preset fixed code corresponding to the first instruction encoding format;

[0024] The step of selecting the first instruction encoding format from the set of instruction encoding formats corresponding to the preset instruction set architecture is re-executed to continue generating the next invalid instruction, thereby obtaining an invalid instruction sequence containing multiple invalid instructions.

[0025] Optionally, the method further includes:

[0026] Obtain the fixed bit range information corresponding to the first instruction encoding format;

[0027] Based on the fixed segment range information, the fixed segment length corresponding to each fixed segment of the first instruction encoding format is determined.

[0028] The total length of the fixed segments is determined based on the length of each fixed segment.

[0029] On the other hand, embodiments of the present invention disclose an invalid instruction generation apparatus, the apparatus comprising:

[0030] The selection module is used to select the first instruction encoding format from the set of instruction encoding formats corresponding to the preset instruction set architecture;

[0031] The generation module is used to generate a first random code whose encoding length is equal to the total length of the fixed bit segments of the first instruction encoding format;

[0032] The instruction module is used to generate an invalid instruction corresponding to the preset instruction set architecture based on the first random encoding when the first random encoding is inconsistent with each preset fixed encoding corresponding to the first instruction encoding format; wherein the invalid instruction is used to test the central processing unit.

[0033] Optionally, the instruction module includes:

[0034] The pending instruction submodule is used to generate a pending instruction corresponding to the first instruction encoding format based on the first random encoding.

[0035] The invalid instruction submodule is used to determine the pending instruction as an invalid instruction corresponding to the preset instruction set architecture when the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture; wherein, the other instruction encoding formats refer to instruction encoding formats other than the first instruction encoding format in the preset instruction set architecture.

[0036] Optionally, the device further includes:

[0037] The first fixed bit segment encoding module is used to extract each first fixed bit segment encoding corresponding to the other instruction encoding formats from the pending instruction based on the fixed bit segment range information corresponding to the other instruction encoding formats in the instruction encoding format set.

[0038] The comparison encoding module is used to concatenate the first fixed bit segment codes based on the bit segment order corresponding to each first fixed bit segment code to obtain the comparison encoding;

[0039] The determination module is used to determine that the pending instruction does not match the other instruction encoding formats corresponding to the preset instruction set architecture when the code to be compared is inconsistent with each of the preset fixed codes corresponding to the other instruction encoding formats.

[0040] Optionally, the pending instruction submodule includes:

[0041] A random encoding unit is used to generate a second random code corresponding to the variable bit segment of the first instruction encoding format;

[0042] The pending instruction generation unit is used to concatenate the first random code and the second random code to obtain the pending instruction corresponding to the first instruction encoding format.

[0043] Optionally, the pending instruction generation unit includes:

[0044] The segmentation subunit is used to segment the first random code based on the fixed bit range information of the first instruction encoding format to obtain the second fixed bit segment code corresponding to each fixed bit segment of the first instruction encoding format.

[0045] The pending instruction splicing subunit is used to splice the second random code and each second fixed bit segment code according to the bit segment order corresponding to the second random code and each second fixed bit segment code to obtain the pending instruction corresponding to the first instruction encoding format.

[0046] Optionally, the device further includes:

[0047] A preset fixed encoding module is used to determine the first random encoding corresponding to the invalid instruction as a preset fixed encoding corresponding to the first instruction encoding format;

[0048] The invalid instruction sequence module is used to re-execute the step of selecting the first instruction encoding format from the instruction encoding format set corresponding to the preset instruction set architecture, and continue to generate the next invalid instruction, thereby obtaining an invalid instruction sequence containing multiple invalid instructions.

[0049] Optionally, the device further includes:

[0050] The fixed bit range information module is used to obtain the fixed bit range information corresponding to the first instruction encoding format;

[0051] The fixed segment length module is used to determine the fixed segment length corresponding to each fixed segment of the first instruction encoding format based on the fixed segment range information.

[0052] The fixed segment total length module is used to determine the total length of the fixed segment based on the fixed segment lengths corresponding to each fixed segment.

[0053] In another aspect, embodiments of the present invention disclose an electronic device, including: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, the executable instruction causing the processor to execute the aforementioned method.

[0054] This invention also discloses a computer-readable storage medium storing instructions that, when executed by one or more processors, cause the processors to perform the methods described above.

[0055] The embodiments of the present invention have the following advantages: In the invalid instruction generation method provided in the embodiments of the present invention, a first instruction encoding format is selected from the instruction encoding format set corresponding to a preset instruction set architecture; a first random code with an encoding length equal to the total length of the fixed segments of the first instruction encoding format is generated; and when the first random code is inconsistent with each preset fixed code corresponding to the first instruction encoding format, an invalid instruction corresponding to the preset instruction set architecture is generated based on the first random code. This method can directly generate invalid instructions that do not conform to the instruction encoding format corresponding to the preset instruction set architecture by random generation, which helps to improve the efficiency of generating invalid instructions for the preset instruction set architecture. Attached Figure Description

[0056] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a flowchart of the steps of an invalid instruction generation method provided in an embodiment of the present invention;

[0058] Figure 2 This is a schematic diagram of an invalid instruction generation process provided by an embodiment of the present invention;

[0059] Figure 3 This is a block diagram of an invalid instruction generation device provided in an embodiment of the present invention;

[0060] Figure 4This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0061] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0062] Reference Figure 1 The flowchart illustrates the steps of an invalid instruction generation method provided by an embodiment of the present invention, as follows: Figure 1 As shown, the method may specifically include the following steps:

[0063] Step 101: Select the first instruction encoding format from the set of instruction encoding formats corresponding to the preset instruction set architecture.

[0064] During the design and verification of a central processing unit (CPU), test instructions are typically generated for testing. These instructions are then used to perform actual or simulated tests on the CPU core under test. The test environment can include both hardware and simulation environments; that is, the CPU core under test can be a physical core or a simulated core. The test instructions mentioned above can refer to instructions generated according to certain rules, or they can refer to randomly generated instructions.

[0065] When testing a CPU core, it is necessary to test not only whether the CPU core can respond correctly to valid instructions with clear definitions, but also whether the CPU core's response to invalid instructions can proceed smoothly according to design requirements. That is, it is necessary to test whether the CPU core's response to receiving invalid instructions meets design requirements. These responses may include, but are not limited to, exception jumps, exception triggering situations, the accuracy of exception triggering types, interrupt logic, etc., to evaluate the CPU core's security, robustness, stability, and other characteristics. An invalid instruction can refer to an instruction that does not conform to the instruction encoding specifications of the instruction set architecture of the CPU core under test. Invalid instructions can also be called undefined instructions, illegal instructions, violation instructions, erroneous instructions, exception instructions, etc., and this embodiment of the invention does not impose specific limitations.

[0066] In this embodiment of the invention, to generate invalid instructions, a first instruction encoding format can be selected from the instruction encoding format set corresponding to a preset instruction set architecture. Here, the preset instruction set architecture represents the instruction set architecture of the CPU core under test, such as RISC-V, ARM, x86, etc.; the instruction encoding format set can include all instruction encoding formats corresponding to the preset instruction set architecture. The instruction encoding format is used to define the structure of binary instructions that the processor can recognize and execute, that is, to specify the binary representation of valid instructions. Specifically, the instruction encoding format can define which bit fields are included in the binary encoding of the instruction in the corresponding instruction set architecture, and the meaning of each bit field.

[0067] For example, an instruction encoding format A can be shown in Table 1 below:

[0068] Table 1

[0069]

[0070] The instruction encoding format A is 12 bits long and contains 4 bit segments. The binary bits in the 0th to 3rd positions are bit segment 1, the binary bits in the 4th and 5th positions are bit segment 2, and so on.

[0071] In this embodiment of the invention, an instruction encoding format set containing all instruction encoding formats corresponding to a preset instruction set architecture can be pre-established. When it is necessary to generate an invalid instruction for the preset instruction set architecture, an instruction encoding format is selected from the corresponding instruction encoding format set as the first instruction encoding format. The above selection method may include, but is not limited to, random selection, sequential selection, selection according to rules, etc., and this embodiment of the invention does not impose specific limitations.

[0072] Step 102: Generate a first random code whose encoding length is equal to the total length of the fixed bit segments of the first instruction encoding format.

[0073] In this embodiment of the invention, after selecting the first instruction encoding format, the total length of the fixed bit segments corresponding to the first instruction encoding format can be determined. The total length of the fixed bit segments represents the sum of the lengths of all fixed bit segments defined in the corresponding first instruction encoding format. A fixed bit segment represents a bit segment with predefined specific content in the binary encoding of the instruction. Fixed bit segments may include, but are not limited to, bit segments used to define the instruction opcode, bit segments used to define the instruction function, etc. That is, the specific content of the fixed bit segments can determine the instruction type, and each instruction type corresponds to a fixed bit segment with explicit content. For example, if an instruction encoding format includes fixed bit segment 1 and fixed bit segment 2, and the instruction type ADD has a preset fixed bit segment 1 content of 0010 and a fixed bit segment 2 content of 0001, then if the binary encoding of an instruction C has fixed bit segment 1 as 0010 and fixed bit segment 2 as 0001, then the instruction C is identified as an ADD instruction.

[0074] In one implementation, each instruction encoding format in the instruction encoding format set may correspond to a fixed total length of bit segments. Each instruction encoding format may be recorded in the instruction encoding format set using a format identifier. Therefore, after selecting a first instruction encoding format from the instruction encoding format set, the corresponding fixed total length of bit segments can be queried using the format identifier to obtain the fixed total length of bit segments corresponding to the first instruction encoding format. Then, a random code with a length equal to the fixed total length of bit segments is generated as the first random code. The generated random code is in binary form, meaning each bit of the random code is either 0 or 1.

[0075] In another implementation, the instruction encoding format in the instruction encoding format set may include specific format information. After selecting the first instruction encoding format from the instruction encoding format set, the format information of the first instruction encoding format can be analyzed to determine the length of each fixed bit segment and sum them to obtain the total length of the fixed bit segments. Then, a random code with an encoding length equal to the total length of the fixed bit segments is generated as the first random code.

[0076] In this embodiment of the invention, the first random code described above can be generated using a random number generator. In one implementation, a binary number and the number of bits in the first random number (the total length of a fixed segment) can be input into the random number generator, causing the generator to output a first random code with a length equal to the total length of the fixed segment all at once. In another implementation, a binary number and the number of bits in the second random number (a factor of the total length of the fixed segment) can be input into the random number generator, causing it to output multiple random numbers with a length equal to that factor. These random numbers are then concatenated to obtain the first random code with a length equal to the total length of the fixed segment. This embodiment of the invention does not specifically limit the method for generating the first random code.

[0077] Step 103: When the first random code is inconsistent with each of the preset fixed codes corresponding to the first instruction encoding format, an invalid instruction corresponding to the preset instruction set architecture is generated based on the first random code; wherein, the invalid instruction is used to test the central processing unit.

[0078] In this embodiment of the invention, after obtaining the first random code, it can be compared with all preset fixed codes corresponding to the first instruction encoding format. If the first random code is different from all preset fixed codes corresponding to the first instruction encoding format, it indicates that the first random code does not match any instruction type defined under the first instruction encoding format, and an invalid instruction corresponding to a preset instruction set architecture can be generated based on the first random code. Here, a preset fixed code corresponding to the instruction encoding format represents the code obtained by concatenating the contents of all fixed bit segments corresponding to an instruction type defined under the instruction encoding format.

[0079] For example, if bit segment 1 and bit segment 3 are fixed bits in the instruction encoding format shown in Table 1 above, and this instruction encoding format defines two instruction types: instruction type C1 and instruction type C2, where instruction type C1 defines bit segment 1 as 0000 and bit segment 3 as 101; and instruction type C2 defines bit segment 1 as 1010 and bit segment 3 as 010. Then, the preset fixed code corresponding to instruction type C1 defined in this instruction encoding format can be 1010000 (obtained by concatenating the bit segment 1 and bit segment 3 contents corresponding to instruction C1), and the preset fixed code corresponding to instruction type C2 can be 1010010. The method of concatenating the content of each segment can include either high-order segment first and low-order segment last, or low-order segment first and high-order segment last. For example, if the high-order segment first and low-order segment last concatenation method is used, the preset fixed code corresponding to instruction type C2 is 1010010; if the low-order segment first and high-order segment last concatenation method is used, the preset fixed code corresponding to instruction type C1 is 0010101. In this embodiment of the invention, all segment concatenation processes can adopt the high-order segment first and low-order segment last method. The preset fixed code of the instruction encoding format obtained by concatenation in this way can be represented by the following set CAT_SET1:

[0080] CAT_SET1 = {1010000,1010010}.

[0081] Specifically, if the first random code is inconsistent with all preset fixed codes corresponding to the corresponding first instruction encoding format, the first random code can be expanded according to the instruction encoding format corresponding to the first random code, expanding it to the instruction bit length defined by the corresponding instruction encoding format to obtain an invalid instruction, while maintaining the position of the code corresponding to each fixed bit segment in the first random code in the invalid instruction in accordance with the definition of the instruction encoding format. That is, the first random code is padded to obtain the instruction binary code of the corresponding invalid instruction.

[0082] In one implementation, the binary bits filled in the invalid instruction can be preset bits (e.g., 1 bit or 0 bits), that is, the binary bits filled in the invalid instruction can be all 1 bits or all 0 bits. In another implementation, the binary bits filled in the invalid instruction can also be random binary bits, and the embodiments of the present invention do not impose specific limitations.

[0083] Using the example above, if the first random code is "1110110", the corresponding first instruction encoding format is shown in Table 1. We can first compare the first random code "1110110" with each element of the set CAT_SET1. Since the first random code "1110110" does not match any of the elements, we can further generate an invalid instruction based on the first random code "1110110". Since the high-order bit "111" in the first random code corresponds to bit segment 3, and the low-order bit "0110" corresponds to bit segment 1, we can insert two preset bits (0 bits) corresponding to bit segment 2 between "111" and "0110", and insert three preset bits (0 bits) corresponding to bit segment 4 to the left of "111", resulting in the corresponding invalid instruction "000111000110".

[0084] In this embodiment of the invention, after identifying an invalid instruction, step 101 can be re-executed to select a first instruction encoding format from the instruction encoding format set corresponding to the preset instruction set architecture, and continue generating invalid instructions corresponding to that first instruction encoding format. This allows for the generation of a large number of invalid instructions for testing the corresponding CPU core. Furthermore, multiple invalid instructions can be combined into an invalid instruction stream, thereby enabling a large-scale testing of the CPU core with invalid instructions at once, improving testing efficiency.

[0085] In summary, the invalid instruction generation method provided by this invention involves selecting a first instruction encoding format from a set of instruction encoding formats corresponding to a preset instruction set architecture; generating a first random code whose encoding length is equal to the total length of fixed segments of the first instruction encoding format; and generating an invalid instruction corresponding to the preset instruction set architecture based on the first random code when none of the first random code corresponds to any of the preset fixed codes corresponding to the first instruction encoding format. This random generation method can directly generate invalid instructions that do not conform to the instruction encoding format corresponding to the preset instruction set architecture, thus improving the efficiency of generating invalid instructions for the preset instruction set architecture.

[0086] Optionally, in some embodiments, the step of generating a first random code with a length equal to the total length of the fixed bit segments of the first instruction encoding format can be implemented through the following process:

[0087] In this embodiment of the invention, when generating the first random code, the random constraints for generating the first random code can be determined by using a set of preset fixed codes corresponding to the first instruction encoding format. Specifically, the random constraints may include: the generated random code does not belong to any code in the preset fixed code set. Therefore, through these random constraints, a first random code that is inconsistent with all preset fixed codes corresponding to the first instruction encoding format can be directly generated. This eliminates the need to actually match the first random code with all preset fixed codes corresponding to the first instruction encoding format. The first random code obtained under this generation method can be directly determined to be inconsistent with all preset fixed codes corresponding to the first instruction encoding format, and the step of generating invalid instructions corresponding to the preset instruction set architecture based on the first random code can be directly executed, which helps improve the efficiency of generating invalid instructions. It should be noted that the above random constraints may also include base constraints, length constraints, value range constraints, etc., which are not specifically limited in this embodiment of the invention.

[0088] Optionally, in some embodiments, the step of generating invalid instructions corresponding to the preset instruction set architecture based on the first random encoding may specifically include:

[0089] Step 1031: Generate a pending instruction corresponding to the first instruction encoding format based on the first random encoding.

[0090] In this embodiment of the invention, since the instruction encoding format set corresponding to the preset instruction set architecture can contain multiple instruction encoding formats, when the instruction encoding format set contains multiple instruction encoding formats, the ultimately generated invalid instruction must be invalid for all instruction encoding formats in the instruction encoding format set in order to be determined as an invalid instruction corresponding to the preset instruction set architecture. Therefore, in this embodiment of the invention, when the instruction encoding format set contains multiple instruction encoding formats, a pending instruction corresponding to the preset instruction set architecture is first generated based on the first random encoding. Here, the pending instruction represents an instruction whose fixed bit field does not match the preset fixed encoding defined by the first instruction encoding format.

[0091] It should be noted that the method of generating the above-mentioned pending instructions can be the same as the method of generating invalid instructions in step 103 above, and will not be described again in this embodiment of the invention.

[0092] Optionally, in some embodiments, the step of generating the pending instruction corresponding to the first instruction encoding format based on the first random encoding may specifically include:

[0093] Step A1: Generate a second random code corresponding to the variable bit segment of the first instruction encoding format.

[0094] In this embodiment of the invention, the instruction encoding format may also define variable bit fields. A variable bit field is a bit field composed of bits used to record variable information such as logical register numbers and immediate values ​​in the instruction. Generally speaking, bit fields other than fixed bit fields are variable bit fields.

[0095] In this embodiment of the invention, since the instruction encoding format defines not only fixed bit fields but also variable bit fields, in order to generate a pending instruction composed of fixed bit fields and variable bit fields, a second random code corresponding to the variable bit fields can also be generated for the corresponding first instruction encoding format.

[0096] Specifically, the first instruction encoding format can define the length and position of each variable bit segment. Based on the length of the variable bit segments, a second random code corresponding to each variable bit segment can be generated. For example, in the instruction encoding format shown in Table 1, if bit segments 2 and 4 are variable bit segments, a 2-bit second random code 1 (e.g., 10) and a 3-bit second random code 2 (e.g., 001) can be generated for bit segments 2 and 4 respectively.

[0097] Step A2: Concatenate the first random code and the second random code to obtain the pending instruction corresponding to the first instruction encoding format.

[0098] In this embodiment of the invention, the first random code and the second random code can be concatenated to obtain a complete pending instruction corresponding to the first instruction encoding format. During the concatenation process, the codes corresponding to each fixed bit segment in the first random code and the codes corresponding to each variable bit segment in the second random code can be combined according to the bit segment order defined in the corresponding first instruction encoding format to obtain a pending instruction that satisfies the first instruction encoding format.

[0099] By generating a second random code corresponding to the variable bit field of the first instruction encoding format, and concatenating the first and second random codes, a pending instruction corresponding to the first instruction encoding format is obtained. This allows the encoding of both the fixed and variable bit fields in the pending instruction to be obtained based on random encoding, thereby generating a pending instruction with high randomness under the preset instruction set architecture. This improves the unpredictability of the pending instruction and helps to enhance the effectiveness of testing the CPU core based on invalid instructions determined from the pending instruction.

[0100] Optionally, the step of concatenating the first random code and the second random code to obtain the pending instruction corresponding to the first instruction encoding format may specifically include:

[0101] Step A21: Based on the fixed segment range information of the first instruction encoding format, segment the first random code to obtain the second fixed segment code corresponding to each fixed segment of the first instruction encoding format.

[0102] In this embodiment of the invention, the instruction encoding format may include fixed bit range information, which is used to represent the range of binary bits of each fixed bit segment in the corresponding instruction binary encoding. For example, taking the instruction encoding format described in Table 1 above, its fixed bit range information may include: bits 0 to 3 belonging to a fixed bit segment, and bits 6 to 8 belonging to a fixed bit segment.

[0103] In this embodiment of the invention, the length of each fixed bit segment can be determined based on the fixed bit segment range information of the first instruction encoding format. Then, the first random code is segmented according to the bit segment length of each fixed bit segment to obtain the second fixed bit segment code corresponding to each fixed bit segment of the first instruction encoding format.

[0104] For example, if the first random code is 1110110, the corresponding first instruction encoding format is shown in Table 1. Its fixed bit range information may include: bits 0 to 3 belong to fixed bit ranges, and bits 6 to 8 belong to fixed bit ranges. Based on the fixed bit range information, the bit lengths of each fixed bit range can be determined as follows: bit range 1 has a bit length of 4, and bit range 3 has a bit length of 3. Based on the above bit lengths, the first random code 1110110 is divided to obtain the second fixed bit range codes 111 and 0110.

[0105] Step A22: Based on the bit order corresponding to the second random code and each second fixed bit segment code, concatenate the second random code and each second fixed bit segment code to obtain the pending instruction corresponding to the first instruction encoding format.

[0106] In this embodiment of the invention, the second random code and each second fixed bit segment code can be concatenated based on the bit segment order corresponding to the second random code and each second fixed bit segment code to obtain the pending instruction corresponding to the first instruction encoding format.

[0107] Specifically, since each second random code corresponds to a corresponding variable bit segment, and each second fixed bit segment code corresponds to a corresponding fixed bit segment, the bit order of each variable and fixed bit segment is defined in the corresponding first instruction encoding format. Therefore, the corresponding second random code and the second fixed bit segment code can be directly concatenated according to the bit order defined in the first instruction encoding format to obtain the instruction to be determined. It should be noted that the above bit order can be determined by calculation based on the position / range information of each bit segment, or it can be directly predefined. This embodiment of the invention does not impose specific limitations.

[0108] In this embodiment of the invention, based on the fixed segment range information of the first instruction encoding format, the first random code can be segmented to obtain the second fixed segment code corresponding to each fixed segment of the first instruction encoding format; based on the segment order corresponding to the second random code and each second fixed segment code, the second random code and each second fixed segment code are concatenated to obtain the pending instruction corresponding to the first instruction encoding format. This method can determine the codes of each fixed segment and variable segment, and accurately concatenate these codes based on the defined segment order to obtain the corresponding pending instruction, which helps improve the stability and accuracy of the pending instruction generation process.

[0109] Step 1032: If the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture, the pending instruction is determined as an invalid instruction corresponding to the preset instruction set architecture; wherein, the other instruction encoding formats refer to instruction encoding formats other than the first instruction encoding format in the preset instruction set architecture.

[0110] In this embodiment of the invention, it can be determined whether the pending instruction matches other instruction encoding formats in the preset instruction set architecture. If the pending instruction does not match any of the other instruction encoding formats in the preset instruction set architecture, the pending instruction can be determined as an invalid instruction corresponding to the preset instruction set architecture. If the pending instruction matches at least one other instruction encoding format in the preset instruction set architecture, it means that the pending instruction is legal for at least one instruction encoding format and cannot be regarded as an invalid instruction of the preset instruction set architecture. Here, "other instruction encoding formats" can refer to all instruction encoding formats corresponding to the preset instruction set architecture, excluding the first instruction encoding format.

[0111] In this embodiment of the invention, if a pending instruction matches at least one other instruction encoding format in the preset instruction set architecture, the pending instruction can be discarded, and a first random code with an encoding length equal to the total length of the fixed bit segments of the first instruction encoding format can be regenerated, i.e., a new first random code is generated. Then, based on the new first random code, the above step 1031 is re-executed to generate a new pending instruction for further judgment, until a pending instruction is obtained that does not match any other instruction encoding format corresponding to the preset instruction set architecture. The pending instruction is then regarded as an invalid instruction of the preset instruction set architecture.

[0112] The system generates pending instructions corresponding to a preset instruction set architecture based on a first random encoding. If the pending instructions do not match the encoding formats of other instructions corresponding to the preset instruction set architecture, the pending instructions are treated as invalid instructions corresponding to the preset instruction set architecture. This ensures that all instruction encoding formats for the generated invalid instructions are undefined for the preset instruction set architecture, thus improving the accuracy of the generated invalid instructions.

[0113] Optionally, in some embodiments, the following steps can be used to determine whether the encoding format of the pending instruction matches that of other instructions:

[0114] Step B1: Based on the fixed segment range information corresponding to other instruction encoding formats in the instruction encoding format set, extract the first fixed segment codes corresponding to the other instruction encoding formats from the pending instruction.

[0115] In this embodiment of the invention, for each other instruction encoding format in the instruction encoding format set, the fixed bit range information corresponding to that other instruction encoding format can be obtained. Based on the fixed bit range information, the first fixed bit segment code corresponding to each fixed bit segment of the other instruction encoding format can be extracted from the pending instruction. The first fixed bit segment code represents the fixed bit segment code in the pending instruction that corresponds to the fixed bit segment defined by the other instruction encoding format.

[0116] For example, if the preset instruction set architecture contains two instruction encoding formats, and the first instruction encoding format is selected in a certain generation process as shown in Table 1 above, then the other instruction encoding format can be used as another instruction encoding format, which can be shown in Table 2 below:

[0117] Table 2

[0118]

[0119] In the other instruction encoding formats shown in Table 2, bit segment 1, bit segment 3, and bit segment 5 are fixed bit segments, while bit segment 2 and bit segment 4 are variable bit segments. Therefore, the corresponding fixed bit segment range information can be: bit 0 to bit 2 (bit segment 1), bit 5 to bit 7 (bit segment 3), and bit 10 to bit 11 (bit segment 5).

[0120] If the generated pending instruction is “000111000110”, then based on the fixed bit range information of the other instruction encoding formats mentioned above, bits 0 to 2, bits 5 to 7, and bits 10 to 11 of the pending instruction can be extracted to obtain the first fixed bit range codes “110”, “110” and “00” respectively.

[0121] Step B2: Based on the segment order corresponding to each first fixed segment code, concatenate each first fixed segment code to obtain the code to be compared.

[0122] In this embodiment of the invention, to improve comparison efficiency, each first fixed bit segment code can be concatenated according to the corresponding bit segment order to obtain the code to be compared. The bit segment order corresponding to each first fixed bit segment code can be determined based on the fixed bit segment range information of each first fixed bit segment code.

[0123] Using the example above, if the first fixed segment code includes "110", "110" and "00", the code to be compared can be obtained by concatenating the segments according to the order of the segments corresponding to each first fixed segment code.

[0124] Step B3: If the code to be compared is inconsistent with each of the preset fixed codes corresponding to the other instruction encoding formats, it is determined that the instruction to be compared does not match the other instruction encoding formats corresponding to the preset instruction set architecture.

[0125] In this embodiment of the invention, for each other instruction encoding format, all preset fixed codes corresponding to the other instruction encoding format can be obtained, and the code to be compared corresponding to the other instruction encoding format can be compared one by one with each of its corresponding preset fixed codes. If the code to be compared is inconsistent with all its preset fixed codes, it can be determined that the pending instruction corresponding to the code to be compared does not match the other instruction encoding format. The preset fixed codes corresponding to other instruction encoding formats can be composed of the contents of all fixed bit fields corresponding to the instruction type defined by one other instruction encoding format.

[0126] For example, if an other instruction encoding format is as shown in Table 2 above, assuming that this other instruction encoding format defines three instruction types: instruction type C3, instruction type C4, and instruction type C5. Since this other instruction encoding format has three fixed bit fields: bit field 1, bit field 3, and bit field 5, assuming that the bit field 5 encoding (content) of instruction type C3 is 00, the bit field 3 encoding is 101, and the bit field 1 encoding is 100; the bit field 5 encoding of instruction type C4 is 11, the bit field 3 encoding is 001, and the bit field 1 encoding is 010; and the bit field 5 encoding of instruction type C5 is 10, the bit field 3 encoding is 000, and the bit field 1 encoding is 111. Then the preset fixed encoding corresponding to this other instruction encoding format can include "00101100" composed of the contents of each fixed bit field of instruction type C3, "11001010" composed of the contents of each fixed bit field of instruction type C4, and "10000111" composed of the contents of each fixed bit field of instruction type C5. In this embodiment of the invention, all segment splicing processes can adopt the method of high-order segments first and low-order segments last. The preset fixed code of the other instruction encoding format obtained by splicing in this way can be represented by the following set CAT_SET2:

[0127] CAT_SET2 = {00101100,11001010,10000111}.

[0128] When the code to be compared is "00110110", it can be compared with each element of the aforementioned set CAT_SET2. Since "00110110" does not match any element, it can be determined that the code to be compared, "00110110", does not match any of the preset fixed codes corresponding to this other instruction encoding format. Since it is determined that the code to be compared, "00110110", does not match any of the preset fixed codes corresponding to other instruction encoding formats, it can be determined that the pending instruction corresponding to this code does not match any of the other instruction encoding formats corresponding to the preset instruction set architecture.

[0129] In this embodiment of the invention, based on the fixed bit range information corresponding to other instruction encoding formats in the instruction encoding format set, the first fixed bit segment code corresponding to other instruction encoding formats can be extracted from the pending instruction. Based on the bit segment order corresponding to each first fixed bit segment code, the first fixed bit segment codes are concatenated to obtain the code to be compared. If the code to be compared is inconsistent with all preset fixed codes corresponding to other instruction encoding formats, it is determined that the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture. This method can accurately determine the matching relationship between the pending instruction and all instruction types defined under other instruction encoding formats, thereby helping to improve the accuracy of determining whether the pending instruction matches other instruction encoding formats.

[0130] Optionally, in some embodiments, after the step of generating invalid instructions corresponding to the preset instruction set architecture based on the first random encoding, the process may specifically include:

[0131] Step C1: Determine the first random code corresponding to the invalid instruction as a preset fixed code corresponding to the first instruction encoding format.

[0132] In this embodiment of the invention, after generating an invalid instruction, the first random code corresponding to the invalid instruction can be added to the preset fixed code set corresponding to the first instruction encoding format as a preset fixed code, so as to continue generating subsequent invalid instructions.

[0133] Step C2: Re-execute the step of selecting the first instruction encoding format from the instruction encoding format set corresponding to the preset instruction set architecture, and continue to generate the next invalid instruction, thereby obtaining an invalid instruction sequence containing multiple invalid instructions.

[0134] In this embodiment of the invention, after using the first random code corresponding to the generated invalid instruction as a preset fixed code corresponding to the first instruction encoding format, the next invalid instruction can be generated. That is, the next first instruction encoding format is selected again from the instruction encoding format set corresponding to the preset instruction set architecture, and then the next invalid instruction is determined according to the next first instruction encoding format. Since the first random code in each previously generated invalid instruction is used as a preset fixed code of the corresponding instruction encoding format, when determining the next invalid instruction according to the next first instruction encoding format, if the generated first random code is the same as any previously generated first random code, the first random code generated this time will match the corresponding preset fixed code. Therefore, an invalid instruction will not be generated based on this first random code, and the first random code can be regenerated, which can effectively avoid generating invalid instructions with duplicate content in fixed bit segments. This helps to improve the diversity of generated invalid instructions.

[0135] In this embodiment of the invention, multiple invalid instructions can be combined into an invalid instruction sequence. Each invalid instruction in the invalid instruction sequence has different fixed bit field content. This not only improves the efficiency of testing the CPU core through the invalid instruction sequence, but also increases the probability of discovering CPU core problems when testing the CPU core through the invalid instruction sequence due to the high diversity of invalid instructions, thus improving the accuracy of the test.

[0136] Optionally, in some embodiments, the total length of the fixed-bit segment of the first instruction encoding format can be determined by the following steps:

[0137] Step D1: Obtain the fixed bit range information corresponding to the first instruction encoding format.

[0138] In this embodiment of the invention, different instruction set architectures and different instruction encoding formats typically have different total lengths of fixed bit segments. Therefore, in order to improve the adaptability of this solution to different instruction set architectures, the total length of fixed bit segments corresponding to the first instruction encoding format can be automatically determined based on the fixed bit segment range information corresponding to the first instruction encoding format, thereby improving the applicability of the solution to different instruction set architectures and different instruction encoding formats.

[0139] Specifically, the fixed bit range information corresponding to the first instruction encoding format can be obtained. This fixed bit range information can be recorded in tabular form, key-value pair form, etc., and the embodiments of the present invention do not impose specific limitations.

[0140] Step D2: Determine the fixed segment length corresponding to each fixed segment of the first instruction encoding format based on the fixed segment range information.

[0141] In this embodiment of the invention, the fixed segment length corresponding to each fixed segment of the first instruction encoding format can be determined based on the fixed segment range information corresponding to the first instruction encoding format. For example, if the first instruction encoding format is as shown in Table 2 above, since the first instruction encoding format has three fixed segments: segment 1, segment 3, and segment 5, the fixed segment range information of the first instruction encoding format can be: bits 0 to 2 (segment 1), bits 5 to 7 (segment 3), and bits 10 to 11 (segment 5). Therefore, the fixed segment length corresponding to fixed segment 1 can be determined to be 3, the fixed segment length corresponding to fixed segment 3 to be 2, and the fixed segment length corresponding to fixed segment 5 to be 2.

[0142] Specifically, since the fixed segment range information can include the start position and end position of each fixed segment, the fixed segment length of the corresponding fixed segment can be obtained by calculating the difference between the start position and end position of each fixed segment in the fixed segment range information and adding 1 to the difference.

[0143] Step D3: Determine the total length of the fixed segments based on the length of each fixed segment.

[0144] After determining the length of each fixed segment in the first instruction encoding format, the lengths of each fixed segment can be summed to obtain the total length of the fixed tail of the first instruction encoding format.

[0145] In this embodiment of the invention, the fixed bit range information corresponding to the first instruction encoding format can be obtained; the fixed bit length corresponding to each fixed bit segment of the first instruction encoding format can be determined based on the fixed bit range information; and the total length of the fixed bit segments can be determined based on the fixed bit length corresponding to each fixed bit segment. Therefore, calculating the corresponding total length of the fixed bit segments through the fixed bit range information of the first instruction encoding format helps improve the adaptability of this solution to different instruction set architectures and different instruction encoding formats, and expands the overall applicability of the solution.

[0146] Reference Figure 2 , Figure 2 This diagram illustrates an invalid instruction generation process provided by an embodiment of the present invention, such as... Figure 2 As shown. First, based on the preset instruction set architecture, a preset fixed encoding set corresponding to each instruction encoding format in the preset instruction set architecture can be constructed. When it is necessary to generate an invalid instruction corresponding to the preset instruction set architecture, a first instruction encoding format is randomly selected from all instruction encoding formats of the preset instruction set architecture, and random constraints are constructed according to the corresponding preset fixed encoding set; then, a first random code is generated according to the random constraints; subsequently, a second random code corresponding to the variable bit field of the first instruction encoding format is randomly generated; then, the first random code and the second random code are concatenated to obtain the pending instruction; it can be determined whether the pending instruction matches other instruction encoding formats corresponding to the preset instruction set architecture. If the determination result is a match, the pending instruction is discarded, and a first instruction encoding format is randomly selected again from all instruction encoding formats of the preset instruction set architecture; if the determination result is a mismatch, the pending instruction is determined as an invalid instruction.

[0147] Reference Figure 3 The diagram shows a block diagram of an invalid instruction generation apparatus provided in an embodiment of the present invention, such as... Figure 3 As shown, the device may specifically include:

[0148] The selection module 301 is used to select a first instruction encoding format from the set of instruction encoding formats corresponding to the preset instruction set architecture;

[0149] The generation module 302 is used to generate a first random code whose encoding length is equal to the total length of the fixed bit segments of the first instruction encoding format;

[0150] The instruction module 303 is used to generate an invalid instruction corresponding to the preset instruction set architecture based on the first random encoding when the first random encoding is inconsistent with each preset fixed encoding corresponding to the first instruction encoding format; wherein the invalid instruction is used to test the central processing unit.

[0151] Optionally, the instruction module includes:

[0152] The pending instruction submodule is used to generate a pending instruction corresponding to the first instruction encoding format based on the first random encoding.

[0153] The invalid instruction submodule is used to determine the pending instruction as an invalid instruction corresponding to the preset instruction set architecture when the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture; wherein, the other instruction encoding formats refer to instruction encoding formats other than the first instruction encoding format in the preset instruction set architecture.

[0154] Optionally, the device further includes:

[0155] The first fixed bit segment encoding module is used to extract each first fixed bit segment encoding corresponding to the other instruction encoding formats from the pending instruction based on the fixed bit segment range information corresponding to the other instruction encoding formats in the instruction encoding format set.

[0156] The comparison encoding module is used to concatenate the first fixed bit segment codes based on the bit segment order corresponding to each first fixed bit segment code to obtain the comparison encoding;

[0157] The determination module is used to determine that the pending instruction does not match the other instruction encoding formats corresponding to the preset instruction set architecture when the code to be compared is inconsistent with each of the preset fixed codes corresponding to the other instruction encoding formats.

[0158] Optionally, the pending instruction submodule includes:

[0159] A random encoding unit is used to generate a second random code corresponding to the variable bit segment of the first instruction encoding format;

[0160] The pending instruction generation unit is used to concatenate the first random code and the second random code to obtain the pending instruction corresponding to the first instruction encoding format.

[0161] Optionally, the pending instruction generation unit includes:

[0162] The segmentation subunit is used to segment the first random code based on the fixed bit range information of the first instruction encoding format to obtain the second fixed bit segment code corresponding to each fixed bit segment of the first instruction encoding format.

[0163] The pending instruction splicing subunit is used to splice the second random code and each second fixed bit segment code according to the bit segment order corresponding to the second random code and each second fixed bit segment code to obtain the pending instruction corresponding to the first instruction encoding format.

[0164] Optionally, the device further includes:

[0165] A preset fixed encoding module is used to determine the first random encoding corresponding to the invalid instruction as a preset fixed encoding corresponding to the first instruction encoding format;

[0166] The invalid instruction sequence module is used to re-execute the step of selecting the first instruction encoding format from the instruction encoding format set corresponding to the preset instruction set architecture, and continue to generate the next invalid instruction, thereby obtaining an invalid instruction sequence containing multiple invalid instructions.

[0167] Optionally, the device further includes:

[0168] The fixed bit range information module is used to obtain the fixed bit range information corresponding to the first instruction encoding format;

[0169] The fixed segment length module is used to determine the fixed segment length corresponding to each fixed segment of the first instruction encoding format based on the fixed segment range information.

[0170] The fixed segment total length module is used to determine the total length of the fixed segment based on the fixed segment lengths corresponding to each fixed segment.

[0171] In summary, the invalid instruction generation apparatus provided in this embodiment of the invention selects a first instruction encoding format from a set of instruction encoding formats corresponding to a preset instruction set architecture; generates a first random code whose encoding length is equal to the total length of fixed segments of the first instruction encoding format; and generates an invalid instruction corresponding to the preset instruction set architecture based on the first random code when none of the first random code matches any of the preset fixed codes corresponding to the first instruction encoding format. This random generation method can directly generate invalid instructions that do not conform to the instruction encoding format corresponding to the preset instruction set architecture, thus improving the efficiency of generating invalid instructions for the preset instruction set architecture.

[0172] Reference Figure 4 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Figure 4As shown, the electronic device includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other via the communication bus. The memory stores at least one executable instruction, which causes the processor to execute the invalid instruction generation method described in the preceding embodiment. The executable instructions can form a program.

[0173] This invention provides a computer-readable storage medium storing instructions that, when executed by one or more processors, enable the processors to perform the invalid instruction generation method described in the foregoing embodiments.

[0174] The embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other.

[0175] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. It should be noted that all actions involving the acquisition of signals, information, or data in the present invention are performed in compliance with the relevant data protection regulations and policies of the country where the invention is located, and with authorization from the owner of the corresponding device. Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0176] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0177] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0178] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0179] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0180] The present invention has provided a detailed description of an invalid instruction generation method, an invalid instruction generation device, an electronic device, and a storage medium. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for generating invalid instructions, characterized in that, The method includes: Select the first instruction encoding format from the set of instruction encoding formats corresponding to the preset instruction set architecture; The number base and the factor of the total length of the fixed bit segment of the first instruction encoding format are input into the random number generator, so that the random number generator outputs multiple random numbers with the length of the factor. Multiple random numbers with lengths equal to the factor are concatenated to obtain a first random code whose encoding length is equal to the total length of the fixed bit segment; When the first random encoding is inconsistent with each of the preset fixed encodings corresponding to the first instruction encoding format, an invalid instruction corresponding to the preset instruction set architecture is generated based on the first random encoding; wherein, the invalid instruction is used to test the central processing unit; The step of selecting the first instruction encoding format from the set of instruction encoding formats corresponding to the preset instruction set architecture is re-executed, and multiple invalid instructions corresponding to the first instruction encoding format are generated again. Combine the multiple invalid instructions into an invalid instruction stream; The step of generating invalid instructions corresponding to the preset instruction set architecture based on the first random encoding includes: According to the instruction encoding format corresponding to the first random code, the first random code is expanded using a preset bit. The first random code expanded to the instruction bit length defined by the instruction encoding format is regarded as an invalid instruction, and the position of the code corresponding to each fixed bit segment in the first random code in the invalid instruction is kept in accordance with the definition of the instruction encoding format; the preset bit is a random binary bit.

2. The invalid instruction generation method according to claim 1, characterized in that, The step of generating invalid instructions corresponding to the preset instruction set architecture based on the first random encoding further includes: Based on the first random encoding, generate a pending instruction corresponding to the first instruction encoding format; If the pending instruction does not match other instruction encoding formats corresponding to the preset instruction set architecture, the pending instruction is determined as an invalid instruction corresponding to the preset instruction set architecture; wherein, the other instruction encoding formats refer to instruction encoding formats other than the first instruction encoding format in the preset instruction set architecture.

3. The invalid instruction generation method according to claim 2, characterized in that, The method further includes: Based on the fixed bit range information corresponding to other instruction encoding formats in the instruction encoding format set, extract the first fixed bit segment codes corresponding to the other instruction encoding formats from the pending instruction; Based on the bit segment order corresponding to each first fixed bit segment code, the first fixed bit segment codes are concatenated to obtain the code to be compared; If the code to be compared is inconsistent with each of the preset fixed codes corresponding to the other instruction encoding formats, it is determined that the instruction to be compared does not match the other instruction encoding formats corresponding to the preset instruction set architecture.

4. The invalid instruction generation method according to claim 2, characterized in that, The step of generating the pending instruction corresponding to the first instruction encoding format based on the first random encoding includes: Generate a second random code corresponding to the variable bit segment of the first instruction encoding format; By concatenating the first random code and the second random code, a pending instruction corresponding to the first instruction encoding format is obtained.

5. The invalid instruction generation method according to claim 4, characterized in that, The step of concatenating the first random code and the second random code to obtain the pending instruction corresponding to the first instruction encoding format includes: Based on the fixed bit range information of the first instruction encoding format, the first random code is segmented to obtain the second fixed bit segment code corresponding to each fixed bit segment of the first instruction encoding format. Based on the bit order corresponding to the second random code and each second fixed bit segment code, the second random code and each second fixed bit segment code are concatenated to obtain the pending instruction corresponding to the first instruction encoding format.

6. The invalid instruction generation method according to claim 1, characterized in that, After generating invalid instructions corresponding to the preset instruction set architecture based on the first random encoding, the method further includes: The first random code corresponding to the invalid instruction is determined as a preset fixed code corresponding to the first instruction encoding format; The step of selecting the first instruction encoding format from the set of instruction encoding formats corresponding to the preset instruction set architecture is re-executed to continue generating the next invalid instruction, thereby obtaining an invalid instruction sequence containing multiple invalid instructions.

7. The invalid instruction generation method according to claim 1, characterized in that, The method further includes: Obtain the fixed bit range information corresponding to the first instruction encoding format; Based on the fixed segment range information, the fixed segment length corresponding to each fixed segment of the first instruction encoding format is determined. The total length of the fixed segments is determined based on the length of each fixed segment.

8. An invalid instruction generation device, characterized in that, The device includes: The selection module is used to select the first instruction encoding format from the set of instruction encoding formats corresponding to the preset instruction set architecture; The generation module is used to generate a first random code whose encoding length is equal to the total length of the fixed bit segments of the first instruction encoding format; The instruction module is configured to, when the first random encoding is inconsistent with each of the preset fixed encodings corresponding to the first instruction encoding format, generate invalid instructions corresponding to the preset instruction set architecture based on the first random encoding; re-execute the step of selecting a first instruction encoding format from the set of instruction encoding formats corresponding to the preset instruction set architecture, and continue to generate multiple invalid instructions corresponding to the first instruction encoding format; combine the multiple invalid instructions into an invalid instruction stream; wherein, the invalid instructions are used to test the central processing unit; The generation module is further configured to input the base number and the factor of the total length of the fixed bit segment into the random number generator, so that the random number generator outputs multiple random numbers with the length of the factor; and to concatenate the multiple random numbers with the length of the factor to obtain a first random code with a code length equal to the total length of the fixed bit segment. The instruction module is further configured to, when the first random code is inconsistent with each of the preset fixed codes corresponding to the first instruction encoding format, expand the first random code using preset bits according to the instruction encoding format corresponding to the first random code, and take the first random code expanded to the instruction bit length defined by the instruction encoding format as an invalid instruction, while maintaining the position of the code corresponding to each fixed bit segment in the first random code in the invalid instruction in accordance with the definition of the instruction encoding format; the preset bits are random binary bits.

9. An electronic device, characterized in that, include: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store executable instructions that cause the processor to execute the invalid instruction generation method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, It stores instructions that, when executed by one or more processors, cause the processors to perform the invalid instruction generation method as described in any one of claims 1 to 7.

Images