Thread bundle scheduling method and device, graphics processor and computer equipment

Abstract

The embodiment of the invention provides a thread bundle scheduling method and device, a graphics processor and computer equipment, and the method is applied to the graphics processor and comprises the steps that current hardware resource use information of the graphics processor is acquired; based on the hardware resource use information and a task type of each thread bundle in a to-be-scheduled thread bundle queue, determining a target thread bundle from the thread bundle queue; the task type of each thread bundle corresponds to the hardware resource demand of the thread bundle; and scheduling and executing the target thread bundle. Thus, by comprehensively considering the hardware resource demand of the thread bundle and the current hardware resource use condition of the graphics processor, the thread bundle is scheduled, hardware resources in the graphics processor can be utilized more fully and reasonably, the situation that execution is delayed due to the fact that the scheduled target thread bundle waits for resource release is reduced, and the execution efficiency is improved. Therefore, the processing performance of the graphics processor and the overall execution efficiency of each thread bundle can be improved.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of computer technology, and in particular to a warp scheduling method, apparatus, graphics processor, and computer equipment. Background Art

[0002] Graphics Processing Unit (GPU) is widely used in multi-threaded task processing scenarios, and is executed at the granularity of warp or wave. Usually, each warp contains several threads (such as 32 or 64). When there are many parallel warps, the GPU needs to use some scheduling method to decide which group of warps can be executed. However, the warp scheduling scheme in the related art is difficult to reasonably utilize the hardware resources in the GPU, which affects the processing performance of the GPU. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure at least provide a warp scheduling method, apparatus, graphics processor, and computer equipment.

[0004] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] The present disclosure provides a thread warp scheduling method, which is applied to a graphics processor. The method includes:

[0006] Get the current hardware resource usage information of the graphics processor;

[0007] Based on the hardware resource usage information and the task type of each warp in the warp queue to be scheduled, determining a target warp from the warp queue; the task type of each warp corresponds to the hardware resource requirement of the warp;

[0008] Schedules the target warp for execution.

[0009] The present disclosure provides a thread warp scheduling device, which is applied to a graphics processor. The device includes:

[0010] Resource monitoring module, used to obtain the current hardware resource usage information of the graphics processor;

[0011] The scheduling and execution module is used to: determine the target thread warp from the thread warp queue based on the hardware resource usage information and the task type of each thread warp in the thread warp queue to be scheduled; the task type of each thread warp corresponds to the hardware resource requirement of the thread warp; and schedule and execute the target thread warp.

[0012] The embodiment of the present disclosure provides a graphics processor, including the thread warp scheduling device in the above embodiment.

[0013] An embodiment of the present disclosure provides a computer device, comprising the graphics processor in the above embodiment.

[0014] In the disclosed embodiment, the current hardware resource usage information of the graphics processor is obtained; based on the hardware resource usage information and the task type of each thread bundle in the thread bundle queue to be scheduled, the target thread bundle is determined from the thread bundle queue; the task type of each thread bundle corresponds to the hardware resource requirement of the thread bundle; and the target thread bundle is scheduled for execution. In this way, by comprehensively considering the hardware resource requirements of the thread bundle and the current hardware resource usage of the graphics processor, the thread bundle is scheduled, which can more fully and reasonably utilize the hardware resources in the graphics processor, reduce the situation where the scheduled target thread bundle is delayed in execution due to waiting for resource release, and thus improve the processing performance of the graphics processor and the overall execution efficiency of each thread bundle.

[0015] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0017] Figure 1 A schematic diagram of an implementation flow of a thread warp scheduling method provided in an embodiment of the present disclosure;

[0018] Figure 2 A schematic diagram of the structure of a thread warp scheduling device provided in an embodiment of the present disclosure Figure 1 ;

[0019] Figure 3 A schematic diagram of the structure of a thread warp scheduling device provided in an embodiment of the present disclosure Figure 1 ;

[0020] Figure 4 A schematic diagram of the structure of a graphics processor provided by an embodiment of the present disclosure;

[0021] Figure 5 A schematic diagram of the structure of a computer device provided in an embodiment of the present disclosure;

[0022] Figure 6 A schematic diagram of an implementation architecture of a thread warp scheduling method provided in an embodiment of the present disclosure;

[0023] Figure 7 A schematic diagram comparing the task execution timing of a warp scheduling method provided in an embodiment of the present disclosure and a polling scheduling scheme in related technologies. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0025] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0026] The terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged with a specific order or sequence where permitted so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the present disclosure and are not intended to limit the present disclosure.

[0028] The embodiment of the present disclosure provides a thread warp scheduling method, which can be executed by a graphics processor. Figure 1 A schematic diagram of an implementation flow of a thread warp scheduling method provided in an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the method may include the following steps S101 to S103:

[0029] Step S101, obtaining the current hardware resource usage information of the graphics processor.

[0030] Here, the hardware resource usage information may include usage information of any appropriate hardware resource in the graphics processor, wherein the hardware resource may include but is not limited to at least one of memory access resources, computing resources, communication resources, and the like.

[0031] The hardware resource usage information may include but is not limited to at least one of the utilization rate of the hardware resources, the idle rate of the hardware resources, the idle amount of the hardware resources, the busyness of the hardware resources, the idleness of the hardware resources, etc.

[0032] Step S102 : determining a target warp from the warp queue based on the hardware resource usage information and the task type of each warp in the warp queue to be scheduled; the task type of each warp corresponds to the hardware resource requirement of the warp.

[0033] Here, the warp queue may include a plurality of warps currently to be scheduled in the graphics processor.

[0034] Each warp in the warp queue has a corresponding task type, and the task type can reflect the hardware resource requirements for executing the warp.

[0035] During implementation, those skilled in the art may adopt any appropriate method according to actual conditions to determine the task type corresponding to the hardware resource requirement for the warp, and the embodiments of the present disclosure are not limited to this.

[0036] For example, when more memory access resources are required for executing a warp, the task type of the warp may be memory access intensive, that is, the warp executes a memory access intensive task.

[0037] For another example, when more computing resources are required to execute a warp, the task type of the warp may be computationally intensive, that is, the warp executes a computationally intensive task.

[0038] For another example, when more communication resources are required to execute a warp, the task type of the warp may be a communication type, that is, the warp executes a communication type task.

[0039] In some implementations, the task type of each warp may be manually set in advance by a developer according to the hardware resource requirements of the warp. For example, when a task execution instruction is triggered, the task type of each warp corresponding to the task execution instruction may be set in a software interface or function that generates the task execution instruction.

[0040] In some implementations, the task type of each warp may be determined by a graphics processor after analyzing hardware resource requirements of each warp.

[0041] The target warp may be determined from the warp queue after comprehensively considering the hardware resource requirements of the warp and the current hardware resource usage of the graphics processor.

[0042] Step S103: scheduling and executing the target warp.

[0043] Here, after the target warp is determined, the target warp may be scheduled to allocate corresponding hardware resources to execute the target warp.

[0044] In the disclosed embodiment, the current hardware resource usage information of the graphics processor is obtained; based on the hardware resource usage information and the task type of each thread bundle in the thread bundle queue to be scheduled, the target thread bundle is determined from the thread bundle queue; the task type of each thread bundle corresponds to the hardware resource requirement of the thread bundle; and the target thread bundle is scheduled for execution. In this way, by comprehensively considering the hardware resource requirements of the thread bundle and the current hardware resource usage of the graphics processor, the thread bundle is scheduled, which can more fully and reasonably utilize the hardware resources in the graphics processor, reduce the situation where the scheduled target thread bundle is delayed due to waiting for resource release, and thus improve the processing performance of the graphics processor and the overall execution efficiency of each thread bundle. In some embodiments, the task type is obtained through a software interface, and the current hardware resource usage information of the graphics processor is obtained through hardware monitoring. The target thread bundle is scheduled based on the task type obtained through the software interface and the current hardware resource usage information obtained through hardware monitoring, thereby achieving more reasonable scheduling.

[0045] In some embodiments, the above step S102 may include the following steps S111 and S112:

[0046] Step S111 : determining a target task type to be scheduled with priority from the plurality of task types based on the hardware resource usage information.

[0047] Here, based on the hardware resource usage information of the graphics processor, relatively idle hardware resources in the graphics processor can be determined, and thus, according to the relatively idle hardware resources, the target task type to be scheduled preferentially can be determined from multiple task types.

[0048] In some implementations, when the hardware resource usage information includes utilization rates of multiple hardware resources, the target task type to be scheduled first can be determined based on at least one hardware resource whose utilization rate is lower than a first threshold. The first threshold can be predetermined by those skilled in the art according to actual conditions, and the embodiments of the present disclosure do not limit this.

[0049] In some implementations, when the hardware resource usage information includes the idle amounts of multiple hardware resources, the target task type to be scheduled first can be determined based on at least one hardware resource whose idle amount is higher than the second threshold. The second threshold can be predetermined by those skilled in the art according to actual conditions, and the embodiments of the present disclosure do not limit this.

[0050] Step S112 : determining a target warp from at least one candidate warp in the warp queue, wherein the task type of the candidate warp is the target task type.

[0051] Here, the manner of determining the target warp from at least one candidate warp may be determined according to actual conditions, and the embodiments of the present disclosure are not limited thereto.

[0052] In some implementations, the candidate warp that is ranked first in the warp queue may be determined as the target warp according to the order of the candidate warps in the warp queue.

[0053] In some implementations, the candidate warp that consumes the least hardware resources among the candidate warps may be determined as the target warp.

[0054] In the above embodiment, based on the hardware resource usage information, the target task type to be scheduled with priority is determined from multiple task types, and the target warp is determined from at least one candidate warp in the warp queue, and the task type of the candidate warp is the target task type. In this way, the target task type to be scheduled with priority can be determined simply and quickly.

[0055] In some embodiments, the hardware resource usage information includes utilization rates of multiple hardware resources;

[0056] The above step S111 may include the following steps S121 and S122:

[0057] Step S121, determining the target hardware resource with the lowest utilization rate among the multiple hardware resources.

[0058] Step S122: Based on the target hardware resources, determine a target task type to be scheduled with priority from the multiple task types, and the hardware resource requirements corresponding to the target task type match the target hardware resources.

[0059] It can be understood that the target hardware resource is the hardware resource with the lowest utilization rate among multiple hardware resources, that is, the target hardware resource is the hardware resource with the highest idleness among multiple hardware resources. Therefore, based on the target hardware resource, a task type whose hardware resource requirements match the target hardware resource can be selected from multiple task types as the target task type to be scheduled with priority.

[0060] In this way, the determined target thread warp can be more compatible with the current hardware resource usage of the GPU, so that the hardware resources in the GPU can be more reasonably utilized, further improving the processing performance of the GPU and the overall execution efficiency of each thread warp.

[0061] In some embodiments, the multiple hardware resources include memory access resources, computing resources, and communication resources; the multiple task types include memory access intensive, computing intensive, and communication types.

[0062] The above step S122 may include at least one of the following steps S131 to S133:

[0063] Step S131, when the target hardware resource is the memory access resource, determining that the type of the target task to be scheduled with priority is memory access intensive.

[0064] In this way, since the target hardware resource is a memory access resource, it indicates that the utilization rate of the current memory access resource in the graphics processor is the lowest. Therefore, by determining the target task type to be scheduled first as memory access intensive, the graphics processor can prioritize the scheduling of memory access intensive thread bundles that have a greater demand for memory access resources, thereby improving the utilization rate of memory access resources. In addition, since the memory access intensive thread bundle has a relatively small demand for other hardware resources other than memory access resources, it can reduce the situation where the scheduled target thread bundle is delayed in execution due to waiting for the release of other hardware resources other than memory access resources, thereby further improving the processing performance of the graphics processor.

[0065] Step S132, when the target hardware resource is the computing resource, determining that the type of the target task to be scheduled with priority is computing intensive.

[0066] In this way, since the target hardware resource is a computing resource, it indicates that the utilization rate of the current computing resource in the graphics processor is the lowest. Therefore, by determining the target task type to be scheduled first as computing intensive, the graphics processor can prioritize the scheduling of computing intensive thread bundles that have a large demand for computing resources, thereby improving the utilization rate of computing resources. In addition, since the computing intensive thread bundle has a relatively small demand for other hardware resources other than computing resources, it can reduce the situation where the scheduled target thread bundle is delayed in execution due to waiting for the release of other hardware resources other than computing resources, thereby further improving the processing performance of the graphics processor.

[0067] Step S133, when the target hardware resource is the communication resource, determine that the target task type to be scheduled with priority is a communication type.

[0068] In this way, since the target hardware resource is a communication resource, it indicates that the utilization rate of the current communication resource in the graphics processor is the lowest. Therefore, by determining the target task type to be scheduled preferentially as a communication type, the graphics processor can preferentially schedule the communication type thread bundles that have a greater demand for communication resources, thereby improving the utilization rate of communication resources. In addition, since the communication type thread bundles have relatively small demands for other hardware resources other than communication resources, the situation where the scheduled target thread bundles are delayed in execution due to waiting for the release of other hardware resources other than communication resources can be reduced, thereby further improving the processing performance of the graphics processor.

[0069] In some embodiments, the above step S101 may include at least one of the following steps S141 to S143:

[0070] Step S141, when the multiple hardware resources include memory access resources, determine the utilization rate of the memory access resources based on the maximum memory access bandwidth supported by the graphics processor and the current memory access bandwidth usage of the graphics processor.

[0071] Here, the maximum memory access bandwidth refers to the maximum memory access bandwidth supported by the memory in the graphics processor, wherein the memory may be the main memory and / or other storage modules in the graphics processor, which is not limited in the embodiments of the present disclosure.

[0072] The maximum memory access bandwidth represents the maximum number of memory access request bytes that the memory can receive in a single clock cycle. For example, the maximum memory access bandwidth may be a theoretical bandwidth of the memory, and the theoretical bandwidth may be an inherent hardware parameter of the memory.

[0073] The current memory access bandwidth usage of the graphics processor may refer to the number of memory access request bytes actually received by the memory in the current clock cycle, or may refer to the average number of memory access request bytes received by the memory in each clock cycle in multiple clock cycles before the current clock cycle. The embodiments of the present disclosure are not limited to this.

[0074] In some implementations, the ratio between the current memory access bandwidth usage of the graphics processor and the maximum memory access bandwidth supported by the graphics processor may be determined as the current memory access resource utilization of the graphics processor.

[0075] In this way, the current memory access resource utilization of the graphics processor can be determined quickly and accurately.

[0076] Step S142, when the multiple hardware resources include computing resources, determine the utilization rate of the computing resources based on the maximum computing amount supported by the graphics processor in a single clock cycle and the actual computing amount of the graphics processor in the current clock cycle.

[0077] Here, the maximum amount of operations supported by the graphics processor in a single clock cycle refers to the maximum amount of operations (ie, the number of operations) that a computing unit in the graphics processor can provide in a single clock cycle.

[0078] In some implementations, the maximum amount of operations may be a hardware design parameter of a graphics processor.

[0079] The actual amount of operations performed by the graphics processor in the current clock cycle may refer to the number of operations actually performed by the operation unit in the graphics processor in the current clock cycle, or may refer to the average number of operations performed by the operation unit in the graphics processor in each clock cycle in multiple clock cycles before the current clock cycle. The embodiments of the present disclosure are not limited to this.

[0080] In some implementations, the ratio between the actual amount of computation performed by the graphics processor in the current clock cycle and the maximum amount of computation supported by the graphics processor in a single clock cycle may be determined as the utilization rate of the current computational resources of the graphics processor.

[0081] In this way, the utilization rate of the current computing resources of the graphics processor can be determined quickly and accurately.

[0082] Step S143, when the multiple hardware resources include communication resources, determining the utilization rate of the communication resources based on the maximum communication bandwidth supported by the graphics processor and the current communication bandwidth usage of the graphics processor.

[0083] Here, the maximum communication bandwidth refers to the maximum communication bandwidth supported by the communication unit in the graphics processor, wherein the communication unit may include but is not limited to at least one of a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) unit, a communication unit based on NVLink (a bus and communication protocol), etc., and the embodiments of the present disclosure are not limited to this.

[0084] The maximum communication bandwidth represents the maximum number of communication request bytes that the communication unit in the graphics processor can receive in a single clock cycle. For example, the maximum communication bandwidth may be a theoretical bandwidth of the communication unit, and the theoretical bandwidth may be a hardware design parameter of the communication unit in the graphics processor.

[0085] The current communication bandwidth usage of the graphics processor may refer to the number of communication request bytes actually received by the communication unit in the current clock cycle, or may refer to the average number of communication request bytes received by the communication unit in each clock cycle in multiple clock cycles before the current clock cycle. The embodiments of the present disclosure are not limited to this.

[0086] In some implementations, the communication resources in the graphics processor are used to support communication between the graphics processor and other processors. The other processors may include but are not limited to at least one of other graphics processors, other central processing units (CPUs), and the like.

[0087] In some implementations, the ratio between the current communication bandwidth usage of the graphics processor and the maximum communication bandwidth supported by the graphics processor may be determined as the current communication resource utilization of the graphics processor.

[0088] In this way, the utilization rate of the current computing resources of the graphics processor can be determined quickly and accurately.

[0089] In some embodiments, the above method may further include the following steps S151 and S152:

[0090] Step S151, receiving a task execution instruction, wherein the task execution instruction includes task information of a task to be executed, and the task information includes task execution parameters and a preset task type.

[0091] Here, the task execution instruction may be generated by the main processor (such as a CPU or other GPU, etc.) during the execution of the task processing program, by calling an interface or function in the program software and sent to the graphics processor.

[0092] During implementation, the main processor may generate a task execution instruction by calling any suitable interface or function, and send the task execution instruction to the graphics processor, which is not limited in the embodiments of the present disclosure. For example, the task execution instruction may be generated and sent to the graphics processor by calling the GPU kernel under the Compute Unified Device Architecture (CUDA).

[0093] The task execution parameters may include any appropriate parameters required for executing the task, and those skilled in the art may reasonably set them according to the tasks actually executed.

[0094] The preset task type is used to characterize the task type of the task to be executed, and the preset task type corresponds to the hardware resource requirement of the task to be executed.

[0095] In some embodiments, the preset task type of the task to be executed can be manually set in advance by the developer according to the hardware resource requirements of the task to be executed. For example, when writing a software interface or function that generates a task execution instruction corresponding to the task to be executed, the task type of the task to be executed can be set in the software interface or function.

[0096] In some implementations, the task type of the task to be executed may be determined by analyzing the hardware resource requirements of each warp.

[0097] In some implementations, the preset task type may be represented by a preset type value. In particular, corresponding type values ​​may be pre-set for various task types. For example, "0" may be used to represent computationally intensive, "1" may be used to represent memory access intensive, and "2" may be used to represent communication type.

[0098] Step S152: creating at least one new warp based on the task execution parameter, and adding the at least one new warp to the warp queue; the task type of each of the new warps is the preset task type.

[0099] Here, at least one new warp for executing the task to be executed can be created based on the task execution parameters of the task to be executed, so that the task content of the task to be executed is divided into each new warp for execution. In addition, the preset task type of the task to be executed can be used as the task type of each new warp.

[0100] During implementation, those skilled in the art may adopt any appropriate method according to actual conditions to create at least one new warp based on the task execution parameters, and the embodiments of the present disclosure are not limited to this.

[0101] In the above embodiment, a task execution instruction is received, the task execution instruction includes task information of the task to be executed, and the task information includes task execution parameters and preset task types; based on the task execution parameters, at least one new thread bundle is created, and at least one new thread bundle is added to the thread bundle queue; the task type of each new thread bundle is the preset task type. In this way, by carrying the preset task type of the task to be executed in the task execution instruction, the corresponding task type can be specified for the at least one new thread bundle corresponding to the task to be executed, so that the task type of each thread bundle in the thread bundle queue can be made more accurate and flexible to set.

[0102] In some embodiments, the above step S151 may include the following step S161:

[0103] Step S161, receiving the task execution instruction sent by the main processor; the task execution instruction is generated by the main processor based on the task execution parameters and the preset task type, and the preset task type is determined by the main processor based on the hardware resource requirements of the task to be executed.

[0104] Here, the main processor may determine a preset task type based on the hardware resource requirements of the task to be executed, and generate a task execution instruction based on the task execution parameters of the task to be executed and the preset task type, and then send the task execution instruction to the graphics processor.

[0105] In some embodiments, the main processor can generate a task execution instruction based on the task execution parameters of the task to be executed and the preset task type by calling a preset software interface, and send the task execution instruction to the graphics processor. The graphics processor can receive the task execution instruction sent by the main processor through the preset software interface. For example, the preset software interface can include but is not limited to the kernel function of the graphics processor.

[0106] In this way, the main processor can flexibly set a suitable task type for the task to be executed according to the hardware resource requirements of the task to be executed, and generate corresponding task execution instructions, so that the corresponding task type can be flexibly and conveniently specified for at least one newly created thread bundle corresponding to the task to be executed through software.

[0107] The step S152 of creating at least one new warp based on the task execution parameters may include the following steps S162 and S163:

[0108] Step S162: Determine the task type code based on the preset task type.

[0109] In some implementations, after receiving the task execution instruction, the graphics processor may parse the task execution instruction to obtain the task execution parameters and the preset task type of the task to be executed contained in the task execution instruction.

[0110] After obtaining the preset task type, the graphics processor can encode the preset task type to obtain the task type code. The graphics processor can encode the preset task type in any suitable encoding manner, which is not limited in the embodiment of the present disclosure.

[0111] In some implementations, different codes may be pre-set for each candidate task type in the set candidate task type set, and after the image processor obtains the preset task type, the code corresponding to the preset task type may be used as the task type code. For example, in the case of computing intensive, memory access intensive, and communication types in the candidate task type set, the code corresponding to computing intensive may be pre-set as "00", the code corresponding to memory access intensive may be pre-set as "01", and the code corresponding to communication type may be pre-set as "10".

[0112] In some implementations, corresponding type values ​​may be set for various task types in advance, and the type values ​​corresponding to the task types may be converted into binary codes to obtain the task type codes corresponding to the task types. For example, type value 0 may be used to represent computationally intensive, type value 1 may be used to represent memory access intensive, and type value 2 may be used to represent communication type. Then the task type code corresponding to computationally intensive is "00", the task type code corresponding to memory access intensive is "01", and the task type code corresponding to communication type is "10".

[0113] Step S163: creating at least one new warp based on the task execution parameter, and associating the at least one new warp with the task type code respectively, wherein the task type code is used to indicate that the task type of the new warp is the preset task type.

[0114] Here, after the graphics processor creates at least one new thread warp for executing the task to be executed based on the task execution parameters, each new thread warp can be associated with the task type code. In this way, the task type code associated with each thread warp can be referred to during the process of determining and scheduling the target thread warp from the thread warp queue, and the task type of each thread warp can be quickly and intuitively determined according to the task type code.

[0115] An embodiment of the present disclosure provides a thread warp scheduling device, which can be applied to a graphics processor. Figure 2 A schematic diagram of the structure of a thread warp scheduling device provided in an embodiment of the present disclosure Figure 1 ,like Figure 2 As shown, the thread warp scheduling device 200 includes a resource monitoring module 210 and a scheduling execution module 220, wherein:

[0116] The resource monitoring module 210 is used to obtain the current hardware resource usage information of the graphics processor;

[0117] The scheduling execution module 220 is used to: determine the target warp from the warp queue based on the hardware resource usage information and the task type of each warp in the warp queue to be scheduled; correspond the task type of each warp to the hardware resource requirement of the warp; and schedule and execute the target warp.

[0118] In the disclosed embodiment, thread bundles are scheduled by comprehensively considering the hardware resource requirements of the thread bundles and the current hardware resource usage of the graphics processor. This can more fully and reasonably utilize the hardware resources in the graphics processor, reduce the situation where the scheduled target thread bundles are delayed in execution due to waiting for resource release, and thus improve the processing performance of the graphics processor and the overall execution efficiency of each thread bundle.

[0119] In some embodiments, the scheduling execution module 220 is further used to: determine a target task type to be scheduled preferentially from the multiple task types based on the hardware resource usage information; determine a target thread warp from at least one candidate thread warp in the thread warp queue, wherein the task type of the candidate thread warp is the target task type.

[0120] In some embodiments, the hardware resource usage information includes the utilization rates of multiple hardware resources; the scheduling execution module 220 is also used to: determine the target hardware resource with the lowest utilization rate among the multiple hardware resources; based on the target hardware resource, determine the target task type to be scheduled first from the multiple task types, and the hardware resource requirements corresponding to the target task type match the target hardware resource.

[0121] In some embodiments, the multiple hardware resources include memory access resources, computing resources, and communication resources; the multiple task types include memory access intensive, computing intensive, and communication types; the scheduling execution module 220 is also used for at least one of the following: when the target hardware resource is the memory access resource, determining that the target task type to be scheduled with priority is memory access intensive; when the target hardware resource is the computing resource, determining that the target task type to be scheduled with priority is computing intensive; when the target hardware resource is the communication resource, determining that the target task type to be scheduled with priority is a communication type.

[0122] In some embodiments, the resource monitoring module 210 is also used for at least one of the following: when the multiple hardware resources include memory access resources, based on the maximum memory access bandwidth supported by the graphics processor and the current memory access bandwidth usage of the graphics processor, determining the utilization of the computing resources; when the multiple hardware resources include computing resources, based on the maximum computing amount supported by the graphics processor in a single clock cycle and the actual computing amount of the graphics processor in the current clock cycle, determining the utilization of the computing resources; when the multiple hardware resources include communication resources, based on the maximum communication bandwidth supported by the graphics processor and the current communication bandwidth usage of the graphics processor, determining the utilization of the communication resources.

[0123] In some embodiments, Figure 3 As shown, the thread warp scheduling device 200 also includes: a thread warp creation module 230, which is used to: receive a task execution instruction, wherein the task execution instruction includes task information of a task to be executed, wherein the task information includes task execution parameters and a preset task type; based on the task execution parameters, create at least one new thread warp, and add the at least one new thread warp to the thread warp queue; the task type of each of the new thread warps is the preset task type.

[0124] The present disclosure provides a graphics processor. Figure 4 As shown, the graphics processor 400 includes the above-mentioned thread warp scheduling device 200 .

[0125] The present disclosure provides a computer device. Figure 5As shown, the computer device 500 includes the above-mentioned graphics processor 400 .

[0126] The following describes the application of the thread warp scheduling method provided by the embodiment of the present disclosure in a practical scenario.

[0127] GPUs are widely used in multi-threaded task processing scenarios, and they execute tasks at the granularity of thread bundles, where each thread bundle usually contains several threads. When there are many parallel thread bundles, the GPU needs to use a certain scheduling method to determine which thread bundle can be executed. In related technologies, the scheduling method for thread bundles in GPUs is round-robin scheduling.

[0128] However, the workloads of different thread bundles (i.e., the hardware resources required for execution) may be different, and the hardware resources in the GPU (such as computing units or memory access bandwidth, etc.) are all limited. Therefore, the polling scheduling method may cause some hardware resources to be occupied too much, and the scheduled thread bundles cannot be effectively executed because they need to wait for the release of hardware resources.

[0129] In the thread warp scheduling method provided in the embodiment of the present disclosure, the type of workload of each thread warp in the GPU (corresponding to the task type in the aforementioned embodiment) can be provided through a software interface, such as computationally intensive, memory-access intensive, or inter-card communication type (corresponding to the communication type in the aforementioned embodiment), etc. In the process of hardware scheduling thread warps, more effective scheduling can be performed based on the type of workload of each thread warp in the thread warp queue to be scheduled, combined with the current hardware resource occupancy in the GPU (such as main memory bandwidth utilization, computing resource utilization, communication resource utilization, etc.), so that hardware resources can be better utilized.

[0130] Figure 6 A schematic diagram of an implementation architecture of a thread warp scheduling method provided by an embodiment of the present disclosure. Figure 6 As shown, the method can be implemented by the software layer 61 and the hardware 62 in collaboration. In the software layer 61, the programmer can define the preset task type KERNEL_TYPE of the task to be executed through the software interface when starting the GPU kernel (Kernels) to execute the task to be executed based on the understanding of the task to be executed, so as to indicate the demand of the task to be executed for different hardware resources in the GPU. Among them, the preset task type KERNEL_TYPE can be, for example: computationally intensive, memory-access intensive, or inter-card communication type. Taking CUDA calling the GPU kernel (kernel function) to generate a task execution instruction as an example, the software interface called can be:

[0131] gpu_kernel<<<BLOCK_NUMBER,BLOCK_SIZE,KERNEL_TYPE> >>(ARG_A,ARG_B,ARG_C);

[0132] Among them, BLOCK_NUMBER indicates the number of the thread block that executes the corresponding task to be executed, BLOCK_SIZE indicates the size of the thread block, KERNEL_TYPE indicates the preset task type, and ARG_A, ARG_B and ARG_C are all task execution parameters of the task to be executed. It can be defined that when KERNEL_TYPE is 0, it means that the task to be executed is a computation-intensive task; when KERNEL_TYPE is 1, it means that the task to be executed is a memory-intensive task; when KERNEL_TYPE is 2, it means that the task to be executed is a card-to-card communication task used for inter-card communication.

[0133] Continue to see Figure 6 In the hardware 62 of the GPU, according to the preset task type KERNEL_TYPE passed in by the software, the hardware 62 can encode the preset task type KERNEL_TYPE to obtain the task type of each thread bundle corresponding to the task to be executed. Taking the three types of task types currently supported (i.e., computation-intensive, memory-access-intensive, and inter-card communication) as an example, the hardware 62 only needs to do 2-bit encoding, for example, encoding "00" represents computation-intensive, encoding "01" represents memory-access-intensive, and encoding "10" represents inter-card communication. After the work of the task to be executed corresponding to the GPU kernel is divided into multiple thread bundles (corresponding to the newly created thread bundles in the aforementioned embodiment), each divided thread bundle is attached with this 2-bit encoding as a task type (such as task type Type0, Type1, TypeN) for the scheduler to identify; each divided thread bundle is added to the thread bundle queue Warps_Array to be scheduled, and the thread bundle queue can record the task type of each thread bundle (such as thread bundles Warp_0, Warp_1, Warp_N).

[0134] The GPU hardware 62 may include a scheduler 621 , a selector 622 , a hardware monitor 623 , and hardware resources for executing tasks. The hardware resources include a computing unit 624 , a memory access unit 625 , and a communication unit 626 .

[0135] The hardware monitor 623 can be used to monitor the busyness of different hardware resources in the GPU. For memory access resources, the bandwidth of the main memory can be monitored. For example, the number of request bytes received within a fixed number of clock cycles. Then divided by the theoretical maximum number of request bytes that can be received, the bandwidth utilization of memory access can be obtained. For example, the theoretical bandwidth of the main memory is 10Byte / cycle (this is a hardware inherent property, so it is a constant value for a certain hardware), and a total of 500 bytes of request data are received within 1000 cycles, then the bandwidth utilization of memory access can be calculated by hardware as 500 / (10*1000)=5%. Similarly, for the operation unit / communication unit, the corresponding utilization can be calculated. For example, if the communication unit uses a PCIE communication unit, the utilization of the communication module is the bandwidth utilization of the PCIE (here it is not limited to only the PCIE communication unit). Operation units, such as ALUs, also have indicators of the amount of operations (i.e., the number of operations) that can be provided per unit time. The hardware monitor 623 can count the actual workload of a certain type of hardware resources in a certain period of time, and then divide it by the theoretical maximum workload upper limit of the hardware resources to obtain the utilization rate of the hardware resources.

[0136] The scheduler 621 needs to perform weighted round-robin to schedule the execution of thread warps in combination with the utilization of each hardware resource monitored by the hardware monitor 623. For example, the current thread warp queue has 10 thread warps, of which the task types of the last two thread warps are computationally intensive (the scheduler 621 can identify this based on the code that characterizes the task type). At this time, the hardware monitor 623 feeds back that the utilization of the computing unit 624 is 50%, and the utilization of the memory access unit 625 is 90%. Then the scheduler 621 can think that the computing unit 624 is relatively idle at this time, so the selector 622 can be used to preferentially schedule the last two computationally intensive thread warps.

[0137] The thread warp scheduling method provided by the embodiment of the present disclosure can more reasonably utilize the hardware resources inside the GPU. Otherwise, when the utilization rate of the memory access unit is very high, thread warps with heavy memory access (i.e., thread warps with memory access intensive tasks) are still allocated, which may cause the execution of the thread warp to stagnate, thereby affecting the overall processing performance of the GPU. Figure 7 A schematic diagram comparing the task execution timing of a thread warp scheduling method provided by an embodiment of the present disclosure and a polling scheduling scheme in related technologies, such as Figure 7As shown, in the polling scheduling scheme 71, the thread bundles corresponding to the memory access task 1, the thread bundles corresponding to the memory access task 2, and the thread bundles corresponding to the computing task 3 are scheduled in turn. Due to the memory bandwidth limitation, the memory access task 2 can only be executed after the memory access task 1 is completed, so that the memory access task 1, the memory access task 2, and the computing task 3 finally take 12ms to complete. However, in the thread bundle scheduling method 72 provided in the embodiment of the present disclosure, considering the memory bandwidth limitation when executing the memory access task 1, after scheduling the thread bundle corresponding to the memory access task 1, the thread bundle corresponding to the computing task 3 is preferentially scheduled, and then the thread bundle corresponding to the memory access task 2 is scheduled. In this way, the thread bundle corresponding to the computing task 3 does not need to wait for the thread bundle corresponding to the memory access task 1 to be executed, so that the memory access task 1, the memory access task 2, and the computing task 3 may be completed in 10ms. It can be seen that the thread bundle scheduling method provided in the embodiment of the present disclosure can more reasonably utilize the hardware resources inside the GPU and improve the overall performance of task processing.

[0138] It should be noted that the resource monitoring module in the aforementioned embodiment can be implemented by the aforementioned hardware monitor, and the scheduling execution module can be implemented by the aforementioned scheduler and selector.

[0139] It should be pointed out here that the description of the various embodiments above tends to emphasize the differences between the various embodiments, and the same or similar aspects can be referenced to each other. The description of the above device, graphics processor and computer equipment embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. In some embodiments, the functions or modules included in the device, graphics processor and computer equipment provided in the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments. For technical details not disclosed in the device embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure for understanding.

[0140] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned steps / processes does not mean the order of execution. The execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0141] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0142] In the several embodiments provided in the present disclosure, it should be understood that the disclosed graphics processor and method can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0143] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, the functional units in the various embodiments of the present disclosure may all be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0144] A person skilled in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, etc., various media that can store program codes.

[0145] The above description is only an implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A thread warp scheduling method, characterized in that: Applied to a graphics processor, the method comprises: Obtaining current hardware resource usage information of the graphics processor; Based on the hardware resource usage information and the task type of each warp in the warp queue to be scheduled, determining a target warp from the warp queue; the task type of each warp corresponds to the hardware resource requirement of the warp; The target warp is scheduled for execution.

2. The thread warp scheduling method according to claim 1, characterized in that: The determining a target warp from the warp queue based on the hardware resource usage information and the task type of each warp in the warp queue to be scheduled includes: Based on the hardware resource usage information, determining a target task type to be scheduled with priority from the multiple task types; A target warp is determined from at least one candidate warp in the warp queue, wherein the task type of the candidate warp is the target task type.

3. The thread warp scheduling method according to claim 2, characterized in that: The hardware resource usage information includes utilization rates of various hardware resources; The determining of a target task type to be scheduled preferentially from a plurality of task types based on the hardware resource usage information includes: Determine the target hardware resource with the lowest utilization rate among the multiple hardware resources; Based on the target hardware resources, a target task type to be scheduled with priority is determined from the multiple task types, and the hardware resource requirements corresponding to the target task type match the target hardware resources.

4. The thread warp scheduling method according to claim 3, characterized in that: The multiple hardware resources include memory access resources, computing resources, and communication resources; the multiple task types include memory access intensive, computing intensive, and communication types; The determining, based on the target hardware resources, a target task type to be scheduled preferentially from the multiple task types comprises at least one of the following: In a case where the target hardware resource is the memory access resource, determining that the type of the target task to be scheduled with priority is memory access intensive; In a case where the target hardware resource is the computing resource, determining that the type of the target task to be scheduled preferentially is computing intensive; In the case where the target hardware resource is the communication resource, it is determined that the target task type to be scheduled with priority is a communication type.

5. The thread warp scheduling method according to claim 3, characterized in that: The obtaining of the current hardware resource usage information of the graphics processor includes at least one of the following: In a case where the multiple hardware resources include memory access resources, determining the utilization rate of the memory access resources based on a maximum memory access bandwidth supported by the graphics processor and a current memory access bandwidth usage of the graphics processor; In a case where the multiple hardware resources include computing resources, determining the utilization rate of the computing resources based on a maximum amount of computing supported by the graphics processor in a single clock cycle and an actual amount of computing performed by the graphics processor in a current clock cycle; In a case where the plurality of hardware resources include communication resources, the utilization rate of the communication resources is determined based on a maximum communication bandwidth supported by the graphics processor and a current communication bandwidth usage of the graphics processor.

6. The thread warp scheduling method according to any one of claims 1 to 5, characterized in that: The method further comprises: Receive a task execution instruction, wherein the task execution instruction includes task information of a task to be executed, and the task information includes task execution parameters and a preset task type; Based on the task execution parameters, at least one new thread warp is created, and the at least one new thread warp is added to the thread warp queue; the task type of each of the new thread warps is the preset task type.

7. The thread warp scheduling method according to claim 6, characterized in that: The task type is obtained through a software interface, the current hardware resource usage information of the graphics processor is obtained through hardware monitoring, and the target thread bundle is scheduled based on the task type obtained through the software interface and the current hardware resource usage information obtained through hardware monitoring.

8. A thread warp scheduling device, characterized in that: Applied to a graphics processor, the device comprises: A resource monitoring module, used to obtain the current hardware resource usage information of the graphics processor; The scheduling and execution module is used to: determine a target thread warp from the thread warp queue based on the hardware resource usage information and the task type of each thread warp in the thread warp queue to be scheduled; the task type of each thread warp corresponds to the hardware resource requirement of the thread warp; and schedule and execute the target thread warp.

9. The thread warp scheduling device according to claim 8, characterized in that: The device also includes: A thread warp creation module is used to: receive a task execution instruction, wherein the task execution instruction includes task information of a task to be executed, wherein the task information includes task execution parameters and a preset task type; based on the task execution parameters, create at least one new thread warp, and add the at least one new thread warp to the thread warp queue; the task type of each of the new thread warps is the preset task type.

10. A graphics processor, characterized in that: It comprises the thread warp scheduling device as claimed in claim 8 or 9.

11. A computer device, characterized in that: Comprising the graphics processor of claim 10.

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