Communication method and device based on TrustZone, equipment and medium

Abstract

The invention relates to a TrustZone-based communication method and device, equipment and a medium. In the scheme, data transmission can be performed through the shared memory, efficient data communication between the TEE and the REE is realized, extra overhead in message transmission is avoided, communication efficiency and system performance are improved, and delay of data exchange is remarkably reduced; moreover, the shared memory is planned and arranged, and a pre-allocation mechanism of the data area is realized, so that the memory allocation efficiency is improved, and the system performance is improved.

Description

Technical Field

[0001] The present application relates to the field of computer security technology, and in particular to a TrustZone-based communication method, apparatus, device and medium. Background Art

[0002] With the continuous improvement of processor performance and the growing security requirements, how to improve the system's operating efficiency while ensuring data security has become an important research topic. ARM (Advanced RISC Machine, processor architecture) TrustZone technology is a system-wide security solution. TrustZone isolates all SoC (System on Chip) hardware and software resources. Its core principle is to enhance the security of the system through hardware-level isolation and protection. This technology provides security by implementing two different security domains in the ARM architecture, including the secure world and the non-secure world. The non-secure world provides a common execution environment (Rich Execution Environment, REE), and the secure world provides a trusted execution environment (Trusted Execution Environment, TEE). When REE and TEE communicate, if traditional communication methods such as message passing are used, the performance overhead is large; and using shared memory cannot allocate memory efficiently.

[0003] Therefore, how to improve the communication efficiency and system performance between REE and TEE is a problem that needs to be solved by those skilled in the art. Summary of the invention

[0004] The present application provides a TrustZone-based communication method, apparatus, device, and storage medium to improve the communication efficiency and system performance between REE and TEE.

[0005] In a first aspect, the present application provides a communication method based on TrustZone, the communication method is based on REE, and the communication method includes:

[0006] Receive data sending request sent by application;

[0007] According to the data transmission request, a target command header memory block and a target load memory block are determined from the shared memory, and target data to be transmitted is generated; wherein the shared memory includes an index data area, a command header data area, and at least one load data area corresponding to different capacities; the command header data area includes at least one command header memory block, and the load data area includes at least one load memory block of corresponding capacity; the target data includes: target index data, target command header data, and target load data;

[0008] The target index data is stored in the index data area, the target command header data is stored in the target command header memory block, the target payload data is stored in the target payload memory block, and an interrupt signal is sent to the TEE so that the TEE obtains the target data from the shared memory and stores the response data in the corresponding response payload memory block;

[0009] Receive the interrupt signal sent by the TEE, obtain the response data from the response load memory block, and send it to the application.

[0010] In a second aspect, the present application provides a communication device based on TrustZone, the communication device is based on REE, and the communication device includes:

[0011] A receiving module, used for receiving a data sending request sent by an application;

[0012] A first determination module is used to determine a target command header memory block and a target load memory block from a shared memory according to the data sending request; wherein the shared memory includes an index data area, a command header data area, and at least one load data area corresponding to different capacities; the command header data area includes at least one command header memory block, and the load data area includes at least one load memory block of corresponding capacity;

[0013] A generating module, used for generating target data to be sent; the target data includes: target index data, target command header data and target load data;

[0014] a storage module, configured to store the target index data in the index data area, store the target command header data in the target command header memory block, store the target load data in the target load memory block, and send an interrupt signal to the TEE so that the TEE obtains the target data from the shared memory and stores the response data in the corresponding response load memory block;

[0015] An acquisition module, used for receiving an interrupt signal sent by the TEE, and acquiring the response data from the response load memory block;

[0016] A sending module is used to send the response data to the application.

[0017] In a third aspect, the present application provides an electronic device, including:

[0018] A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor executes the steps of the above-mentioned communication method of the present application through the computer program.

[0019] In a fourth aspect, the present application further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the steps of the above-mentioned communication method of the present application.

[0020] The above technical solution provided by the embodiment of the present application has the following advantages over the prior art: The embodiment of the present application discloses a communication method, device, equipment and medium based on TrustZone. In this solution, data transmission can be carried out through shared memory to achieve efficient data communication between TEE and REE, avoiding the extra overhead in message transmission, improving communication efficiency and system performance, and significantly reducing the delay of data exchange; and, by planning and laying out the shared memory, the present application implements a pre-allocation mechanism for the data area, thereby improving memory allocation efficiency and system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0023] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0024] Figure 1 A schematic diagram of a system architecture provided for an embodiment of the present application;

[0025] Figure 2 A schematic diagram of a TrustZone software architecture provided for an embodiment of the present application;

[0026] Figure 3A flow chart of a communication method based on TrustZone provided in an embodiment of the present application;

[0027] Figure 4 A communication architecture diagram based on shared memory provided in an embodiment of the present application;

[0028] Figure 5 A communication flow diagram provided for an embodiment of the present application;

[0029] Figure 6 A general plan layout diagram of the shared memory provided in the embodiment of the present application;

[0030] Figure 7 A detailed planning layout diagram of the shared memory provided in the embodiment of the present application;

[0031] Figure 8 A schematic diagram of a communication device structure based on TrustZone provided in an embodiment of the present application;

[0032] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] TrustZone is a technology developed by ARM that uses hardware isolation to enhance device security. TrustZone technology provides security by implementing secure domains and non-secure domains in the ARM architecture, which is equivalent to virtualizing a physical core into two cores, a secure core (Secure Core) and a non-secure core (Non-SecureCore, NS Core). The two domains are isolated at the hardware level to ensure that data and instructions in the secure domain will not be accessed or modified by the non-secure domain. All operations that require confidentiality are performed in the secure domain (such as password processing, data encryption and decryption, etc.), and the rest of the operations are performed in the non-secure domain (such as the user's operating system, various applications, etc.).

[0034] The non-secure domain, also known as the "non-secure world", provides a universal execution environment (REE), which usually refers to an environment running a standard operating system, such as Android (mobile operating system), iOS (mobile operating system) or Linux (operating system). REE usually runs on a standard CPU (Central Processing Unit) core without additional hardware isolation features. REE is an open environment that allows users to install and run a variety of applications, but this also makes it vulnerable to malware attacks, which may lead to sensitive data leakage or abuse. REE runs client applications (CA) with low security requirements. The system and application running in REE are Rich OS and CA, respectively.

[0035] The security domain, also known as the "secure world", provides a trusted execution environment (TEE), which is an independent processing environment with computing and storage capabilities and can provide security and integrity protection. It is used to run security-critical software such as secure boot programs, encryption algorithms, and security authentication. TEE provides an isolated environment to implement secure computing based on memory isolation, ensuring that sensitive data is processed in an isolated and trusted environment and remains secure even when the main operating system (REE) is threatened. TEE runs trusted applications (TA) whose security needs to be guaranteed. The system and application running in TEE are Trusted OS and TA, respectively.

[0036] CA and TA communicate through the communication mechanism provided by ARM TrustZone, just like a client and server. Figure 1 , is a schematic diagram of a system architecture provided in an embodiment of the present application, through Figure 1 It can be seen that the ARM processor introduces a special mechanism, namely: monitor mode, which is responsible for switching between different execution environments. The non-secure core can only access non-secure system resources, but the secure core can access all resources. See Figure 2 , is a schematic diagram of a TrustZone software architecture provided in an embodiment of the present application. Figure 2 It can be seen that the security software architecture includes two areas: the secure world and the normal world. The switching between the two is achieved through a monitor. Currently, most solutions are strictly implemented based on this architecture.

[0037] The communication between TEE and REE needs to be implemented through specific interfaces and security mechanisms to ensure that sensitive data is not leaked or tampered with during transmission. Among them, Shared Memory is the most direct communication method between TEE and REE. TEE and REE can exchange data through a shared memory area. TEE and REE share a memory area through a specific hardware mechanism (such as ARM TrustZone's TZASC (TrustZone Address Space Controller). First, the shared memory is configured, such as the size of the shared memory, the physical address start position of the shared memory, etc. The application in REE sends a request to TEE through a system call or a specific interface, and writes the request data to the shared memory. After TEE reads the data in the shared memory and processes it, it writes the response data to the shared memory, and REE reads the result data from the shared memory. This method has the advantages of high efficiency and low latency. Data can be exchanged directly in memory without going through an additional transmission process. It is fast and suitable for scenarios that require fast response. However, if security control is not appropriate, malware in REE may attempt to access sensitive data in TEE, and additional hardware is required to support the division and protection of memory areas to prevent unauthorized access.

[0038] TrustZone implements task execution environments with different security levels through hardware isolation mechanisms. This mechanism is very suitable for trusted computing, payment systems, identity authentication, encryption services, secure boot, data protection and other scenarios. In the Feiteng series processors, since they use the ARM architecture, TrustZone technology can be used to build a secure and trusted operating environment. Here, the application of shared memory in the trusted computing platform based on the dual architecture is explained: In the trusted computing platform based on the dual architecture, the computing resources run in the REE environment, and the protection resources run in the TEE environment. The application in the REE writes the request command data of the trusted computing to the shared memory and sends an interrupt signal to notify the TEE. After receiving the specified interrupt signal, the program in the TEE calls the corresponding interrupt processing function. The interrupt processing function reads the trusted computing request information in the shared memory and processes it. After completing the encryption, verification or trusted measurement processing operations, it writes the response data to the shared memory and sends the specified interrupt notification REE. The REE then reads the processing results from the shared memory and sends the trusted computing processing results to the trusted computing management server.

[0039] However, in practical applications, especially in scenarios where multiple tasks are executed in parallel, data exchange and shared memory management between different security levels (between the secure world and the non-secure world) have become a challenge. Traditional memory management methods often cannot meet the needs of efficient and secure data interaction. Traditional communication methods such as message passing are secure but have high performance overhead, while simple shared memory methods are efficient but have security risks.

[0040] Therefore, the embodiments of the present application disclose a communication method, apparatus, device and storage medium based on TrustZone to improve the communication efficiency and system performance between REE and TEE, and the security of communication between REE and TEE.

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0042] The disclosure below provides many different embodiments or examples to implement different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0043] See also Figure 3 , is a flow chart of a communication method based on TrustZone provided in an embodiment of the present application, the communication method is based on REE, and the communication method includes the following steps:

[0044] S101, receiving a data sending request sent by an application;

[0045] In this application, a solution for communicating between TEE and REE through shared memory based on TrustZone technology based on Feiteng series processors is proposed. In this solution, when an application in REE needs to send data, the application needs to generate a data sending request, which carries information such as the target load data to be sent.

[0046] S102, according to the data sending request, determine the target command header memory block and the target load memory block from the shared memory, and generate the target data to be sent; wherein the shared memory includes an index data area, a command header data area, and at least one load data area corresponding to different capacities; the command header data area includes at least one command header memory block, and the load data area includes at least one load memory block of corresponding capacity; the target data includes: target index data, target command header data and target load data;

[0047] In this application, REE and TEE divide a physical address range according to the agreement as a dedicated shared memory data area, which can be accessed by TEE and REE at the same time. And configure the size and starting physical address of the shared memory data area to facilitate the subsequent mapping of physical addresses to virtual addresses when REE and TEE communicate. In addition, the memory allocation algorithm of the existing scheme does not have scientific planning and management for the shared memory data area when processing a large number of concurrent requests. The memory size is different each time, which is very easy to generate memory fragmentation and affect the memory allocation efficiency. Therefore, in this application, the shared memory is divided into multiple sub-memory areas according to the different memory sizes applied each time, including: an index data area, at least one command header data area, and at least one load data area corresponding to different capacities. Among them, the index data area is used to store the index data for communication between REE and TEE, the command header data area is used to store the command header data of communication, and the payload data area is used to store the payload data. For example: the total size of the configured shared memory is 12M, and the starting physical address is 0xFF000000, which is divided into 3 sub-memory segments, namely the index data area (4K size), the command header data area (1020K size), and the payload data area (11M size).

[0048] Among them, the command header data area in the present application includes multiple command header memory blocks, the number of load data areas in the present application is multiple, and the sizes of load memory blocks in different load data areas are different. The present application can predict the size of common memory blocks by analyzing typical application scenarios, and pre-allocate a certain number of small, medium, and large load memory blocks when the system starts, so that when allocating memory, the existing pre-allocated load memory blocks of appropriate size can be used. For example: the present application divides the load data area into: 4K load data area, 8K load data area, 16K load data area, 32K load data area, 64K load data area, 128K load data area, 256K load data area, 512K load data area, and load data areas of different capacities include multiple load memory blocks of the capacity, for example: a 4K load data area includes 256 4K load memory blocks.

[0049] After receiving the data sending request sent by the application, the present application first needs to apply for memory, including a target command header memory block for storing the target command header data, and a target load memory block for storing the target load data; wherein, when applying for the target load memory block, it can be directly allocated and used in the corresponding memory load data area according to the size of the memory block to be applied for, which effectively reduces the situation of memory fragmentation. After the present application allocates the target command header memory block and the target load memory block to the data sending request, it is necessary to generate target data, and the target data includes target index data, target command header data and target load data, wherein the target index data includes the physical address of the target command header memory block, and the target command header data includes the physical address of the target load memory block and the physical address of the response load memory block.

[0050] S103, storing the target index data in the index data area, storing the target command header data in the target command header memory block, storing the target payload data in the target payload memory block, and sending an interrupt signal to the TEE so that the TEE obtains the target data from the shared memory and stores the response data in the corresponding response payload memory block;

[0051] After the present application determines the target index data, target command header data and target load data, they need to be stored in the corresponding data areas of the shared memory respectively, that is: the target index data is stored in the index data area, the target command header data is stored in the target command header memory block in the command header data area, the target load data is stored in the target load memory block in the load data area, and an interrupt signal is sent to the TEE.

[0052] See also Figure 4 , is a diagram of a communication architecture based on shared memory provided in an embodiment of the present application, Figure 4 It can be seen that after REE stores the target data in the shared memory through the communication driver module, TEE first obtains the index data from the index data area, obtains the target command header data according to the physical address of the target command header memory block recorded in the index data, obtains the physical address of the target load memory block from the target command header data, and obtains the target load data from the target load memory block; after processing the target load data to generate response data, it is also necessary to store the response data in the corresponding response load memory block according to the physical address of the response data memory block recorded in the target command header data.

[0053] S104, receiving the interrupt signal sent by TEE, obtaining the response data from the response load memory block, and sending it to the application.

[0054] In this application, after TEE stores the response data in the corresponding response payload memory block, it sends an interrupt signal to REE. After receiving the interrupt signal, REE obtains the response data from the response payload memory block and sends it to the application.

[0055] In summary, in this solution, data can be transmitted through shared memory to achieve efficient data communication between TEE and REE, avoid additional overhead in message passing, improve communication efficiency and system performance, and significantly reduce data exchange delays; and, this application plans and lays out shared memory to implement a pre-allocation mechanism for data areas, thereby improving memory allocation efficiency and improving system performance.

[0056] In another embodiment of the present application, generating target data to be sent includes:

[0057] Generate target index data using the index data protocol, generate target command header data using the command header data protocol, and generate target payload data using the payload data protocol;

[0058] Among them, the target index data includes the physical address of the target command header memory block, the target command header data includes the physical address of the target load memory block, and the physical address of the response load memory block, so that TEE obtains the target command header data according to the physical address of the target command header memory block in the target index data, obtains the target load data according to the physical address of the target load memory block in the target command header data, and stores the response data according to the physical address of the response load memory block in the target command header data.

[0059] In this application, a set of secure communication protocols is disclosed to standardize the format, timing and verification mechanism of data transmission between TEE and REE through shared memory data area. This application involves three communication data structures, including index data area protocol, command header data protocol and load data protocol. These three protocols are described here respectively:

[0060] 1. The index data protocol includes the following main functional fields:

[0061] Command type: indicates the type of command sent by REE to TEE, which can be either synchronous communication or asynchronous communication.

[0062] Command content length: indicates the size of the command header data.

[0063] Command serial number: The serial number corresponding to each command, which is used in increments.

[0064] Command header address: During this communication, the physical address of the command header memory block filled with command header data. Command header data is applied for in units of 4K.

[0065] Command processed flag: A value of 0 indicates that the command data sent by REE to TEE has not been processed by the TEE program.

[0066] Command return value: indicates the return value of success or failure in the subsequent execution process after the TEE program receives the data.

[0067] 2. The command header data protocol includes the following main function fields:

[0068] Input data address: indicates the physical address of the input data, which is the physical address of the target load memory block. The target load memory block is used to store the target load data sent by REE to TEE.

[0069] Input data length: indicates the size of the payload data sent by REE to TEE.

[0070] Output data address: indicates the physical address assigned by REE to TEE, which is the physical address of the response load memory block. The response load memory block is used to store the response load data returned by TEE to REE.

[0071] Output data length: indicates the size of the response payload data returned by TEE to REE.

[0072] Command return value: indicates the return value of success or failure in the subsequent execution process after the TEE program receives the data.

[0073] 3. The payload data protocol includes the following main functional fields:

[0074] Command tag: Data identifier, indicating whether it is data sent by REE to TEE or data sent by TEE to REE.

[0075] Command data length: indicates the total size of the payload data.

[0076] Command code: Command identifier, used to distinguish command types for performing different operations.

[0077] Other valid data: other valid data that the operation command needs to carry, such as configuration data sent by REE to TEE.

[0078] Therefore, when generating data, the present application needs to use the index data protocol to generate target index data, use the command header data protocol to generate target command header data, and use the load data protocol to generate target load data.

[0079] In some embodiments of the present application, in order to ensure the security and integrity of data in shared memory, data is transmitted between REE and TEE through a verification mechanism; the verification mechanism includes a data encryption and decryption mechanism and / or a signature verification mechanism. The present application can ensure the confidentiality and integrity of the transmitted data through a verification mechanism. For example: before the present application stores the target data in the shared memory, it is necessary to perform encryption and signing operations on the target data, and then store it in the shared memory; after obtaining the target data, the TEE needs to decrypt and verify the target data. If the verification is successful, the subsequent process will continue to be executed. If the verification fails, it means that the data may be tampered with; similarly, after the TEE performs encryption and signing operations on the response payload data, it is stored in the shared memory. After the REE obtains the response payload data from the shared memory, it decrypts and verifies the response data. If the verification is successful, the subsequent process will continue to be executed. If the verification fails, it means that the data may be tampered with.

[0080] In addition, the present application can notify the other party that the entity data is available or the request is completed through two methods: the corresponding field mark of the communication protocol and the soft interrupt mechanism. For example, after REE stores the target data in the shared memory, it sends an interrupt signal to TEE; after TEE stores the response payload data in the shared memory, it sends an interrupt signal to REE; or, after TEE stores the response payload data in the shared memory, it can set the data processing mark in the shared memory to processed. After REE detects that the data processing mark is set to processed, it can read the response payload data from the shared memory.

[0081] See also Figure 5 , which is a communication process diagram provided in an embodiment of the present application. It can be seen that the process includes the following steps: the non-secure world REE application sends data to the secure world TEE through the driver, the REE writes the data to the shared memory area through the driver, and the REE notifies the TEE that the data is available through the interrupt mechanism; after the TEE receives the interrupt, the corresponding encryption and decryption operations are performed through the interrupt processing function driven by the TEE, and the TEE writes the returned data back to the shared memory area and sets the data processing mark to processed. The REE driver learns that the returned data is available by polling the data processing mark in the shared memory, reads the returned data from the shared memory area, clears the data processing mark, and returns the returned data to the corresponding application.

[0082] In summary, this application can standardize the format, timing and verification mechanism of data transmission between TEE and REE through the shared memory data area through the three communication protocols of index data area protocol, command header data protocol and payload data protocol; and, this application can encrypt the data in the shared memory area through the encryption and decryption mechanism, and ensure the integrity of the data and the authenticity of the source through the signature verification mechanism, thereby ensuring the security of data communication.

[0083] In another embodiment of the present application, before receiving the data sending request sent by the application, the following operations are also included:

[0084] Determine the physical address segment of the shared memory; map the physical address segment to the virtual address segment; divide the virtual address segment into an index data area, at least one command header data area, and at least one load data area corresponding to different capacities; initialize a one-dimensional usage status array of the command header data area, a two-dimensional usage status array of the load data area, and the next available command header memory block index value, and the next available load memory block index value corresponding to different capacities.

[0085] In this application, during the driver initialization process, the configured shared memory physical address segment is pre-mapped to a virtual memory segment to reduce the overhead of dynamic allocation. Every time the REE-side program applies for memory to communicate with TEE, it calls the memory allocation interface and directly finds the corresponding free memory address from the virtual memory segment for use. After the communication is completed, the memory recycling interface is called to release the memory address segment. Inside the memory allocation and recycling interface, a data tag is used to indicate whether the current memory address is in use or in idle state. See Figure 6 , which is a general plan layout diagram of the shared memory provided in the embodiment of the present application, see Figure 7 , which is a detailed planning layout diagram of the shared memory provided by the embodiment of the present application. The present application can divide a specific area in the physical memory of the Feiteng processor as the shared memory of the secure world and the non-secure world. The configuration parameters include: the starting physical address of the shared memory, the size of the shared memory, when the communication driver is initialized, a virtual address is mapped from the shared memory physical address for use, the starting virtual address and size of the index data area are set, the starting virtual address and size of the command header data area are set, the total starting virtual address and size of the load data area are set, and the starting virtual address and size of the memory block areas of different sizes in the load data area are set.

[0086] like Figure 6 and Figure 7 As shown, a planning layout diagram is set up by taking a 12-megabyte shared memory as an example. The shared memory includes an index data area, a command header data area, and a payload data area. The memory capacity of the index data area is 4K, and the total memory capacity of the command header data area is 1020K, including 255 command header data areas of 4K unit size. The total memory capacity of the payload data area is 11M, including 256 payload data areas of 4K unit size, 128 payload data areas of 8K unit size, 64 payload data areas of 16K unit size, 32 payload data areas of 32K unit size, 16 payload data areas of 64K unit size, 8 payload data areas of 128K unit size, 8 payload data areas of 256K unit size, and 6 payload data areas of 512K unit size.

[0087] The initialization process of the command header data area in this application is as follows: initialize the next available command header memory block index value to the index value of the last command header memory block, for example: the command header data area of ​​1020K is composed of 255 command header memory blocks of 4K, and the index values ​​corresponding to each command header memory block are 0, 1, 2...254. Then the index value of the next available command header memory block is 254, and initialize a one-dimensional usage status array containing 255 elements to save the usage status of each command header memory block.

[0088] The initialization process of the load data area in this application is as follows: initialize a 1-dimensional array containing n elements to save the next available load memory block index value in the load data area of ​​n capacity; wherein n represents the total number of load data areas of different capacity, for example: the load data area includes: 4K load data area, 8K load data area, 16K load data area, 32K load data area, 64K load data area, 128K load data area, 256K load data area and 512K load data area, then n is 8, at this time, it is necessary to initialize a 1-dimensional array containing 8 elements, and initialize the index value of the next available load memory block of each capacity to the index value of the last load memory block in the load data area of ​​the capacity, that is, when allocating memory, it is allocated in order from back to front. For example: a 1M load data area includes 128 8K load memory blocks, and the index values ​​corresponding to each load memory block are 0, 1, 2...127 respectively. Then the index value of the next available load memory block is 127. Then initialize a 2-dimensional array to save the usage status of each load memory block in the load data area of ​​different capacities. The number of the first dimension of the array is n, which represents the load data area of ​​different capacities. The value of the second dimension of the array is the number of load memory blocks of the load data area of ​​the corresponding capacity. For example, a 1M load data area can be divided into 256 load memory blocks according to the 4K unit size, and can be divided into 128 load memory blocks according to the 8K unit size, and so on.

[0089] In another embodiment of the present application, the process of determining the target command header memory block and the target load memory block from the shared memory according to the data sending request specifically includes: using the next available command header memory block index value to determine the first starting virtual address of the target command header memory block from the shared memory, and converting the first starting virtual address to the physical address of the target command header memory block; determining the required capacity value of the data sending request, and determining the target capacity of the corresponding load data area according to the required capacity value; using the next available load memory block index value corresponding to the target capacity, determining the second starting virtual address of the target load memory block from the shared memory, and converting the second starting virtual address to the physical address of the target load memory block.

[0090] Correspondingly, after the present application determines the target command header memory block and the target load memory block from the shared memory, it is also necessary to update the usage status of the target command header memory block in the one-dimensional usage status array of the command header data area to in use, and determine the next available command header memory block index value; update the usage status of the target load memory block in the two-dimensional usage status array of the load data area to in use, and determine the next available load memory block index value.

[0091] Specifically, when allocating a command header memory block, the present application can determine the target command header memory block according to the next available command header memory block index value, and set the state value corresponding to the index value in the one-dimensional usage state array to -2 (-2 means in use, and other values ​​mean idle). The virtual address of the target command header memory block can be calculated through the index value and the starting virtual address of the command header data area. In the present application, the virtual address of the target command header memory block is referred to as the first virtual address, and then the first virtual address is converted into a physical address and returned to the memory applicant for use. For example: the starting virtual address of the command header data area plus the index value multiplied by the capacity of each command header memory block (4K) is the requested virtual address. Furthermore, it is also necessary to update the index value of the next available command header memory block to the index value of the previous command header memory block.

[0092] When allocating a load memory block, the application first determines the required capacity value of the data transmission request, and determines the target capacity of the corresponding load data area according to the required capacity value; for example: if the required capacity value is 7K, the target capacity of the determined load data area is 8K, that is, the load memory block in the 8K load data area needs to be allocated to store data. Then, the target load memory block is determined according to the next available load memory block index value corresponding to the target capacity. And the state value of the element corresponding to the index value in the two-dimensional usage status array is set to -2. The virtual address of the target load memory block can be calculated through the index value and the starting virtual address of the load data area. In this application, the virtual address of the target load memory block is called the second virtual address, and then the second virtual address is converted into a physical address and returned to the memory applicant for use. For example: the starting virtual address of the load data area with a target capacity of 8K units, plus the index value multiplied by the size of each load memory block (8K), is the second virtual address returned by the application, and the next available load memory block index value in the 1-dimensional array is updated to the index of the previous load memory block.

[0093] In another embodiment of the present application, after obtaining response data from the response load memory block and sending it to the application, it also includes: treating the target command header memory block and the target load memory block as memory blocks to be released, and performing a memory release operation on the memory block to be released; updating the usage status of the target command header memory block in the one-dimensional usage status array of the command header data area to idle, and using the index value of the target command header memory block as the next available command header memory block index value; updating the usage status of the target load memory block in the two-dimensional usage status array of the load data area to idle, and using the index value of the target load memory block as the next available load memory block index value corresponding to the target capacity.

[0094] In this application, after the communication between TEE and REE is completed, the corresponding command header memory block or load memory block needs to be released through the memory recovery mechanism. Among them, there are two general memory recovery mechanisms: one is to explicitly provide an interface for memory allocation and memory release, and the programmer explicitly performs memory allocation and release operations. The advantages of this solution are simple design, high system operation efficiency, and good stability, but it may cause memory resource leakage due to the negligence of programmers; the other is an automatic memory recovery mechanism, such as an automatic garbage collection mechanism based on reference counting, which uses periodic inspection to identify memory areas that are no longer used and release them in time, which can reduce the risk of memory leakage, but at the cost of increasing the complexity and instability of system design. In this application, the designer can explicitly perform memory allocation and release operations.

[0095] Among them, when a command header memory block needs to be released, the index value of the command header memory block to be released is obtained by calculating the difference between the virtual address of the passed-in command header memory block and the starting virtual address of the command header data area, and then dividing it by the size of each memory block in the command header data area, and the state value of the element of the one-dimensional usage state array corresponding to the index value is updated to the available state, and the index value of the next available load memory block is updated to the index value.

[0096] When a load memory block needs to be released, the index value of the load memory block to be released is obtained by calculating the difference between the virtual address of the incoming load memory block and the starting virtual address of the load data area, and then dividing it by the size of each load memory block in the load data area. The status value of the element of the two-dimensional usage status array corresponding to the index value is updated to the available status, and the next available load memory block index value in the one-dimensional array is updated to the index value.

[0097] In summary, this application proposes a solution based on the Feiteng series processors and TrustZone technology to use shared memory to communicate between TEE and REE, including the design of communication protocols, shared memory planning, shared memory allocation, shared memory use, shared memory recycling and other links. This solution can improve the efficiency and flexibility of communication between the secure world and the non-secure world, while reducing the consumption of system resources during the communication process.

[0098] In order to clearly illustrate this solution, a specific embodiment is provided here:

[0099] 1. The memory address allocation and release process of the command header data area:

[0100] This solution is a shared memory management method suitable for scenarios that require efficient allocation and release of memory blocks of the same size. In this solution, the size of each memory block is 4KB.

[0101] The specific steps include:

[0102] 1. Memory area configuration:

[0103] Define the total size of the command header data area CMD_HEADER_AREA_SIZE to 1020KB.

[0104] Define each command header buffer size BUF_SIZE as 4KB.

[0105] Calculate the number of command header buffers CMD_BUFFER_NUMBER as

[0106] CMD_HEADER_AREA_SIZE / BUF_SIZE.

[0107] 2. Data structure definition:

[0108] short cmd_headers[CMD_BUFFER_NUMBER]: integer array used to store the status or index value of each command header buffer.

[0109] int cmd_next: An integer variable that initially points to the last memory block index and is used to track the next available command header index.

[0110] struct cmd_header*cmd_header_base: pointer to the virtual address base address of the command header buffer.

[0111] 3. Initialization method:

[0112] Initialize the command header buffer in shared memory to the base address of the virtual memory.

[0113] Use a loop to initialize the cmd_headers array, setting each element to its index minus one to form the initial free list.

[0114] Set cmd_next to the index of the last element.

[0115] 4. Command header memory address allocation method:

[0116] If cmd_next is not equal to -1, it means there is a free command header buffer.

[0117] Get the index index of the next allocatable command header buffer.

[0118] Update cmd_next to point to the next free command header buffer.

[0119] Mark cmd_headers[index] as in use (set to -2).

[0120] Returns a pointer to the newly allocated command header (through pointer arithmetic, returns the address of cmd_header_base plus index multiplied by BUF_SIZE, that is, the address pointer pointing to the newly allocated command header).

[0121] 5. Command header memory address release method:

[0122] By calculating the offset between the passed command header pointer and cmd_header_base, the index of the released command header is determined.

[0123] Verify that cmd_headers[index] is marked as in use (equal to -2).

[0124] If the verification passes, set cmd_headers[index] to the idle state (set to cmd_next).

[0125] Update cmd_next to index, indicating that the next allocatable command header buffer is the currently released command header.

[0126] Here, the memory address allocation and release process of the command header data area is specifically described. For example, the command header data area includes 255 4K memory blocks.

[0127] Define a one-dimensional array: short cmd_headers

[255] ; save the usage status or index information of each command header memory block.

[0128] 1) Initialization:

[0129] The values ​​of cmd_headers

[255] are initialized to:

[0130] -1 0 1 2 3 4 5.....253

[0131] The value of cmd_next is initialized to: 254, which represents the index of the next available memory block.

[0132] 2) The algorithm for allocating the command header memory block for the first time: find the next available index, and convert it into the virtual address of the corresponding memory block based on the index and the command header memory block virtual address base address.

[0133] Set index = cmd_next value, which is 254;

[0134] Set the value of cmd_next to the value of cmd_headers[index], which is 253;

[0135] Set cmd_headers[index] = -2; that is, cmd_headers

[254] = -2; -2 is the status that has been used.

[0136] The virtual address of the allocated command header memory block is obtained through cmd = (struct cmd_header*)(base+index*BUF_SIZE). It is returned to the caller for use. BUF_SIZE is the size of the memory block, 4K.

[0137] 3) The algorithm for releasing the first command header memory block:

[0138] By entering the header parameter (the virtual address of the command header memory block to be released), the corresponding index is calculated according to this method: index = ((unsigned long) header - (unsigned long) cmd_header_base) / BUF_SIZE;

[0139] Determine whether the memory block corresponding to the index (254) is in use: if (cmd_headers[index]!=-2), if it is in use, proceed to the next step;

[0140] Set cmd_headers[index] = cmd_next; i.e. cmd_headers

[254] = 253;

[0141] Set cmd_next = index; that is, cmd_next = 254;

[0142] 2. The algorithm process of allocating and releasing the memory address of the load data:

[0143] This solution is a shared memory management method, which is particularly suitable for scenarios that require efficient allocation and release of memory blocks of different sizes. The idea of ​​this solution is the same as that of the command header memory address allocation algorithm. The difference is that the array that saves the state of each memory address of the command header is a one-dimensional array, and this algorithm uses a two-dimensional array. Because the size of each command header memory block is the same, all are 4K, and the size of each load data area memory block is different, this embodiment plans different sizes of 4K, 8K, 16K and other load data areas for it.

[0144] The specific steps include:

[0145] 1. Initialization method:

[0146] First, a virtual memory is mapped out according to the physical address start address of the configured shared memory and the size of the shared memory. Subsequent memory allocation, memory use and memory release are all based on this virtual memory. Then, according to the offset and size of each load data area, the start virtual address and end virtual address of the load data area are calculated respectively.

[0147] Initialize the index value corresponding to the next available free load memory block in each load data area of ​​different unit size, and save the index value in a 1D array. In this application, 12M shared memory corresponds to a 1D array of 8 elements.

[0148] Initialize a two-dimensional usage status array to save the usage status information of each memory block in each load data area. -2 means that the memory block has been allocated and used, and other values ​​mean that the memory block is free and can be allocated for use.

[0149] 2. Allocation algorithm of memory blocks in the payload data area:

[0150] First, according to the size of the memory block to be allocated, a legality check is performed to determine whether it is within the range of the pre-allocated memory block sizes. If it is within a reasonable range, the next step is executed. According to the size of the memory block to be allocated, determine which load data area it belongs to, such as the load data area of ​​4K units, the inner load data area of ​​8K units, etc. For example: if you want to allocate a 7K memory block, you should allocate it in the 8K load data area.

[0151] The following example uses the allocation of a 7K memory block as an example. In the 1D array corresponding to the 8K load data area, find the index corresponding to the next available free load memory block, and set the status information corresponding to the load memory block in the 2D usage status array to -2, indicating that it is already in use. Then, based on the index value corresponding to the next available free load memory block, calculate the corresponding virtual memory address in the mapped virtual memory (the offset of the 8K load data area is returned through pointer arithmetic, plus the address after the index value is multiplied by the unit memory size (8K), that is, the address pointer pointing to the newly allocated load data memory block).

[0152] 3. Release algorithm of the memory block in the payload data area:

[0153] First, based on the address of the incoming load memory block to be released, determine whether the address is within the range of the starting virtual address and the ending virtual address of the load data area that have been set in the initialization method. Only if it is within the range will the next step be executed.

[0154] According to the incoming address and the offset of each load data area, it can be calculated which data area of ​​the 8 load data areas the address belongs to. For example: it belongs to the 4K load data area, the 8K load data area or the 16K load data area, etc. Subtract the starting address of the load data area from the incoming address, and then divide it by the size of each memory block (such as 4K, 8K, etc.), you can get the index value of which memory block the incoming address belongs to. Through this index value, it is determined whether the corresponding state saved in the two-dimensional array is -2, indicating a used state. If so, the next step of release operation is performed, otherwise an error state is returned.

[0155] The element corresponding to the index value of the load data area of ​​the two-dimensional usage status array is set to an idle state. The index value corresponding to the next available free memory block is updated to the index value of the currently released memory block. In addition, the application implements the initialization interface, allocation interface and release interface of the memory block respectively, which are used to implement the initialization operation, memory allocation operation and memory release operation of the shared memory, and are explicitly called by the developer.

[0156] From the above, it can be seen that due to the problem that traditional TrustZone communication technology cannot meet the needs of efficient and secure data interaction, this application uses shared memory as the basis for data exchange, realizes scientific planning and layout of shared memory data areas, realizes memory address area pre-allocation mechanism, realizes a set of secure communication protocols, realizes efficient shared memory allocation and recovery algorithm, and realizes data signature verification mechanism, thereby significantly improving the communication efficiency and security between REE and TEE. Specifically, this application can effectively improve the efficiency and security of Feiteng processors' shared memory data area communication in the TrustZone environment, which is mainly reflected in the following aspects:

[0157] 1. Improve communication efficiency: Data is transmitted through a shared memory data area, which enables efficient data communication between TEE and REE, avoids additional overhead in message passing, improves communication efficiency and system performance, and significantly reduces data exchange delays.

[0158] 2. Enhanced security: Through the isolation mechanism of hardware components such as TZASC, combined with security mechanisms such as encryption and signing, the confidentiality and integrity of data transmission are ensured.

[0159] 3. Flexibility and scalability: The configuration of the communication protocol and the shared memory data area can be flexibly adjusted according to specific needs, such as modifying the size of the shared memory data area, modifying the starting physical address of the shared memory data area, etc. In addition, the communication protocol can support multiple types of data and commands.

[0160] 4. Improved memory utilization: Improved memory utilization and reduced memory fragmentation problems.

[0161] 5. Rich support scenarios: Supports a variety of communication scenarios, such as trusted computing, security authentication, data encryption, etc.

[0162] 6. Simple implementation and deployment: easy to implement and deploy, suitable for various ARM processors.

[0163] See also Figure 8 , Figure 8 A schematic diagram of a communication device structure based on TrustZone provided in an embodiment of the present application, the communication device is based on REE and specifically includes:

[0164] A receiving module 11 is used to receive a data sending request sent by an application;

[0165] The first determination module 12 is used to determine the target command header memory block and the target load memory block from the shared memory according to the data sending request; wherein the shared memory includes an index data area, a command header data area, and at least one load data area corresponding to different capacities; the command header data area includes at least one command header memory block, and the load data area includes at least one load memory block of corresponding capacity;

[0166] The generating module 13 is used to generate target data to be sent; the target data includes: target index data, target command header data and target load data;

[0167] The storage module 14 is used to store the target index data in the index data area, store the target command header data in the target command header memory block, store the target load data in the target load memory block, and send an interrupt signal to the TEE so that the TEE obtains the target data from the shared memory and stores the response data in the corresponding response load memory block;

[0168] An acquisition module 15, configured to receive an interrupt signal sent by the TEE and acquire the response data from the response load memory block;

[0169] The sending module 16 is used to send the response data to the application.

[0170] As an optional embodiment, the device further includes:

[0171] A second determination module is used to determine the physical address segment of the shared memory;

[0172] A mapping module, used for mapping the physical address segment into a virtual address segment;

[0173] A partitioning module, used for partitioning the virtual address segment into an index data area, at least one command header data area, and at least one load data area corresponding to different capacities;

[0174] An initialization module is used to initialize the one-dimensional usage status array of the command header data area, the two-dimensional usage status array of the load data area, the next available command header memory block index value, and the next available load memory block index value corresponding to different capacities.

[0175] As an optional embodiment, the first determining module includes:

[0176] A first address determining unit, configured to determine a first starting virtual address of a target command header memory block from a shared memory by using a next available command header memory block index value;

[0177] A first conversion unit, configured to convert the first starting virtual address into a physical address of the target command header memory block;

[0178] a capacity determination unit, configured to determine a required capacity value of the data transmission request, and determine a target capacity of a corresponding payload data area according to the required capacity value;

[0179] A second address determining unit, configured to determine a second starting virtual address of a target load memory block from the shared memory using a next available load memory block index value corresponding to the target capacity;

[0180] A second conversion unit is configured to convert the second starting virtual address into a physical address of the target load memory block.

[0181] As an optional embodiment, the device further includes:

[0182] A first updating module, configured to update the usage status of the target command header memory block in the one-dimensional usage status array of the command header data area to in use, and determine a next available command header memory block index value;

[0183] The second updating module is used to update the usage status of the target load memory block in the two-dimensional usage status array of the load data area to in use, and determine the next available load memory block index value.

[0184] As an optional embodiment, the device further includes:

[0185] A release module, used for taking the target command header memory block and the target load memory block as memory blocks to be released, and performing a memory release operation on the memory blocks to be released;

[0186] A third updating module is used to update the usage status of the target command header memory block in the one-dimensional usage status array of the command header data area to idle, and use the index value of the target command header memory block as the next available command header memory block index value;

[0187] The fourth update module is used to update the usage status of the target load memory block in the two-dimensional usage status array of the load data area to idle, and use the index value of the target load memory block as the next available load memory block index value corresponding to the target capacity.

[0188] As an optional embodiment, data is transmitted between the REE and the TEE through a verification mechanism; the verification mechanism includes a data encryption and decryption mechanism and / or a signature verification mechanism.

[0189] As an optional embodiment, the generating module is specifically used to: generate target index data using an index data protocol, generate target command header data using a command header data protocol, and generate target load data using a load data protocol;

[0190] Among them, the target index data includes the physical address of the target command header memory block, the target command header data includes the physical address of the target load memory block, and the physical address of the response load memory block, so that TEE obtains the target command header data according to the physical address of the target command header memory block in the target index data, obtains the target load data according to the physical address of the target load memory block in the target command header data, and stores the response data according to the physical address of the response load memory block in the target command header data.

[0191] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0192] See also Fig. 9 , Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application, the electronic device specifically includes:

[0193] The processor 21, the memory 22 and the computer program stored in the memory 22 and executable on the processor 21, the processor 21 executes the steps of the communication method described in any of the above method embodiments through the computer program.

[0194] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0195] The memory 22 may include one or more computer-readable storage media, which may be non-transitory. The memory 22 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 22 is at least used to store the following computer program 221, wherein, after the computer program is loaded and executed by the processor 21, it can implement the relevant steps in the communication method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 22 may also include an operating system 222 and data 223, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 222 may include Windows, Unix, Linux, etc.

[0196] In some embodiments, the electronic device may further include a display screen 23 , an input / output interface 24 , a communication interface 25 , a sensor 26 , a power source 27 , and a communication bus 28 .

[0197] certainly, Fig. 9 The structure of the electronic device shown does not constitute a limitation on the electronic device in the embodiments of the present application. In actual applications, the electronic device may include Fig. 9 More or fewer components than shown, or combinations of certain components.

[0198] In another exemplary embodiment, a computer storage medium is also provided, and when the program instructions are executed by a processor, the steps of the communication method described in any of the above method embodiments are implemented. The storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0199] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments, and this embodiment will not be described in detail here.

[0200] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0201] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A communication method based on TrustZone, characterized in that: The communication method is based on REE, and the communication method includes: Receive data sending request sent by application; According to the data transmission request, a target command header memory block and a target load memory block are determined from the shared memory, and target data to be transmitted is generated; wherein the shared memory includes an index data area, a command header data area, and at least one load data area corresponding to different capacities; the command header data area includes at least one command header memory block, and the load data area includes at least one load memory block of corresponding capacity; the target data includes: target index data, target command header data, and target load data; The target index data is stored in the index data area, the target command header data is stored in the target command header memory block, the target payload data is stored in the target payload memory block, and an interrupt signal is sent to the TEE so that the TEE obtains the target data from the shared memory and stores the response data in the corresponding response payload memory block; Receive the interrupt signal sent by the TEE, obtain the response data from the response load memory block, and send it to the application.

2. The communication method according to claim 1, characterized in that: Before receiving the data sending request sent by the application, it also includes: Determine the physical address segment of the shared memory; Mapping the physical address segment to a virtual address segment; Dividing the virtual address segment into an index data area, at least one command header data area, and at least one load data area corresponding to different capacities; Initialize the one-dimensional usage status array of the command header data area, the two-dimensional usage status array of the load data area, the next available command header memory block index value, and the next available load memory block index value corresponding to different capacities.

3. The communication method according to claim 2, characterized in that: According to the data sending request, determining a target command header memory block and a target load memory block from a shared memory includes: Determine a first starting virtual address of a target command header memory block from a shared memory using a next available command header memory block index value, and convert the first starting virtual address into a physical address of the target command header memory block; Determine a required capacity value of the data transmission request, and determine a target capacity of a corresponding payload data area according to the required capacity value; A second starting virtual address of the target load memory block is determined from the shared memory using a next available load memory block index value corresponding to the target capacity, and the second starting virtual address is converted into a physical address of the target load memory block.

4. The communication method according to claim 3, characterized in that: After determining the target command header memory block and the target load memory block from the shared memory, it also includes: Update the usage status of the target command header memory block in the one-dimensional usage status array of the command header data area to in use, and determine the next available command header memory block index value; The usage status of the target load memory block in the two-dimensional usage status array of the load data area is updated to in use, and the next available load memory block index value is determined.

5. The communication method according to claim 3, characterized in that: After obtaining the response data from the response payload memory block and sending it to the application, the method further includes: The target command header memory block and the target load memory block are used as memory blocks to be released, and a memory release operation is performed on the memory blocks to be released; Update the usage status of the target command header memory block in the one-dimensional usage status array of the command header data area to idle, and use the index value of the target command header memory block as the next available command header memory block index value; The usage status of the target load memory block in the two-dimensional usage status array of the load data area is updated to idle, and the index value of the target load memory block is used as the next available load memory block index value corresponding to the target capacity.

6. The communication method according to claim 1, characterized in that: The communication method further comprises: The REE and the TEE transmit data via a verification mechanism; the verification mechanism includes a data encryption and decryption mechanism and / or a signature verification mechanism.

7. The communication method according to any one of claims 1 to 6, characterized in that: The generating of target data to be sent includes: Generate target index data using the index data protocol, generate target command header data using the command header data protocol, and generate target payload data using the payload data protocol; Among them, the target index data includes the physical address of the target command header memory block, the target command header data includes the physical address of the target load memory block, and the physical address of the response load memory block, so that TEE obtains the target command header data according to the physical address of the target command header memory block in the target index data, obtains the target load data according to the physical address of the target load memory block in the target command header data, and stores the response data according to the physical address of the response load memory block in the target command header data.

8. A communication device based on TrustZone, characterized in that: The communication device is based on REE, and the communication device includes: A receiving module, used for receiving a data sending request sent by an application; A first determination module is used to determine a target command header memory block and a target load memory block from a shared memory according to the data sending request; wherein the shared memory includes an index data area, a command header data area, and at least one load data area corresponding to different capacities; the command header data area includes at least one command header memory block, and the load data area includes at least one load memory block of corresponding capacity; A generating module, used for generating target data to be sent; the target data includes: target index data, target command header data and target load data; a storage module, configured to store the target index data in the index data area, store the target command header data in the target command header memory block, store the target load data in the target load memory block, and send an interrupt signal to the TEE so that the TEE obtains the target data from the shared memory and stores the response data in the corresponding response load memory block; An acquisition module, used for receiving an interrupt signal sent by the TEE, and acquiring the response data from the response load memory block; A sending module is used to send the response data to the application.

9. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor executes the steps of the communication method described in any one of claims 1 to 7 of the present application through the computer program.

10. A computer storage medium, characterized in that: The computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the steps of the communication method described in any one of claims 1 to 7 of the present application.

Images