A method and device for intelligent recognition server configuration and adaptive configuration of PCIe bandwidth

Abstract

The present invention relates to a method and device for configuring an intelligent recognition server and adaptively configuring PCIe bandwidth. The method includes the following steps: configuring the wiring mode between the I / O expander and the on-board PCIE slot in each server expansion card connected to the server motherboard; starting the server power supply, after the baseboard management controller is initialized, obtaining the register values of the I / O expander on each server expansion card through the IIC communication protocol; the baseboard management controller sending the register values of all I / O expanders to the complex programmable logic device; the complex programmable logic device sending the register values of all I / O expanders to the central processing unit of the server through the vGPIO communication protocol; based on the register values of the I / O expander, the basic input / output system allocates bandwidth and resources to the on-board PCIE slots in each server expansion card. The present invention can both reduce the number of general server boards and adaptively configure PCIe bandwidth, reducing the probability of errors.

Description

Technical Field

[0001] The present invention belongs to the field of servers, and particularly relates to a method and device for intelligently identifying server configurations and adaptively configuring PCIe bandwidth. Background Art

[0002] With the development of the digital economy, while the market share of servers is increasing, the increasingly diverse configuration requirements of servers also pose huge challenges to server manufacturers. Traditional server manufacturers often adopt the solutions of customizing servers or adding various daughter cards on general server motherboards for various configurations, which often involves a large amount of design costs. In addition, multiple configurations also bring higher complexity to the operations of production lines and customers, increasing the probability of errors. Summary of the Invention

[0003] The present invention provides a method and device for intelligently identifying server configurations and adaptively configuring PCIe bandwidth, aiming to solve at least one of the technical problems existing in the prior art.

[0004] The technical solution of the present invention relates to a method for intelligently identifying server configurations and adaptively configuring PCIe bandwidth, which is applied to a device for intelligently identifying server configurations and adaptively configuring PCIe bandwidth. The device for intelligently identifying server configurations and adaptively configuring PCIe bandwidth includes: a server expansion card (Riser card), the server expansion card (Riser card) is installed on the motherboard PCIE slot of the server motherboard, the number of the server expansion cards is at least one, and each server expansion card (Riser card) is provided with at least one on-board PCIE slot and an I / O expander; a baseboard management controller (Baseboard Management Controller, BMC), each server expansion card (Riser card) is electrically connected to the baseboard management controller (Baseboard Management Controller, BMC) respectively; a complex programmable logic device (CPLD), the complex programmable logic device (CPLD) is electrically connected to the baseboard management controller (Baseboard Management Controller, BMC); a basic input / output system (Basic Input Output System, BIOS), the complex programmable logic device (CPLD) is electrically connected to the basic input / output system (Basic Input Output System, BIOS) through a central processing unit (CPU) provided on the motherboard. The method for intelligently identifying server configurations and adaptively configuring PCIe bandwidth includes the following steps:

[0005] S100. Configure the wiring method between the I / O expander and the on-board PCIE slot in each server expansion card (Riser card) connected to the server motherboard. Different wiring methods correspond to different register values of the I / O expander;

[0006] S200. Power on the server. After the Baseboard Management Controller (BMC) is initialized, obtain the register values of the I / O expander on each server expansion card (Riser card) through the IIC communication protocol;

[0007] S300. The Baseboard Management Controller (BMC) sends the register values of all I / O expanders to the Complex Programmable Logic Device (CPLD);

[0008] S400. The Complex Programmable Logic Device (CPLD) sends the register values of all I / O expanders to the Central Processing Unit (CPU) of the server through the vGPIO communication protocol;

[0009] S500. Based on the register values of the I / O expander, the Basic Input Output System (BIOS) allocates bandwidth and resources to the on-board PCIE slots in each server expansion card (Riser card).

[0010] Furthermore, in S100, the wiring methods between the I / O expander and the on-board PCIE slot in the server expansion card (Riser card) include:

[0011] When a single on-board PCIE slot in the server expansion card (Riser card) is only connected to one MCIO cable, the connection ports of the I / O expander connected to the on-board PCIE slot are one high-level signal and one low-level signal, and the channel width of the current on-board PCIE slot is x8;

[0012] When a single on-board PCIE slot in the server expansion card (Riser card) is simultaneously connected to two MCIO cables, the connection ports of the I / O expander connected to the on-board PCIE slot are two high-level signals, and the channel width of the current on-board PCIE slot is x16;

[0013] When a single on-board PCIE slot in the server expansion card (Riser card) is not connected to an MCIO cable, the connection ports of the I / O expander connected to the on-board PCIE slot are two low-level signals, and the current on-board PCIE slot is in a disabled state.

[0014] Further, based on the OCSP standard specification, the server riser card reuses idle pins to connect to the I / O expander, and defines the bandwidth width adapted to the current on-board PCIe slot through the level state of the idle pins.

[0015] Further, the idle pins are the B27 pins on the server riser card.

[0016] Further, the present invention also proposes a device for intelligent identification and adaptive configuration of PCIe bandwidth of a server, which is used to implement the method for intelligent identification of server configuration and adaptive configuration of PCIe bandwidth. The device for intelligent identification and adaptive configuration of PCIe bandwidth of a server includes:

[0017] Server riser cards, the server riser cards are installed on the motherboard PCIe slots on the server motherboard, the number of the server riser cards is at least one, and each server riser card is provided with at least one on-board PCIe slot and an I / O expander;

[0018] Among them, each on-board PCIe slot is connected to two I / O ports of the I / O expander based on the OCSP MCIO PIN standard;

[0019] Baseboard Management Controller (BMC), each server riser card is electrically connected to the Baseboard Management Controller (BMC);

[0020] Complex Programmable Logic Device (CPLD), the Complex Programmable Logic Device (CPLD) is electrically connected to the Baseboard Management Controller (BMC);

[0021] Basic Input Output System (BIOS), the Complex Programmable Logic Device (CPLD) is electrically connected to the Basic Input Output System (BIOS) through a Central Processing Unit (CPU) provided on the motherboard.

[0022] Further, the channel width of the on-board PCIe slot is x16, and the model of the I / O expander is PCA9554.

[0023] Furthermore, the server riser card is provided with at least an I / O expander and three on-board PCIe slots. Among them,

[0024] The three on-board PCIe slots include:

[0025] The first slot (PCIe slot1), and the first slot (PCIe slot1) is connected to two I / O ports of the I / O expander through two MCIO cables respectively;

[0026] The second slot (PCIe slot2), and the channel width of the second slot (PCIe slot2) is one of x8 and x16;

[0027] The third slot (PCIe slot3), and the third slot (PCIe slot3) is connected to two I / O ports of the I / O expander through two MCIO cables respectively.

[0028] Furthermore, the I / O expander is provided with at least a first input port and a third input port. There are two first input ports, and the first input ports are respectively connected to two MCIO cables of the first slot (PCIe slot1). There are two third input ports, and the third input ports are respectively connected to two MCIO cables of the third slot (PCIe slot3).

[0029] Furthermore, the register value output by the I / O expander is one data byte, and the data byte includes bits 0 - 7. Among them,

[0030] Bits 0 and 1 are the level values connected to two MCIO cables of the first slot (PCIe slot1),

[0031] Bits 2 and 3 are the level values connected to two MCIO cables of the third slot (PCIe slot3),

[0032] Bits 4 to 7 are the number flag bits of the current server riser card.

[0033] Furthermore, the present invention also proposes a computer-readable storage medium, on which program instructions are stored. When the program instructions are executed by a processor, the method for intelligent identification of server configuration and adaptive configuration of PCIe bandwidth is implemented.

[0034] Compared with the existing technology, the present invention has the following characteristics.

[0035] The method and device for configuring an intelligent recognition server and adaptively configuring PCIe bandwidth can not only reduce the number of general server boards, unify materials, and thus reduce production costs, but also adaptively configure PCIe bandwidth, reduce manual operations, and reduce the probability of errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is the overall flowchart of the method for configuring an intelligent recognition server and adaptively configuring PCIe bandwidth.

[0037] Figure 2 It is a schematic diagram of the overall topological structure of the device for configuring an intelligent recognition server and adaptively configuring PCIe bandwidth.

[0038] Figure 3 It is the flowchart of the server intelligent recognition configuration and adaptive PCIe bandwidth configuration in the method for configuring an intelligent recognition server and adaptively configuring PCIe bandwidth.

[0039] Figure 4(a) is a schematic diagram of a server expansion card (Riser card) in the method for configuring an intelligent recognition server and adaptively configuring PCIe bandwidth, which is provided with two I / O expanders and three on-board PCIE slots.

[0040] Figure 4(b) is a schematic diagram of a server expansion card (Riser card) in the method for configuring an intelligent recognition server and adaptively configuring PCIe bandwidth, which is provided with one I / O expander and two on-board PCIE slots.

[0041] Figure 4(c) is a schematic diagram of a server expansion card (Riser card) in the method for configuring an intelligent recognition server and adaptively configuring PCIe bandwidth, which is provided with one I / O expander and one on-board PCIE slot.

[0042] Figure 4(d) is a schematic diagram of a server expansion card (Riser card) in the method for configuring an intelligent recognition server and adaptively configuring PCIe bandwidth, which is provided with two I / O expanders and two on-board PCIE slots.

[0043] Figure 5 It is a schematic diagram of the OCSP MCIO PIN definition standard in the method for configuring an intelligent recognition server and adaptively configuring PCIe bandwidth.

[0044] Figure 6 It is a connection schematic diagram when neither the first slot nor the third slot is wired in the method for configuring an intelligent recognition server and adaptively configuring PCIe bandwidth.

[0045] Figure 7Schematic diagram of the connection when all cables are connected to the first slot and the third slot in the method for configuring and adaptively configuring PCIe bandwidth for an intelligent recognition server.

[0046] Figure 8 Schematic diagram of the connection when the two MCIOs of the first slot are not wired and the two MCIOs of the third slot are wired in the method for configuring and adaptively configuring PCIe bandwidth for an intelligent recognition server.

[0047] Figure 9 Schematic diagram of the connection when only one MCIO cable is connected to both the first slot and the third slot in the method for configuring and adaptively configuring PCIe bandwidth for an intelligent recognition server.

[0048] Figure 10 Byte values corresponding to different server expansion cards (Riser cards) and different wiring methods in the server system of the method for configuring and adaptively configuring PCIe bandwidth for an intelligent recognition server.

[0049] Figure 11 True value table of the whole machine system data processing in the method for configuring and adaptively configuring PCIe bandwidth for an intelligent recognition server.

[0050] Figure 12 Schematic diagram of a configuration example of the whole machine in the method for configuring and adaptively configuring PCIe bandwidth for an intelligent recognition server. Detailed implementation manners

[0051] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0052] The concept, specific structure, and technical effects generated by the present invention will be clearly and completely described below in combination with the embodiments and the drawings to fully understand the objectives, solutions, and effects of the present invention.

[0053] It should be noted that, unless otherwise specified, when a feature is referred to as "fixed" or "connected" to another feature, it can be directly fixed or connected to the other feature, or indirectly fixed or connected to the other feature. The singular forms "a", "the", and "said" used herein are also intended to include the plural forms, unless the context clearly dictates otherwise. In addition, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this technology belongs. The terms used in the description of this specification are only for describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0054] It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various elements, these elements should not be limited to these terms. These terms are only used to distinguish elements of the same type from each other. For example, without departing from the scope of this disclosure, the first element may also be referred to as the second element, and similarly, the second element may also be referred to as the first element. The use of any and all examples or exemplary language ("for example", "such as", etc.) provided herein is only intended to better illustrate the embodiments of the present invention and will not impose a limitation on the scope of the present invention unless otherwise required. In addition, the industry term "pose" used herein refers to the position and orientation of a certain element relative to a spatial coordinate system.

[0055] Refer to Figures 1 to 12, embodiments of the present invention provide a method for intelligent identification server configuration and adaptive configuration of PCIe bandwidth, which is applied to a device for intelligent identification configuration and adaptive configuration of PCIe bandwidth in a server. The device for intelligent identification configuration and adaptive configuration of PCIe bandwidth in the server includes: a server expansion card (Riser card), the server expansion card (Riser card) is installed on the motherboard PCIE slot on the server motherboard, the number of the server expansion cards is at least one, and each server expansion card (Riser card) is provided with at least one on-board PCIE slot and an I / O expander; a baseboard management controller (Baseboard Management Controller, BMC), each server expansion card (Riser card) is electrically connected to the baseboard management controller (Baseboard Management Controller, BMC); a complex programmable logic device (CPLD), the complex programmable logic device (CPLD) is electrically connected to the baseboard management controller (Baseboard Management Controller, BMC); a basic input / output system (Basic InputOutput System, BIOS), the complex programmable logic device (CPLD) is electrically connected to the basic input / output system (Basic Input Output System, BIOS) through a central processing unit (CPU) provided on the motherboard, referring to Figure 1 and Figure 3 , the method for intelligent identification server configuration and adaptive configuration of PCIe bandwidth includes the following steps:

[0056] S100. Configure the wiring mode between the I / O expander and the on-board PCIE slot in each server expansion card (Riser card) connected to the server motherboard. Different wiring modes correspond to different register values of the I / O expander;

[0057] S200. Start the server power supply. After the baseboard management controller (Baseboard Management Controller, BMC) is initialized, obtain the register values of the I / O expander on each server expansion card (Riser card) through the IIC communication protocol;

[0058] S300. The baseboard management controller (Baseboard Management Controller, BMC) sends the register values of all I / O expanders to the complex programmable logic device (CPLD);

[0059] S400. The complex programmable logic device (CPLD) sends the register values of all I / O expanders to the central processing unit (CPU) of the server through the vGPIO communication protocol;

[0060] S500. Based on the register values of the I / O expander, the Basic Input Output System (BIOS) allocates bandwidth and resources to the on-board PCIE slots in each server expansion card (Riser card).

[0061] Compared with the existing technology, the present invention has the following characteristics.

[0062] The method and device for intelligent identification server configuration and adaptive PCIe bandwidth configuration according to the present invention can not only reduce the number of general server boards, unify materials and thus reduce production costs, but also adaptively configure PCIe bandwidth, reduce manual operations and reduce the probability of errors.

[0063] The key points of the design scheme are to design a lightweight, highly mobile, low-cost and more intelligent liquid-cooled server: (1) intelligent identification configuration and adaptive PCIe bandwidth configuration, eliminating the production configuration steps, reducing the production process and reducing the probability of errors; (2) decoupling the information collection module, information processing module and bandwidth configuration module, which can be reused on multiple platforms without changing the whole set of solutions; (3) wiring according to customer needs to use PCIe resources without wasting resources, making the configuration more flexible; (4) a single card supports multiple configurations, reducing the number of single cards, concentrating the requirements on a single board, normalizing materials and reducing material costs.

[0064] Specifically, in the method and device for intelligent identification server configuration and adaptive PCIe bandwidth configuration, the server expansion card (Riser card) supports PCIe bandwidth X8 or X16 respectively through different wiring situations, so as to achieve that one server expansion card (Riser card) supports multiple configurations. There is a PCA9554 chip on the server expansion card (Riser card), and the registers corresponding to different wiring methods will have different values, so that different configurations can be identified and the PCIe bandwidth can be allocated to the Basic Input Output System (BIOS).

[0065] Refer to Figure 2, the overall topological structure is that the Baseboard Management Controller (BMC) or Complex Programmable Logic Device (CPLD) reads the register values of the PCA9554 chip on the server riser card through I2C to collect information, and then transmits the information to the Complex Programmable Logic Device (CPLD) for data processing. The processed data is transmitted to the Basic Input Output System (BIOS) through vGPIO. After receiving the information, the Basic Input Output System (BIOS) performs PCIe allocation, thus achieving the technical effect of an adaptive allocation function.

[0066] Refer to Figure 2 , the Baseboard Management Controller (BMC) or Complex Programmable Logic Device (CPLD) is connected to four server riser cards. Each server riser card is provided with a PCA9554 chip for reading the on-board PCIE slot. By changing the wiring method between the I / O expander and the on-board PCIE slot in each server riser card connected to the server motherboard, the register value is changed. The register value is sequentially transmitted to the Central Processing Unit (CPU) and the Basic Input Output System (BIOS) through the Complex Programmable Logic Device (CPLD). The Basic Input Output System (BIOS) allocates bandwidth and resources for the on-board PCIE slots in each server riser card.

[0067] For the previous solutions to collect information and allocate PCIe bandwidth, the information (D1) of the device, or the DIP switch (D2), or the special ID PIN foot and connector (D3) are often required. However, in the case where this patent can meet the OCSP standard specification (all PIN feet are defined and there is no dedicated ID PIN foot), only through different wiring methods with different configurations according to customer requirements can the required bandwidth allocation be identified.

[0068] Furthermore, in the S100, the wiring method between the I / O expander and the on-board PCIE slot in the server riser card includes:

[0069] When a single on-board PCIE slot in a server riser card is only connected to one MCIO cable, the connection ports corresponding to the I / O expander connected to the on-board PCIE slot are one high-level signal and one low-level signal, and the current channel width of the on-board PCIE slot is x8;

[0070] When a single on-board PCIE slot in a server riser card is connected to two MCIO cables at the same time, the connection ports corresponding to the I / O expander connected to the on-board PCIE slot are two high-level signals, and the current channel width of the on-board PCIE slot is x16;

[0071] When a single on-board PCIE slot in a server riser card is not connected to an MCIO cable, the connection ports corresponding to the I / O expander connected to the on-board PCIE slot are two low-level signals, and the current on-board PCIE slot is in a disabled state.

[0072] Furthermore, based on the OCSP standard specification, the server riser card reuses the idle pins and connects them to the I / O expander, and defines the bandwidth width adapted to the current on-board PCIE slot through the level state of the idle pins.

[0073] Furthermore, the idle pins are the B27 pins on the server riser card.

[0074] Specifically, the method for identifying whether an MCIO cable is plugged into the server riser card is as follows: When there are no extra PINs, one PIN is reused according to the application scenario and connected to the PCA9554 chip, thus solving the problem of how to identify whether a cable is plugged in. All the PINs of MCIO on the motherboard in the OCSP standard specification are used, but the B27 pin on the server riser card is NC and not used. Therefore, this PIN on the server riser card can be used to judge whether a cable is connected, so as to judge what configuration is needed and perform PCIe bandwidth configuration.

[0075] Refer to Figure 5, at the mainboard end, the A27 of the MCIO cable is connected to HP_SMB_ALERT#, which is the interrupt signal for NVMe hot plug. At the mainboard end, it needs to be strongly pulled up by 1K. This signal is not used when the MCIO is connected to the server expansion card (Riser card). Therefore, at the server expansion card (Riser card) end, the corresponding B27 of the MCIO is weakly pulled down by 50K, and B27 is connected to the PCA9554 chip. By connecting the B27 of different MCIO cables to different IOs of the PCA9554 chip, it is possible to read through I2C which cable is connected and which is not. When multiple modules are combined and information is processed, the configuration of the entire machine can be intelligently identified.

[0076] Furthermore, the present invention also proposes a device for intelligent identification of server configuration and adaptive configuration of PCIe bandwidth, which is used to implement the method for intelligent identification of server configuration and adaptive configuration of PCIe bandwidth. The device for intelligent identification of server configuration and adaptive configuration of PCIe bandwidth includes:

[0077] Server expansion card (Riser card), the server expansion card (Riser card) is installed on the mainboard PCIE slot on the server mainboard, and the number of the server expansion cards is at least one. Each server expansion card (Riser card) is provided with at least one on-board PCIE slot and an I / O expander;

[0078] Among them, each on-board PCIE slot is connected to two I / O ports of the I / O expander based on the OCSP MCIO PIN standard;

[0079] Baseboard Management Controller (BMC), each server expansion card (Riser card) is electrically connected to the Baseboard Management Controller (BMC) respectively;

[0080] Complex Programmable Logic Device (CPLD), the Complex Programmable Logic Device (CPLD) is electrically connected to the Baseboard Management Controller (BMC);

[0081] Basic Input Output System (BIOS), the Complex Programmable Logic Device (CPLD) is electrically connected to the Basic Input Output System (BIOS) through the Central Processing Unit (CPU) set on the mainboard.

[0082] Further, the channel width of the on-board PCIE slot is x16, and the model of the I / O expander is PCA9554.

[0083] Further, referring to FIG. 4(a), the server expansion card (Riser card_ PR2715B_Riser1&2A) is provided with at least two I / O expanders and three on-board PCIE slots. Among them,

[0084] The three on-board PCIE slots include:

[0085] The first slot (PCIe slot1), and the first slot (PCIe slot1) is connected to two I / O ports of the I / O expander through two MCIO cables respectively;

[0086] The second slot (PCIe slot2), and the channel width of the second slot (PCIe slot2) is one of x8 and x16;

[0087] The third slot (PCIe slot3), and the third slot (PCIe slot3) is connected to two I / O ports of the I / O expander through two MCIO cables respectively.

[0088] Specifically, the second slot (PCIe slot2) is provided with signals by the gold fingers and is fixed to the PCIe signal of X16, while the first slot (PCIe slot1) and the third slot (PCIe slot3) provide the PCIe signal of X16, the PCIe signal of X8 and do not provide the PCIe signal according to the wiring method. Therefore,

[0089] Referring to Figure 6 , when neither the first slot (PCIe slot1) nor the third slot (PCIe slot3) is wired, one X16 PCIe device is supported, and the obtained byte value is 0000 0000;

[0090] Referring to Figure 7 , when all four MCIO cables on the server expansion card (Riser card) are connected, a total of 3 X16 PCIe devices are supported, and the obtained byte value is 0000 1111;

[0091] Referring to Figure 8 , when the two MCIO of the first slot (PCIe slot1) are not wired and the two MCIO of the third slot (PCIe slot3) are wired, 2 X16 PCIe devices are supported, and the obtained byte value is 0000 1100;

[0092] Referring to Figure 9, when only one MCIO cable is connected to both the first slot (PCIe slot1) and the third slot (PCIe slot3), it supports one X16 PCIe device and two X8 PCIes, and the obtained byte value is 0000 0101;

[0093] When no MCIO cable is connected to the first slot (PCIe slot1) and only one MCIO cable is connected to the third slot (PCIe slot3), it supports one X16 PCIe device and one X8 PCIe.

[0094] Thus, a server expansion card (Riser card) can support multiple customer application types, simplifying the number of daughter cards. Moreover, when the PCIe resources on the server expansion card (Riser card) are not fully utilized, this part of the PCIe resources can be given to the hard disk and other devices for use.

[0095] The server expansion card (Riser card) supports multiple configurations. In some embodiments, referring to Figure 4(b), the server expansion card (Riser card_ PR2715B_Riser1&2A_L) is provided with one I / O expander and two on-board PCIE slots.

[0096] Referring to Figure 4(c), the server expansion card (Riser card_ PR2715B-Riser3A) is provided with one I / O expander and two on-board PCIE slots.

[0097] Referring to Figure 4(d), the server expansion card (Riser card_ PR2715B-Riser3B) is provided with two I / O expanders and two on-board PCIE slots.

[0098] The above are several examples. Actually, according to the above principle, different server expansion cards (Riser cards) and wiring methods configured respectively can obtain corresponding Byte values. Refer to Figure 10 , and the wiring method not under the recommended configuration can report an error.

[0099] Referring to Figure 10 , the connection method can be known through the byte. A wrong connection means there is no such wiring method, reminding the customer that the cable is connected wrongly):

[0100] The slot positions of the whole machine are used as Figure 10 supplement,

[0101] Among them, the slot positions occupied by IO module 1 are Slot 1 to Slot 3; corresponding to Figure 10 BYTE1 in

[0102] The slots occupied by the IO module 2 are Slot 4 to Slot 6; corresponding to Figure 10 BYTE2 in

[0103] The slots occupied by the IO module 3 are Slot 7 to Slot 8; corresponding to Figure 10 BYTE3 in

[0104] The slots occupied by the IO module 4 are Slot 9 to Slot 10; corresponding to Figure 10 BYTE4 in

[0105] Refer to Figure 11 , after the information collection in the previous stage, the data of the system can be known according to the Byte byte value data, and then after data processing, vGOIO can be output to the Basic Input Output System (BIOS). The Basic Input Output System (BIOS) performs relative bandwidth configuration according to the corresponding vGOIO.

[0106] Specifically, refer to Figure 11 , the bandwidth allocation required for the whole machine can be known through the BYTE obtained previously. After being processed by the CPLD, vGPIO signals are output. Different vGPIO signals represent different configurations, and the BIOS allocates after obtaining the configurations.

[0107] Refer to Figure 12 , which is a configuration example for the whole machine. Among them, for the IO module 1 and the IO module 2, it is optional to connect to PR2715B_Riser1&2A and PR2715B_Riser1&2A_L; for the IO module 3 and the IO module 4, it is optional to connect to PR2715B-Riser3A and PR2715B-Riser3B.

[0108] Furthermore, the I / O expander is provided with at least a first input port and a third input port. The first input port has two, and the first input ports are respectively connected to two MCIO cables of the first slot (PCIe slot1). The third input port has two, and the third input ports are respectively connected to two MCIO cables of the third slot (PCIe slot3).

[0109] Furthermore, the register value output by the I / O expander is one data byte, and the data byte includes bits 0 - 7. Among them,

[0110] Bits 0 and 1 are the level values connected to the two MCIO cables of the first slot (PCIe slot1).

[0111] The second and third bits are the level values connected to the two MCIO cables of the third slot (PCIe slot3).

[0112] The fourth to seventh bits are the number flag bits of the current server expansion card (Riser card).

[0113] Specifically, taking RISER1 as an example, the 8 IO connections of the PCA9554 chip are as follows.

[0114] Riser1&2A:

[0115] IO7--Pulled down to GND.

[0116] IO6--Pulled down to GND.

[0117] IO5--Pulled down to GND.

[0118] IO4--Pulled down to GND.

[0119] IO3—MCIO_B27 of Slot3(8 - 15).

[0120] IO2—MCIO_B27 of Slot3(0 - 7).

[0121] IO1--MCIO_B27 of Slot1(8 - 15).

[0122] IO0--MCIO_B27 of Slot1(0 - 7).

[0123] Different wiring methods correspond to different configurations, and different bytes are obtained.

[0124] Furthermore, the present invention also proposes a computer-readable storage medium, on which program instructions are stored. When the program instructions are executed by a processor, the method for intelligent identification of server configuration and adaptive configuration of PCIe bandwidth is implemented.

[0125] It should be recognized that the method steps in the embodiments of the present invention can be implemented or carried out by computer hardware, a combination of hardware and software, or computer instructions stored in a non-transitory computer-readable memory. The method can use standard programming techniques. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if necessary, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. In addition, for this purpose, the program can run on a dedicated integrated circuit programmed for this purpose.

[0126] In addition, the operations of the processes described herein can be performed in any suitable order, unless otherwise indicated herein or otherwise clearly contradicted by the context. The processes described herein (or variations and / or combinations thereof) can be performed under the control of one or more computer systems configured with executable instructions and can be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) executed jointly on one or more processors, by hardware, or by a combination thereof. The computer program includes a plurality of instructions executable by one or more processors.

[0127] Further, the method can be implemented in any type of computing platform operatively connected to a suitable one, including but not limited to personal computers, minicomputers, mainframes, workstations, network or distributed computing environments, separate or integrated computer platforms, or communicating with charged particle tools or other imaging devices, etc. Aspects of the present invention can be implemented in machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into the computing platform, such as a hard disk, optical read and / or write storage medium, RAM, ROM, etc., such that it can be read by a programmable computer and can be used to configure and operate the computer to perform the processes described herein when the storage medium or device is read by the computer. In addition, the machine-readable code, or portions thereof, can be transmitted via a wired or wireless network. When such media includes instructions or programs that implement the above-described steps in combination with a microprocessor or other data processor, the inventions described herein include these and other different types of non-transitory computer-readable storage media. When programmed according to the methods and techniques of the present invention, the present invention can also include the computer itself.

[0128] The computer program can be applied to the input data to perform the functions described herein, thereby transforming the input data to generate output data stored in non-volatile memory. The output information can also be applied to one or more output devices such as a display. In a preferred embodiment of the present invention, the transformed data represents physical and tangible objects, including a specific visual depiction of the physical and tangible objects generated on the display.

[0129] The above are only the preferred embodiments of the present invention. The present invention is not limited to the above-described embodiments. As long as it achieves the technical effects of the present invention by the same means, any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention. Within the scope of protection of the present invention, its technical solutions and / or implementation manners can have various different modifications and variations.

Claims

1. A method for intelligently identifying server configuration and adaptively configuring PCIe bandwidth, applied to a device for intelligently identifying and adaptively configuring PCIe bandwidth for a server, the device for intelligently identifying and adaptively configuring PCIe bandwidth for a server comprising: A server expansion card, wherein the server expansion card is installed on a mainboard PCIE slot on a server mainboard, the number of the server expansion card is at least one, and each of the server expansion cards is provided with at least one onboard PCIE slot and an I / O expander; A baseboard management controller, each of the server expansion cards is electrically connected to the baseboard management controller; a complex programmable logic device, the complex programmable logic device is electrically connected to the baseboard management controller; a basic input and output system, the complex programmable logic device is electrically connected to the basic input and output system through a central processing unit arranged on a motherboard, wherein the method for intelligently identifying server configuration and adaptively configuring PCIe bandwidth comprises the following steps: S100, configuring a wiring mode between an I / O expander and an onboard PCIE slot in each server expansion card connected to the server mainboard, wherein different wiring modes correspond to different register values ​​of the I / O expander; S200, starting the server power supply, after the baseboard management controller is initialized, obtaining the register value of the I / O expander on each server expansion card through the IIC communication protocol; S300, the baseboard management controller sends the register values ​​of all I / O expanders to the complex programmable logic device; S400, the complex programmable logic device sends the register values ​​of all I / O expanders to the central processor of the server through the vGPIO communication protocol; S500, based on the register value of the I / O expander, the basic input and output system allocates bandwidth and resources to the onboard PCIE slot in each server expansion card; In S100, the wiring method between the I / O expander in the server expansion card and the onboard PCIE slot includes: When a single onboard PCIE slot in a server expansion card is connected to only one MCIO cable, the connection port corresponding to the I / O expander connected to the onboard PCIE slot is a high-level signal and a low-level signal, and the channel width of the current onboard PCIE slot is x8; When a single onboard PCIE slot in a server expansion card is connected to two MCIO cables at the same time, the connection port corresponding to the I / O expander connected to the onboard PCIE slot is a two-bit high-level signal, and the channel width of the current onboard PCIE slot is x16; When a single onboard PCIE slot in a server expansion card is not connected to an MCIO cable, a connection port corresponding to an I / O expander connected to the onboard PCIE slot is a two-bit low-level signal, and the current onboard PCIE slot is in a disabled state.

2. The method for intelligently identifying server configuration and adaptively configuring PCIe bandwidth according to claim 1, characterized in that: Based on the OCSP standard specification, the server expansion card reuses the idle pins to connect to the I / O expander, and the bandwidth width adapted by the current onboard PCIE slot is defined by the level state of the idle pins.

3. The method for intelligently identifying server configuration and adaptively configuring PCIe bandwidth according to claim 2, characterized in that: The idle pin is the B27 pin on the server expansion card.

4. A device for intelligently identifying and adaptively configuring PCIe bandwidth of a server, used to implement the method for intelligently identifying and adaptively configuring PCIe bandwidth of a server as claimed in any one of claims 1 to 3, characterized in that: The device for intelligently identifying and adaptively configuring PCIe bandwidth of a server includes: A server expansion card, wherein the server expansion card is installed on a mainboard PCIE slot on a server mainboard, the number of the server expansion card is at least one, and each of the server expansion cards is provided with at least one onboard PCIE slot and an I / O expander; Among them, each onboard PCIE slot is connected to two I / O ports of the I / O expander based on the OCSP MCIO PIN standard; A baseboard management controller, each of the server expansion cards is electrically connected to the baseboard management controller; A complex programmable logic device, the complex programmable logic device being electrically connected to the baseboard management controller; The basic input-output system is electrically connected to the complex programmable logic device through a central processing unit arranged on a mainboard.

5. The device for intelligently identifying and adaptively configuring PCIe bandwidth of a server according to claim 4, characterized in that: The channel width of the onboard PCIE slot is x16, and the model of the I / O expander is PCA9554.

6. The device for intelligently identifying and adaptively configuring PCIe bandwidth of a server according to claim 4, characterized in that: The server expansion card is provided with at least an I / O expander and three onboard PCIE slots, wherein: The three onboard PCIE slots include: A first slot, wherein the first slot is connected to two I / O ports of the I / O expander through two MCIO cables respectively; A second slot, wherein the channel width of the second slot is one of x8 and x16; The third slot is connected to two I / O ports of the I / O expander through two MCIO cables respectively.

7. The device for intelligently identifying and adaptively configuring PCIe bandwidth of a server according to claim 6, characterized in that: The I / O expander is provided with at least a first input port and a third input port. There are two first input ports, which are respectively connected to two MCIO cables of the first slot. There are two third input ports, which are respectively connected to two MCIO cables of the third slot.

8. The device for intelligently identifying and adaptively configuring PCIe bandwidth of a server according to claim 7, characterized in that: The register value output by the I / O expander is a data byte, and the data byte includes bits 0-7, wherein: Bits 0 and 1 are the voltage levels connected to the two MCIO cables in the first slot. The second and third bits are the voltage levels for the two MCIO cables connected to the third slot. The 4th to 7th bits are the number flags of the current server expansion card.

9. A computer-readable storage medium having program instructions stored thereon, characterized in that: When the program instructions are executed by a processor, the method according to any one of claims 1 to 3 is implemented.

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