Multi-chip CCGA packaging welding column failure risk evaluation method

Abstract

The invention discloses a multi-chip CCGA packaging welding column failure risk evaluation method, and belongs to the technical field of electronic packaging and reliability analysis, and the method comprises the steps: building a finite element analysis model through obtaining the geometric and material parameters of a multi-chip CCGA packaging structure; non-uniform working conditions are set, boundary conditions and constraints are applied, and non-uniform distribution thermal stress of the welding column is obtained through thermal cycle loading analysis; key data are extracted, the fatigue life of the welding column is calculated through a Coffin-Manson thermal fatigue model, and a life matrix is determined; the welding column damage amount is calculated based on a thermal fatigue model and a linear accumulation damage theory, and a damage matrix is obtained; welding column failure is judged according to the damage matrix, and a risk level matrix is obtained. According to the method, the stress distribution and failure mechanism of the welding column under the multi-chip coupling scene can be rapidly and accurately evaluated in the design and early verification stage according to the actual working condition, and scientific support is provided for research and development of high-reliability electronic products.

Description

Technical Field

[0001] The present application relates to the technical field of electronic packaging and reliability analysis, and in particular to a method for evaluating the failure risk of solder pillars in a multi-chip CCGA package. Background Art

[0002] With the continuous integration of electronic product functions and the increasing requirements for high performance and high reliability, multi-chip packaging technology has gradually become an important trend in the development of the integrated circuit industry. Among them, CCGA (Ceramic Column Grid Array) is an extension of the concept of ceramic ball grid array CBGA. Due to its excellent heat dissipation characteristics and good solderability, it is widely used in aerospace, communication base stations, automotive electronics and other fields with high requirements for environmental adaptability; in the multi-chip CCGA packaging structure, the slender and soft solder column (Solder Column) serves as an electrical interconnection channel and also plays a mechanical support role between the chip and the substrate, which is of key significance to the stability and reliability of the overall package.

[0003] However, with the reduction of package size, the increase of chip number, and the superposition of complex working conditions such as temperature cycle, mechanical stress, vibration and shock, the solder column is prone to failure modes such as cracks and fatigue fractures during use, causing serious functional failures or reliability problems. Traditional solder column failure analysis mostly uses experimental or single-chip model inference methods, which cannot accurately evaluate the stress distribution and failure mechanism in multi-chip coupling scenarios, and it is difficult to quickly evaluate and optimize different structures and material solutions in the design stage. There is an urgent need for a comprehensive evaluation method that combines finite element analysis, thermal fatigue model and cumulative damage theory to provide effective guidance for multi-chip CCGA package design and failure risk prediction. Summary of the invention

[0004] The purpose of this application is to provide a multi-chip CCGA package solder column failure risk assessment method to address the above-mentioned deficiencies in the prior art, so as to solve the problem that the actual working conditions cause the risk of solder column failure to increase and the single-chip model inference method is difficult to accurately assess the stress distribution and failure mechanism of the solder column in the multi-chip coupling scenario, so as to improve the accuracy and efficiency of failure analysis evaluation.

[0005] In order to achieve the above application purpose, the technical solutions adopted in this application include the following: S1: Obtain geometric parameters and material parameters of a multi-chip CCGA packaging structure; S2: Establishing a finite element analysis model of a multi-chip CCGA package: establishing a geometric model of the multi-chip CCGA package structure based on the geometric parameters, and adding material parameters to the geometric model to form a finite element analysis model of the multi-chip CCGA package, wherein the geometric model is a plurality of chips, a ceramic substrate, a solder column array and a printed circuit board stacked sequentially from top to bottom, and the plurality of chips are laid side by side on the ceramic substrate; S3: Using the finite element analysis model, a coupling analysis is performed under non-uniform temperature loads: boundary conditions and constraints are applied to the constructed finite element analysis model, different operating temperature conditions are set for different chips, and thermal stress distribution of solder columns is simulated and obtained under thermal cycle loading conditions; S4: extract key data according to the finite element analysis model of the multi-chip CCGA package and the stress distribution of the solder column under the non-uniform distribution temperature, obtain the relevant fatigue parameters of the Coffin-Manson thermal fatigue model, calculate the fatigue life of the solder column by the Coffin-Manson thermal fatigue model formula, and determine the CCGA package solder column fatigue parameter life matrix; S5: Perform risk assessment of non-uniform damage: Based on the Coffin-Manson thermal fatigue model and linear cumulative damage theory, calculate the damage amount of the solder column under non-uniformly distributed thermal stress and obtain the multi-chip CCGA package solder column damage matrix; perform solder column failure judgment according to the CCGA package solder column damage matrix and obtain the risk level matrix of the multi-chip CCGA package solder column.

[0006] In a possible implementation, in S2, establishing a finite element analysis model of a multi-chip CCGA package includes: Creating a parametric geometric model of the multi-chip CCGA packaging structure based on finite element simulation: establishing a geometric model of each device according to the acquired geometric parameters of the components of the multi-chip CCGA packaging structure, assembling the geometric models of each device to form a geometric model of the multi-chip CCGA packaging structure; Specific material parameters are added to each device of the geometric model of the multi-chip CCGA packaging structure to form a meta-analysis model of the multi-chip CCGA packaging.

[0007] In a possible implementation, in S3, the applied boundary condition is that the overall temperature of the element analysis model of the multi-chip CCGA package is set to an initial temperature of , the maximum temperature is The imposed constraint is that the displacement constraint of the bottom printed circuit board foot point is zero, simulating the fixed installation method of the printed circuit board.

[0008] In a possible implementation, the S4 includes: S41: Obtain the plastic strain amplitude of the weld column during the thermal cycle, which can be calculated by the following formula:

[0009] in, is the plastic strain amplitude of the weld column during thermal cycling, is the thermal expansion coefficient of the solder column material, is the temperature variation amplitude of the thermal cycle; S42: The fatigue life of the weld column is calculated using the Coffin-Manson thermal fatigue model formula. i Line j Fatigue life of solder pillars in multi-chip CCGA packages , the calculation formula is as follows:

[0010] in, It is i Line j The plastic strain amplitude of the solder column of the multi-chip CCGA package is shown in Figure 2. It is i Line j The material fatigue onset strain amplitude of the solder column of the multi-chip CCGA package is shown in the figure. It is i Line j The Coffin-Manson constants of the materials for the solder pillars of the multi-chip CCGA package; S43: Based on the calculated fatigue parameters of each welding column, the following formula is constructed: i Line j The fatigue parameter life matrix of the column weld is listed;

[0011] S44: establishing a fatigue parameter life matrix of solder pillars for a multi-chip CCGA package as shown below based on the calculated fatigue parameter life matrix of each solder pillar;

[0012] in, K is the fatigue parameter life matrix of solder pillars in multi-chip CCGA package, i It is the first in the multi-chip CCGA package i Welding column, j It is the first in the multi-chip CCGA package j Column welding, n is the total number of solder column rows in the multi-chip CCGA package, m is the total number of solder column columns in the multi-chip CCGA package, is the fatigue parameter life matrix of the solder column in row 1 and column 1 in the multi-chip CCGA package, It is the first in the multi-chip CCGA package i Line j The fatigue parameter life matrix of the weld column is: It is the first in the multi-chip CCGA package n Line m Fatigue parameter life matrix of the column weld.

[0013] In a possible implementation, the step of obtaining a multi-chip CCGA package solder column damage matrix includes: S51: The Coffin-Manson thermal fatigue model and linear cumulative damage theory are used to calculate the damage amount of the solder column of the multi-chip CCGA package, which can be calculated by the following formula:

[0014] in, It is i Line j The accumulated damage of the weld column is It is i Line j Fatigue life of weld column, k is the number of thermal cycles; S52: Based on the calculated accumulated damage amounts, a damage matrix of the solder column of the multi-chip CCGA package is established as shown below D ;

[0015] in, i It is the first in the multi-chip CCGA package i Welding column, j It is the first in the multi-chip CCGA package j Welding column, n is the total number of solder column rows in the multi-chip CCGA package, m is the total number of solder column columns in the multi-chip CCGA package, is the accumulated damage of the solder column in row 1 and column 1 of the multi-chip CCGA package. It is the first in the multi-chip CCGA package i Line j The accumulated damage of the weld column, It is the first in the multi-chip CCGA package n Line m The accumulated damage of the weld column, D The damage matrix of solder pillars for multi-chip CCGA packages; S53: Perform solder column failure determination according to the multi-chip CCGA package solder column damage matrix, and set For low risk, For medium risk, As high risk, a risk level matrix for multi-chip CCGA package solder pillars is established as shown below M ;

[0016] in, is the risk level of the solder column in row 1 and column 1 in a multi-chip CCGA package. It is the first in the multi-chip CCGA package i Line j The risk level of the weld column is listed as follows, It is the first in the multi-chip CCGA package n Line m The risk level of the weld column is listed as follows, M Risk level matrix for solder pillars in multi-chip CCGA packages.

[0017] Compared with the prior art, the present application establishes a finite element analysis model of a multi-chip CCGA package, incorporates information such as multiple chips, substrates, solder columns and their material properties, geometric parameters, etc. into the overall coupling analysis, and realizes full-field simulation of the thermal-mechanical environment. The precise modeling of this multi-chip structure can more realistically reflect the actual packaging situation, so that the obtained thermal stress distribution of the solder columns is more in line with the actual situation, avoiding the deviation caused by the traditional method of using a single chip and uniform temperature assumption; at the same time, the key parameters of thermal fatigue of the solder columns are obtained, and the stress-strain amplitude of the solder columns and the fatigue damage indicators required by the thermal fatigue model are extracted based on the simulation results, providing accurate data support for subsequent life prediction. Since multi-chip coupling and non-uniform thermal stress are taken into account, these parameters can more accurately reflect the fatigue characteristics of the solder columns under actual working conditions; in addition, the thermal fatigue life model and cumulative damage theory are introduced to calculate the fatigue life and damage amount of different solder columns under non-uniformly distributed thermal stress, which can more carefully evaluate the damage of the solder columns.

[0018] Through the above-mentioned technical means, the present application can quickly and accurately perform quantitative assessment of the failure risk of multi-chip CCGA package solder columns during the design stage and early verification, providing scientific technical support for the research and development and production of high-reliability electronic products. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of a multi-chip CCGA packaging structure provided in an embodiment of the present application; Figure 2 A front view of a multi-chip CCGA packaging structure provided in an embodiment of the present application; Figure 3 A top view of a multi-chip CCGA packaging structure provided in an embodiment of the present application; Figure 4 A flow chart of a method for evaluating the risk of solder column failure in a multi-chip CCGA package provided in an embodiment of the present application.

[0020] Figure numerals: 1 - ceramic substrate, 2 - solder column array, 3 - printed circuit board, 4 - chip. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0022] In order to more clearly illustrate the multi-chip CCGA package solder column failure risk assessment method provided in the embodiment of the present application, a possible application scenario of the multi-chip CCGA package solder column failure risk assessment method provided in the embodiment of the present application will be exemplified below. It can be understood that the following example is only a possible application scenario of the multi-chip CCGA package solder column failure risk assessment method provided in the embodiment of the present application. In other possible embodiments, the multi-chip CCGA package solder column failure risk assessment method provided in the embodiment of the present application can also be applied to other possible application scenarios, and the following example does not impose any limitations on this.

[0023] Traditional solder column failure analysis mostly uses a single-chip model inference method, which mainly calculates boundary conditions for uniform temperature distribution. However, in the case of multiple chips, it is necessary to consider the thermal stress caused by non-uniform temperature distribution. Thermal stress is caused by the constraint when the material expands or contracts under temperature changes. Under uniform temperature distribution, thermal stress may be relatively uniform, but when the temperature distribution is uneven, the degree of expansion in different areas is different, resulting in complex internal stress, which may produce greater local stress and accelerate fatigue failure.

[0024] It is understandable that multi-chip packaging technology has gradually become an important trend in the development of the integrated circuit industry, integrating chips with different processes and functions into a single package through advanced packaging technology to form a complete system function. In the multi-chip CCGA packaging structure, the slender and soft solder pillars serve as electrical interconnection channels and mechanical support between the chip and the substrate, which is of key significance to the stability and reliability of the overall package.

[0025] However, traditional CCGA solder column failure analysis is mostly based on the uniform temperature assumption or single-point heat source model. The failure analysis only considers the stress impact of the overall temperature cycle on the solder joint, and does not involve the local thermal coupling effect caused by the multi-chip layout, which is not close to the actual scenario.

[0026] Based on this, the embodiment of the present application provides a method for evaluating the failure risk of solder pillars in a multi-chip CCGA package. Figure 1-Figure 3 As shown, the multi-chip CCGA packaging structure used in this embodiment uses a ceramic substrate 1 as a substrate, a solder column array 2 is welded on the bottom surface of the ceramic substrate, and the other side of the solder column array 2 is connected to a printed circuit board (PCB) 3. A plurality of chips 4 are arranged on the top of the ceramic substrate 1, taking three chips as an example.

[0027] like Figure 4 As shown, the specific implementation of this application is as follows: S1: Obtain geometric parameters and material parameters of a multi-chip CCGA packaging structure.

[0028] The geometric parameters and material parameters of each component of the multi-chip CCGA packaging structure are collected. The components include a printed circuit board, a solder column, a ceramic substrate, and a chip. The solder column is a cylinder with a height of 0.2 mm and a diameter of 0.2 mm. The dimension parameter table of each component is shown in Table 1: Table 1 Device size parameter table

[0029] The solder pillars used in this embodiment are tin-lead solder. This example involves a 10×10 solder pillar array with a pitch of 0.6 mm and a total of 100 pillars. The printed circuit board is made of FR-4 material, the ceramic substrate is made of ceramic material, and the chip is made of silicon material. This embodiment takes three chips as an example, and the material parameter table of each device is shown in Table 2: Table 2 Device material parameters

[0030] Table 2 provides four types of devices, each row represents a material parameter of a device, and each column represents a material performance parameter and the corresponding specific parameters.

[0031] S2: Establish a finite element analysis model for multi-chip CCGA packaging.

[0032] S21: According to the size parameters in Table 1, the geometric models of each device are drawn based on finite element simulation. Then, at the bottom is the printed circuit board 3, followed by a solder column matrix 2 formed by 100 columnar solder columns arranged in a 10×10 array with a pitch of 0.6 mm, and above that is a ceramic substrate 1. On the ceramic substrate are three chips 4, and the size of each chip is shown in Table 1.

[0033] S22: According to the material properties of each device, use Abaqus finite element simulation software to add specific material properties to the corresponding devices in the geometric model to obtain a finite element analysis model of the multi-chip CCGA package.

[0034] S3: Using the finite element analysis model, conduct coupling analysis under non-uniform temperature loads: apply boundary conditions and constraints to the constructed finite element analysis model, set different operating temperature conditions for different chips, simulate under thermal cycle loading conditions and obtain the thermal stress distribution of the solder column.

[0035] Set the operating temperature table of different chips as shown in Table 3, and the overall initial temperature of the model is , The temperature of the three chips is set to rise from 40°C to 140°C, the temperature of chip 2 is set to rise from 40°C to 130°C, and the temperature of chip 3 is set to rise from 40°C to 120°C. The temperature of the ceramic substrate, solder column and printed circuit board changes according to the temperature heat transfer of the chip.

[0036] Table 3 Chip operating temperature table

[0037] The boundary condition imposed on the built model is to set the overall temperature of the model to the initial temperature. , is 40℃, the highest temperature is ; The constraints imposed are to impose full constraints on the bottom printed circuit board feet, that is, the displacement constraints of the feet are zero, simulating its fixed installation method.

[0038] S4: According to the finite element analysis model of the multi-chip CCGA package and the stress distribution of the solder column under non-uniform temperature distribution, key data is extracted to obtain relevant fatigue parameters of the Coffin-Manson thermal fatigue model, and the fatigue life of the solder column is calculated by the Coffin-Manson thermal fatigue model formula to determine the fatigue parameter life matrix of the solder column of the multi-chip CCGA package.

[0039] Specifically: S41: Obtain the plastic strain amplitude of the weld column during the thermal cycle, which can be calculated by the following formula:

[0040] in, is the plastic strain amplitude of the weld column during thermal cycling, is the thermal expansion coefficient of the solder column material, is the temperature variation amplitude of the thermal cycle; S42: The fatigue life of the weld column is calculated using the Coffin-Manson thermal fatigue model formula. i Linej Fatigue life of solder pillars in multi-chip CCGA packages , the calculation formula is as follows:

[0041] in, It is i Line j The plastic strain amplitude of the solder column of the multi-chip CCGA package is shown in Figure 2. It is i Line j The fatigue initial strain amplitude of the material of the multi-chip CCGA package solder column is 0.5. It is i Line j The Coffin-Manson constant of the material of the multi-chip CCGA package solder column is -0.5; S43: Based on the calculated fatigue parameters of each welding column, the following formula is constructed: i Line j The fatigue parameter life matrix of the column weld is listed;

[0042] S44: Establishing the fatigue parameter life matrix of the solder pillars of the multi-chip CCGA package as shown below according to the calculated fatigue parameter life matrix of each solder pillar, and the fatigue parameter life matrix table of each solder pillar is shown in Table 4:

[0043] in, K is the fatigue parameter life matrix of solder pillars in multi-chip CCGA package, i It is the first in the multi-chip CCGA package i Welding column, j It is the first in the multi-chip CCGA package j Column welding, n is the total number of solder column rows in the multi-chip CCGA package, m is the total number of solder column columns in the multi-chip CCGA package, is the fatigue parameter life matrix of the solder column in row 1 and column 1 in the multi-chip CCGA package, It is the first in the multi-chip CCGA package i Line j The fatigue parameter life matrix of the weld column is: It is the first in the multi-chip CCGA package n Line m Fatigue parameter life matrix of the column weld.

[0044] Table 4 Fatigue parameter life matrix of weld column

[0045] Table 4

[0046] Table 4

[0047] Table 4

[0048] Table 4

[0049] S5: Perform risk assessment of non-uniform damage: Based on the Coffin-Manson thermal fatigue model and linear cumulative damage theory, calculate the damage amount of the solder column under non-uniformly distributed thermal stress and obtain the multi-chip CCGA package solder column damage matrix; perform solder column failure judgment based on the multi-chip CCGA package solder column damage matrix and obtain the risk level matrix of the multi-chip CCGA package solder column.

[0050] Specifically, S51: Use the Coffin-Manson thermal fatigue model and linear cumulative damage theory to calculate the damage amount of the solder column of the multi-chip CCGA package, which can be calculated by the following formula:

[0051] in, It is i Line j The accumulated damage of the weld column is It is i Line j Fatigue life of weld column, k is the number of thermal cycles; S52: Based on the calculated accumulated damage amounts, a damage matrix of the solder column of the multi-chip CCGA package is established as shown below D :

[0052] in, i It is the first in the multi-chip CCGA package i Welding column, j It is the first in the multi-chip CCGA package j Column welding, n is the total number of solder column rows in the multi-chip CCGA package, m is the total number of solder column columns in the multi-chip CCGA package, is the accumulated damage of the solder column in row 1 and column 1 of the multi-chip CCGA package. It is the first in the multi-chip CCGA package iLine j The accumulated damage of the weld column, It is the first in the multi-chip CCGA package n Line m The accumulated damage of the weld column, D The damage matrix of solder pillars for multi-chip CCGA packages; The cumulative damage matrix D of the solder column of the multi-chip CCGA package is shown in Table 5: Table 5 Accumulated damage matrix of weld column

[0053] Table 5

[0054] S53: Perform solder column failure determination according to the multi-chip CCGA package solder column damage matrix, and set For low risk, For medium risk, As high risk, a risk level matrix for multi-chip CCGA package solder pillars is established as shown below M ;

[0055] in, is the risk level of the solder column in row 1 and column 1 in a multi-chip CCGA package. It is the first in the multi-chip CCGA package i Line j The risk level of the weld column is listed as follows, It is the first in the multi-chip CCGA package n Line m The risk level of the weld column is listed as follows, M Risk level matrix for solder pillars in multi-chip CCGA packages.

[0056] The risk level matrix M of the solder pillars of multi-chip CCGA packages is shown in Table 6.

[0057] Table 6 Risk level matrix of welding column

[0058] Table 6

[0059] The purpose of this application is to overcome the fact that the prior art ignores the impact of actual working conditions on the risk assessment of solder column failure, and that the traditional single-chip model inference method is difficult to accurately assess the stress distribution and failure mechanism of the solder column in the multi-chip coupling scenario, and provides a multi-chip CCGA package solder column failure risk assessment method. This method uses the following technical means to achieve accurate analysis of the stress, strain, displacement distribution and potential failure points of the solder column under thermal cycles and other complex working conditions, and quantify the overall failure risk of the multi-chip CCGA package. First, a finite element analysis model for a multi-chip CCGA package is established, and information such as the chip, substrate, solder column and its material properties, geometric parameters, etc. are incorporated into the overall coupling analysis to achieve full-field simulation of the thermal-mechanical environment. This precise modeling of the multi-chip structure can more realistically reflect the actual packaging situation, so that the obtained thermal stress distribution of the solder column is more in line with the actual situation, avoiding the deviation caused by the traditional method using a single chip and uniform temperature assumptions. Secondly, the key parameters of thermal fatigue of the weld column are obtained, and the stress-strain amplitude of the weld column and the fatigue damage index required by the thermal fatigue model are extracted based on the simulation results, providing accurate data support for subsequent life prediction. Since multi-chip coupling and non-uniform thermal stress are taken into account, these parameters can more accurately reflect the fatigue characteristics of the weld column under actual working conditions. In addition, the thermal fatigue life model and cumulative damage theory are introduced to calculate the fatigue life and damage amount of different weld columns under non-uniformly distributed thermal stress, which can more carefully evaluate the damage of the weld column.

[0060] Through the above-mentioned technical means, the present application can quickly and accurately perform quantitative assessment of the failure risk of multi-chip CCGA package solder columns during the design stage and early verification, providing scientific technical support for the research and development and production of high-reliability electronic products.

[0061] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present application, and should be understood that the protection scope of the present application is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present application based on the technical revelations disclosed in the present application, and these variations and combinations are still within the protection scope of the present application.

Claims

1. A multi-chip CCGA package solder column failure risk assessment method, characterized in that: The method comprises: S1: Obtain geometric parameters and material parameters of a multi-chip CCGA packaging structure; S2: Establishing a finite element analysis model of a multi-chip CCGA package: establishing a geometric model of the multi-chip CCGA package structure based on the geometric parameters, and adding material parameters to the geometric model to form a finite element analysis model of the multi-chip CCGA package, wherein the geometric model is a plurality of chips, a ceramic substrate, a solder column array and a printed circuit board stacked sequentially from top to bottom, and the plurality of chips are laid side by side on the ceramic substrate; S3: Using the finite element analysis model, a coupling analysis is performed under non-uniform temperature loads: boundary conditions and constraints are applied to the constructed finite element analysis model, different operating temperature conditions are set for different chips, and thermal stress distribution of solder columns is simulated and obtained under thermal cycle loading conditions; S4: extract key data according to the finite element analysis model of the multi-chip CCGA package and the stress distribution of the solder column under the non-uniform distribution temperature, obtain the relevant fatigue parameters of the Coffin-Manson thermal fatigue model, calculate the fatigue life of the solder column by the Coffin-Manson thermal fatigue model formula, and determine the fatigue parameter life matrix of the solder column of the multi-chip CCGA package; S5: Perform risk assessment of non-uniform damage: Based on the Coffin-Manson thermal fatigue model and linear cumulative damage theory, calculate the damage amount of the solder column under non-uniformly distributed thermal stress and obtain the multi-chip CCGA package solder column damage matrix; perform solder column failure judgment based on the multi-chip CCGA package solder column damage matrix and obtain the risk level matrix of the multi-chip CCGA package solder column.

2. The method for evaluating the failure risk of solder pillars in a multi-chip CCGA package according to claim 1, characterized in that: In S2, the step of establishing a finite element analysis model of a multi-chip CCGA package includes: Creating a parametric geometric model of the multi-chip CCGA packaging structure based on finite element simulation: establishing a geometric model of each device according to the acquired geometric parameters of the components of the multi-chip CCGA packaging structure, assembling the geometric models of each device to form a geometric model of the multi-chip CCGA packaging structure; Specific material parameters are added to each device of the geometric model of the multi-chip CCGA packaging structure to form a meta-analysis model of the multi-chip CCGA packaging.

3. The multi-chip CCGA package solder column failure risk assessment method according to claim 1, characterized in that: In S3, the applied boundary condition is that the overall temperature of the element analysis model of the multi-chip CCGA package is set to the initial temperature , the maximum temperature is The imposed constraint is that the displacement constraint of the bottom foot point of the printed circuit board is zero, simulating the fixed installation method of the printed circuit board.

4. The method for evaluating the failure risk of solder pillars in a multi-chip CCGA package according to claim 1, characterized in that: The S4 includes: S41: Obtain the plastic strain amplitude of the weld column during the thermal cycle, which can be calculated by the following formula: in, is the plastic strain amplitude of the weld column during thermal cycling, is the thermal expansion coefficient of the solder column material, is the temperature variation amplitude of the thermal cycle; S42: The fatigue life of the weld column is calculated using the Coffin-Manson thermal fatigue model formula. i Line j Fatigue life of solder pillars in multi-chip CCGA packages , the calculation formula is as follows: in, It is i Line j The plastic strain amplitude of the solder column of the multi-chip CCGA package is shown in Figure 2. It is i Line j The material fatigue onset strain amplitude of the solder column of the multi-chip CCGA package is shown in the figure. It is i Line j The Coffin-Manson constants of the material of the multi-chip CCGA package solder pillars; S43: Based on the calculated fatigue parameters of each welding column, the following formula is constructed: i Line j The fatigue parameter life matrix of the column weld is listed; S44: establishing a fatigue parameter life matrix of solder pillars for a multi-chip CCGA package as shown below based on the calculated fatigue parameter life matrix of each solder pillar; in, K is the fatigue parameter life matrix of solder pillars in multi-chip CCGA package, i It is the first in the multi-chip CCGA package i Welding column, j It is the first in the multi-chip CCGA package j Welding column, n is the total number of solder column rows in the multi-chip CCGA package, m is the total number of solder column columns in the multi-chip CCGA package, is the fatigue parameter life matrix of the solder column in row 1 and column 1 in the multi-chip CCGA package, It is the first in the multi-chip CCGA package i Line j The fatigue parameter life matrix of the weld column is: It is the first in the multi-chip CCGA package n Line m Fatigue parameter life matrix of the column weld.

5. The multi-chip CCGA package solder column failure risk assessment method according to claim 1, characterized in that: The step of obtaining a multi-chip CCGA package solder column damage matrix includes: S51: The Coffin-Manson thermal fatigue model and linear cumulative damage theory are used to calculate the damage amount of the solder column of the multi-chip CCGA package, which can be calculated by the following formula: in, It is i Line j The accumulated damage of the weld column is It is i Line j Fatigue life of weld column, k is the number of thermal cycles; S52: Based on the calculated accumulated damage amounts, a damage matrix of the solder column of the multi-chip CCGA package is established as shown below D ; in, i It is the first in the multi-chip CCGA package i Welding column, j It is the first in the multi-chip CCGA package j Welding column, n is the total number of solder column rows in the multi-chip CCGA package, m is the total number of solder column columns in the multi-chip CCGA package, is the accumulated damage of the solder column in row 1 and column 1 of the multi-chip CCGA package. It is the first in the multi-chip CCGA package i Line j The accumulated damage of the weld column, It is the first in the multi-chip CCGA package n Line m The accumulated damage of the weld column, D The damage matrix of solder pillars for multi-chip CCGA packages; S53: Perform solder column failure determination according to the multi-chip CCGA package solder column damage matrix, and set For low risk, For medium risk, As high risk, a risk level matrix for multi-chip CCGA package solder pillars is established as shown below M ; in, is the risk level of the solder column in row 1 and column 1 in a multi-chip CCGA package. It is the first in the multi-chip CCGA package i Line j The risk level of the weld column is listed as follows, It is the first in the multi-chip CCGA package n Line m The risk level of the weld column is listed as follows, M Risk level matrix for solder pillars in multi-chip CCGA packages.

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