Hybrid precision storage and calculation control circuit based on Sense-Switch type pFLASH

Abstract

The invention discloses a hybrid precision storage and calculation control circuit based on a Sense-Switch type pFLASH. The hybrid precision storage and calculation control circuit comprises an NOR FLASH type SSpF storage and calculation array, a hybrid precision array controller, a hybrid precision shift adder and an AD module. The NOR FLASH type SSpF storage and calculation array is used for realizing convolution operation; the mixed precision array controller divides the NOR FLASH type SSpF memory calculation array according to the configured calculation precision, and completes input control and output sampling of 4, 8 or 16-bit convolution operation, and 4-bit weight programming and reading; the mixing precision shift adder performs shift addition on the output of the mixing precision array controller according to the sequence and the channel according to the configured calculation precision to obtain a 4, 8 or 16-bit convolution calculation result; the AD module is used for converting current output of the NOR FLASH type SSpF storage array into voltage output and converting an analog signal into a 4-bit digital signal. According to the method, 4, 8 or 16-bit convolution calculation can be realized in parallel, and the calculation precision can be configured.

Description

Technical Field

[0001] The present invention relates to the technical field of very large scale integrated circuits, and in particular to a mixed precision storage and calculation control circuit based on a Sense-Switch type pFLASH. Background Art

[0002] As the amount of computing required for edge AI chips surges, solving computing energy efficiency issues and enhancing local processing capabilities have become key. The traditional von Neumann architecture leads to "storage wall" and "power wall" problems due to the separation of storage and computing, while the in-memory computing architecture has great advantages in energy efficiency due to the integration of computing and storage.

[0003] This concept was first proposed in the 1990s and began to receive more widespread attention and research in the 2010s. Compared with near-memory computing, in-memory computing performs computing operations directly in memory, which can significantly reduce data transmission time. Because computing and storage are performed in the same location, data movement between memory and processor is reduced, and the performance of processing big data and complex calculations is greatly improved. In addition, in-memory computing is compatible with existing memory architectures and can be used in combination with a variety of processors to improve system flexibility.

[0004] According to the signal type, the storage and computing architecture can be divided into three categories, namely analog storage and computing architecture, digital storage and computing architecture, and digital-analog hybrid storage and computing architecture. Among them, the digital storage and computing architecture is characterized by performing computing operations in digital circuits. The digital computing precision and accuracy of the calculation results are higher, so this advantage can be used to implement complex computing operations, but the disadvantages are high hardware design complexity, high power consumption, and the need for additional power supply and heat dissipation design; the analog storage and computing architecture uses analog circuits to perform computing operations. Its advantages are low hardware design complexity and low energy consumption, so the system performance is greatly improved. However, due to the poor stability of analog devices and the sensitivity of analog circuits to changes in environmental conditions, the calculation precision and accuracy of analog storage are low. In order to maintain the accuracy of calculations, it is necessary to consider the circuit stability under various environmental conditions; the digital-analog hybrid storage and computing architecture combines the characteristics of analog and digital circuits, combines analog and digital computing units together, and realizes hybrid computing functions. This type of architecture takes into account the accuracy of digital computing and the efficiency of analog computing, and can flexibly select analog or digital computing units to perform computing operations according to specific application requirements. Its design complexity is higher, and the interface and signal conversion issues between analog and digital computing units need to be considered. There are few existing studies.

[0005] Since the analog storage and computing architecture has low power consumption, combined with the advantages of large-scale integration of SSpF devices, it can significantly improve performance, reduce energy consumption and cost. However, FLASH storage and computing chips still have problems in design flexibility: it is difficult to adapt to different computing precision requirements. Summary of the invention

[0006] The object of the present invention is to provide a mixed precision storage and calculation control circuit based on Sense-Switch type pFLASH to solve the problems in the background technology.

[0007] In order to solve the above technical problems, the present invention provides a mixed precision storage and calculation control circuit based on Sense-Switch type pFLASH, comprising: The NOR FLASH type SSpF storage and calculation array is used to implement convolution operations, and is composed of reconfigurable differential Sense-Switch type pFLASH storage and calculation units. The reconfigurable differential Sense-Switch type pFLASH storage and calculation units support 4-bit signed weight storage and implement 4-bit signed multiplication operations. The mixed precision array controller is composed of a state machine, a configurable register, a counter, a WL decoder and a BL decoder. It divides the NOR FLASH type SSpF storage array according to the configured calculation precision, completes the input control and output sampling of 4, 8 or 16-bit convolution operations, and 4-bit weight burning and reading; The mixed precision shift adder is composed of a sequence shift adder, a channel shift adder, a state machine and a configuration register. The output of the mixed precision array controller is added in sequence and channel shift according to the configured calculation accuracy to obtain a 4, 8 or 16-bit convolution calculation result; The AD module is composed of a current-voltage conversion circuit and an analog-to-digital conversion circuit, which can convert the current output of the NOR FLASH type SSpF storage array into a voltage output and convert the analog signal into a 4-bit digital signal.

[0008] In one embodiment, the reconfigurable differential Sense-Switch pFLASH storage unit is a differential structure formed by two Sense-Switch pFLASH devices, and a single Sense-Switch pFLASH device is a three-terminal FLASH device including a bit line BL, a source line SL, and a word line WL, wherein the BL terminal is an input terminal, the WL terminal is a selection terminal, and the SL terminal is an output terminal; No. i The output current of the line is expressed as: in, For the i OK j The equivalent conductance of the Sense-Switch pFLASH device is shown in Figure 2. For the jThe input voltage of the column is used to realize multiplication and accumulation operation in parallel for each row; the IV characteristics of the device working in the linear region are used: is the carrier mobility, is the oxide layer capacitance, is the aspect ratio of the device, is the gate-source voltage, is the threshold voltage, is the drain-source voltage.

[0009] Based on this formula, the output current of the SL terminal under the differential structure eliminates the second-order term in the original formula: For the i Line j Column positive weight current, For the i Line j Column negative weight current, For the j The positive weighted input voltage, For the j The input voltage of the column is negative weighted. Considered as input voltage, the input is changed by changing the voltage value of BL terminal; As the signed conductivity G ij , the conductance is changed by changing the threshold voltage: G ij .

[0010] In one embodiment, the mixed-precision array controller configures the calculation precision and divides the NOR FLASH type SSpF storage array: when 4-bit calculation precision is configured, no division is performed; when 8-bit calculation precision is configured, the word line WL of the array is divided into two parts, and the upper 4 bits and the lower 4 bits are calculated respectively; when 16-bit calculation precision is configured, the word line WL of the array is divided into four parts, and each part calculates 4 bits, and the erasing, weight burning and reading of the NOR FLASH type SSpF storage array are completed through the APB protocol.

[0011] In one embodiment, the mixed precision shift adder configures the calculation precision and performs shift and addition operations on the output results of the mixed precision array controller: the serial shift adder shifts and adds the storage results of each input periodically, and controls the number of shift bits and the number of additions through a counter; the channel shift adder combines the mixed precision array controller to divide the NOR FLASH type SSpF storage matrix, shifts and adds the results of the same output channel according to the configured precision and outputs the results.

[0012] The present invention provides a mixed-precision storage and calculation control circuit based on Sense-Switch type pFLASH, which supports configurable calculation precision through mixed-precision array controller and shift adder design, realizes 4, 8 or 16-bit convolution calculation, and can be applied to a mixed-precision in-memory calculation core architecture based on SSpF to realize 4, 8 or 16-bit convolution calculation in parallel, and the calculation precision is configurable. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a diagram of the architecture of the SSpF-based mixed-precision storage and calculation control circuit provided by the present invention.

[0014] Figure 2 This is a structural diagram of the NOR FLASH type SSpF storage and computing array provided by the present invention.

[0015] Figure 3 This is a timing diagram of weight writing and erasing of the mixed precision array controller provided by the present invention.

[0016] Figure 4 This is a timing diagram of the mixed precision array controller weight reading provided by the present invention.

[0017] Figure 5 This is a timing diagram of the weight storage and calculation of the mixed precision array controller provided by the present invention.

[0018] Figure 6 A schematic diagram of a mixed-precision storage and computing array partitioning method provided by the present invention.

[0019] Figure 7 This is a flow chart of the mixed precision algorithm provided by the present invention.

[0020] Figure 8 This is a structural diagram of the mixed-precision shift adder provided by the present invention. DETAILED DESCRIPTION

[0021] The following is a further detailed description of a mixed precision storage and calculation control circuit based on a Sense-Switch type pFLASH proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0022] The present invention provides a mixed precision storage and calculation control circuit based on Sense-Switch type pFLASH, and its overall architecture is as follows: Figure 1As shown, it includes a NOR FLASH type SSpF storage array, a mixed precision array controller, a mixed precision shift adder and an AD module. Among them, the NOR FLASH type SSpF storage array is composed of a reconfigurable differential Sense-Switch type pFLASH (SSpF) storage unit, which is used to implement convolution operations; the mixed precision array controller inputs the input data in the form of a bit stream, and inputs a single bit in each cycle from low to high order to the NOR FLASH type SSpF storage array. The NOR FLASH type SSpF storage array outputs the current obtained by multiplication and accumulation to the AD module. The AD module converts the analog signal into a digital signal after current conversion to voltage, and transmits the digital signal to the mixed precision array controller. The mixed precision array controller samples the calculation results according to the output timing of the ADC in the AD module, and outputs it to the mixed precision shift adder. In addition, the mixed precision array controller can realize the burning and reading of weights and the erasure of the array by the APB protocol. The following will describe each module in detail.

[0023] The weights in the convolutional neural network can be replaced by the number of charges written to the SSpF. When it works as a synapse, information is transmitted from the drain to the source. In addition, multiple units connected in parallel to the same gate control line can be regarded as a neuron to complete multiplication and accumulation operations. An SSpF can be regarded as a three-terminal FLASH device containing BL, SL, and WL. BL is connected to the drain of FLASH, WL is connected to the control gate terminal of FLASH, and SL is connected to the source of FLASH. When inputting data, FLASH has two working areas corresponding to different input methods: inputting data from the BL terminal and inputting data from the WL terminal.

[0024] When FLASH works in the linear region, its current is: in, is the carrier mobility, is the oxide layer capacitance, is the aspect ratio of the device, is the gate-source voltage, is the drain-source voltage, is the threshold voltage; based on this formula, the read current at the SL end is the product of the two minus a second-order term, and the second-order term cannot be ignored. When two SSpFs form a differential structure, the two currents are subtracted, and the second-order term of the original formula is eliminated, ensuring linearity. In addition, the weight can be represented by the difference of a set of SSpF threshold voltages, which can be expressed as a positive or negative number.

[0025] The following table shows the IV characteristic relationship and read current range of SSpF in different working ranges.

[0026] As can be seen from the table, when the device works in the subthreshold region, the read current range is smaller, so the power consumption is smaller, but the derived formula includes logarithmic operations, which makes the calculation more complex. When the device works in the deep linear region, the voltage range that meets the conditions is smaller, and the drain-source current I DS and drain-source voltage V DS The approximate linear relationship leads to errors in the calculation results, and additional circuit design is required for correction. When the device works in the linear region, the second-order term in the IV formula can be offset by differential design to obtain a linear relationship. Compared with the first two solutions, the calculation error is smaller and the calculation complexity is lower.

[0027] The present invention adopts a NOR FLASH type SSpF storage array as a storage simulation array, and its structure is as follows: Figure 2 As shown, each BL is connected to the drain of each row of FLASH, each WL is connected to the control gate of each column, and each SL is connected to the source of each column. The following is a specific derivation of the vector-matrix multiplication. The known vector-matrix multiplication formula is: The voltage amplitude input method is used to perform vector-matrix multiplication and the current is passed through the conductance G L Convert current to voltage (IVC circuit). Both the input vector X and the output vector Y are voltage signals, and the vector-matrix multiplication is: Conductivity G ij The threshold voltage of FLASH is changed by programming and erasing for storage. The output current of a single device is accumulated based on the NOR FLASH array and Kirchhoff's current law. i The total current of the line I oi and input voltage V j The relationship can be expressed as: When working in the linear region, set W ij = W i+j W i-j , W i+j Indicates i Line j The forward weight value of the column; W i - j Indicates i Line j The negative weight value of the column has the following formula: in, For the i Line j Column positive weight current, For the i Line j Column negative weight current, For the j The positive weighted input voltage, For the j The negative weighted input voltage, is the carrier mobility, is the oxide layer capacitance, is the aspect ratio of the device, For the i Row gate-source voltage, For the i Line j Column positive weight drain-source voltage, For the i Line j Column negative weight drain-source voltage; And meet the conditions: For the i Line j Column drain-source voltage, For the i Row negative weight gate-source voltage, For the i Row positive weight gate-source voltage, Then the output current of the differential SSpF storage unit can be obtained as: at this time can be regarded as the input voltage, that is , the input can be changed by changing the voltage value of the BL terminal. Can be regarded as the conductivity G ij , the conductance can be changed by changing the threshold voltage.

[0028] The main function of the mixed precision array controller is to output the digital signal to the NORFLASH type SSpF storage array according to the timing required by the analog circuit, and at the same time receive the digital signal output by the ADC and perform corresponding processing. In order to save the DAC circuit to reduce the design complexity, the present invention adopts a bit stream input method. For example, if you want to achieve 4-bit input accuracy, you need to input the data in 4 clock cycles, and input 1 bit in each clock cycle. At this time, the output result of the NOR FLASH type SSpF storage array cannot be directly transmitted to the operator module, but a shift accumulation operation is performed. The output of the 0th cycle remains unchanged, and the output result of the 1st cycle corresponds to the 1st input data. It needs to be shifted left by 1 bit and accumulated with the result of the 0th cycle, and so on. After 4 cycles, the final accumulation result is obtained.

[0029] In order to realize the configurability of information such as calculation accuracy, storage delay, write and erase pulse width, the designed digital circuit is divided into three modules, namely, configuration register module, read-write-erase control module and storage control module. Correspondingly, the control circuit of the present invention has three states, namely, configuration register state, write, erase and read weight state, and storage state.

[0030] The configuration register is written by APB when configuring parameters. After completing parameter configuration, write, erase and read weight instructions can be sent through APB. The addresses of erase and write are different. The write operation needs to enter the address of the corresponding FLASH unit, and only a fixed address is needed for erase. According to the requirements of the analog circuit, the BL and WL ends need to design corresponding decoding circuits. In addition, multiple buffer signals are required before starting the analog array. The write and erase timing design is as follows: Figure 3 As shown, Figure 3 A signal delay and hold counter configuration scheme is given in , where WRITE represents the weight writing state, ERASE represents the erase state, and IDLE represents the initial state. The read operation needs to be coordinated with the output timing of the AD module. The sampling time is controlled by increasing the counter. When the ADC output in the AD module is valid, the data is transmitted to the prdata port of the APB. The read timing design of the mixed precision array controller is as follows Figure 4 As shown, READ represents the read weight status.

[0031] In the storage and calculation state, the input data is continuously input in multiple cycles. For example, when the calculation accuracy is 8 bits, it needs to be input in 8 cycles. The mixed precision array controller shifts the upstream data internally. During this period, the upstream handshake signal ready_o is pulled low until the storage and calculation are completed. The timing design is as follows: Figure 5 As shown. Among them, BLEN is input to the analog array, is the BL terminal selection signal, and CIM represents the storage and calculation state. The control circuit of the present invention transmits the array output result to the downstream shift-add circuit.

[0032] The mixed precision implementation method of weights is to divide the NOR FLASH type SSpF storage and calculation array. For example, if the scale of the simulation array is 2j*i, that is, 2j WL ends and i BL ends, each NOR FLASH type SSpF storage and calculation unit stores 4-bit precision weights. When the calculation precision is configured to 4, the array does not need to be divided. When the calculation precision is configured to 8, the array is divided into two blocks, the first j rows are responsible for the low 4-bit calculation, and the last j rows are responsible for the high 4-bit calculation. Similarly, when the calculation precision is 16, the array is divided into 4 blocks, each with 64 rows and responsible for 4-bit calculation in order of high and low. Figure 6 This shows how the matrix is ​​divided when the precision is configured to 8.

[0033] Figure 7 Taking a 4-bit weight storage to realize 8*8-bit operation as an example, the mixed-precision operation process is demonstrated through bit stream input, sequence shift adder and channel shift adder. Therefore, by changing the value of the configuration register, shift accumulation operations of different precisions can be realized. In order to ensure the stability of the calculation process, only the state is allowed to change in the configuration parameter stage, and the state remains unchanged in the storage state. The shift adder is divided into two parts: the sequence shift adder and the channel shift adder. The internal structure is shown in Figure 8 Among them, the number of sequence shift adders is the same as the number of WLs in the storage array. The storage result of each bit is calculated in parallel, and the number of shift bits and additions are controlled by the counter. Therefore, the output of the sequence shift adder is the complete storage result of each WL end. If mixed precision is to be achieved, it is also necessary to combine the matrix partitioning method and perform shift addition on the results of the same output channel according to the precision configuration.

[0034] IVC (Integrate-and-Voltage Converter) is a circuit that converts an input current signal into a corresponding voltage signal. The IVC module has two functions: (1) clamping the voltage of the FLASH storage array source lines SLP and SLN, and providing the storage array with the required storage current; (2) converting the computing current of the FLASH storage array into voltage and converting it into a digital code by the ADC. In this structure, the source lines SLP and SLN of the FLASH storage array are clamped through the negative input terminal of the op amp, and the current flowing through the source line is converted through a resistor to convert the current into a corresponding voltage signal. Subsequently, the converted voltage signal is sent to the back-end ADC for quantization, thereby achieving accurate data sampling and processing. The differential expression of the signal output by the IVC is: The ADC circuit (Analog to Digital Converter) is an important component for converting analog signals into digital signals. Its working principle is as follows: (1) Sampling and quantization: The ADC circuit first samples the input continuous analog signal and quantizes it into discrete digital values. This process usually includes two steps: time sampling and amplitude quantization, ensuring that each instantaneous value of the analog signal can be accurately captured. (2) Encoding: After completing sampling and quantization, the ADC converts the quantized value into binary code and outputs a digital signal for subsequent digital circuit processing.

[0035] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A mixed precision storage and calculation control circuit based on Sense-Switch type pFLASH, characterized in that: It includes a NORFLASH type SSpF storage and calculation array, a mixed precision array controller, a mixed precision shift adder and an AD module; The NOR FLASH type SSpF storage and calculation array is used to implement convolution operations, and is composed of reconfigurable differential Sense-Switch type pFLASH storage and calculation units. The reconfigurable differential Sense-Switch type pFLASH storage and calculation units support 4-bit signed weight storage and implement 4-bit signed multiplication operations. The mixed precision array controller is composed of a state machine, a configurable register, a counter, a WL decoder and a BL decoder. It divides the NOR FLASH type SSpF storage array according to the configured calculation precision, completes the input control and output sampling of 4, 8 or 16-bit convolution operations, and 4-bit weight burning and reading; The mixed precision shift adder is composed of a sequence shift adder, a channel shift adder, a state machine and a configuration register. The output of the mixed precision array controller is added in sequence and channel shift according to the configured calculation accuracy to obtain a 4, 8 or 16-bit convolution calculation result; The AD module is composed of a current-voltage conversion circuit and an analog-to-digital conversion circuit, which can convert the current output of the NOR FLASH type SSpF storage array into a voltage output and convert the analog signal into a 4-bit digital signal.

2. The mixed precision storage and calculation control circuit based on Sense-Switch type pFLASH according to claim 1, characterized in that: The reconfigurable differential Sense-Switch pFLASH storage unit is a differential structure composed of two Sense-Switch pFLASH devices. A single Sense-Switch pFLASH device is a three-terminal FLASH device including a bit line BL, a source line SL, and a word line WL. The BL terminal is an input terminal, the WL terminal is a selection terminal, and the SL terminal is an output terminal. No. i The output current of the line is expressed as: in, For the i OK j The equivalent conductance of the Sense-Switch pFLASH device is shown in Figure 2. For the j The input voltage of the column is used to realize multiplication and accumulation operation in parallel for each row; the IV characteristics of the device working in the linear region are used: is the carrier mobility, is the oxide layer capacitance, is the aspect ratio of the device, is the gate-source voltage, is the threshold voltage, is the drain-source voltage; Based on this formula, the output current of the SL terminal under the differential structure eliminates the second-order term in the original formula: For the i Line j Column positive weight current, For the i Line j Column negative weight current, For the j The positive weighted input voltage, For the j The input voltage of the column is negative weighted. Considered as input voltage, the input is changed by changing the voltage value of BL terminal; As a signed conductivity G ij , the conductance is changed by changing the threshold voltage: G ij .

3. The mixed precision storage and calculation control circuit based on Sense-Switch type pFLASH as claimed in claim 2, characterized in that: The mixed precision array controller configures the calculation precision and divides the NOR FLASH type SSpF storage array: when the 4-bit calculation precision is configured, no division is performed; when the 8-bit calculation precision is configured, the word line WL of the array is divided into two parts, and the upper 4 bits and the lower 4 bits are calculated respectively; when the 16-bit calculation precision is configured, the word line WL of the array is divided into four parts, and each part calculates 4 bits. The erasing, weight burning and reading of the NOR FLASH type SSpF storage array are completed through the APB protocol.

4. The mixed precision storage and calculation control circuit based on the Sense-Switch type pFLASH as claimed in claim 3, characterized in that: The mixed precision shift adder configures the calculation precision and performs shift and addition operations on the output results of the mixed precision array controller: the sequence shift adder shifts and adds the storage calculation results of each input in a cycle, and controls the shift bit number and the number of additions through a counter; the channel shift adder combines the mixed precision array controller to divide the NOR FLASH type SSpF storage calculation matrix, and performs shift addition on the results of the same output channel according to the configured precision and outputs the results.

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