Wafer defect detection method, device, equipment, storage medium and program product

Abstract

The invention discloses a wafer defect detection method, device and equipment, a storage medium and a program product, relates to the technical field of image recognition, and aims to solve the problems that the common pooling operation in the current algorithm loses defect details, so that the fitting capability of the current algorithm on slender shape defects in a wafer defect graph is limited, and the detection efficiency is low. In order to solve the problem of low wafer defect detection accuracy caused by the fact that a wafer defect is detected in the prior art, the invention provides a wafer defect detection method which comprises the following steps: acquiring a first wafer picture, and identifying the first wafer picture through a preset first defect identification model to obtain a wafer defect identification result; according to the method, the cavity convolution module is arranged in the model, so that the receptive field of the convolution kernel is improved, values in a preset range are skipped during convolution, the situation that the resolution of the feature map is reduced due to convolution of excessive elements is avoided, the fitting capacity of the thin and long shape defects in the wafer is improved by capturing information in a larger range, and the fitting precision of the thin and long shape defects in the wafer is improved. Therefore, the wafer defect detection accuracy is improved.

Description

Technical Field

[0001] The present application relates to the field of image recognition technology, and in particular to a wafer defect detection method, device, equipment, storage medium and program product. Background Art

[0002] ‌Wafer manufacturing is a vital part of the modern electronics industry. As the demand for wafers in the semiconductor industry continues to increase, timely detection and accurate identification of wafer defects becomes increasingly important.

[0003] Currently, wafer defects are usually detected through target detection algorithms. There are long and slender defects in wafer defects, and the detection algorithm is required to capture the global information of the long and slender defects. However, the pooling operation commonly used in the current algorithm will lose the defect details, which makes the current target detection algorithm have limited fitting ability for the long and slender defects in the wafer defect map, resulting in missed detection and false detection during wafer defect detection, which in turn leads to low detection accuracy of wafer defects. Summary of the invention

[0004] The main purpose of this application is to provide a wafer defect detection method, device, equipment, storage medium and program product, aiming to solve the technical problem of low wafer defect detection accuracy.

[0005] To achieve the above objectives, the present application proposes a wafer defect detection method, the method comprising: Get the first wafer image; The first wafer image is identified by a preset first defect recognition model to obtain a first recognition result, wherein the first recognition result includes a defect category of the corresponding wafer or a corresponding wafer without defects, and the first defect recognition model has a hole convolution module, and the hole convolution module skips values ​​within a preset range during convolution operation to expand the receptive field of the convolution kernel in the first defect recognition model without reducing the resolution of the feature map obtained by convolving the first wafer image.

[0006] In one embodiment, before the step of obtaining the first wafer image, the method further includes: Get wafer sample images; Based on a plurality of dilated convolution modules with different dilated rates in the model to be trained, feature extraction is performed on the wafer sample image to obtain a multi-scale feature map; Based on the multi-scale feature map and the classification module of the model to be trained, wafer defect recognition is performed to obtain a defect recognition result; Based on the defect recognition result, the parameters of the model to be trained are adjusted to obtain a first defect recognition model.

[0007] In one embodiment, the step of extracting features from the wafer sample image based on the dilated convolution modules with multiple different dilated rates in the model to be trained to obtain multi-scale features includes: Based on multiple void convolution modules with different void rates in the model to be trained, feature extraction is performed on the wafer sample images respectively to obtain void feature maps of different scales; Performing a pooling operation on the wafer sample image to obtain a pooling feature map; Based on the feature map channels respectively corresponding to each of the hole feature maps and the pooled feature map, splicing each of the hole feature maps and the pooled feature map to obtain a spliced ​​feature map; The concatenated feature map is convolved point by point to obtain a multi-scale feature map.

[0008] In one embodiment, the first wafer image is composed of a plurality of second wafer images, the second wafer images are obtained by imaging the same wafer using different imaging methods, and the first defect recognition model includes a plurality of second defect recognition models for recognizing the second wafer images; The step of identifying the first wafer image by using a preset first defect recognition model to obtain a first recognition result includes: Determining a corresponding second defect recognition model based on an imaging type identification of each of the second wafer images, wherein the imaging type identification is used to identify the second wafer image based on the imaging type when performing an imaging operation; Based on each of the second defect recognition models, each of the second wafer images is recognized respectively to obtain a second recognition result corresponding to each of the second wafer images, wherein the second recognition result includes a defect category of the corresponding wafer or a corresponding wafer having no defects; The second recognition results are aggregated to obtain a first recognition result.

[0009] In one embodiment, the step of aggregating the second recognition results to obtain the first recognition result includes: Based on each of the second recognition results, determining whether there is a same wafer defect; If so, the same wafer defect is regarded as the first wafer defect, and the remaining wafer defects are regarded as the second wafer defects; Based on the geometric parameters of each of the first wafer defects, determining one of the wafer defects as a second wafer defect from a plurality of identical wafer defects corresponding to each of the first wafer defects; The second wafer defects are summarized to obtain a first recognition result.

[0010] In one embodiment, the second recognition result further includes the origin coordinates of the corresponding wafer defect, and the step of determining whether the same wafer defect exists based on each of the second recognition results includes: Based on each of the second identification results, determining whether there are wafer defects of the same type; If so, calculating the difference between the origin coordinates of the wafer defects of the same type; If the difference is within a preset difference range, it is determined that the wafer defects of the same type are the same wafer defects.

[0011] In addition, to achieve the above-mentioned purpose, the present application also proposes a wafer defect detection device, the wafer defect detection device comprising: An image acquisition module, used to acquire the first wafer image; A defect recognition module is used to identify the first wafer image through a preset first defect recognition model to obtain a first recognition result, wherein the first recognition result includes the defect category of the corresponding wafer or the corresponding wafer is defect-free, and the first defect recognition model has a hole convolution module, and the hole convolution module skips values ​​within a preset range during the convolution operation, so as to expand the receptive field of the convolution kernel in the first defect recognition model while not reducing the resolution of the feature map obtained by convolving the first wafer image.

[0012] In addition, to achieve the above-mentioned purpose, the present application also proposes a wafer defect detection device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, and the computer program is configured to implement the steps of the wafer defect detection method described above.

[0013] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by the processor, the steps of the wafer defect detection method described above are implemented.

[0014] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps of the wafer defect detection method described above are implemented.

[0015] One or more technical solutions proposed in this application have at least the following technical effects: The present application obtains a first wafer image, identifies the first wafer image through a preset first defect recognition model, and obtains a first recognition result, wherein the first recognition result includes a defect category of the corresponding wafer or the corresponding wafer is defect-free.

[0016] The hole convolution module in the model of the present application skips the values ​​within the preset range during the convolution operation. Therefore, for the convolution kernel of the same size, the present application can convolve elements in a larger range, thereby improving the receptive field of the convolution kernel in the first defect recognition model. Moreover, since the values ​​within the preset range are skipped during the convolution, the reduction in feature map resolution caused by convolution of too many elements is avoided. Therefore, the present application can improve the fitting ability of slender defects in wafers, thereby improving the detection accuracy of wafer defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0019] Figure 1 A schematic diagram of a process flow provided for Embodiment 1 of the wafer defect detection method of the present application; Figure 2 A schematic diagram of a first scenario provided in Example 1 of the wafer defect detection method of the present application; Figure 3 A schematic diagram of a second scenario provided in Example 1 of the wafer defect detection method of the present application; Figure 4 A schematic diagram of a third scenario provided in Embodiment 1 of the wafer defect detection method of the present application; Figure 5 A schematic diagram of a fourth scenario provided in Embodiment 1 of the wafer defect detection method of the present application; Figure 6 A fifth scenario schematic diagram provided for the first embodiment of the wafer defect detection method of the present application; Figure 7 A sixth scenario schematic diagram provided for the first embodiment of the wafer defect detection method of the present application; Figure 8 A schematic diagram of a process flow provided for Embodiment 2 of the wafer defect detection method of the present application; Fig. 9 A schematic diagram of a scenario provided for Embodiment 2 of the wafer defect detection method of the present application; Fig.10 A schematic diagram of a process flow provided for Embodiment 3 of the wafer defect detection method of the present application; Fig.11 This is a schematic diagram of the module structure of a wafer defect detection device according to an embodiment of the present application; Fig.12 Schematic diagram of the device structure of the hardware operating environment involved in the wafer defect detection method in the embodiment of the present application.

[0020] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0021] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0022] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0023] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device capable of realizing the above functions, a wafer defect detection device, etc. The following takes a wafer defect detection device as an example to illustrate this embodiment and the following embodiments.

[0024] Based on this, the present application embodiment provides a wafer defect detection method, referring to Figure 1 , Figure 1 This is a flow chart of the first embodiment of the wafer defect detection method of the present application.

[0025] In this embodiment, the specific application scenario may be: After the wafer is manufactured, the defects of the manufactured wafer can be detected through the target detection algorithm, so as to avoid the wafer from having a greater impact on the quality and performance of electronic devices. However, the current target detection algorithm has the problem of insufficient receptive field of the convolution kernel, or low resolution of the feature map obtained after convolution, which makes the current target detection algorithm have limited fitting ability for slender shape defects in the wafer defect map, and there are missed detections and false detections when performing wafer defect detection, resulting in low detection accuracy of wafer defects. Therefore, the application scenario of this embodiment is mainly the scenario of accurate detection of wafer defects in the wafer manufacturing industry.

[0026] In this embodiment, the wafer defect detection method includes steps S10 to S20: Step S10, obtaining a first wafer image; It should be noted that the first wafer image is a collection of multiple wafer images, and the multiple wafer images are obtained by imaging the same wafer using different imaging methods.

[0027] It is understandable that in this embodiment, wafer defects are detected by a target detection algorithm. The target detection algorithm usually identifies objects of a specific category (that is, wafer defects in this embodiment) in an image or video. Therefore, in order to identify wafer defects, it is necessary to first obtain the corresponding first wafer image.

[0028] It should also be noted that the wafer defect detection of this embodiment can be automatically controlled by software. The interface of the software is shown in FIG. Figure 2 Before obtaining the first wafer image, the wafer will be placed by a wafer robot, and the position and size of the wafer will be determined by a wafer edge finder.

[0029] The wafer robot is an automated device used to achieve high-precision and high-efficiency wafer placement. It can be driven directly without a deceleration mechanism, thus providing excellent rigidity and motion stability, greatly improving the factory's production efficiency and precision while reducing labor costs. The wafer robot is designed with an embedded controller, which simplifies the installation and debugging process and reduces the need for additional controller settings and wiring space.

[0030] The wafer edge finder determines the precise position and size of the wafer by scanning the edge of the wafer. The wafer edge finder contains optical sensors and signal processors. The optical sensors are used to detect the light reflected from the surface of the wafer and transmit the signal to the signal processor for processing. The signal processor analyzes the signal, determines the position and size of the wafer, and sends instructions to other devices for operation. For the specific process of wafer placement and edge finding, refer to Figure 3 .

[0031] Step S20, identifying the first wafer image through a preset first defect recognition model to obtain a first recognition result, wherein the first recognition result includes the defect category of the corresponding wafer or the corresponding wafer is defect-free, and the first defect recognition model has a hole convolution module, and the hole convolution module skips values ​​within a preset range during the convolution operation to expand the receptive field of the convolution kernel in the first defect recognition model while not reducing the resolution of the feature map obtained by convolving the first wafer image.

[0032] It should be noted that the first defect recognition model can be a model obtained based on any target detection algorithm. In this embodiment, the target detection algorithm is the YOLOv8 algorithm (You Only Look Once version 8). The first defect recognition model obtained by the YOLOv8 algorithm can accurately detect defects on wafers.

[0033] The defect categories of wafers are different types of defects generated due to different reasons during the wafer manufacturing process. This embodiment uses a dilated convolution module to better fit the elongated defects in each defect category. The dilated convolution module skips certain input positions in the convolution operation to perform convolution on a larger area. In this embodiment, the values ​​within the preset range are the values ​​of the input positions that need to be skipped, and the specific preset range is determined by the dilated convolution rate.

[0034] The dilation rate is the size of the interval between the convolution kernel elements when performing dilation convolution. When the dilation rate is 1, the dilation convolution is equivalent to the standard convolution. When the dilation rate is greater than 1, the dilation convolution will skip some values ​​based on the dilation rate.

[0035] Specifically, if the size of the convolution kernel is 3×3 and the void ratio is 2, the interval size between the convolution kernel elements is 1, which is equivalent to convolving some elements within the range of 5×5; if the size of the convolution kernel is 3×3 and the void ratio is 3, the interval size between the convolution kernel elements is 2, which is equivalent to convolving some elements within the range of 7×7.

[0036] It is understandable that the wafers produced by manufacturing may have long and thin defects, and such long and thin defects require the model to learn the details of the defects. The YOLOv8 algorithm performs a fast pyramid pooling operation (pooling operations are performed at multiple scales and the results are connected as inputs to subsequent layers), and the downsampling of the pooling will lose the details of the defects. Therefore, in order to enable the model to better learn the details of the long and thin defects, this embodiment does not use the fast pyramid pooling operation that the YOLOv8 algorithm usually uses, but extracts the feature map through a dilated convolution.

[0037] For long and thin defects in wafer defects, smaller convolution kernels will not be able to fully learn the long and thin defects due to insufficient receptive field, while larger convolution kernels will convolve too many elements, resulting in reduced resolution of the extracted feature map (i.e., the characteristic details of the long and thin defects are lost).

[0038] Since the hole convolution module skips some values ​​when performing the convolution operation, the receptive field of the convolution kernel can be expanded without convolving too many elements. Therefore, when detecting wafer defects, it is necessary to identify the first wafer image through the first defect recognition model with the hole convolution module to obtain the first recognition result.

[0039] In a feasible implementation manner, the first wafer image is composed of a plurality of second wafer images, the second wafer images are obtained by imaging the same wafer in different imaging modes, and the first defect recognition model includes a plurality of second defect recognition models for recognizing the second wafer images; the step of recognizing the first wafer image by using the preset first defect recognition model to obtain a first recognition result includes: Based on the imaging type identification of each of the second wafer images, the corresponding second defect recognition model is determined, wherein the imaging type identification is used to identify the second wafer image based on the imaging type when performing an imaging operation, and based on each of the second defect recognition models, each of the second wafer images is identified to obtain a second recognition result corresponding to each of the second wafer images, wherein the second recognition result includes the defect category of the corresponding wafer or the corresponding wafer is defect-free, and the second recognition results are summarized to obtain a first recognition result.

[0040] It should be noted that the wafer imaging method is a variety of imaging technologies used to detect and analyze wafer surface features or defects. The wafer imaging method can be X-ray imaging, infrared imaging, bright field imaging, dark field imaging, and PL (Photoluminescence) field imaging. The imaging methods in this embodiment are bright field imaging, dark field imaging, and PL field imaging. The second wafer images obtained by the above three imaging methods are bright field wafer images, dark field wafer images, and PL field wafer images.

[0041] In this embodiment, the second defect recognition model includes a bright field defect model, a dark field defect model and a PL field defect model, which are used to perform defect detection on bright field wafer images, dark field wafer images and PL field wafer images respectively, and the detection result is the second recognition result.

[0042] The second recognition result includes the defect category of the wafer or the corresponding wafer is defect-free. Different imaging methods can display different defect categories of the wafer. In this implementation, the defect categories of the bright field wafer image include Particle, Micropipe, Inclusion, Pit, White, Bump, and Scratch; the defect categories of the dark field include Scratch; the defect categories of the PL field include PL_White, PL_Black, BSF (Back Surface Field), and IDL (Isolated Dislocation Loop). Bright field defects can be referred to Figure 4 , PL field defects can be referred to Figure 5 , dark field defects can be referred to Figure 6 .

[0043] It is understandable that there may be multiple defects in the wafer, and it is difficult to fully detect multiple defects in the wafer using only one imaging method. Different imaging technologies can provide complementary information about the wafer, thereby fully displaying the defects. For example, BSF defects are difficult to display in dark field, but can be displayed through PL field.

[0044] Therefore, it is necessary to image the wafer using different imaging methods, perform defect identification on different second wafer images obtained by imaging, and obtain a second defect identification result.

[0045] It should also be noted that the second defect recognition model of this embodiment also includes multiple third defect recognition models for detecting defects of different categories. When setting the third defect recognition model, a different third defect recognition model can be set for each category of defects, or multiple defect categories can be identified using one third defect recognition model. This embodiment will eventually summarize the third recognition results obtained by each third defect recognition model to obtain the second recognition result.

[0046] Specifically, in this embodiment, the Particle, Micropipe, and Inclusion of the bright field are detected by model No. 1, the Scratch of the bright field is detected by model No. 2, the Pit, White, and Bump of the bright field are detected by model No. 3; the Scratch of the dark field is detected by model No. 4; the PL_White and PL_Black of the PL field are detected by model No. 5, and the BSF (Back Surface Field) and IDL (Isolated Dislocation Loop) of the PL field are detected by model No. 6; the model deployment of the detection system can refer to Figure 7 .

[0047] It is understandable that multiple types of defects may occur during wafer manufacturing, each with unique characteristics and causes. A single model may not be able to effectively identify all types of defects, while a specific type of model can provide higher detection accuracy for specific types of defects. Therefore, it is necessary to identify different types of defects in the wafer through multiple third defect recognition models, and finally summarize the third recognition results to obtain the second recognition results.

[0048] In summary, this embodiment obtains a first wafer image, identifies the first wafer image through a preset first defect recognition model, and obtains a first recognition result, wherein the first recognition result includes a defect category of the corresponding wafer or a corresponding wafer without defects.

[0049] The hole convolution module in the model of this embodiment skips the values ​​within the preset range during the convolution operation. Therefore, for the convolution kernel of the same size, the present application can convolve elements in a larger range, thereby improving the receptive field of the convolution kernel in the first defect recognition model. Moreover, since the values ​​within the preset range are skipped during the convolution, the reduction in feature map resolution caused by convolution of too many elements is avoided. Therefore, this embodiment can improve the fitting ability of slender defects in wafers, thereby improving the detection accuracy of wafer defects.

[0050] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can refer to the above introduction, and will not be repeated later. Figure 8 Before step S10, the wafer defect detection method further includes steps S01 to S04: Step S01, obtaining a wafer sample image; It should be noted that the wafer sample images are composed of wafer images of various imaging types and various defect types. In this embodiment, before model training, online data enhancement is performed on the wafer sample images. The specific enhancement methods may be: hue enhancement, saturation enhancement, value enhancement, image rotation, image translation, image scaling, image flipping, image mosaic, random erasing, etc.

[0051] It is understandable that the untrained wafer defect detection model has a low recognition accuracy rate for wafer defects, and this embodiment needs to detect different defects of the wafer through different models. Therefore, it is necessary to first obtain a wafer sample image consisting of wafer images of each imaging type and each defect type, and select the corresponding wafer sample images to train different defect detection models. And this embodiment enhances the wafer sample images so that the model learns different images, thereby improving the network accuracy.

[0052] Step S02, based on a plurality of dilated convolution modules with different dilated rates in the model to be trained, feature extraction is performed on the wafer sample image to obtain a multi-scale feature map; It should be noted that the model to be trained is a model to complete the training, and the number of dilated convolution modules with different dilated rates and the dilated rate of each dilated convolution module can be set based on the specific usage scenario. In this embodiment, the number of convolution modules is 4, including a 1*1 convolution module and three dilated convolution modules with dilated rates of 6, 12, and 18 and a convolution kernel size of 3×3.

[0053] It is understandable that different voiding rates can be convolved through different receptive fields without changing the size of the convolution kernel to obtain feature maps of different scales. Since this embodiment needs to better learn the slender defects of the wafer, by combining the feature maps after convolution operations with different voiding rates, a multi-scale feature map containing multi-level information can be formed, thereby enhancing the model's understanding of features of different scales and promoting information exchange between cross-scale features.

[0054] In a feasible implementation manner, the specific implementation manner of extracting features from the wafer sample image based on the hole convolution modules with multiple different hole rates in the model to be trained to obtain multi-scale features may also be: Based on a plurality of hole convolution modules with different hole rates in the model to be trained, feature extraction is performed on the wafer sample images respectively to obtain hole feature maps of different scales, pooling operation is performed on the wafer sample images to obtain a pooled feature map, based on feature map channels respectively corresponding to the hole feature maps and the pooled feature maps, the hole feature maps and the pooled feature maps are spliced ​​to obtain a spliced ​​feature map, and point-by-point convolution is performed on the spliced ​​feature map to obtain a multi-scale feature map.

[0055] It should be noted that, in this embodiment, the wafer sample images of different channels are pooled through a window of size 1×1. The pooling operation can be maximum pooling, minimum pooling and average pooling, and this embodiment uses average pooling.

[0056] Specifically, each pixel of the wafer sample image of this embodiment has three feature channels. The different channels of each pixel are averaged and pooled through a window of size 1×1. The average value of the three feature channels of each pixel can be used as the value of the pixel to obtain a single-channel pooled feature map.

[0057] It should also be noted that after obtaining a single-channel pooled feature map, this embodiment can perform a convolution operation on each pixel through a convolution module of size 1×1 to change the number of channels of the pooled feature map, and can further change the resolution of the feature map through an upsampling operation.

[0058] It is understandable that the hole convolution can capture information in a larger range through a larger receptive field, while the pooling operation can obtain high-level features of the global wafer sample image. In order to enable the model to learn the local details and global structure of wafer defects, it is necessary to splice the hole feature map and the pooling feature map based on the feature map channels corresponding to each of the hole feature map and the pooling feature map, and fuse the features of different scales through point-by-point convolution, and finally obtain the fused multi-scale features. The specific module structure of feature extraction and fusion can be referred to. Fig. 9 .

[0059] Step S03, performing wafer defect recognition based on the multi-scale feature map and the classification module of the model to be trained to obtain a defect recognition result; It is understandable that by combining the feature maps extracted from different void ratios, a multi-scale feature map containing multi-level wafer defect information can be obtained. Therefore, based on the classification module and the multi-scale feature map, a more accurate wafer defect recognition result can be obtained. By adjusting the model parameters based on the obtained defect recognition results, the convergence speed of the model can be accelerated and the model can have a better effect.

[0060] Step S04: based on the defect recognition result, adjust the parameters of the model to be trained to obtain a first defect recognition model.

[0061] It should be noted that in this embodiment, the loss value is calculated based on the defect recognition result and the real defect of the wafer sample image, and the parameters of the model to be trained are adjusted based on the loss value, and finally the first defect recognition model is obtained. The first defect recognition model is the model obtained after the training is terminated. The termination condition of the model training can be that the training rounds of the model reach the preset rounds, or the error in the model training process is less than the preset threshold.

[0062] This embodiment uses a training set and a model configuration file to train the model, and adjusts the parameter settings of the learning rate, optimizer, and loss function during the training process so that the training outputs the optimal wafer defect detection model.

[0063] It is understandable that since the model to be trained is a model whose parameters have not been adjusted, the accuracy of the results obtained by using the model for identification is relatively low. Therefore, the loss value is calculated based on the defect identification result of the model to be trained, and the parameters of the model to be trained are adjusted based on the loss value, so as to improve the recognition accuracy of the model. Through multiple rounds of training, a first defect identification model with a high recognition accuracy can be finally obtained.

[0064] In summary, this embodiment obtains a wafer sample image, performs feature extraction on the wafer sample image based on a plurality of void convolution modules with different void rates in the model to be trained, and obtains a multi-scale feature map, performs wafer defect identification based on the multi-scale feature map and the classification module of the model to be trained, and obtains a defect identification result, and adjusts the parameters of the model to be trained based on the defect identification result to obtain a first defect recognition model.

[0065] Since the hole convolution module skips some values ​​when performing convolution, there is no need to add additional parameters or calculations to expand the receptive field, and the pooling operation can reduce the spatial dimension of the feature map while retaining important feature information. Therefore, the hole feature map obtained in this embodiment has information of different scales in a large range, while the pooled feature map has high-level features of the global wafer sample image. By splicing the obtained hole feature map and pooled feature map and performing feature fusion, the model can learn the local details and global structure of wafer defects, thereby improving the recognition accuracy of the model.

[0066] Based on the first and second embodiments of the present application, in the third embodiment of the present application, the same or similar contents as those in the first and second embodiments above can be referred to the above introduction, and will not be described in detail later. Fig.10 After the step of summarizing the second recognition results to obtain the first recognition result, the wafer defect detection method further includes steps S21 to S24: Step S21, judging whether there is a same wafer defect based on each of the second recognition results; It should be noted that the same wafer defects are wafer defects with the same defect type and position in the second identification result.

[0067] It is understandable that different defects in the same wafer can be identified by different imaging types. In the above identification process, some types of defects can be imaged in different imaging methods (for example, scratch-type defects can be obtained in both bright field and dark field images).

[0068] Therefore, it is necessary to determine whether the same wafer defect exists based on each of the second identification results to avoid repeated identification of the same defect.

[0069] The second recognition result also includes the origin coordinates of the corresponding wafer defect. The specific implementation method of judging whether there is the same wafer defect based on each of the second recognition results may also be: Based on each of the second identification results, determine whether there are wafer defects of the same type. If so, calculate the difference between the origin coordinates of the wafer defects of the same type. If the difference is within a preset difference range, determine that the wafer defects of the same type are the same wafer defects.

[0070] It should be noted that the origin coordinates of the wafer defect can be set according to the specific defect type. In this embodiment, the origin coordinates of the wafer defect are the geometric center point of the wafer defect. The preset difference range can be set based on specific identification requirements. In this embodiment, the preset difference range is 5 pixels, that is, if the origin difference of two defects of the same type is within 5 pixels, then the two defects of the same type are the same defects.

[0071] It is understandable that when identifying wafer defects, there may be two defects of the same type located at different positions on the wafer. At this time, if the identified defects are determined to be the same defects only by the defect type of the wafer, misjudgment may occur. Therefore, it is necessary to calculate the difference between the origin coordinates of the same type of wafer defects, and determine whether the calculated difference is within the preset difference range to determine whether the identified defects are the same type of defects.

[0072] Step S22, if it exists, the same wafer defect is taken as the first wafer defect, and the remaining wafer defects are taken as the second wafer defects; It is understandable that defects of the same type may be the same defect that is repeatedly identified and need further judgment. If there is no defect of the same type as the defect identified, the defect is not the same defect that is repeatedly identified and no further judgment is required. Therefore, the same wafer defect needs to be regarded as the first wafer defect and the remaining wafer defects need to be regarded as the second wafer defect for subsequent judgment.

[0073] Step S23, based on the geometric parameters of each of the first wafer defects, determining one of the wafer defects as the second wafer defect from a plurality of identical wafer defects corresponding to each of the first wafer defects; It should be noted that the geometric parameters are parameters such as the length, width and area of ​​the identified wafer defects, and the specific parameters used can be set according to requirements.

[0074] It is understandable that for the same defects that are repeatedly identified, one of them needs to be selected as the identification result. Since the same defect is identified in wafer images of different imaging types, and for the same defect, although it can be imaged in different imaging methods, the imaging effect will be different. Therefore, in order to achieve better identification results, this embodiment is based on the geometric parameters of each of the first wafer defects, and from the multiple identical wafer defects corresponding to each of the first wafer defects, one of the wafer defects is determined as the second wafer defect, so as to select the defect with the best imaging effect as the identification result.

[0075] Step S24, summarizing the second wafer defects to obtain a first recognition result.

[0076] It can be understood that, through the above-mentioned judgment and selection of the same defects, there are no defects that are repeatedly identified in the second wafer defects, and the second wafer defects identified are the identification results with the best imaging effect. Therefore, by summarizing the second wafer defects, the first identification result is obtained, thereby identifying all defects in the wafer.

[0077] In summary, this embodiment determines whether the same wafer defect exists based on each of the second identification results. If so, the same wafer defect is used as the first wafer defect, and the remaining wafer defects are used as the second wafer defects. Based on the geometric parameters of each of the first wafer defects, one of the multiple same wafer defects corresponding to each of the first wafer defects is determined as the second wafer defect, and the second wafer defects are summarized to obtain the first identification result.

[0078] Since this embodiment recognizes images of different imaging types of the same wafer, there may be repeated recognition of the same defect. Therefore, this embodiment determines whether the same defect exists by the difference between the defect type and the defect origin, and selects one of the same wafer defects as the recognition result by the geometric parameters of the defect, so that the defect obtained by recognition is the defect with the best effect. Therefore, this embodiment can improve the effect of wafer defect recognition.

[0079] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the wafer defect detection method of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0080] This application also provides a wafer defect detection device, please refer to Fig.11 , the wafer defect detection device comprises: The image acquisition module 10 is used to acquire the first wafer image; The defect recognition module 20 is used to identify the first wafer image through a preset first defect recognition model to obtain a first recognition result, wherein the first recognition result includes the defect category of the corresponding wafer or the corresponding wafer is defect-free, and the first defect recognition model has a hole convolution module, and the hole convolution module skips the values ​​within a preset range during the convolution operation, so as to expand the receptive field of the convolution kernel in the first defect recognition model while not reducing the resolution of the feature map obtained by convolving the first wafer image.

[0081] In one embodiment, the wafer defect detection device further includes: A sample acquisition module is used to acquire wafer sample images; A feature extraction module, used for extracting features from the wafer sample image based on a plurality of dilated convolution modules with different dilated rates in the model to be trained, to obtain a multi-scale feature map; A classification module, used to perform wafer defect recognition based on the multi-scale feature map and the classification module of the model to be trained to obtain a defect recognition result; A parameter adjustment module is used to adjust the parameters of the model to be trained based on the defect recognition result to obtain a first defect recognition model.

[0082] In one embodiment, the feature extraction module includes: A feature extraction submodule, used for extracting features from the wafer sample images based on a plurality of void convolution modules with different void rates in the model to be trained, to obtain void feature maps of different scales; A pooling submodule, used for performing a pooling operation on the wafer sample image to obtain a pooling feature map; A feature splicing submodule, used for splicing each of the hole feature maps and the pooled feature map based on the feature map channels respectively corresponding to each of the hole feature maps and the pooled feature map, to obtain a spliced ​​feature map; The feature fusion submodule is used to perform point-by-point convolution on the concatenated feature map to obtain a multi-scale feature map.

[0083] In one embodiment, the defect identification module includes: A model selection submodule, used to determine the corresponding second defect recognition model based on the imaging type identification of each of the second wafer images, wherein the imaging type identification is to identify the second wafer image based on the imaging type when performing the imaging operation; A defect recognition submodule, for respectively identifying each of the second wafer images based on each of the second defect recognition models, and obtaining second recognition results respectively corresponding to each of the second wafer images, wherein the second recognition results include a defect category of the corresponding wafer or a corresponding wafer having no defects; The result aggregation submodule is used to aggregate the second recognition results to obtain the first recognition result.

[0084] In one embodiment, the result summary submodule includes: A defect judgment unit, used for judging whether there is a same wafer defect based on each of the second recognition results; a defect classification unit, for classifying the same wafer defect as a first wafer defect if any, and the remaining wafer defects as a second wafer defect; a defect selection unit, configured to determine, based on geometric parameters of each of the first wafer defects, one of the wafer defects from a plurality of identical wafer defects corresponding to each of the first wafer defects as a second wafer defect; A result summarizing unit is used to summarize the second wafer defects to obtain a first recognition result.

[0085] In one embodiment, the defect judgment unit includes: A defect judgment subunit, used for judging whether there are wafer defects of the same type based on each of the second recognition results; a difference calculation subunit, for calculating the difference between the origin coordinates of the wafer defects of the same type, if any; The defect selection subunit is used to determine that the wafer defects of the same type are the same wafer defects if the difference is within a preset difference range.

[0086] The wafer defect detection device provided by the present application adopts the wafer defect detection method in the above embodiment, which can solve the technical problem of low detection accuracy of wafer defects. Compared with the prior art, the beneficial effects of the wafer defect detection device provided by the present application are the same as the beneficial effects of the wafer defect detection method provided by the above embodiment, and the other technical features in the wafer defect detection device are the same as the features disclosed in the above embodiment method, which will not be repeated here.

[0087] The present application provides a wafer defect detection device, which includes: at least one processor; and a memory that is communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the wafer defect detection method in the above-mentioned embodiment one.

[0088] Reference below Fig.12, which shows a schematic diagram of the structure of a wafer defect detection device suitable for implementing the embodiment of the present application. The wafer defect detection device in the embodiment of the present application may include but is not limited to mobile terminals such as mobile phones, tablet computers, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig.12 The wafer defect detection device shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0089] like Fig.12 As shown, the wafer defect detection device may include a processing device 1001 (such as a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. In RAM1004, various programs and data required for the operation of the wafer defect detection device are also stored. The processing device 1001, ROM1002, and RAM1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the wafer defect detection device to communicate with other devices wirelessly or wired to exchange data. Although the figure shows a wafer defect detection device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or provided instead.

[0090] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0091] The wafer defect detection device provided by the present application adopts the wafer defect detection method in the above embodiment, which can solve the technical problem of low detection accuracy of wafer defects. Compared with the prior art, the beneficial effects of the wafer defect detection device provided by the present application are the same as the beneficial effects of the wafer defect detection method provided by the above embodiment, and the other technical features in the wafer defect detection device are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0092] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0093] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0094] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, and the computer-readable program instructions are used to execute the wafer defect detection method in the above-mentioned embodiment.

[0095] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM: Random Access Memory), a read-only memory (ROM: Read Only Memory), an erasable programmable read-only memory (EPROM: Erasable Programmable Read Only Memory or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM: CD-Read Only Memory), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency: Radio Frequency), etc., or any suitable combination of the above.

[0096] The computer-readable storage medium may be included in the wafer defect detection device; or may exist independently without being assembled into the wafer defect detection device.

[0097] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by the wafer defect detection device, the wafer defect detection device executes the wafer defect detection method.

[0098] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0099] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to each embodiment of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0100] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0101] The readable storage medium provided in the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned wafer defect detection method, and can solve the technical problem of low detection accuracy of wafer defects. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in the present application are the same as the beneficial effects of the wafer defect detection method provided in the above-mentioned embodiment, and will not be described in detail here.

[0102] The present application also provides a computer program product, including a computer program, which implements the steps of the above-mentioned wafer defect detection method when executed by a processor.

[0103] The computer program product provided in this application can solve the technical problem of low wafer defect detection accuracy. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the wafer defect detection method provided in the above embodiment, which will not be repeated here.

[0104] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A wafer defect detection method, characterized in that: The method includes: Get the first wafer image; The first wafer image is identified by a preset first defect recognition model to obtain a first recognition result, wherein the first recognition result includes a defect category of the corresponding wafer or a corresponding wafer without defects, and the first defect recognition model has a hole convolution module, and the hole convolution module skips values ​​within a preset range during convolution operation to expand the receptive field of the convolution kernel in the first defect recognition model without reducing the resolution of the feature map obtained by convolving the first wafer image.

2. The method according to claim 1, characterized in that Before the step of obtaining the first wafer image, the method further includes: Get wafer sample images; Based on a plurality of dilated convolution modules with different dilated rates in the model to be trained, feature extraction is performed on the wafer sample image to obtain a multi-scale feature map; Based on the multi-scale feature map and the classification module of the model to be trained, wafer defect recognition is performed to obtain a defect recognition result; Based on the defect recognition result, the parameters of the model to be trained are adjusted to obtain a first defect recognition model.

3. The method according to claim 2, characterized in that The step of extracting features from the wafer sample image based on the hole convolution modules with multiple different hole rates in the model to be trained to obtain multi-scale features includes: Based on multiple void convolution modules with different void rates in the model to be trained, feature extraction is performed on the wafer sample images respectively to obtain void feature maps of different scales; Performing a pooling operation on the wafer sample image to obtain a pooling feature map; Based on the feature map channels respectively corresponding to each of the hole feature maps and the pooled feature map, splicing each of the hole feature maps and the pooled feature map to obtain a spliced ​​feature map; The concatenated feature map is convolved point by point to obtain a multi-scale feature map.

4. The method according to claim 1, characterized in that The first wafer image is composed of a plurality of second wafer images, the second wafer images are obtained by imaging the same wafer in different imaging modes, and the first defect recognition model includes a plurality of second defect recognition models for recognizing the second wafer images; The step of identifying the first wafer image by using a preset first defect recognition model to obtain a first recognition result includes: Determining a corresponding second defect recognition model based on an imaging type identification of each of the second wafer images, wherein the imaging type identification is used to identify the second wafer image based on the imaging type when performing an imaging operation; Based on each of the second defect recognition models, each of the second wafer images is recognized respectively to obtain a second recognition result corresponding to each of the second wafer images, wherein the second recognition result includes a defect category of the corresponding wafer or a corresponding wafer having no defects; The second recognition results are aggregated to obtain a first recognition result.

5. The method according to claim 4, characterized in that: The step of aggregating the second recognition results to obtain the first recognition result comprises: Based on each of the second recognition results, determining whether there is a same wafer defect; If so, the same wafer defect is regarded as the first wafer defect, and the remaining wafer defects are regarded as the second wafer defects; Based on the geometric parameters of each of the first wafer defects, determining one of the wafer defects as a second wafer defect from a plurality of identical wafer defects corresponding to each of the first wafer defects; The second wafer defects are summarized to obtain a first recognition result.

6. The method according to claim 5, characterized in that The second recognition result also includes the origin coordinates of the corresponding wafer defect, and the step of judging whether there is the same wafer defect based on each of the second recognition results includes: Based on each of the second identification results, determining whether there are wafer defects of the same type; If so, calculating the difference between the origin coordinates of the wafer defects of the same type; If the difference is within a preset difference range, it is determined that the wafer defects of the same type are the same wafer defects.

7. A wafer defect detection device, characterized in that: The device comprises: An image acquisition module, used to acquire the first wafer image; A defect recognition module is used to identify the first wafer image through a preset first defect recognition model to obtain a first recognition result, wherein the first recognition result includes the defect category of the corresponding wafer or the corresponding wafer is defect-free, and the first defect recognition model has a hole convolution module, and the hole convolution module skips values ​​within a preset range during the convolution operation, so as to expand the receptive field of the convolution kernel in the first defect recognition model while not reducing the resolution of the feature map obtained by convolving the first wafer image.

8. A wafer defect detection device, characterized in that: The device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the wafer defect detection method according to any one of claims 1 to 6.

9. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the wafer defect detection method according to any one of claims 1 to 6 are implemented.

10. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the wafer defect detection method according to any one of claims 1 to 6 are implemented.

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