Wafer Defect Detection Method, Device, Equipment, Storage Medium and Program Product

Abstract

The present application discloses a method, device, equipment, storage medium and program product for wafer defect detection, which relates to the technical field of image recognition. Aiming at the problem that the pooling operation commonly used in current algorithms will lose defect details, resulting in limited fitting ability of current algorithms for slender-shaped defects in wafer defect maps, and thus low accuracy of wafer defect detection, the present application proposes a method for wafer defect detection: obtaining a first wafer image, and identifying the first wafer image through a preset first defect recognition model to obtain a wafer defect recognition result; by setting a dilated convolution module in the model, the receptive field of the convolution kernel is increased, and values within a preset range are skipped during convolution, avoiding the reduction of the feature map resolution caused by convolving too many elements. By capturing information in a larger range, the fitting ability for slender-shaped defects in the wafer is improved, thereby improving the accuracy of wafer defect detection.

Description

Technical Field

[0001] This application relates to the field of image recognition technology, and particularly to a wafer defect detection method, device, equipment, storage medium and program product. Background Art

[0002] Wafer manufacturing is a crucial part of the modern electronics industry. With the increasing demand for wafers in the semiconductor industry, the timely detection and accurate identification of wafer defects have become increasingly important.

[0003] Currently, wafer defects are usually detected by object detection algorithms. There are slender-shaped defects in wafer defects, and the detection algorithm needs to capture the global information of the slender defects. However, the commonly used pooling operation in the current algorithm will lose defect details, resulting in limited fitting ability of the current object detection algorithm for slender-shaped defects in the wafer defect map, leading to missed detections and false detections during wafer defect detection, and thus resulting in low detection accuracy of wafer defects. Summary of the Invention

[0004] The main purpose of this application is to provide a wafer defect detection method, device, equipment, storage medium and program product, aiming to solve the technical problem of low detection accuracy of wafer defects.

[0005] To achieve the above purpose, this application proposes a wafer defect detection method, and the method includes:

[0006] Obtain a first wafer picture;

[0007] Identify the first wafer picture through a preset first defect recognition model to obtain a first recognition result, where the first recognition result includes the defect category of the corresponding wafer or the corresponding wafer has no defect, and the first defect recognition model has a dilated convolution module, and the dilated convolution module skips values within a preset range during the convolution operation to expand the receptive field of the convolution kernel in the first defect recognition model while not reducing the resolution of the feature map obtained by convolving the first wafer picture.

[0008] In one embodiment, before the step of obtaining the first wafer picture, the method further includes:

[0009] Obtain a wafer sample picture;

[0010] Extract features from the wafer sample picture based on dilated convolution modules with multiple different dilation rates in the model to be trained to obtain multi-scale feature maps;

[0011] Based on the multi-scale feature maps and the classification module of the model to be trained, perform wafer defect recognition to obtain a defect recognition result;

[0012] Based on the defect recognition result, adjust the parameters of the model to be trained to obtain a first defect recognition model.

[0013] In one embodiment, the step of extracting multi-scale features from the wafer sample image based on atrous convolution modules with multiple different dilation rates in the model to be trained includes:

[0014] Based on atrous convolution modules with multiple different dilation rates in the model to be trained, extract features from the wafer sample image respectively to obtain atrous feature maps with different scales;

[0015] Perform a pooling operation on the wafer sample image to obtain a pooled feature map;

[0016] Based on the feature map channels corresponding to each of the atrous feature maps and the pooled feature map, splice each of the atrous feature maps and the pooled feature map to obtain a spliced feature map;

[0017] Perform pointwise convolution on the spliced feature map to obtain a multi-scale feature map.

[0018] In one embodiment, the first wafer image is composed of multiple second wafer images, the second wafer images are obtained by imaging the same wafer with different imaging methods, and the first defect recognition model includes multiple second defect recognition models for recognizing the second wafer images;

[0019] The step of recognizing the first wafer image through the preset first defect recognition model to obtain a first recognition result includes:

[0020] Based on the imaging type identifiers of each of the second wafer images, determine the corresponding second defect recognition model, where the imaging type identifier is used to identify the second wafer image based on the imaging type during the imaging operation;

[0021] Based on each of the second defect recognition models, recognize each of the second wafer images respectively to obtain second recognition results corresponding to each of the second wafer images, where the second recognition result includes the defect category of the corresponding wafer or the corresponding wafer has no defect;

[0022] Summarize each of the second recognition results to obtain a first recognition result.

[0023] In one embodiment, the step of summarizing each of the second recognition results to obtain a first recognition result includes:

[0024] Based on each of the second recognition results, determine whether there are the same wafer defects;

[0025] If it exists, the same wafer defects are taken as the first wafer defects, and the remaining wafer defects are taken as the second wafer defects;

[0026] Based on the geometric parameters of each of the first wafer defects, one wafer defect is determined from the multiple identical wafer defects corresponding to each of the first wafer defects as the second wafer defect;

[0027] The second wafer defects are summarized to obtain a first recognition result.

[0028] In one embodiment, the second recognition result further includes the origin coordinates of the corresponding wafer defects. The step of determining whether there are identical wafer defects based on each of the second recognition results includes:

[0029] Based on each of the second recognition results, it is determined whether there are wafer defects of the same type;

[0030] If so, the difference between the origin coordinates of the wafer defects of the same type is calculated;

[0031] If the difference is within a preset difference range, the wafer defects of the same type are determined to be identical wafer defects.

[0032] In addition, to achieve the above object, the present application further provides a wafer defect detection device, and the wafer defect detection device includes:

[0033] An image acquisition module, configured to acquire a first wafer image;

[0034] A defect recognition module, configured to recognize the first wafer image through a preset first defect recognition model to obtain a first recognition result, wherein the first recognition result includes the defect category of the corresponding wafer or the corresponding wafer has no defect, and the first defect recognition model has a dilated convolution module, and the dilated convolution module skips values within a preset range during the convolution operation to expand the receptive field of the convolution kernel in the first defect recognition model while not reducing the resolution of the feature map obtained by convolving the first wafer image.

[0035] In addition, to achieve the above object, the present application further provides a wafer defect detection device, and the device includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, and the computer program is configured to implement the steps of the wafer defect detection method as described above.

[0036] In addition, to achieve the above object, the present application further provides a storage medium, the storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium, and when the computer program is executed by a processor, the steps of the wafer defect detection method as described above are implemented.

[0037] In addition, to achieve the above object, the present application also provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of the wafer defect detection method described above are implemented.

[0038] One or more technical solutions proposed by the present application have at least the following technical effects:

[0039] The present application obtains a first wafer image, and identifies the first wafer image through a preset first defect recognition model to obtain a first recognition result, where the first recognition result includes the defect category of the corresponding wafer or the corresponding wafer has no defect.

[0040] The dilated convolution module in the model of the present application skips values within a preset range during the convolution operation. Therefore, for the same-sized convolution kernel, the present application can perform convolution on elements in a larger range, improving the receptive field of the convolution kernel in the first defect recognition model. And because values within the preset range are skipped during convolution, it avoids the reduction of the feature map resolution caused by convolving too many elements. Therefore, the present application can improve the fitting ability for slender-shaped defects in the wafer, thereby improving the detection accuracy of wafer defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0042] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0043] Figure 1 It is a schematic flowchart provided for the first embodiment of the wafer defect detection method of the present application;

[0044] Figure 2 It is a schematic diagram of the first scenario provided for the first embodiment of the wafer defect detection method of the present application;

[0045] Figure 3 It is a schematic diagram of the second scenario provided for the first embodiment of the wafer defect detection method of the present application;

[0046] Figure 4 It is a schematic diagram of the third scenario provided for the first embodiment of the wafer defect detection method of the present application;

[0047] Figure 5Schematic diagram of the fourth scenario provided for the first embodiment of the wafer defect detection method of the present application;

[0048] Figure 6 Schematic diagram of the fifth scenario provided for the first embodiment of the wafer defect detection method of the present application;

[0049] Figure 7 Schematic diagram of the sixth scenario provided for the first embodiment of the wafer defect detection method of the present application;

[0050] Figure 8 Flow chart provided for the second embodiment of the wafer defect detection method of the present application;

[0051] Figure 9 Schematic diagram of the scenario provided for the second embodiment of the wafer defect detection method of the present application;

[0052] Figure 10 Flow chart provided for the third embodiment of the wafer defect detection method of the present application;

[0053] Figure 11 Schematic diagram of the module structure of the wafer defect detection device according to the embodiment of the present application;

[0054] Figure 12 Schematic diagram of the device structure of the hardware operating environment involved in the wafer defect detection method according to the embodiment of the present application.

[0055] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0056] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application, and are not used to limit the present application.

[0057] For a better understanding of the technical solutions of the present application, the following will be described in detail with reference to the accompanying drawings of the specification and specific implementation manners.

[0058] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device, a wafer defect detection device, etc. that can implement the above functions. The following will take the wafer defect detection device as an example to illustrate this embodiment and the following embodiments.

[0059] Based on this, the embodiment of the present application provides a wafer defect detection method, referring to Figure 1 , Figure 1 Flow chart of the first embodiment of the wafer defect detection method of the present application.

[0060] In this embodiment, the specific application scenario can be:

[0061] After manufacturing the wafer, the target detection algorithm can be used to detect the defects of the manufactured wafer, thereby avoiding a great impact of the wafer on the quality and performance of electronic devices. However, the current target detection algorithm has problems such as insufficient receptive field of the convolutional kernel or low resolution of the feature map obtained after convolution, resulting in limited fitting ability of the current target detection algorithm for slender-shaped defects in the wafer defect map, and there are cases of missed detection and false detection during wafer defect detection, leading to low detection accuracy of wafer defects. Therefore, the application scenario of this embodiment is mainly in the wafer manufacturing industry for the scenario of accurately detecting wafer defects.

[0062] In this embodiment, the wafer defect detection method includes steps S10 to S20:

[0063] Step S10, obtain the first wafer image;

[0064] It should be noted that the first wafer image is a collection of multiple wafer images, and the multiple wafer images are obtained by imaging the same wafer with different imaging methods.

[0065] It can be understood that in this embodiment, the target detection algorithm is used to detect wafer defects. And the target detection algorithm usually identifies specific classes of objects (in this embodiment, the defects of the wafer) in images or videos. Therefore, in order to identify the defects of the wafer, it is necessary to first obtain the corresponding first wafer image.

[0066] It should also be noted that the wafer defect detection of this embodiment can be automatically controlled by software, and the interface of the software refers to Figure 2 . Before obtaining the first wafer image, the wafer will be placed by a wafer robot, and the position and size of the wafer will be determined by a wafer edge finder.

[0067] A wafer robot is an automated device used to achieve high-precision and high-efficiency wafer picking and placing. It can be directly driven without a speed reduction mechanism, thereby providing excellent rigidity and motion smoothness, greatly improving the production efficiency and precision of the factory, and reducing the labor cost at the same time. And the wafer robot simplifies the installation and debugging process through an embedded controller design, reducing the need for additional controller settings and wiring space.

[0068] The wafer edge finder determines the precise position and size of the wafer by scanning the edge of the wafer. There are an optical sensor and a signal processor in the wafer edge finder. The optical sensor is used to detect the light reflected from the wafer surface and transmit the signal to the signal processor for processing. The signal processor analyzes the signal, determines the position and size of the wafer, and sends instructions to other devices for operation. The specific process of wafer placement and edge finding refers toFigure 3 。

[0069] Step S20, identify the first wafer image through a preset first defect identification model to obtain a first identification result, where the first identification result includes the defect category of the corresponding wafer or the corresponding wafer has no defect. The first defect identification model has a dilated convolution module, and the dilated convolution module skips values within a preset range during the convolution operation, so as to expand the receptive field of the convolution kernel in the first defect identification model while not reducing the resolution of the feature map obtained by convolving the first wafer image.

[0070] It should be noted that the first defect identification model can be a model obtained based on any object detection algorithm. In this embodiment, the object detection algorithm is the YOLOv8 algorithm (You Only Look Once version 8, the eighth version of the You Only Look Once algorithm). The first defect identification model obtained through the YOLOv8 algorithm can accurately detect the defects of the wafer.

[0071] The defect categories of the wafer are different types of defects generated due to different reasons during the wafer manufacturing process. In this embodiment, a dilated convolution module is used to better fit the slender defects in each defect category. The dilated convolution module skips some input positions during the convolution operation to convolve a larger area. In this embodiment, the values within the preset range are the values of the input positions to be skipped, and the specific preset range is determined by the dilation rate of the dilated convolution.

[0072] The dilation rate is the interval size between the elements of the convolution kernel during dilated convolution. When the dilation rate is 1, the dilated convolution is equivalent to the standard convolution; the dilated convolution with a dilation rate greater than 1 will skip some values based on the dilation rate.

[0073] Specifically, if the size of the convolution kernel is 3×3 and the dilation rate is 2, the interval size between the convolution kernel elements is 1. At this time, it is equivalent to convolving some elements within the range of 5×5; if the size of the convolution kernel is 3×3 and the dilation rate is 3, the interval size between the convolution kernel elements is 2. At this time, it is equivalent to convolving some elements within the range of 7×7.

[0074] It can be understood that the wafers produced by manufacturing may have slender defects, and such slender defects require the model to learn the details of the defects. The YOLOv8 algorithm will perform fast pyramid pooling operations (pooling operations at multiple scales and connecting the results as the input of the subsequent layer), and the downsampling of pooling will lose the details of the defects. Therefore, in order to enable the model to better learn the details of the slender defects, this embodiment does not use the fast pyramid pooling operation that the YOLOv8 algorithm usually uses, but extracts the feature map through dilated convolution.

[0075] For slender defects in wafer defects, a smaller convolutional kernel cannot comprehensively learn slender defects due to insufficient receptive fields, while a larger convolutional kernel will reduce the resolution of the extracted feature map (i.e., lose the feature details of slender defects) due to convolving too many elements.

[0076] Since the dilated convolution module skips some values during the convolution operation, it can expand the receptive field of the convolutional kernel without convolving too many elements. Therefore, when detecting wafer defects, it is necessary to identify the first wafer image through a first defect recognition model with a dilated convolution module to obtain a first recognition result.

[0077] In a feasible implementation manner, the first wafer image is composed of multiple second wafer images, the second wafer images are obtained by imaging the same wafer with different imaging methods, and the first defect recognition model includes multiple second defect recognition models for identifying the second wafer images; the step of identifying the first wafer image through a preset first defect recognition model to obtain a first recognition result includes:

[0078] Based on the imaging type identifiers of the second wafer images, determine the corresponding second defect recognition models, where the imaging type identifiers are used to identify the second wafer images based on the imaging type during the imaging operation. Based on the second defect recognition models, respectively identify each of the second wafer images to obtain second recognition results corresponding to each of the second wafer images, where the second recognition results include the defect categories of the corresponding wafers or that the corresponding wafers have no defects, and summarize the second recognition results to obtain a first recognition result.

[0079] It should be noted that the wafer imaging method refers to various imaging technologies used to detect and analyze the surface features or defects of wafers. The wafer imaging method can be ray imaging, infrared imaging, bright-field imaging, dark-field imaging, and PL (Photoluminescence) field imaging. The imaging methods in this embodiment are bright-field imaging, dark-field imaging, and PL field imaging, and the second wafer images obtained through the above three imaging methods are bright-field wafer images, dark-field wafer images, and PL field wafer images.

[0080] In this embodiment, the second defect recognition models include a bright-field defect model, a dark-field defect model, and a PL field defect model, which are respectively used to detect defects in bright-field wafer images, dark-field wafer images, and PL field wafer images, and the results obtained from the detection are the second recognition results.

[0081] The second recognition result includes the defect category of the wafer or the corresponding wafer is defect-free. Different imaging methods can display different defect categories of the wafer. In this embodiment, the defect categories in bright-field wafer images are Particle, Micropipe, Inclusion, Pit, White, Bump, and Scratch; the defect category in dark-field is Scratch; the defect categories in the PL field are PL_White, PL_Black, BSF (Back Surface Field), and IDL (Isolated Dislocation Loop). Bright-field defects can be referred to Figure 4 , PL-field defects can be referred to Figure 5 , dark-field defects can be referred to Figure 6 .

[0082] It can be understood that a wafer may have multiple defects, and it is difficult to comprehensively detect multiple defects in the wafer using only one imaging method. Different imaging techniques can provide complementary information about the wafer, so as to comprehensively display the defects. For example, BSF defects are difficult to display in the dark-field, but can be displayed through the PL field.

[0083] Therefore, it is necessary to image the wafer through different imaging methods, identify the defects in different second wafer images obtained by imaging, and obtain the second defect recognition result.

[0084] It should also be noted that the second defect recognition model in this embodiment further includes multiple third defect recognition models for detecting different categories of defects. When setting up the third defect recognition model, different third defect recognition models can be set for each category of defects, or multiple defect categories can be identified using one third defect recognition model. In this embodiment, the third recognition results obtained by each third defect recognition model will be finally summarized to obtain the second recognition result.

[0085] Specifically, in this embodiment, the Particle, Micropipe, and Inclusion of the bright field are detected by model No. 1, the Scratch of the bright field is detected by model No. 2, the Pit, White, and Bump of the bright field are detected by model No. 3; the Scratch of the dark field is detected by model No. 4; the PL_White and PL_Black of the PL field are detected by model No. 5, and the BSF (Back Surface Field) and IDL (Isolated Dislocation Loop) of the PL field are detected by model No. 6; the model deployment of the detection system can refer to Figure 7 .

[0086] It is understandable that multiple types of defects may occur during wafer manufacturing, each with unique characteristics and causes. A single model may not be able to effectively identify all types of defects, while a specific type of model can provide higher detection accuracy for specific types of defects. Therefore, it is necessary to identify different types of defects in the wafer through multiple third defect recognition models, and finally summarize the third recognition results to obtain the second recognition results.

[0087] In summary, this embodiment obtains a first wafer image, identifies the first wafer image through a preset first defect recognition model, and obtains a first recognition result, wherein the first recognition result includes a defect category of the corresponding wafer or a corresponding wafer without defects.

[0088] The hole convolution module in the model of this embodiment skips the values ​​within the preset range during the convolution operation. Therefore, for the convolution kernel of the same size, the present application can convolve elements in a larger range, thereby improving the receptive field of the convolution kernel in the first defect recognition model. Moreover, since the values ​​within the preset range are skipped during the convolution, the reduction in feature map resolution caused by convolution of too many elements is avoided. Therefore, this embodiment can improve the fitting ability of slender defects in wafers, thereby improving the detection accuracy of wafer defects.

[0089] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can refer to the above introduction, and will not be repeated later. Figure 8 Before step S10, the wafer defect detection method further includes steps S01 to S04:

[0090] Step S01, obtaining a wafer sample image;

[0091] It should be noted that the wafer sample images are composed of wafer images of various imaging types and various defect types. In this embodiment, before model training, online data augmentation will be performed on the wafer sample images. The specific augmentation methods can be: hue augmentation, saturation augmentation, value augmentation, image rotation, image translation, image scaling, image flipping, image mosaic, random erasing, etc.

[0092] It can be understood that the recognition accuracy of the untrained wafer defect detection model for wafer defects is relatively low, and in this embodiment, different models are required to detect different defects of the wafer. Therefore, it is necessary to first obtain wafer sample images composed of wafer images of various imaging types and various defect types, and select the corresponding wafer sample images to train different defect detection models. And in this embodiment, by augmenting the wafer sample images, the model learns different images, thereby improving the network accuracy.

[0093] Step S02: Based on the atrous convolution modules with multiple different dilation rates in the model to be trained, perform feature extraction on the wafer sample images to obtain multi-scale feature maps;

[0094] It should be noted that the model to be trained is a model that has not completed training. The number of atrous convolution modules with different dilation rates and the dilation rates of each atrous convolution module can be set based on specific usage scenarios. In this embodiment, the number of convolution modules is 4, including a 1*1 convolution module and three atrous convolution modules with dilation rates of 6, 12, and 18 respectively and a convolution kernel size of 3×3.

[0095] It can be understood that different dilation rates can perform convolution through different receptive fields without changing the convolution kernel size to obtain feature maps of different scales. Since this embodiment needs to better learn the slender defects of the wafer, by combining the feature maps after convolution operations with different dilation rates, a multi-scale feature map containing multi-level information can be formed, thereby enhancing the model's understanding of different-scale features and promoting information exchange between cross-scale features.

[0096] In a feasible implementation manner, the specific implementation manner of performing feature extraction on the wafer sample images based on the atrous convolution modules with multiple different dilation rates in the model to be trained to obtain multi-scale features can also be:

[0097] Based on the atrous convolution modules with multiple different dilation rates in the model to be trained, the wafer sample images are respectively subjected to feature extraction to obtain atrous feature maps of different scales. The wafer sample images are subjected to a pooling operation to obtain a pooled feature map. Based on the feature map channels corresponding to each of the atrous feature maps and the pooled feature map, each of the atrous feature maps and the pooled feature map are concatenated to obtain a concatenated feature map. The concatenated feature map is subjected to pointwise convolution to obtain a multi-scale feature map.

[0098] It should be noted that in this embodiment, the wafer sample images of different channels are pooled through a window of size 1×1. The pooling operation can be max pooling, min pooling, and average pooling. Average pooling is used in this embodiment.

[0099] Specifically, each pixel point of the wafer sample image in this embodiment has 3 feature channels. By performing average pooling on different channels of each pixel point through a window of size 1×1, the average value of the 3 feature channels of each pixel point can be used as the value of the pixel point to obtain a single-channel pooled feature map.

[0100] It should also be noted that after obtaining the single-channel pooled feature map, in this embodiment, a convolution module of size 1×1 can be used to perform a convolution operation on each pixel point to change the number of channels of the pooled feature map, and the resolution of the feature map can be further changed through an upsampling operation.

[0101] It can be understood that atrous convolution can capture information in a larger range through a larger receptive field, while the pooling operation can obtain the global high-level features of the wafer sample image. In order for the model to learn the local details and global structure of wafer defects, it is necessary to concatenate each of the atrous feature maps and the pooled feature map based on the feature map channels corresponding to each of the atrous feature maps and the pooled feature map, and fuse the features of different scales through pointwise convolution. Finally, the fused multi-scale features are obtained. The specific module structure for feature extraction and fusion can refer to Figure 9 .

[0102] Step S03, based on the multi-scale feature map and the classification module of the model to be trained, wafer defect recognition is performed to obtain a defect recognition result;

[0103] It can be understood that by combining the feature maps extracted with different dilation rates, a multi-scale feature map containing multi-level wafer defect information can be obtained. Therefore, based on the classification module and the multi-scale feature map, a more accurate wafer defect recognition result can be obtained. By adjusting the model parameters through the obtained defect recognition result, the convergence speed of the model can be accelerated, and the model can have a better effect.

[0104] Step S04: Based on the defect recognition result, adjust the parameters of the to-be-trained model to obtain a first defect recognition model.

[0105] It should be noted that in this embodiment, the loss value is calculated based on the defect recognition result and the true defects in the wafer sample pictures, and the parameters of the to-be-trained model are adjusted based on the loss value, and finally a first defect recognition model is obtained. The first defect recognition model is the model obtained after the training is terminated. The termination condition of the model training can be that the number of training rounds of the model reaches a preset number of rounds, or the error in the model training process is less than a preset threshold.

[0106] In this embodiment, the training set and the model configuration file are used to train the model, and the parameter settings of the learning rate, optimizer, and loss function are adjusted during the training process to make the training output the optimal wafer defect detection model.

[0107] It can be understood that since the to-be-trained model is a model whose parameters have not been adjusted yet, the accuracy of the result obtained by recognition through this model is relatively low. Therefore, calculating the loss value based on the defect recognition result of the to-be-trained model and adjusting the parameters of the to-be-trained model based on the obtained loss value can improve the recognition accuracy of the model. Through multiple rounds of training, a first defect recognition model with a high recognition accuracy can be finally obtained.

[0108] In summary, in this embodiment, the wafer sample pictures are obtained, and based on the atrous convolution modules with multiple different dilation rates in the to-be-trained model, the wafer sample pictures are subjected to feature extraction to obtain multi-scale feature maps. Based on the multi-scale feature maps and the classification module of the to-be-trained model, wafer defect recognition is performed to obtain a defect recognition result. Based on the defect recognition result, the parameters of the to-be-trained model are adjusted to obtain a first defect recognition model.

[0109] Since the atrous convolution module skips some values during convolution and does not require additional parameters or computational complexity to expand the receptive field, while the pooling operation can reduce the spatial dimension of the feature map while retaining important feature information. Therefore, the obtained atrous feature maps in this embodiment have information of different scales in a large range, and the pooling feature maps have high-level global features of the wafer sample pictures. By splicing the obtained atrous feature maps and pooling feature maps and performing feature fusion, the model can learn the local details and global structure of wafer defects, thereby improving the recognition accuracy of the model.

[0110] Based on the first embodiment and the second embodiment of the present application, in the third embodiment of the present application, the same or similar content as in the above-mentioned first embodiment and second embodiment can be referred to the above introduction and will not be repeated hereinafter. On this basis, please refer to Figure 10After the step of summarizing each of the second recognition results to obtain the first recognition result, the wafer defect detection method further includes steps S21 to S24:

[0111] Step S21, based on each of the second recognition results, determine whether there are the same wafer defects;

[0112] It should be noted that the same wafer defects refer to the wafer defects with the same type and position in the second recognition results.

[0113] It can be understood that different defects in the same wafer can be recognized through different imaging types. During the above recognition process, there will be some types of defects that can be imaged in different imaging methods (for example, scratch-type defects can be obtained in bright-field pictures and dark-field pictures).

[0114] Therefore, it is necessary to determine whether there are the same wafer defects based on each of the second recognition results to avoid repeated recognition of the same defects.

[0115] The second recognition result further includes the origin coordinates corresponding to the wafer defects. The specific implementation manner of determining whether there are the same wafer defects based on each of the second recognition results can also be:

[0116] Based on each of the second recognition results, determine whether there are the same type of wafer defects. If so, calculate the difference between the origin coordinates of the same type of wafer defects. If the difference is within the preset difference range, determine that the same type of wafer defects are the same wafer defects.

[0117] It should be noted that the origin coordinates of the wafer defects can be set according to the specific defect type. In this embodiment, the origin coordinates of the wafer defects are the geometric center points of the wafer defects. The preset difference range can be set based on specific recognition requirements. In this embodiment, the preset difference range is 5 pixel points, that is, if the origin difference between two same-type defects is within 5 pixel points, then these two same-type defects are the same defects.

[0118] It can be understood that when recognizing wafer defects, there may be two same-type defects at different positions on the wafer. At this time, if only the defect type of the wafer is used to determine whether the recognized defects are the same defects, misjudgment may occur. Therefore, it is necessary to calculate the difference between the origin coordinates of the same type of wafer defects, and determine whether the recognized defects are the same type of defects by judging whether the calculated difference is within the preset difference range.

[0119] Step S22, if any exist, regard the same wafer defects as the first wafer defects, and regard the remaining wafer defects as the second wafer defects;

[0120] It can be understood that defects of the same type may be the same defect that is repeatedly identified, and further judgment is required. If there are no defects of the same type as the identified defects, then the defect is not the same defect obtained by repeated identification, and further judgment on this defect is not required. Therefore, it is necessary to regard the same wafer defects as the first wafer defects, and regard the remaining wafer defects as the second wafer defects for subsequent judgment.

[0121] Step S23, based on the geometric parameters of each of the first wafer defects, respectively determine one of the wafer defects as the second wafer defect from the multiple identical wafer defects corresponding to each of the first wafer defects;

[0122] It should be noted that the geometric parameters are parameters such as the length, width, and area of the identified wafer defects, and the specific parameters used can be set according to requirements.

[0123] It can be understood that for the same defects that are repeatedly identified, one of them needs to be selected as the recognition result. Since the same defects are identified in wafer images of different imaging types, and for the same defects, although they can be imaged in different imaging methods, the imaging effects will be different. Therefore, in order to obtain a better recognition result, in this embodiment, based on the geometric parameters of each of the first wafer defects, respectively determine one of the wafer defects as the second wafer defect from the multiple identical wafer defects corresponding to each of the first wafer defects, so as to select the defect with the best imaging effect as the recognition result.

[0124] Step S24, summarize the second wafer defects to obtain the first recognition result.

[0125] It can be understood that through the above judgment and selection of the same defects, there are no defects that are repeatedly identified in the second wafer defects, and the identified second wafer defects are the recognition results with the best imaging effect. Therefore, by summarizing the second wafer defects, the first recognition result is obtained, thereby identifying all the defects in the wafer.

[0126] In summary, in this embodiment, based on each of the second recognition results, it is judged whether there are the same wafer defects. If any exist, regard the same wafer defects as the first wafer defects, and regard the remaining wafer defects as the second wafer defects. Based on the geometric parameters of each of the first wafer defects, respectively determine one of the wafer defects as the second wafer defect from the multiple identical wafer defects corresponding to each of the first wafer defects, and summarize the second wafer defects to obtain the first recognition result.

[0127] Since the present embodiment will identify pictures of different imaging types of the same wafer, there may be a situation where the same defect is repeatedly identified. Therefore, in the present embodiment, by the difference between the type of the defect and the origin of the defect, it is determined whether there is the same defect, and one of the same wafer defects is selected as the recognition result through the geometric parameters of the defect, so that the defect obtained by recognition is the defect with the best effect. Therefore, the present embodiment can improve the effect of wafer defect recognition.

[0128] It should be noted that the above examples are only for understanding the present application and do not constitute a limitation on the wafer defect detection method of the present application. Based on this technical concept, more forms of simple transformation are within the protection scope of the present application.

[0129] The present application also provides a wafer defect detection device. Please refer to Figure 11 , the wafer defect detection device includes:

[0130] An image acquisition module 10 for acquiring a first wafer image;

[0131] A defect recognition module 20 for recognizing the first wafer image through a preset first defect recognition model to obtain a first recognition result, wherein the first recognition result includes the defect category of the corresponding wafer or the corresponding wafer has no defect, and the first defect recognition model has a dilated convolution module, and the dilated convolution module skips values within a preset range during the convolution operation, so as to expand the receptive field of the convolution kernel in the first defect recognition model while not reducing the resolution of the feature map obtained by convolving the first wafer image.

[0132] In one embodiment, the wafer defect detection device further includes:

[0133] A sample acquisition module for acquiring a wafer sample image;

[0134] A feature extraction module for extracting features from the wafer sample image based on dilated convolution modules with multiple different dilation rates in the model to be trained, to obtain multi-scale feature maps;

[0135] A classification module for performing wafer defect recognition based on the multi-scale feature maps and the classification module of the model to be trained, to obtain a defect recognition result;

[0136] A parameter adjustment module for adjusting the parameters of the model to be trained based on the defect recognition result to obtain a first defect recognition model.

[0137] In one embodiment, the feature extraction module includes:

[0138] A feature extraction sub-module, which is used to respectively extract features from the wafer sample pictures based on the atrous convolution modules with multiple different dilation rates in the model to be trained, and obtain atrous feature maps of different scales;

[0139] A pooling sub-module, which is used to perform a pooling operation on the wafer sample pictures to obtain a pooled feature map;

[0140] A feature splicing sub-module, which is used to splice each of the atrous feature maps and the pooled feature map based on the corresponding feature map channels of each of the atrous feature maps and the pooled feature map, and obtain a spliced feature map;

[0141] A feature fusion sub-module, which is used to perform pointwise convolution on the spliced feature map to obtain a multi-scale feature map.

[0142] In one embodiment, the defect recognition module includes:

[0143] A model selection sub-module, which is used to determine the corresponding second defect recognition model based on the imaging type identifier of each of the second wafer pictures, wherein the imaging type identifier is used to identify the second wafer pictures based on the imaging type during the imaging operation;

[0144] A defect recognition sub-module, which is used to respectively recognize each of the second wafer pictures based on each of the second defect recognition models, and obtain the second recognition results corresponding to each of the second wafer pictures, wherein the second recognition results include the defect category of the corresponding wafer or the corresponding wafer has no defect;

[0145] A result summary sub-module, which is used to summarize each of the second recognition results to obtain a first recognition result.

[0146] In one embodiment, the result summary sub-module includes:

[0147] A defect judgment unit, which is used to judge whether there are the same wafer defects based on each of the second recognition results;

[0148] A defect classification unit, which is used to, if any, regard the same wafer defects as the first wafer defects and regard the remaining wafer defects as the second wafer defects;

[0149] A defect selection unit, which is used to respectively determine one of the wafer defects as the second wafer defect from the multiple same wafer defects corresponding to each of the first wafer defects based on the geometric parameters of each of the first wafer defects;

[0150] A result summary unit, which is used to summarize the second wafer defects to obtain a first recognition result.

[0151] In one embodiment, the defect judgment unit includes:

[0152] A defect judgment subunit, configured to judge whether there are wafer defects of the same type based on each of the second recognition results;

[0153] A difference calculation subunit, configured to calculate the difference between the origin coordinates of the wafer defects of the same type if any;

[0154] A defect selection subunit, configured to determine the wafer defects of the same type as the same wafer defects if the difference is within a preset difference range.

[0155] The wafer defect detection device provided by the present application adopts the wafer defect detection method in the above embodiment, and can solve the technical problem of low detection accuracy of wafer defects. Compared with the prior art, the beneficial effects of the wafer defect detection device provided by the present application are the same as those of the wafer defect detection method provided by the above embodiment, and other technical features in the wafer defect detection device are the same as those disclosed in the method of the above embodiment, and will not be elaborated here.

[0156] The present application provides a wafer defect detection device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the wafer defect detection method in the first embodiment above.

[0157] Next, refer to Figure 12 , which shows a schematic structural diagram of a wafer defect detection device suitable for implementing the embodiments of the present application. The wafer defect detection device in the embodiments of the present application may include, but is not limited to, mobile terminals such as mobile phones, tablet computers, notebook computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PMPs (Portable Media Players), vehicle terminals (such as vehicle navigation terminals), etc. and fixed terminals such as digital TVs, desktop computers, etc. Figure 12 The wafer defect detection device shown is only an example, and should not impose any limitation on the functions and usage scope of the embodiments of the present application.

[0158] As Figure 12As shown, the wafer defect detection device may include a processing device 1001 (such as a central processing unit, a graphics processing unit, etc.), which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM: Random Access Memory) 1004. In the RAM 1004, various programs and data required for the operation of the wafer defect detection device are also stored. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems may be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 may allow the wafer defect detection device to communicate with other devices wirelessly or wiredly to exchange data. Although the figure shows a wafer defect detection device having various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems may be alternatively implemented or had.

[0159] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes program codes for executing the methods shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network through the communication device, or installed from the storage device 1003, or installed from the ROM 1002. When the computer program is executed by the processing device 1001, the above functions defined in the methods of the embodiments disclosed in the present application are executed.

[0160] The wafer defect detection device provided by the present application adopts the wafer defect detection method in the above embodiments, and can solve the technical problem of low detection accuracy of wafer defects. Compared with the prior art, the beneficial effects of the wafer defect detection device provided by the present application are the same as those of the wafer defect detection method provided by the above embodiments, and other technical features in the wafer defect detection device are the same as those disclosed in the method of the previous embodiment, and will not be elaborated here.

[0161] It should be understood that each part disclosed in this application can be implemented by hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0162] As described above, the above are only specific embodiments of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application, and all should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

[0163] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., computer programs) stored thereon, and the computer-readable program instructions are used to execute the wafer defect detection method in the above embodiments.

[0164] The computer-readable storage medium provided by this application can be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination of the above. More specific examples of computer-readable storage media can include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) or flash memory, optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this embodiment, the computer-readable storage medium can be any tangible medium that contains or stores a program, and the program can be used by or combined with an instruction execution system, device, or device. The program code contained on the computer-readable storage medium can be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0165] The above computer-readable storage medium can be included in the wafer defect detection device; or it can exist alone without being assembled into the wafer defect detection device.

[0166] The above computer-readable storage medium carries one or more programs, and when the above one or more programs are executed by the wafer defect detection device, the wafer defect detection device is caused to: execute the above wafer defect detection method.

[0167] Computer program code for performing the operations of this application can be written in one or more programming languages or combinations thereof. The above-mentioned programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (for example, by connecting through an Internet service provider using the Internet).

[0168] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of the systems, methods, and computer program products according to the embodiments of this application. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of the code, and this module, program segment, or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0169] The modules described in the embodiments of this application can be implemented in software or in hardware. Among them, the name of the module does not constitute a limitation on the unit itself in some cases.

[0170] The readable storage medium provided by this application is a computer-readable storage medium, and the computer-readable storage medium stores computer-readable program instructions (i.e., computer programs) for performing the above-mentioned wafer defect detection method, which can solve the technical problem of low detection accuracy of wafer defects. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by this application are the same as those of the wafer defect detection method provided in the above embodiments, and will not be elaborated here.

[0171] The present application also provides a computer program product, including a computer program which, when executed by a processor, implements the steps of the wafer defect detection method as described above.

[0172] The computer program product provided by the present application can solve the technical problem of low detection accuracy of wafer defects. Compared with the prior art, the beneficial effects of the computer program product provided by the present application are the same as those of the wafer defect detection method provided by the above embodiments, and will not be elaborated here.

[0173] The above are only partial embodiments of the present application, and thus do not limit the patent scope of the present application. Any equivalent structural transformation made under the technical concept of the present application by using the content of the specification and drawings of the present application, or direct / indirect application in other related technical fields, is included in the patent protection scope of the present application.

Claims

1. A wafer defect detection method, characterized in that: The method includes: Acquire a first wafer image, wherein the first wafer image is composed of a plurality of second wafer images, and the second wafer images are obtained by imaging the same wafer using different imaging methods; The first wafer image is identified by a preset first defect recognition model to obtain a first recognition result, wherein the first defect recognition model includes a plurality of second defect recognition models for identifying the second wafer image, the first recognition result includes a defect category of the corresponding wafer or a corresponding wafer without defects, and the first defect recognition model has a hole convolution module, and the hole convolution module skips values ​​within a preset range during the convolution operation, so as to expand the receptive field of the convolution kernel in the first defect recognition model without reducing the resolution of the feature map obtained by convolving the first wafer image, and fit the slender defects in each defect category; The step of identifying the first wafer image by using a preset first defect recognition model to obtain a first recognition result includes: Determining a corresponding second defect recognition model based on an imaging type identification of each of the second wafer images, wherein the imaging type identification is used to identify the second wafer image based on the imaging type when performing an imaging operation; Based on each of the second defect recognition models, each of the second wafer images is recognized respectively to obtain second recognition results corresponding to each of the second wafer images, wherein the second recognition result includes a defect category of the corresponding wafer or the corresponding wafer is defect-free, the second defect recognition model also includes a plurality of third defect recognition models for detecting defects of different categories, and the second recognition result is obtained by summarizing the third recognition results obtained by the third defect recognition models; The second recognition results are aggregated to obtain a first recognition result.

2. The method according to claim 1, characterized in that Before the step of obtaining the first wafer image, the method further includes: Get wafer sample images; Based on a plurality of dilated convolution modules with different dilated rates in the model to be trained, feature extraction is performed on the wafer sample image to obtain a multi-scale feature map; Based on the multi-scale feature map and the classification module of the model to be trained, wafer defect recognition is performed to obtain a defect recognition result; Based on the defect recognition result, the parameters of the model to be trained are adjusted to obtain a first defect recognition model.

3. The method according to claim 2, characterized in that The step of extracting features from the wafer sample image based on the hole convolution modules with multiple different hole rates in the model to be trained to obtain multi-scale features includes: Based on multiple void convolution modules with different void rates in the model to be trained, feature extraction is performed on the wafer sample images respectively to obtain void feature maps of different scales; Performing a pooling operation on the wafer sample image to obtain a pooling feature map; Based on the feature map channels respectively corresponding to each of the hole feature maps and the pooled feature map, splicing each of the hole feature maps and the pooled feature map to obtain a spliced ​​feature map; The concatenated feature map is convolved point by point to obtain a multi-scale feature map.

4. The method according to claim 1, characterized in that: The step of aggregating the second recognition results to obtain the first recognition result comprises: Based on each of the second recognition results, determining whether there is a same wafer defect; If so, the same wafer defect is regarded as the first wafer defect, and the remaining wafer defects are regarded as the second wafer defects; Based on the geometric parameters of each of the first wafer defects, determining one of the wafer defects as a second wafer defect from a plurality of identical wafer defects corresponding to each of the first wafer defects; The second wafer defects are summarized to obtain a first recognition result.

5. The method according to claim 4, characterized in that: The second recognition result also includes the origin coordinates of the corresponding wafer defect, and the step of judging whether there is the same wafer defect based on each of the second recognition results includes: Based on each of the second identification results, determining whether there are wafer defects of the same type; If so, calculating the difference between the origin coordinates of the wafer defects of the same type; If the difference is within a preset difference range, it is determined that the wafer defects of the same type are the same wafer defects.

6. A wafer defect detection device, characterized in that: The device comprises: An image acquisition module is used to acquire a first wafer image, wherein the first wafer image is composed of a plurality of second wafer images, and the second wafer images are obtained by imaging the same wafer in different imaging modes; A defect recognition module, used to recognize the first wafer image through a preset first defect recognition model to obtain a first recognition result, wherein the first defect recognition model includes a plurality of second defect recognition models for recognizing the second wafer image, the first recognition result includes a defect category of the corresponding wafer or a corresponding wafer without defects, and the first defect recognition model has a hole convolution module, the hole convolution module skips values ​​within a preset range during the convolution operation, so as to expand the receptive field of the convolution kernel in the first defect recognition model without reducing the resolution of the feature map obtained by convolving the first wafer image, and fit the slender defects in each defect category; A model selection submodule, used to determine the corresponding second defect recognition model based on the imaging type identification of each of the second wafer images, wherein the imaging type identification is to identify the second wafer image based on the imaging type when performing the imaging operation; A defect recognition submodule, for respectively recognizing each of the second wafer images based on each of the second defect recognition models, and obtaining second recognition results corresponding to each of the second wafer images, wherein the second recognition result includes a defect category of the corresponding wafer or a corresponding wafer without defects, the second defect recognition model also includes a plurality of third defect recognition models for detecting defects of different categories, and the second recognition result is obtained by summarizing the third recognition results obtained by the third defect recognition models; The result aggregation submodule is used to aggregate the second recognition results to obtain the first recognition result.

7. A wafer defect detection device, characterized in that: The device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the wafer defect detection method according to any one of claims 1 to 5.

8. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the wafer defect detection method according to any one of claims 1 to 5 are implemented.

9. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the wafer defect detection method according to any one of claims 1 to 5 are implemented.

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