Gate driving circuit, driving method thereof and display device

Abstract

The invention provides a gate driving circuit, a driving method thereof and a display device. The gate drive circuit comprises: a node control module configured to control potentials of a first node and a second node according to a clock signal and an input signal; the output control module is configured to provide the voltage of the first node or a first voltage signal to a third node and provide the voltage of the first node or the first voltage signal to a fourth node according to a control signal; and the output module is configured to alternately output the first voltage signal and the second voltage signal according to the potentials of the second node, the third node and the fourth node. According to the technical scheme provided by the invention, the output stability of the gate drive circuit can be improved, and the problems of non-uniform display and the like caused by output voltage fluctuation are reduced.

Description

Technical Field

[0001] The present application relates to the field of display driving technology, and in particular to a gate driving circuit and a driving method thereof, and a display device. Background Art

[0002] At a time when display technology is developing rapidly, the gate drive circuit is the core component of display devices such as active matrix organic light-emitting diode displays (AMOLED), and its output stability is crucial to ensuring display uniformity. However, the gate drive circuit in the current display device has the problem of unstable output voltage, which easily leads to obvious uneven brightness and color on the display panel, which not only damages the user's visual experience, but also limits the further application of display technology in the field of high-precision display. Summary of the invention

[0003] In view of this, the embodiments of the present application are directed to providing a gate driving circuit and a driving method thereof, and a display device, so as to solve the problem of uneven display caused by unstable output voltage of the gate driving circuit.

[0004] In a first aspect, the present application provides a gate drive circuit, comprising: a node control module, configured to control the potential of a first node and a second node according to a clock signal and an input signal; an output control module, configured to provide the voltage of the first node or the first voltage signal to a third node and provide the voltage of the first node or the first voltage signal to a fourth node according to the control signal; and an output module, configured to alternately output the first voltage signal and the second voltage signal according to the potentials of the second node, the third node and the fourth node.

[0005] In one embodiment, the output module includes a first output unit and a second output unit, the first output unit is configured to output a second voltage signal according to the potential of the third node, and the second output unit is configured to output a second voltage signal according to the potential of the fourth node; optionally, the first output unit and the second output unit output the second voltage signal alternately; optionally, the first output unit outputs the second voltage signal in at least part of the first time period, and the second output unit outputs the second voltage signal in at least part of the second time period; optionally, the first output unit includes a first transistor, the control electrode of the first transistor is connected to the third node, the first electrode of the first transistor is connected to the second voltage signal, and the second electrode of the first transistor is connected to the gate signal output terminal; the second output unit includes a second transistor, the control electrode of the second transistor is connected to the fourth node, the first electrode of the second transistor is connected to the second voltage signal, and the second electrode of the second transistor is connected to the gate signal output terminal; optionally, the first transistor and the second transistor are alternately turned on.

[0006] In one embodiment, the output module also includes a third output unit, and the third output unit is configured to output a first voltage signal according to the potential of the second node; optionally, the third output unit includes a third transistor, the control electrode of the third transistor is connected to the second node, the first electrode of the third transistor is connected to the first voltage signal, and the second electrode of the third transistor is connected to the gate signal output terminal; optionally, the first time period includes a first sub-time period and a second sub-time period, in the first sub-time period, the third output unit outputs the first voltage signal to the gate signal output terminal, and in the second sub-time period, the first output unit outputs the second voltage signal to the gate signal output terminal; the second time period includes a third sub-time period and a fourth sub-time period, in the third sub-time period, the third output unit outputs the first voltage signal to the gate signal output terminal, and in the fourth sub-time period, the second output unit outputs a second voltage signal to the gate signal output terminal; optionally, the first time period and the second time period are alternately arranged; optionally, in the first sub-time period, the first transistor and the second transistor are turned off, and the third transistor is turned on; in the second sub-time period, the first transistor is turned on, the second transistor is turned off, and the third transistor is turned off; in the third sub-time period, the first transistor and the second transistor are turned off, and the third transistor is turned on; in the fourth sub-time period, the first transistor is turned off, the second transistor is turned on, and the third transistor is turned off; optionally, one of the first voltage signal and the second voltage signal is a low potential and the other is a high potential; optionally, the first voltage signal is a high potential and the second voltage signal is a low potential; optionally, the gate drive circuit also includes a third capacitor, and the two ends of the third capacitor are respectively connected to the control electrode of the third transistor and the first electrode of the third transistor.

[0007] In one embodiment, the output control module includes a first control unit and a second control unit, the control signal includes a first control signal and a second control signal, the first control unit and the second control unit are configured to control the first output unit and the second output unit to alternately output the second voltage signal according to the first control signal and the second control signal; optionally, the first control unit is configured to provide the voltage of the first node to the third node according to the first control signal, and to provide the first voltage signal to the third node according to the second control signal; the second control unit is configured to provide the voltage of the first node to the fourth node according to the second control signal, and to provide the first voltage signal to the fourth node according to the first control signal; optionally, in the first time period and the second time period, one of the first control signal and the second control signal is a high potential, and the other is a low potential; one of the potentials of the first control signal in the first time period and the potential in the second time period is a high potential, and the other is a low potential; one of the potentials of the second control signal in the first time period and the potential in the second time period is a high potential, and the other is a low potential.

[0008] In one embodiment, the first control unit includes a fourth transistor and a fifth transistor, the control electrode of the fourth transistor is connected to the first control signal, the first electrode of the fourth transistor is connected to the first node, the control electrode of the fifth transistor is connected to the second control signal, the first electrode of the fifth transistor is connected to the first voltage signal, and the second electrode of the fourth transistor and the second electrode of the fifth transistor are connected to the third node; the second control unit includes a sixth transistor and a seventh transistor, the control electrode of the sixth transistor is connected to the second control signal, the first electrode of the sixth transistor is connected to the first node, the control electrode of the seventh transistor is connected to the first control signal, the first electrode of the seventh transistor is connected to the first voltage signal, and the second electrode of the sixth transistor and the second electrode of the seventh transistor are connected to the fourth node; optionally, in the first time period, the fourth transistor is turned on, the fifth transistor is turned off, the sixth transistor is turned off, and the seventh transistor is turned on; in the second time period, the fourth transistor is turned off, the fifth transistor is turned on, the sixth transistor is turned on, and the seventh transistor is turned off.

[0009] In one embodiment, the node control module includes an input unit, the clock signal includes a first clock signal, and the input unit is configured to provide the input signal to the first node according to the first clock signal; optionally, the input unit includes an eighth transistor, a first electrode of the eighth transistor is connected to the input signal, a control electrode of the eighth transistor is connected to the first clock signal, and a second electrode of the eighth transistor is connected to the first node.

[0010] Optionally, the input unit further includes a ninth transistor, the second electrode of the eighth transistor is connected to the first electrode of the ninth transistor, the control electrode of the ninth transistor is connected to the second voltage signal, and the second electrode of the ninth transistor is connected to the first node.

[0011] In one embodiment, the node control module further includes a third control unit,

[0012] The third control unit and the input unit are connected to the first node, and the third control unit is configured to provide a first voltage signal to the second node according to the potential of the first node;

[0013] Alternatively, the third control unit and the input unit are connected to the fifth node, the input unit is further configured to provide the input signal to the fifth node according to the first clock signal, and the third control unit is configured to provide the first voltage signal to the second node according to the potential of the fifth node; optionally, the third control unit includes a tenth transistor, the control electrode of the tenth transistor is connected to the fifth node or the first node, the first electrode of the tenth transistor is connected to the first voltage signal, and the second electrode of the tenth transistor is connected to the second node; optionally, the second electrode of the eighth transistor and the first electrode of the ninth transistor are connected to the fifth node.

[0014] In one embodiment, the node control module also includes a fourth control unit, the clock signal also includes a second clock signal, and the fourth control unit is configured to control the potential of the first node according to the input signal, the first clock signal and the second clock signal; optionally, the fourth control unit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fifteenth transistor, the first electrode of the eleventh transistor is connected to the first voltage signal, the second electrode of the eleventh transistor is connected to the second electrode of the twelfth transistor, the first electrode of the twelfth transistor is connected to the second clock signal, the control electrode of the twelfth transistor is connected to the first electrode of the thirteenth transistor, the second electrode of the thirteenth transistor is connected to the first node, the first electrode of the thirteenth transistor and the control electrode of the thirteenth transistor are connected to the second electrode of the fourteenth transistor, the control electrode of the fourteenth transistor is connected to the second voltage signal, the first electrode of the fourteenth transistor is connected to the second electrode of the fifteenth transistor, the control electrode of the fifteenth transistor is connected to the first clock signal, and the first electrode of the fifteenth transistor is connected to the input signal; optionally, the fourth control unit also includes a first capacitor, and the two ends of the first capacitor are respectively connected to the control electrode of the twelfth transistor and the second electrode of the twelfth transistor. Optionally, the node control module also includes a fifth control unit, which is configured to control the potential of the second node according to the first clock signal and the second clock signal; optionally, the fifth control unit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor and a twentieth transistor, the first electrode of the sixteenth transistor is connected to the second voltage signal, the second electrode of the sixteenth transistor and the first electrode of the seventeenth transistor are connected to the control electrode of the eleventh transistor, the control electrode of the sixteenth transistor is connected to the first clock signal, the control electrode of the seventeenth transistor is connected to the second voltage signal, the second electrode of the seventeenth transistor is connected to the control electrode of the eighteenth transistor, the first electrode of the eighteenth transistor is connected to the second clock signal, the second electrode of the eighteenth transistor is connected to the first electrode of the nineteenth transistor, the second electrode of the nineteenth transistor is connected to the second node, the control electrode of the nineteenth transistor is connected to the second clock signal, the first electrode of the twentieth transistor is connected to the first clock signal, the control electrode of the twentieth transistor is connected to the second electrode of the eighth transistor, and the second electrode of the twentieth transistor is connected to the second electrode of the sixteenth transistor; optionally, the fifth control unit also includes a second capacitor, the two ends of the second capacitor are respectively connected to the control electrode of the eighteenth transistor and the second electrode of the eighteenth transistor; optionally, the first clock signal and the second clock signal have the same frequency and different phases.

[0015] A second aspect of the present application provides a driving method for a gate driving circuit, which is applicable to the gate driving circuit mentioned in any of the above embodiments. The driving method includes: in a first time period, inputting a first control signal in a first level state and a second control signal in a second level state to an output control module, so that the first control unit provides the voltage of the first node to the third node according to the first control signal, and the second control unit provides the first voltage signal to the fourth node according to the first control signal; in a second time period, inputting the first control signal in a second level state and the second control signal in a first level state to the output control module, so that the first control unit provides the first voltage signal to the third node according to the second control signal, and the second control unit provides the voltage of the first node to the fourth node according to the second control signal.

[0016] A third aspect of the present application provides a display device, comprising: a gate driving circuit as mentioned in any of the above embodiments.

[0017] The technical solution provided by the present application, by setting an output control module, controls the transmission of the first node voltage according to the control signal, so that the output module can alternately output the second voltage signal according to the potentials of the third node and the fourth node. This arrangement avoids the problem that the output transistor in the related art is affected by negative bias stress for a long time, the threshold voltage drifts, and the output voltage is unstable. Therefore, the technical solution provided by the present application can improve the stability of the gate drive circuit output and reduce the display unevenness problem caused by output voltage fluctuations.

[0018] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 Shown is a schematic structural diagram of a gate driving circuit provided in one embodiment of the present application.

[0021] Figure 2 Shown is a simulation waveform diagram of a gate driving circuit provided in an embodiment of the present application.

[0022] Figure 3 Shown is a schematic structural diagram of a gate driving circuit provided in another embodiment of the present application.

[0023] Figure 4 Shown is a schematic structural diagram of a gate driving circuit provided in yet another embodiment of the present application.

[0024] Figure 5 Shown is a schematic structural diagram of a gate driving circuit provided in yet another embodiment of the present application.

[0025] Figure 6 Shown is a schematic structural diagram of a gate driving circuit provided in yet another embodiment of the present application.

[0026] Figure 7 Shown is a schematic structural diagram of a gate driving circuit provided in yet another embodiment of the present application.

[0027] Figure 8 FIG. 1 is a flow chart of a control method of a gate driving circuit provided in an embodiment of the present application.

[0028] Fig. 9 Shown is a simulation waveform diagram of a gate driving circuit provided by another embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. Connections may include direct connections or indirect connections.

[0031] As mentioned in the background technology, in the related art, the AMOLED display device uses a gate drive integrated circuit to drive the switch device in the pixel. However, the inventors have found that due to the circuit structure, a "step" will appear in the circuit during the low-level output process, and the height of the step is related to the threshold voltage of the output transistor. Because the output transistor is affected by negative bias stress for a long time, its threshold voltage drifts, causing the output voltage to be unstable, thereby causing the display unevenness problem.

[0032] In view of this, the embodiments of the present application are directed to providing a gate driving circuit and a driving method thereof, and a display device, so as to solve the problem of uneven display caused by unstable output voltage of the gate driving circuit.

[0033] Figure 1 FIG. 1 is a schematic diagram of the structure of a gate drive circuit provided by an embodiment of the present application. Figure 1 As shown, the gate drive circuit includes: a node control module 101, configured to control the potential of the first node N1 and the second node N2 according to the clock signal and the input signal EIN; an output control module 102, configured to provide the voltage of the first node N1 or the first voltage signal VGH to the third node N3 according to the control signal, and provide the voltage of the first node N1 or the first voltage signal VGH to the fourth node N4; an output module 103, configured to alternately output the first voltage signal VGH and the second voltage signal VGL according to the potentials of the second node N2, the third node N3 and the fourth node N4.

[0034] Specifically, the node control module 101 is used to control the potential of the first node N1 and the second node N2 according to the clock signal and the input signal EIN to provide an on (or off) voltage for the output module 103. Exemplarily, Figure 2 FIG. 1 is a simulation waveform diagram of a gate drive circuit provided by an embodiment of the present application. Figure 1 and Figure 2 The input signal EIN can be a gate high voltage (Voltage Gate High, VGH) or a gate low voltage (Voltage Gate Low, VGL). The first voltage signal VGH is a gate high voltage, and the second voltage signal VGL is a gate low voltage.

[0035] The output module 103 alternately outputs the first voltage signal VGH and the second voltage signal VGL according to the potentials of the second node N2, the third node N3 and the fourth node N4. However, in the related art, when the output module 103 outputs the second voltage signal VGL, there is a problem of unstable output voltage. The present solution sets an output control module 102, which is connected to the third node N3 and the fourth node N4 with the output module 103. The output control module 102 controls the voltage of the first node N1 and the transmission of the first voltage signal VGH according to the control signal. For example, in a partial period, such as at least a partial period of the first period, the output control module 102 transmits the voltage of the first node N1 to the third node N3 according to the control signal, and transmits the first voltage signal VGH to the fourth node N4 at the same time. For another example, in a partial period, such as at least a partial period of the second period, the output control module 102 transmits the voltage of the first node N1 to the fourth node N4 according to the control signal, and transmits the first voltage signal VGH to the third node N3 at the same time. Exemplarily, when the third node N3 receives the voltage of the first node N1, the fourth node N4 receives the first voltage signal VGH, and the output module 103 outputs the second voltage signal VGL according to the potential of the third node N3. When the fourth node N4 receives the voltage of the first node N1, the third node N3 receives the first voltage signal VGH, and the output module 103 outputs the second voltage signal VGL according to the potential of the fourth node N4. By controlling the control period of the control signal (for example, including the first control signal XT1 and the second control signal XT2), the output module 103 can be controlled to alternately output the second voltage signal VGL according to the potentials of the third node N3 and the fourth node N4.

[0036] The technical solution of this embodiment, by setting the output control module 102, controls the transmission of the voltage of the first node N1 according to the control signal, so that the output module 103 can alternately output the second voltage signal VGL according to the potentials of the third node N3 and the fourth node N4. This arrangement avoids the problem that the output transistor in the related art is affected by the negative bias stress for a long time, the threshold voltage drifts, and the output voltage is unstable. Therefore, the technical solution provided by the embodiment of the present application can improve the stability of the output of the gate drive circuit and reduce the display unevenness caused by the output voltage fluctuation.

[0037] Figure 3 FIG. 2 is a schematic diagram of the structure of a gate drive circuit provided by another embodiment of the present application. Figure 3As shown, the output module 103 includes a first output unit 1031 and a second output unit 1032, the first output unit 1031 is configured to output a second voltage signal VGL according to the potential of the third node N3, and the second output unit 1032 is configured to output the second voltage signal VGL according to the potential of the fourth node N4; optionally, the first output unit 1031 and the second output unit 1032 alternately output the second voltage signal VGL; or, the first output unit 1031 and the second output unit 1032 output the second voltage signal VGL in a time-sharing manner; optionally, the first output unit 1031 outputs the second voltage signal VGL in at least a part of the first time period t1, and the second output unit 1032 outputs the second voltage signal VGL in at least a part of the second time period t2; optionally , the first output unit 1031 includes a first transistor T1, the control electrode of the first transistor T1 is connected to the third node N3, the first electrode of the first transistor T1 is connected to the second voltage signal VGL and / or connected to the second power line (the second voltage signal VGL can be transmitted), and the second electrode of the first transistor T1 is connected to the gate signal output terminal EM_OUT; the second output unit 1032 includes a second transistor T2, the control electrode of the second transistor T2 is connected to the fourth node N4, the first electrode of the second transistor T2 is connected to the second voltage signal VGL and / or connected to the second power line, and the second electrode of the second transistor T2 is connected to the gate signal output terminal EM_OUT; optionally, the first transistor T1 and the second transistor T2 are alternately turned on, or the first transistor T1 and the second transistor T2 are turned on in time division. For example, in at least part of the first time period t1, the first transistor T1 is turned on; in at least part of the second time period t2, the second transistor T2 is turned on.

[0038] For example, the first transistor T1 and the second transistor T2 have the same channel type, for example, the first transistor T1 and the second transistor T2 are N-type transistors, or the first transistor T1 and the second transistor T2 are P-type transistors.

[0039] Specifically, the gate signal output terminal EM_OUT of the gate driving circuit can be used to output the gate driving signal. By controlling the control period of the control signal (for example, including the first control signal XT1 and the second control signal XT2), the output control module 102 can control the first output unit 1031 and the second output unit 1032 to alternately output the second voltage signal VGL according to the potentials of the third node N3 and the fourth node N4, respectively. Exemplarily, the first output unit 1031 outputs the second voltage signal VGL in at least part of the first period t1, and the second output unit 1032 outputs the second voltage signal VGL in at least part of the second period t2, for example, the first period t1 is one or more, the second period t2 is one or more, and the first period t1 and the second period t2 are alternately arranged.

[0040] The control electrode (gate) of the first transistor T1 is connected to the third node N3, which is used to receive the voltage of the first node N1 or the first voltage signal VGH, and control the on-off state of the first transistor T1. The first electrode (source) of the first transistor T1 is connected to the second voltage signal VGL, and the second electrode (drain) of the first transistor T1 is connected to the gate signal output terminal EM_OUT. When the first transistor T1 is turned on, the second electrode of the first transistor T1 outputs the second voltage signal VGL. The control electrode (gate) of the second transistor T2 is connected to the fourth node N4, which is used to receive the voltage of the first node N1 or the first voltage signal VGH, and control the on-off state of the second transistor T2. The first electrode (source) of the second transistor T2 is connected to the second voltage signal VGL, and the second electrode (drain) of the second transistor T2 is connected to the gate signal output terminal EM_OUT. When the second transistor T2 is turned on, the second electrode of the second transistor T2 outputs the second voltage signal VGL. Exemplarily, during at least part of the first time period t1, the first transistor T1 is turned on and the second transistor T2 is turned off; during at least part of the second time period t2, the first transistor T1 is turned off and the second transistor T2 is turned on.

[0041] In this embodiment, by controlling the control electrodes of the first transistor T1 and the second transistor T2 respectively, the first output unit 1031 and the second output unit 1032 can be accurately controlled to output the second voltage signal VGL according to a preset control period. Since the first output unit 1031 and the second output unit 1032 can work independently, the second voltage signal VGL can be alternately output according to the control signal (for example, including the first control signal XT1 and the second control signal XT2), thereby preventing the first transistor T1 or the second transistor T2 from being affected by negative bias stress for a long time, causing the threshold voltage to drift, and causing the problem of unstable output voltage.

[0042] Figure 4 FIG. 2 is a schematic diagram of the structure of a gate drive circuit provided by another embodiment of the present application. Figure 4 As shown, the output module 103 also includes a third output unit 1033, and the third output unit 1033 is configured to output a first voltage signal VGH according to the potential of the second node N2; optionally, the third output unit 1033 includes a third transistor T3, the control electrode of the third transistor T3 is connected to the second node N2, the first electrode of the third transistor T3 is connected to the first voltage signal VGH and / or connected to the first power line (which can transmit the first voltage signal VGH), and the second electrode of the third transistor T3 is connected to the gate signal output terminal EM_OUT.

[0043] Optionally, the first period t1 includes a first sub-period t11 and a second sub-period t12, in which the third output unit 1033 outputs the first voltage signal VGH to the gate signal output terminal EM_OUT, and in the second sub-period t12, the first output unit 1031 outputs the second voltage signal VGL to the gate signal output terminal EM_OUT. Optionally, the second period t2 includes a third sub-period t13 and a fourth sub-period t14, in which the third output unit 1033 outputs the first voltage signal VGH to the gate signal output terminal EM_OUT, and in the fourth sub-period t14, the second output unit 1032 outputs the second voltage signal VGL to the gate signal output terminal EM_OUT.

[0044] Optionally, the first time period t1 and the second time period t2 are alternately arranged. Optionally, in the first sub-time period t11, the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 is turned on; in the second sub-time period t12, the first transistor T1 is turned on, the second transistor T2 is turned off, and the third transistor T3 is turned off; in the third sub-time period t13, the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 is turned on; in the fourth sub-time period t14, the first transistor T1 is turned off, the second transistor T2 is turned on, and the third transistor T3 is turned off.

[0045] Optionally, one of the first voltage signal VGH and the second voltage signal VGL is a low potential, and the other is a high potential; optionally, the first voltage signal VGH is a high potential, and the second voltage signal VGL is a low potential. The first voltage signal VGH and the second voltage signal VGL may be DC potentials.

[0046] Optionally, the gate driving circuit further includes a third capacitor C3, and two ends of the third capacitor C3 are respectively connected to the control electrode of the third transistor T3 and the first electrode of the third transistor T3.

[0047] Specifically, the third output unit 1033 outputs the first voltage signal VGH according to the potential of the second node N2, and the third output unit 1033 and the first output unit 1031 (or the second output unit 1032) work alternately. The control electrode (gate) of the third transistor T3 is connected to the second node N2, which is used to receive the voltage of the second node N2 and control the on-off state of the third transistor T3. The first electrode (source) of the third transistor T3 is connected to the first voltage signal VGH, and the second electrode (drain) of the third transistor T3 is connected to the output node EM_OUT. When the third transistor T3 is turned on, the second electrode of the third transistor T3 outputs the first voltage signal VGH.

[0048] Exemplarily, in the first sub-period t11, the first transistor T1 and the second transistor T2 are turned off, the third transistor T3 is turned on, and the second electrode of the third transistor T3 outputs the first voltage signal VGH. In the second sub-period t12, the first transistor T1 is turned on, the second electrode of the first transistor T1 outputs the second voltage signal VGL, and the second transistor T2 and the third transistor T3 are turned off. In the third sub-period t13, the first transistor T1 and the second transistor T2 are turned off, the third transistor T3 is turned on, and the second electrode of the third transistor T3 outputs the first voltage signal VGH. In the fourth sub-period t14, the first transistor T1 is turned off, the second transistor T2 is turned on, the second electrode of the second transistor T2 outputs the second voltage signal VGL, and the third transistor T3 is turned off.

[0049] In this embodiment, by setting the third output unit 1033, the output module 103 can output the first voltage signal VGH according to the potential of the second node N2, so that the gate driving circuit can alternately output the first voltage signal VGH and the second voltage signal VGL in time periods to control the on-off state of the transistor in the pixel circuit. Further, the reliability of the circuit is enhanced, which is conducive to improving the display unevenness problem.

[0050] Figure 5 FIG. 2 is a schematic diagram of the structure of a gate drive circuit provided by another embodiment of the present application. Figure 5 As shown, the output control module 102 includes a first control unit 1021 and a second control unit 1022, and the control signal includes a first control signal XT1 and a second control signal XT2. The first control unit 1021 and the second control unit 1022 are configured to control the first output unit 1031 and the second output unit 1032 to alternately output the second voltage signal VGL according to the first control signal XT1 and the second control signal XT2; optionally, the first control unit 1021 is configured to provide the voltage of the first node N1 to the third node N3 according to the first control signal XT1, and to provide the first voltage signal VGH to the third node N3 according to the second control signal XT2; the second control unit 1022 is configured to provide the voltage of the first node N1 to the fourth node N4 according to the second control signal XT2, and to provide the first voltage signal VGH to the fourth node N4 according to the first control signal XT1.

[0051] Optionally, in the first time period t1 and the second time period t2, one of the first control signal XT1 and the second control signal XT2 is a high potential, and the other is a low potential; one of the potential of the first control signal XT1 in the first time period t1 and the potential in the second time period t2 is a high potential, and the other is a low potential; one of the potential of the second control signal XT2 in the first time period t1 and the potential in the second time period t2 is a high potential, and the other is a low potential.

[0052] Specifically, the first control unit 1021 controls the working state of the first output unit 1031 according to the first control signal XT1 and the second control signal XT2. The second control unit 1022 controls the working state of the second output unit 1032 according to the first control signal XT1 and the second control signal XT2. Exemplarily, the first control signal XT1 is a low potential in the first period t1 and a high potential in the second period t2; the second control signal XT2 is a high potential in the first period t1 and a low potential in the second period t2. For example, the first control unit 1021 transfers the voltage of the first node N1 to the third node N3 according to the first control signal XT1 and the second control signal XT2, and the second control unit 1022 transfers the first voltage signal VGH to the fourth node N4 according to the first control signal XT1 and the second control signal XT2. When the third node N3 receives the voltage of the first node N1, the fourth node N4 receives the first voltage signal VGH, and the first output unit 1031 outputs the second voltage signal VGL according to the potential of the third node N3. For another example, the second control unit 1022 transmits the voltage of the first node N1 to the fourth node N4 according to the first control signal XT1 and the second control signal XT2, and the first control unit 1021 transmits the first voltage signal VGH to the third node N3 according to the first control signal XT1 and the second control signal XT2. When the fourth node N4 receives the voltage of the first node N1, the third node N3 receives the first voltage signal VGH, and the second output unit 1032 outputs the second voltage signal VGL according to the potential of the fourth node N4. Therefore, by controlling the control period of the first control signal XT1 and the second control signal XT2, the first output unit 1031 and the second output unit 1032 can be controlled to alternately output the second voltage signal VGL according to the potentials of the third node N3 and the fourth node N4.

[0053] In this embodiment, through the configuration of the first control unit 1021 and the second control unit 1022, the first output unit 1031 and the second output unit 1032 can alternately output the second voltage signal VGL, reduce the output voltage fluctuation of the driving circuit, thereby improving the display uniformity, and reducing or eliminating the display problems caused by uneven voltage. Further, the first control unit 1021 and the second control unit 1022 control the first output unit 1031 and the second output unit 1032 respectively, so that the operation logic of the output control module 102 is simpler, which is easy to implement and maintain.

[0054] Figure 6 FIG. 2 is a schematic diagram of the structure of a gate drive circuit provided by another embodiment of the present application. Figure 6As shown, the first control unit 1021 includes a fourth transistor T4 and a fifth transistor T5, the control electrode of the fourth transistor T4 is connected to the first control signal XT1, the first electrode of the fourth transistor T4 is connected to the first node N1, the control electrode of the fifth transistor T5 is connected to the second control signal XT2, the first electrode of the fifth transistor T5 is connected to the first voltage signal VGH and / or connected to the first power line, and the second electrode of the fourth transistor T4 and the second electrode of the fifth transistor T5 are connected to the third node N3. The control electrode of the fourth transistor T4 and the control electrode of the fifth transistor T5 can be connected to different control signals, that is, connected to different control signal lines. For example, the channel type of the fourth transistor T4 and the fifth transistor T5 can be the same, for example, the fourth transistor T4 and the fifth transistor T5 are N-type transistors, or the fourth transistor T4 and the fifth transistor T5 are P-type transistors. For example, the switching states of the fourth transistor T4 and the fifth transistor T5 are opposite.

[0055] In other embodiments, the control electrode of the fourth transistor T4 and the control electrode of the fifth transistor T5 can be connected to the same control signal, that is, connected to the same control signal line. For example, the channel types of the fourth transistor T4 and the fifth transistor T5 can be different. For example, the fourth transistor T4 is a P-type transistor and the fifth transistor T5 is an N-type transistor, or the fourth transistor T4 is an N-type transistor and the fifth transistor T5 is a P-type transistor.

[0056] Optionally, the second control unit 1022 includes a sixth transistor T6 and a seventh transistor T7, the control electrode of the sixth transistor T6 is connected to the second control signal XT2, the first electrode of the sixth transistor T6 is connected to the first node N1, the control electrode of the seventh transistor T7 is connected to the first control signal XT1, the first electrode of the seventh transistor T7 is connected to the first voltage signal VGH and / or connected to the first power line, and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 are connected to the fourth node N4. For example, the channel type of the sixth transistor T6 and the seventh transistor T7 can be the same, for example, the sixth transistor T6 and the seventh transistor T7 are N-type transistors, or the sixth transistor T6 and the seventh transistor T7 are P-type transistors. For example, the switching states of the sixth transistor T6 and the seventh transistor T7 are opposite.

[0057] In other embodiments, the control electrode of the sixth transistor T6 and the control electrode of the seventh transistor T7 can be connected to the same control signal, for example, the channel types of the sixth transistor T6 and the seventh transistor T7 can be different, for example, the sixth transistor T6 is a P-type transistor and the seventh transistor T7 is an N-type transistor, or the sixth transistor T6 is an N-type transistor and the seventh transistor T7 is a P-type transistor.

[0058] For example, the switching states of the fourth transistor T4 and the sixth transistor T6 are opposite. For example, the channel types of the fourth transistor T4 and the sixth transistor T6 may be the same. The fourth transistor T4 and the sixth transistor T6 may be connected to different control signals, that is, connected to different control signal lines.

[0059] For example, the channel types of the fourth transistor T4 and the sixth transistor T6 may be different. The fourth transistor T4 and the sixth transistor T6 may be connected to the same control signal, that is, connected to the same control signal line.

[0060] Optionally, in the first time period t1, the fourth transistor T4 is turned on, the fifth transistor T5 is turned off, the sixth transistor T6 is turned off, and the seventh transistor T7 is turned on; in the second time period t2, the fourth transistor T4 is turned off, the fifth transistor T5 is turned on, the sixth transistor T6 is turned on, and the seventh transistor T7 is turned off.

[0061] Specifically, the control electrode (gate) of the fourth transistor T4 is connected to the first control signal XT1 to control the on-off state of the fourth transistor T4. The first electrode (source) of the fourth transistor T4 is connected to the first node N1 and is connected to the voltage of the first node N1. The second electrode (drain) of the fourth transistor T4 is connected to the third node N3. When the fourth transistor T4 is turned on, the fourth transistor T4 transfers the voltage of the first node N1 to the third node N3 to control the operation of the first transistor T1.

[0062] The control electrode (gate) of the fifth transistor T5 is connected to the second control signal XT2 to control the on-off state of the fifth transistor T5. The first electrode (source) of the fifth transistor T5 is connected to the first voltage signal VGH. The second electrode (drain) of the fifth transistor T5 is connected to the third node N3. When the fifth transistor T5 is turned on, the fifth transistor T5 transmits the first voltage signal VGH to the third node N3 to control the first transistor T1 to stop working.

[0063] The control electrode (gate) of the sixth transistor T6 is connected to the second control signal XT2 to control the on-off state of the sixth transistor T6. The first electrode (source) of the sixth transistor T6 is connected to the first node N1 and is connected to the voltage of the first node N1. The second electrode (drain) of the sixth transistor T6 is connected to the fourth node N4. When the sixth transistor T6 is turned on, the sixth transistor T6 transfers the voltage of the first node N1 to the fourth node N4 to control the operation of the second transistor T2.

[0064] The control electrode (gate) of the seventh transistor T7 is connected to the first control signal XT1 to control the on-off state of the seventh transistor T7. The first electrode (source) of the seventh transistor T7 is connected to the first voltage signal VGH. The second electrode (drain) of the seventh transistor T7 is connected to the fourth node N4. When the seventh transistor T7 is turned on, the seventh transistor T7 transmits the first voltage signal VGH to the fourth node N4 to control the second transistor T2 to stop working.

[0065] Exemplarily, in the first period t1, the fourth transistor T4 is turned on, the fourth transistor T4 transmits the voltage of the first node N1 to the third node N3, the fifth transistor T5 is turned off, and the first transistor T1 is controlled to work; the sixth transistor T6 is turned off, the seventh transistor T7 is turned on, the seventh transistor T7 transmits the first voltage signal VGH to the fourth node N4, and the second transistor T2 is controlled to stop working. In the second period t2, the fourth transistor T4 is turned off, the fifth transistor T5 is turned on, the fifth transistor T5 transmits the first voltage signal VGH to the third node N3, and the first transistor T1 is controlled to stop working; the sixth transistor T6 is turned on, the sixth transistor T6 transmits the voltage of the first node N1 to the fourth node N4, and the seventh transistor T7 is turned off, and the second transistor T2 is controlled to work.

[0066] In this embodiment, through the combination of the fourth transistor T4 and the fifth transistor T5, the first control unit 1021 can accurately switch the voltage of the third node N3 according to the first control signal XT1 and the second control signal XT2, thereby controlling the working state of the first output unit 1031. Through the combination of the sixth transistor T6 and the seventh transistor T7, the second control unit 1022 can accurately switch the voltage of the fourth node N4 according to the first control signal XT1 and the second control signal XT2, thereby controlling the working state of the second output unit 1032. This arrangement avoids the first transistor T1 or the second transistor T2 from being affected by negative bias stress for a long time, causing the threshold voltage to drift, resulting in an unstable output voltage, and further helps to improve the display unevenness problem.

[0067] Figure 7 FIG. 2 is a schematic diagram of the structure of a gate drive circuit provided by another embodiment of the present application. Figure 7 As shown, the node control module 101 includes an input unit, the clock signal includes a first clock signal CK1, and the input unit is configured to provide an input signal EIN to the first node N1 according to the first clock signal CK1; optionally, the input unit includes an eighth transistor T8, a first electrode of the eighth transistor T8 is connected to the input signal EIN, a control electrode of the eighth transistor T8 is connected to the first clock signal CK1, and a second electrode of the eighth transistor T8 is connected to the first node N1.

[0068] Optionally, the input unit further includes a ninth transistor T9, the second electrode of the eighth transistor T8 is connected to the first electrode of the ninth transistor T9; the control electrode of the ninth transistor T9 is connected to the second voltage signal VGL and / or the second power line, and the second electrode of the ninth transistor T9 is connected to the first node N1. That is, the second electrode of the eighth transistor T8 is indirectly connected to the first node N1.

[0069] Specifically, the control electrode (gate) of the eighth transistor T8 is connected to the first clock signal CK1 to control the on-off state of the eighth transistor T8. The first electrode (source) of the eighth transistor T8 is connected to the input signal EIN, and the second electrode (drain) is connected to the first electrode or the first node N1 of the ninth transistor T9. Exemplarily, when the first clock signal CK1 is at a low level, the eighth transistor T8 is turned on and the input signal EIN is transferred to the ninth transistor T9. The control electrode of the ninth transistor T9 is connected to the second voltage signal VGL to control the on-off state of the ninth transistor T9. Exemplarily, the ninth transistor T9 is a P-type transistor. The ninth transistor T9 is a normally open transistor in the gate drive circuit. The second electrode of the ninth transistor T9 is connected to the first node N1 to transfer the received input signal EIN to the first node N1.

[0070] In this embodiment, by using the first clock signal CK1 to control the eighth transistor T8, it is possible to ensure that the input signal EIN is transmitted to the first node N1 at the correct time, thereby achieving synchronization with the entire display system clock. Through the switching characteristics of the transistor, the loss and interference of the signal during the transmission process can be reduced, and the reliability of signal transmission can be improved. The design using a transistor as an input unit can simplify the circuit layout, reduce the number of components, and reduce the complexity and manufacturing cost of the circuit board.

[0071] In one embodiment, see Figure 7 , the node control module 101 also includes a third control unit.

[0072] The third control unit and the input unit are connected to the first node N1 , and the third control unit is configured to provide the first voltage signal VGH to the second node N2 according to the potential of the first node N1 .

[0073] Alternatively, the third control unit and the input unit are connected to the fifth node N5, the input unit is further configured to provide the input signal EIN to the fifth node N5 according to the first clock signal CK1, and the third control unit is configured to provide the first voltage signal VGH to the second node N2 according to the potential of the fifth node N5.

[0074] Optionally, the third control unit includes a tenth transistor T10, and the control electrode of the tenth transistor T10 is connected to the fifth node N5 (eg Figure 7 ) or the first node N1 (as shown Figure 8As shown), the first electrode of the tenth transistor T10 is connected to the first voltage signal VGH, and the second electrode of the tenth transistor T10 is connected to the second node N2; for example, the second electrode of the eighth transistor T8 and the first electrode of the ninth transistor T9 are connected to the fifth node N5.

[0075] Specifically, the input unit not only provides the input signal EIN to the first node N1, but also provides the input signal EIN to the fifth node N5 according to the first clock signal CK1. The third control unit and the input unit are connected to the fifth node N5 or the first node N1, and decide whether to provide the first voltage signal VGH to the second node N2 according to the potential of the fifth node N5 or the first node N1. The control electrode (gate) of the tenth transistor T10 is connected to the fifth node N5 or the first node N1, and the on-off state of the tenth transistor T10 is controlled according to the potential of the fifth node N5 or the first node N1. The first electrode (source) of the tenth transistor T10 is connected to the first voltage signal VGH, and the second electrode (drain) is connected to the second node N2. Exemplarily, when the potential of the fifth node N5 or the first node N1 is at a low level, the tenth transistor T10 is turned on and the input signal EIN is transmitted to the second node N2 to control the third transistor T3 to stop working.

[0076] In this embodiment, when the fifth node N5 or the first node N1 is at a low level, the tenth transistor T10 is turned on, and the first voltage signal VGH is provided to the second node N2, so as to realize the pull-up function of the gate level of the third transistor T3. This arrangement further improves the reliability of the circuit, simplifies the circuit design, reduces additional pull-up resistors or other pull-up components, and reduces the complexity and cost of the circuit.

[0077] In one embodiment, see Figure 7, the node control module 101 also includes a fourth control unit, the clock signal also includes a second clock signal CK2, the fourth control unit is configured to control the potential of the first node N1 according to the input signal EIN, the first clock signal CK1 and the second clock signal CK2; for example, the fourth control unit is configured to provide the input signal EIN to the first node N1 according to the first clock signal CK1 and the second clock signal CK2. Optionally, the fourth control unit includes an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14 and a fifteenth transistor T15, the first electrode of the eleventh transistor T11 is connected to the first voltage signal VGH and / or connected to the first power line, the second electrode of the eleventh transistor T11 is connected to the second electrode of the twelfth transistor T12, the first electrode of the twelfth transistor T12 is connected to the second clock signal CK2, the control electrode of the twelfth transistor T12 is connected to the first electrode of the thirteenth transistor T13, the second electrode of the thirteenth transistor T13 is connected to the first node N1, and the thirteenth transistor The first electrode of T13 and the control electrode of the thirteenth transistor T13 are connected to the second electrode of the fourteenth transistor T14, the control electrode of the fourteenth transistor T14 is connected to the second voltage signal VGL and / or is connected to the second power line, the first electrode of the fourteenth transistor T14 is connected to the second electrode of the fifteenth transistor T15, the control electrode of the fifteenth transistor T15 is connected to the first clock signal CK1, and the first electrode of the fifteenth transistor T15 is connected to the input signal EIN; optionally, the fourth control unit also includes a first capacitor C1, and the two ends of the first capacitor C1 are respectively connected to the control electrode of the twelfth transistor T12 and the second electrode of the twelfth transistor T12.Optionally, the node control module 101 further includes a fifth control unit, which is configured to control the potential of the second node N2 according to the first clock signal CK1 and the second clock signal CK2; optionally, the fifth control unit includes a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19 and a twentieth transistor T20, the first electrode of the sixteenth transistor T16 is connected to the second voltage signal VGL and / or connected to the second power line, the second electrode of the sixteenth transistor T16 and the first electrode of the seventeenth transistor T17 are connected to the control electrode of the eleventh transistor T11, the control electrode of the sixteenth transistor T16 is connected to the first clock signal CK1, the control electrode of the seventeenth transistor T17 is connected to the second voltage signal VGL and / or connected to the second power line, the second electrode of the seventeenth transistor T17 and the first electrode of the eighteenth transistor T18 are connected to the control electrode of the eleventh transistor T11, The control electrode is connected, the first electrode of the eighteenth transistor T18 is connected to the second clock signal CK2, the second electrode of the eighteenth transistor T18 is connected to the first electrode of the nineteenth transistor T19, the second electrode of the nineteenth transistor T19 is connected to the second node N2, the control electrode of the nineteenth transistor T19 is connected to the second clock signal CK2, the first electrode of the twentieth transistor T20 is connected to the first clock signal CK1, the control electrode of the twentieth transistor T20 is connected to the second electrode of the eighth transistor T8, and the second electrode of the twentieth transistor T20 is connected to the second electrode of the sixteenth transistor T16; optionally, the fifth control unit also includes a second capacitor C2, and the two ends of the second capacitor C2 are respectively connected to the control electrode of the eighteenth transistor T18 and the second electrode of the eighteenth transistor T18; optionally, the first clock signal CK1 and the second clock signal CK2 have the same frequency and different phases, for example, opposite.

[0078] Specifically, the fourth control unit includes the eleventh transistor T11 to the fifteenth transistor T15 and the first capacitor C1, which work together to provide the input signal EIN to the first node N1 according to the first clock signal CK1 and the second clock signal CK2. The circuit composed of the eleventh to fifteenth transistors T15 can realize the fourth control function of the potential of the first node N1, that is, under the control of the first clock signal CK1 and the second clock signal CK2, the potential of the first node N1 is pulled down.

[0079] The fifth control unit includes sixteenth transistors T16 to twentieth transistors T20, a second capacitor C2 and a third capacitor C3. These components work together to provide the second voltage signal VGL to the second node N2 according to the first clock signal CK1 and the second clock signal CK2 to control the operation of the third transistor T3. The fifth control unit is used to maintain the stability of the voltage of the second node N2, and is not affected by external interference or fluctuations during signal transmission.

[0080] In this embodiment, the fourth control unit ensures that the potential of the first node N1 can be pulled down when necessary, so that the conduction degree of the first transistor T1 is increased, and the stability of signal transmission is improved. The fifth control unit can effectively maintain the voltage stability of the second node N2 through the combination of transistors and capacitors, which is crucial for the normal operation of the entire circuit. The design of the fifth control unit and the fourth control unit increases the redundancy of the circuit and further improves the reliability of the circuit in the face of voltage fluctuations and external interference.

[0081] In one embodiment, see Figure 7 , the node control module 101 also includes a reset unit, which is configured to control the potential of the fifth node N5 according to the reset signal REST. Exemplarily, the reset unit includes a twenty-first transistor T21, the first electrode of the twenty-first transistor T21 is connected to the first voltage signal VGH and / or connected to the first power line, the control electrode of the twenty-first transistor T21 is connected to the reset signal REST, the second electrode of the twenty-first transistor T21 and the control electrode of the tenth transistor T10 and the first electrode of the ninth transistor T9 are connected to the fifth node, and the second electrode of the twenty-first transistor T21 is connected to the second electrode of the eighth transistor T8. Exemplarily, when the twenty-first transistor T21 is turned on, the second electrode of the twenty-first transistor T21 outputs the first voltage signal VGH to the fifth node N5 to reset the gate drive circuit.

[0082] Each transistor in the above embodiments may include a P-type transistor or an N-type transistor, such as Figure 7 As shown, each transistor may include a P-type transistor.

[0083] Figure 8 FIG. 1 is a flow chart of a driving method of a gate driving circuit provided in an embodiment of the present application, which is applicable to driving the gate driving circuit mentioned in any of the above embodiments. Figure 8 As shown, the driving method includes:

[0084] S110, in the first time period, input a first control signal in a first level state and a second control signal in a second level state to the output control module, so that the first control unit provides the voltage of the first node to the third node according to the first control signal, and the second control unit provides the first voltage signal to the fourth node according to the first control signal.

[0085] For example, one of the first level state and the second level state is a low level state, and the other is a high level state. For example, the first level state is a low level state, and the second level state is a high level state.

[0086] For example, Fig. 9 FIG. 2 is a simulation waveform diagram of a gate drive circuit provided by another embodiment of the present application. Fig. 9As shown, in the first period t1, the first control signal XT1 in the low level state and the second control signal XT2 in the high level state are input to the output control module 102, for example, the fourth transistor T4 and the seventh transistor T7 are connected to the on level, and the fifth transistor T5 and the sixth transistor T6 are connected to the off level, so that the first control unit 1021 provides the voltage of the first node N1 to the third node N3 according to the first control signal XT1, and the potential of the third node N3 is a low potential. The second control unit 1022 provides the first voltage signal VGH to the fourth node N4 according to the first control signal XT1, and the potential of the fourth node N4 is a high potential. Then the first output unit 1031 receives the low level control signal to turn on and output the second voltage signal VGL, and the second output unit 1032 receives the high level control signal to turn off. The first transistor T1 is in the negative bias stress (NBS) state, and the second transistor T2 is in the positive bias stress (PBS) state.

[0087] Exemplarily, in the first sub-period t11, the potential of the third node N3 is a high potential, and the potential of the fourth node N4 is a high potential. Therefore, the first transistor T1 and the second transistor T2 are turned off, the third transistor T3 is turned on, and the second electrode of the third transistor T3 outputs the first voltage signal VGH. In the second sub-period t12, the potential of the third node N3 is a low potential, and the potential of the fourth node N4 is a high potential. Therefore, the first transistor T1 is turned on, the second electrode of the first transistor T1 outputs the second voltage signal VGL, and the second transistor T2 and the third transistor T3 are turned off.

[0088] S120, in the second time period, a first control signal in a second level state and a second control signal in a first level state are input to the output control module, so that the first control unit provides the first voltage signal to the third node according to the second control signal, and the second control unit provides the voltage of the first node to the fourth node according to the second control signal.

[0089] Specifically, in the second period t2, the first control signal XT1 in a high level state and the second control signal XT2 in a low level state are input to the output control module 102, for example, the fourth transistor T4 and the seventh transistor T7 are connected to the off level, and the fifth transistor T5 and the sixth transistor T6 are connected to the on level, so that the first control unit 1021 provides the first voltage signal VGH to the third node N3 according to the second control signal XT2, and the potential of the third node N3 is a high potential. The second control unit 1022 provides the voltage of the first node N1 to the fourth node N4 according to the second control signal XT2, and the potential of the fourth node N4 is a low potential. Then the second output unit 1032 receives the low level control signal to turn on and output the second voltage signal VGL, and the first output unit 1031 receives the high level control signal to turn off. The second transistor T2 is in the NBS state, and the first transistor T1 is in the PBS state.

[0090] Exemplarily, in the third sub-period t13, the potential of the third node N3 is a high potential, and the potential of the fourth node N4 is a high potential. Therefore, the first transistor T1 and the second transistor T2 are turned off, the third transistor T3 is turned on, and the second electrode of the third transistor T3 outputs the first voltage signal VGH. In the fourth sub-period t14, the potential of the third node N3 is a high potential, and the potential of the fourth node N4 is a low potential. Therefore, the first transistor T1 is turned off, the second transistor T2 is turned on, the second electrode of the second transistor T2 outputs the second voltage signal VGL, and the third transistor T3 is turned off.

[0091] The technical solution of this embodiment can realize that the first control unit and the second control unit control the first output unit and the second output unit to alternately output the second voltage signal by switching the level state of the first control signal and the second control signal at different stages. In such a control cycle, the first transistor and the second transistor are periodically switched between the two states, which avoids the first transistor and the second transistor being affected by negative bias stress for a long time, causing the threshold voltage to drift and causing the output voltage to be unstable. Therefore, the technical solution provided by the embodiment of the present application can improve the stability of the output of the gate drive circuit and reduce the problem of uneven display caused by output voltage fluctuations.

[0092] The embodiment of the present application further provides a display device, comprising: a gate drive circuit as mentioned in any of the above embodiments. The display device has the beneficial effects of the gate drive circuit mentioned in any of the above embodiments, and its technical principles and effects are similar, which will not be repeated here. The display device may include electronic products such as mobile phones, tablet computers, laptops, wearable devices, vehicle-mounted devices, smart watches, etc.

[0093] The gate drive circuit may be connected to a first clock line and a second clock line. The first clock line may be used to provide a first clock signal to the odd-numbered gate drive circuit, and the second clock line may be used to provide a second clock signal to the odd-numbered gate drive circuit. The first clock line may be used to provide a second clock signal to the even-numbered gate drive circuit, and the second clock line may be used to provide a first clock signal to the even-numbered gate drive circuit.

[0094] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this application can be executed in parallel, sequentially or in different orders, as long as the expected results of the technical solution of this application can be achieved, and this document is not limited here.

[0095] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this application should be included in the protection scope of this application.

Claims

1. A gate drive circuit, characterized in that: include: A node control module, configured to control the potential of the first node and the second node according to the clock signal and the input signal; an output control module, configured to provide the voltage of the first node or the first voltage signal to the third node and provide the voltage of the first node or the first voltage signal to the fourth node according to a control signal; The output module is configured to alternately output the first voltage signal and the second voltage signal according to the potentials of the second node, the third node and the fourth node.

2. The gate driving circuit according to claim 1, characterized in that: The output module includes a first output unit and a second output unit, the first output unit is configured to output the second voltage signal according to the potential of the third node, and the second output unit is configured to output the second voltage signal according to the potential of the fourth node; Preferably, the first output unit and the second output unit output the second voltage signal alternately; Preferably, the first output unit outputs the second voltage signal in at least part of the first time period, and the second output unit outputs the second voltage signal in at least part of the second time period; Preferably, the first output unit includes a first transistor, the control electrode of the first transistor is connected to the third node, the first electrode of the first transistor is connected to the second voltage signal, and the second electrode of the first transistor is connected to the gate signal output terminal; the second output unit includes a second transistor, the control electrode of the second transistor is connected to the fourth node, the first electrode of the second transistor is connected to the second voltage signal, and the second electrode of the second transistor is connected to the gate signal output terminal; Preferably, the first transistor and the second transistor are turned on alternately.

3. The gate driving circuit according to claim 2, characterized in that: The output module further includes a third output unit, wherein the third output unit is configured to output the first voltage signal according to the potential of the second node; Preferably, the third output unit comprises a third transistor, a control electrode of the third transistor is connected to the second node, a first electrode of the third transistor is connected to the first voltage signal, and a second electrode of the third transistor is connected to the gate signal output terminal; Preferably, the first time period includes a first sub-time period and a second sub-time period, in which the third output unit outputs the first voltage signal to the gate signal output terminal in the first sub-time period, and in which the first output unit outputs the second voltage signal to the gate signal output terminal in the second sub-time period; The second period includes a third sub-period and a fourth sub-period, in which the third output unit outputs the first voltage signal to the gate signal output terminal, and in the fourth sub-period, the second output unit outputs the second voltage signal to the gate signal output terminal; Preferably, the first time period and the second time period are arranged alternately; Preferably, in the first sub-period, the first transistor and the second transistor are turned off, and the third transistor is turned on; in the second sub-period, the first transistor is turned on, the second transistor is turned off, and the third transistor is turned off; In the third sub-period, the first transistor and the second transistor are turned off, and the third transistor is turned on; in the fourth sub-period, the first transistor is turned off, the second transistor is turned on, and the third transistor is turned off; Preferably, one of the first voltage signal and the second voltage signal is a low potential, and the other is a high potential; Preferably, the first voltage signal is a high potential, and the second voltage signal is a low potential; Preferably, the gate driving circuit further includes a third capacitor, and two ends of the third capacitor are respectively connected to the control electrode of the third transistor and the first electrode of the third transistor.

4. The gate driving circuit according to claim 2, characterized in that: The output control module includes a first control unit and a second control unit, the control signal includes a first control signal and a second control signal, and the first control unit and the second control unit are configured to control the first output unit and the second output unit to alternately output the second voltage signal according to the first control signal and the second control signal; Preferably, the first control unit is configured to provide the voltage of the first node to the third node according to the first control signal, and provide the first voltage signal to the third node according to the second control signal; the second control unit is configured to provide the voltage of the first node to the fourth node according to the second control signal, and provide the first voltage signal to the fourth node according to the first control signal; Preferably, in the first time period and the second time period, one of the first control signal and the second control signal is at a high potential, and the other is at a low potential; One of the potentials of the first control signal in the first time period and the potential in the second time period is a high potential, and the other is a low potential; One of the potentials of the second control signal in the first period and in the second period is a high potential, and the other is a low potential.

5. The gate driving circuit according to claim 4, characterized in that: The first control unit includes a fourth transistor and a fifth transistor, the control electrode of the fourth transistor is connected to the first control signal, the first electrode of the fourth transistor is connected to the first node, the control electrode of the fifth transistor is connected to the second control signal, the first electrode of the fifth transistor is connected to the first voltage signal, and the second electrode of the fourth transistor and the second electrode of the fifth transistor are connected to the third node; The second control unit includes a sixth transistor and a seventh transistor, the control electrode of the sixth transistor is connected to the second control signal, the first electrode of the sixth transistor is connected to the first node, the control electrode of the seventh transistor is connected to the first control signal, the first electrode of the seventh transistor is connected to the first voltage signal, and the second electrode of the sixth transistor and the second electrode of the seventh transistor are connected to the fourth node; Preferably, in the first time period, the fourth transistor is turned on, the fifth transistor is turned off, the sixth transistor is turned off, and the seventh transistor is turned on; in the second time period, the fourth transistor is turned off, the fifth transistor is turned on, the sixth transistor is turned on, and the seventh transistor is turned off.

6. The gate driving circuit according to claim 1, characterized in that: The node control module comprises an input unit, the clock signal comprises a first clock signal, and the input unit is configured to provide the input signal to the first node according to the first clock signal; Preferably, the input unit comprises an eighth transistor, a first electrode of the eighth transistor is connected to the input signal, a control electrode of the eighth transistor is connected to the first clock signal, and a second electrode of the eighth transistor is connected to the first node; Preferably, the input unit further includes a ninth transistor, the second electrode of the eighth transistor is connected to the first electrode of the ninth transistor, the control electrode of the ninth transistor is connected to the second voltage signal, and the second electrode of the ninth transistor is connected to the first node.

7. The gate driving circuit according to claim 6, characterized in that: The node control module also includes a third control unit, The third control unit and the input unit are connected to the first node, and the third control unit is configured to provide the first voltage signal to the second node according to the potential of the first node; Alternatively, the third control unit and the input unit are connected to a fifth node, the input unit is further configured to provide the input signal to the fifth node according to the first clock signal, and the third control unit is configured to provide the first voltage signal to the second node according to the potential of the fifth node; Preferably, the third control unit includes a tenth transistor, a control electrode of the tenth transistor is connected to the fifth node or the first node, a first electrode of the tenth transistor is connected to the first voltage signal, and a second electrode of the tenth transistor is connected to the second node; Preferably, the second electrode of the eighth transistor and the first electrode of the ninth transistor are connected to the fifth node.

8. The gate driving circuit according to claim 6, characterized in that: The node control module further includes a fourth control unit, the clock signal further includes a second clock signal, and the fourth control unit is configured to control the potential of the first node according to the input signal, the first clock signal and the second clock signal; Preferably, the fourth control unit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fifteenth transistor, the first electrode of the eleventh transistor is connected to the first voltage signal, the second electrode of the eleventh transistor is connected to the second electrode of the twelfth transistor, the first electrode of the twelfth transistor is connected to the second clock signal, the control electrode of the twelfth transistor is connected to the first electrode of the thirteenth transistor, the second electrode of the thirteenth transistor is connected to the first node, the first electrode of the thirteenth transistor and the control electrode of the thirteenth transistor are connected to the second electrode of the fourteenth transistor, the control electrode of the fourteenth transistor is connected to the second voltage signal, the first electrode of the fourteenth transistor is connected to the second electrode of the fifteenth transistor, the control electrode of the fifteenth transistor is connected to the first clock signal, and the first electrode of the fifteenth transistor is connected to the input signal; Preferably, the fourth control unit further includes a first capacitor, and two ends of the first capacitor are respectively connected to the control electrode of the twelfth transistor and the second electrode of the twelfth transistor; Preferably, the node control module further includes a fifth control unit, and the fifth control unit is configured to control the potential of the second node according to the first clock signal and the second clock signal; Preferably, the fifth control unit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor and a twenty-third transistor, the first electrode of the sixteenth transistor is connected to the second voltage signal, the second electrode of the sixteenth transistor and the first electrode of the seventeenth transistor are connected to the control electrode of the eleventh transistor, the control electrode of the sixteenth transistor is connected to the first clock signal, the control electrode of the seventeenth transistor is connected to the second voltage signal, the second electrode of the seventeenth transistor is connected to the control electrode of the eighteenth transistor, the first electrode of the eighteenth transistor is connected to the second clock signal, the second electrode of the eighteenth transistor is connected to the first electrode of the nineteenth transistor, the second electrode of the nineteenth transistor is connected to the second node, the control electrode of the nineteenth transistor is connected to the second clock signal, the first electrode of the twentieth transistor is connected to the first clock signal, the control electrode of the twentieth transistor is connected to the second electrode of the eighth transistor, and the second electrode of the twentieth transistor is connected to the second electrode of the sixteenth transistor; Preferably, the fifth control unit further includes a second capacitor, and two ends of the second capacitor are respectively connected to the control electrode of the eighteenth transistor and the second electrode of the eighteenth transistor; Preferably, the first clock signal and the second clock signal have the same frequency and different phases.

9. A driving method for a gate driving circuit, characterized in that: Applicable to the gate drive circuit described in right 4 or 5, the driving method comprises: In a first time period, inputting the first control signal in a first level state and the second control signal in a second level state to the output control module, so that the first control unit provides the voltage of the first node to the third node according to the first control signal, and the second control unit provides the first voltage signal to the fourth node according to the first control signal; In the second time period, the first control signal in the second level state and the second control signal in the first level state are input into the output control module, so that the first control unit provides the first voltage signal to the third node according to the second control signal, and the second control unit provides the voltage of the first node to the fourth node according to the second control signal.

10. A display device, characterized in that: include: The gate drive circuit according to any one of claims 1 to 8.

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