Memory storage data error correction method and device, electronic equipment and medium

Abstract

The invention discloses a memory storage data error correction method and device, electronic equipment and a medium, and relates to the technical field of electronics. Wherein each storage unit of the memory is used for storing multi-bit data, and the method comprises the following steps: performing data coding on a multi-bit data set to obtain target verification data of the multi-bit data set, the multi-bit data set comprising a plurality of pieces of multi-bit data; actual verification data of the multi-bit data set is determined according to the coding coefficient of each piece of multi-bit data in the coding process, and the coding coefficients of all the pieces of multi-bit data are different; and under the condition that the actual verification data is different from the target verification data, performing error correction operation on the corresponding multi-bit data based on a difference value between the actual verification data and the target verification data. Thus, error correction of one LSB of multi-bit data instead of data bit error correction is achieved, the requirement for the error correction capability of error correction codes is reduced, and the method has remarkable advantages in reducing verification data storage overhead and coding and decoding overhead.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a method for correcting errors in memory stored data, a device for correcting errors in memory stored data, a computer-readable storage medium, and an electronic device. Background Art

[0002] Storage technology based on RRAM (Resistive Random Access Memory) devices has made great progress in recent years, and the storage capacity of RRAM devices has begun to expand from single-bit storage to multi-bit data storage. However, the data stability of RRAM multi-bit storage is still affected by the non-ideal characteristics of RRAM devices. Coding schemes that correct errors for each bit of data have been widely used in the fields of storage and communication, such as Hamming code, BCH code, LDPC code, etc., and there are also coding schemes such as AN code applied to error correction of multi-bit data. The bit-by-bit error correction coding scheme is used to identify the location of a group of data bits and correct them. It is a coding method widely used in the industry. However, the coding method for correcting errors in data bits is not suitable for error correction of multi-bit data stored in RRAM. Taking the RRAM device storing a 4-bit data 0111 as an example, the offset of the physical state of the RRAM device may cause the 4-bit data it stores to become 1000, and the data bits are flipped by 4 bits. However, the actual data error is only 1 LSB (Least Significant Bit). Even so, the traditional bit-by-bit encoding scheme is still required to have the error correction capability of 4 data bits, resulting in large verification data storage overhead and encoding and decoding overhead. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first purpose of the present application is to propose a method for correcting data stored in a memory, wherein each storage unit of the memory is used to store multi-bit data, and the method includes: encoding a multi-bit data set to obtain target verification data of the multi-bit data set, wherein the multi-bit data set includes multiple multi-bit data; determining the actual verification data of the multi-bit data set according to the coding coefficient of each multi-bit data in the encoding process, wherein the coding coefficient of each multi-bit data is different; when the actual verification data is different from the target verification data, performing error correction operation on the corresponding multi-bit data based on the difference between the actual verification data and the target verification data. In this way, the present application realizes the error correction of 1 LSB error amount of multi-bit data instead of data bit error correction, reduces the demand for error correction capability of error correction code, and has significant advantages in reducing the verification data storage overhead and encoding and decoding overhead.

[0004] The second objective of the present application is to provide a memory storage data error correction device.

[0005] The third object of the present application is to provide a computer-readable storage medium.

[0006] The fourth objective of the present application is to provide an electronic device.

[0007] To achieve the above-mentioned purpose, the first aspect embodiment of the present application proposes a method for correcting data stored in a memory, wherein each storage unit of the memory is used to store multi-bit data, and the method includes: encoding the multi-bit data set to obtain target verification data of the multi-bit data set, wherein the multi-bit data set includes multiple multi-bit data; determining the actual verification data of the multi-bit data set according to the coding coefficient of each multi-bit data in the encoding process, wherein the coding coefficient of each multi-bit data is different; when the actual verification data is different from the target verification data, performing an error correction operation on the corresponding multi-bit data based on the difference between the actual verification data and the target verification data.

[0008] According to an embodiment of the present application, an error correction operation is performed on corresponding multi-bit data based on a difference between actual check data and target check data, including: obtaining a difference between actual check data and target check data; using multi-bit data corresponding to a coding coefficient having the same absolute value as the difference as multi-bit data to be corrected; and performing an error correction operation on the multi-bit data to be corrected based on the difference.

[0009] According to one embodiment of the present application, an error correction operation is performed on the multi-bit data to be corrected based on the difference, including: when the difference is greater than 0, subtracting the multi-bit data to be corrected from a first preset value to perform an error correction operation on the multi-bit data to be corrected; when the difference is less than 0, summing the multi-bit data to be corrected with a second preset value to perform an error correction operation on the multi-bit data to be corrected.

[0010] According to one embodiment of the present application, actual verification data of a multi-bit data set is determined according to a coding coefficient of each multi-bit data in the encoding process, including: obtaining the product of each multi-bit data in the multi-bit data set and its coding coefficient; and determining the actual verification data based on the sum of all products.

[0011] According to one embodiment of the present application, the above method also includes: when storing multiple multi-bit data sets in the memory, verifying the target verification data of each multi-bit data set based on the actual verification data of the multiple multi-bit data sets and the target verification data of the multiple multi-bit data sets.

[0012] According to an embodiment of the present application, target check data of multiple multi-bit data sets are stored in a single-bit memory.

[0013] According to an embodiment of the present application, the above method also includes: when the actual verification data is the same as the target verification data, no error correction operation is required.

[0014] To achieve the above-mentioned purpose, the second aspect embodiment of the present application proposes a memory storage data error correction device, wherein each storage unit of the memory is used to store multi-bit data, and the device includes: an acquisition module, used to encode the multi-bit data set to obtain target verification data of the multi-bit data set, wherein the multi-bit data set includes multiple multi-bit data; a determination module, used to determine the actual verification data of the multi-bit data set according to the coding coefficient of each multi-bit data in the encoding process, wherein the coding coefficient of each multi-bit data is different; an operation module, used to perform an error correction operation on the corresponding multi-bit data based on the difference between the actual verification data and the target verification data when the actual verification data is different from the target verification data.

[0015] To achieve the above-mentioned purpose, the third aspect embodiment of the present application proposes a computer-readable storage medium, on which a memory storage data error correction program is stored. When the memory storage data error correction program is executed by a processor, the aforementioned memory storage data error correction method is implemented.

[0016] To achieve the above-mentioned objectives, the fourth aspect embodiment of the present application proposes an electronic device, including a memory, a processor, and a memory storage data error correction program stored in the memory and executable on the processor. When the processor executes the memory storage data error correction program, the aforementioned memory storage data error correction method is implemented.

[0017] According to the memory storage data error correction method, device, electronic device and medium of the embodiment of the present application, each storage unit of the memory is used to store multi-bit data, and the method includes: data encoding of the multi-bit data set to obtain the target verification data of the multi-bit data set, wherein the multi-bit data set includes multiple multi-bit data; determining the actual verification data of the multi-bit data set according to the coding coefficient of each multi-bit data in the encoding process, wherein the coding coefficient of each multi-bit data is different; when the actual verification data is different from the target verification data, error correction operation is performed on the corresponding multi-bit data based on the difference between the actual verification data and the target verification data. In this way, the present application realizes the error correction of 1 LSB error amount of multi-bit data instead of data bit error correction, reduces the demand for error correction capability of error correction code, and has significant advantages in reducing the verification data storage overhead and encoding and decoding overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A flowchart of a method for correcting errors in memory storage data according to some embodiments of the present application;

[0019] Figure 2 A schematic diagram of target verification data re-verification according to some embodiments of the present application;

[0020] Figure 3 A circuit diagram for correcting memory data stored in a memory according to some embodiments of the present application;

[0021] Figure 4 It is a block diagram of a memory storage data error correction device according to some embodiments of the present application;

[0022] Figure 5 It is a block diagram of an electronic device according to some embodiments of the present application. DETAILED DESCRIPTION

[0023] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0024] The following describes in detail the memory storage data error correction method, device, electronic device and medium according to the embodiments of the present application with reference to the accompanying drawings.

[0025] In some embodiments, each storage unit of the memory is used to store multi-bit data.

[0026] Specifically, the memory includes multiple RRAM devices (storage units), each of which can be used to store multi-bit data. In the embodiment of the present application, each RRAM device stores a 3-bit data, and the memory includes 5 RRAM devices for storing multi-bit data. This is not intended to limit the present application.

[0027] Figure 1 Flowchart of a method for correcting memory data errors according to some embodiments of the present application. Figure 1 The memory storage data error correction method of the embodiment of the present application may include the following steps:

[0028] S110, performing data encoding on a multi-bit data set to obtain target verification data of the multi-bit data set, wherein the multi-bit data set includes a plurality of multi-bit data.

[0029] Specifically, when the memory includes 5 RRAM devices for storing multi-bit data, the multi-bit data set includes 5 multi-bit data, such as multi-bit data 1, multi-bit data 2, ..., multi-bit data 5. The multi-bit data set is encoded based on the coding coefficient corresponding to each multi-bit data to obtain target verification data of the multi-bit data set. It should be noted that the coding coefficient corresponding to each multi-bit data is different.

[0030] Exemplarily, assuming that multi-bit data 1 corresponds to coding coefficient 1, multi-bit data 2 corresponds to coding coefficient 2, ..., multi-bit data 5 corresponds to coding coefficient 5, the calculation formula of the target check data of the multi-bit data set is as follows:

[0031] Target verification data = multi-bit data 1*coding coefficient 1+…+ multi-bit data 5*coding coefficient 5

[0032] After acquiring the target verification data of the multi-bit data set, the multi-bit data set and the target verification data of the multi-bit data set are stored in a row of the RRAM array, so as to facilitate simultaneous reading of the multi-bit data set and the target verification data of the set.

[0033] S120, determining actual check data of the multi-bit data set according to a coding coefficient of each multi-bit data in a coding process, wherein the coding coefficient of each multi-bit data is different.

[0034] Specifically, during the process of reading out the multi-bit data set and the target check data of the multi-bit data set, one of the multi-bit data in the multi-bit data set may be read incorrectly. Therefore, the actual check data of the multi-bit data set is also calculated according to the coding coefficient of each multi-bit data in the coding process.

[0035] S130, when the actual verification data is different from the target verification data, performing an error correction operation on the corresponding multi-bit data based on the difference between the actual verification data and the target verification data.

[0036] Specifically, when the actual verification data is different from the target verification data, it means that the multi-bit data in the multi-bit data set is read incorrectly during the reading process of the multi-bit data set. Therefore, it is necessary to obtain the difference between the actual verification data and the target verification data, and according to the difference, it can be determined which multi-bit data in the multi-bit data set is read incorrectly, and further according to the difference, an error correction operation can be performed on the incorrectly read multi-bit data.

[0037] Exemplarily, after obtaining the difference between the actual verification data and the target verification data, if the difference is a coding coefficient of 1, it means that the multi-bit data 1 is read incorrectly. Further, if the difference between the actual verification data and the target verification data is a positive value, it means that the read multi-bit data is greater than the originally stored multi-bit data, then the read multi-bit data 1 is subtracted by 1 to implement an error correction operation on the multi-bit data 1; if the difference between the actual verification data and the target verification data is a negative value, it means that the read multi-bit data is less than the originally stored multi-bit data, then the read multi-bit data 1 is added by 1 to implement an error correction operation on the multi-bit data 1.

[0038] In this way, the present application realizes 1 LSB error correction of multi-bit data instead of data bit error correction, which reduces the demand for error correction capability of error correction codes and has significant advantages in reducing verification data storage overhead and encoding and decoding overhead.

[0039] In some embodiments, an error correction operation is performed on corresponding multi-bit data based on a difference between actual check data and target check data, including: obtaining a difference between actual check data and target check data; using multi-bit data corresponding to a coding coefficient having the same absolute value as the difference as multi-bit data to be corrected; and performing an error correction operation on the multi-bit data to be corrected based on the difference.

[0040] For example, assuming that multi-bit data 1 is 1, multi-bit data 2 is 2,…, multi-bit data 5 is 5, the coding coefficient corresponding to multi-bit data 1 is 1, the coding coefficient corresponding to multi-bit data 2 is 2,…, the coding coefficient corresponding to multi-bit data 5 is 5, then the target check data of the multi-bit data set is 1*1+2*2+3*3+4*4+5*5=55.

[0041] When reading a multi-bit data set, if the multi-bit data 1 is read from 1 to 2, the actual check data of the read multi-bit data set is 2*1+2*2+3*3+4*4+5*5=56. The absolute value of the difference between the actual check data and the target check data is 1, which is the same as the coding coefficient 1, indicating that the multi-bit data 1 is read incorrectly and the multi-bit data 1 is the multi-bit data to be corrected.

[0042] When reading a multi-bit data set, if the multi-bit data 5 is read from 5 to 4, the actual check data of the read multi-bit data set is 1*1+2*2+3*3+4*4+4*5=50. The absolute value of the difference between the actual check data and the target check data is 5, which is the same as the coding coefficient 5, indicating that the multi-bit data 5 is read incorrectly and the multi-bit data 5 is the multi-bit data to be corrected.

[0043] In some embodiments, performing an error correction operation on the multi-bit data to be corrected based on the difference includes: when the difference is greater than 0, performing an error correction operation on the multi-bit data to be corrected and a first preset value; when the difference is less than 0, performing an error correction operation on the multi-bit data to be corrected and a second preset value. The first preset value is 1, and the second preset value is also 1.

[0044] Exemplarily, when it is determined that the multi-bit data 1 is the multi-bit data to be corrected, if the difference between the actual check data and the target check data is greater than 0, it means that the multi-bit data 1 is read too large, and the read multi-bit data 1 is subtracted by 1 to correct the error of the multi-bit data 1; if the difference between the actual check data and the target check data is less than 0, it means that the multi-bit data 1 is read too small, and the read multi-bit data 1 is added by 1 to correct the error of the multi-bit data 1.

[0045] When it is determined that the multi-bit data 5 is the multi-bit data to be corrected, if the difference between the actual verification data and the target verification data is greater than 0, it means that the multi-bit data 5 is read too large, and the read multi-bit data 5 is subtracted by 1 to correct the error of the multi-bit data 5; if the difference between the actual verification data and the target verification data is less than 0, it means that the multi-bit data 5 is read too small, and the read multi-bit data 5 is added by 1 to correct the error of the multi-bit data 5.

[0046] In some embodiments, actual check data of a multi-bit data set is determined based on a coding coefficient of each multi-bit data in the coding process, including: obtaining the product of each multi-bit data in the multi-bit data set and its coding coefficient; and determining the actual check data based on the sum of all products.

[0047] Specifically, the multi-bit data 1 read also corresponds to the coding coefficient 1, the multi-bit data 2 also corresponds to the coding coefficient 2, ..., the multi-bit data 5 corresponds to the coding coefficient 5, then the calculation formula for the actual check data of the read multi-bit data set is as follows:

[0048] Actual verification data = multi-bit data 1*coding coefficient 1+…+ multi-bit data 5*coding coefficient 5

[0049] In some embodiments, the above method also includes: when multiple multi-bit data sets are stored in the memory, verifying the target verification data of each multi-bit data set based on the actual verification data of the multiple multi-bit data sets and the target verification data of the multiple multi-bit data sets.

[0050] Specifically, refer to Figure 2In the case where multiple multi-bit data sets are stored in a memory, the multiple multi-bit data sets and the multiple target verification data corresponding to the multiple multi-bit data sets are all stored in a row of the RRAM array. When reading the multi-bit data sets and the target verification data of the multi-bit data sets, it is also possible to read the target verification data of the multi-bit data sets incorrectly. Therefore, it is also necessary to encode the multiple target verification data corresponding to the multiple multi-bit data sets to obtain the target verification data of the multiple multi-bit data sets, and determine the actual verification data of the multiple multi-bit data sets according to the encoding coefficient of each target verification data in the encoding process, and further perform error correction operations on the corresponding target verification data according to the difference between the actual verification data and the target verification data.

[0051] For example, in the embodiment of the present application, storing three multi-bit data sets in the memory is used as an example for explanation, but this is not intended to be a limitation to the application.

[0052] Assume that the target check data 1 corresponding to multi-bit data set 1 is 1, the target check data 2 corresponding to multi-bit data set 2 is 2, and the target check data 3 corresponding to multi-bit data set 3 is 3. The target check data 1 corresponds to a coding coefficient of 1, the target check data 2 corresponds to a coding coefficient of 2, and the target check data 3 corresponds to a coding coefficient of 3. Then the target check data of multiple multi-bit data sets is 1*1+2*2+3*3=14.

[0053] When reading multiple target verification data, if the target verification data 2 is read from 2 to 1, the actual verification data of the multiple multi-bit data sets read is 1*1+1*2+3*3=12. The absolute value of the difference between the actual verification data and the target verification data is 2, and the absolute value of the difference is the same as the coding coefficient 2, indicating that the target verification data 2 is read incorrectly. The difference is less than 0, indicating that the target verification data 2 is read smaller, so it is necessary to add 1 to the target verification data 2 to correct the error of the target verification data 2.

[0054] When reading multiple target verification data, if the target verification data 3 is read from 3 to 4, the actual verification data of the multiple multi-bit data sets read is 1*1+2*2+4*3=17. The absolute value of the difference between the actual verification data and the target verification data is 3, which is the same as the coding coefficient 3, indicating that the target verification data 3 is read incorrectly. The difference is greater than 0, indicating that the target verification data 3 is read larger, so it is necessary to subtract 1 from the target verification data 3 to correct the error of the target verification data 3.

[0055] It should be noted that it is necessary to first perform error correction on multiple target check data corresponding to multiple multi-bit data sets, and then perform error correction on multiple multi-bit data in the multi-bit data sets, so as to improve the accuracy when reading data.

[0056] In some embodiments, target parity data of multiple multi-bit data sets are stored in a single-bit memory.

[0057] Specifically, in order to ensure the accuracy of target verification data of multiple multi-bit data sets to a certain extent, the target verification data of multiple multi-bit data sets can be stored in a single-bit RRAM, or in a storage unit with a stable storage state such as SRAM.

[0058] In some embodiments, the above method also includes: when the actual verification data is the same as the target verification data, no error correction operation is required.

[0059] As a specific example, see Figure 3 , multi-bit data 1, multi-bit data 2, ..., multi-bit data 5 are stored in R0R1...R4 respectively, and the target check data is stored in R5R6R7. The target check data with a large number of data bits can be stored by multiple RRAM devices; the readout process of the multi-bit data set and the target check data of the multi-bit data set can be implemented by a multi-bit SA circuit; the multiplication calculation and the addition calculation are implemented by a multiplier and an adder respectively; the difference calculation between the actual check data and the target check data is implemented by a subtractor; finally, the location and correction of the multi-bit data to be corrected are realized by a lookup table circuit.

[0060] In summary, the present application realizes 1 LSB error correction of multi-bit data rather than data bit error correction, which reduces the demand for error correction capability of error correction codes and has significant advantages in reducing verification data storage overhead and encoding and decoding overhead.

[0061] Corresponding to the above-mentioned embodiments, the present application also proposes a memory storage data error correction device.

[0062] In some embodiments, each storage unit of the memory is used to store multiple bits of data. Figure 4 The memory storage data error correction device 400 includes: an acquisition module 410, a determination module 420 and an operation module 430.

[0063] The acquisition module 410 is used to perform data encoding on a multi-bit data set to obtain target verification data of the multi-bit data set, wherein the multi-bit data set includes a plurality of multi-bit data. The determination module 420 is used to determine the actual verification data of the multi-bit data set according to the coding coefficient of each multi-bit data in the encoding process, wherein the coding coefficient of each multi-bit data is different. The operation module 430 is used to perform an error correction operation on the corresponding multi-bit data based on the difference between the actual verification data and the target verification data when the actual verification data is different from the target verification data.

[0064] According to one embodiment of the present application, the operation module 430 is specifically used to obtain the difference between the actual verification data and the target verification data; use the multi-bit data corresponding to the coding coefficient with the same absolute value as the difference as the multi-bit data to be corrected; and perform error correction operations on the multi-bit data to be corrected based on the difference.

[0065] According to one embodiment of the present application, the operation module 430 is specifically used to, when the difference is greater than 0, perform an error correction operation on the multi-bit data to be corrected by subtracting the multi-bit data to be corrected from the first preset value; and when the difference is less than 0, perform an error correction operation on the multi-bit data to be corrected by summing the multi-bit data to be corrected with the second preset value.

[0066] According to an embodiment of the present application, the determination module 420 is specifically used to obtain the product of each multi-bit data in the multi-bit data set and its coding coefficient; and determine the actual verification data based on the sum of all the products.

[0067] According to an embodiment of the present application, when multiple multi-bit data sets are stored in a memory, target verification data of each multi-bit data set is verified based on actual verification data of the multiple multi-bit data sets and target verification data of the multiple multi-bit data sets.

[0068] According to an embodiment of the present application, target check data of multiple multi-bit data sets are stored in a single-bit memory.

[0069] According to an embodiment of the present application, when the actual verification data is the same as the target verification data, no error correction operation is required.

[0070] It should be pointed out that the above-mentioned explanation of the embodiments and beneficial effects of the memory storage data error correction method is also applicable to the memory storage data error correction device of the embodiment of the present application. To avoid redundancy, it will not be elaborated here.

[0071] Corresponding to the above embodiments, the present application also proposes a computer-readable storage medium.

[0072] The computer-readable storage medium of the present application stores a memory storage data error correction program thereon, and the memory storage data error correction program implements the aforementioned memory storage data error correction method when executed by a processor.

[0073] It should be pointed out that the above-mentioned explanation of the embodiments and beneficial effects of the method for correcting data errors in memory is also applicable to the computer-readable storage medium of the embodiments of the present application. To avoid redundancy, they will not be elaborated here.

[0074] Corresponding to the above embodiment, the present application also proposes an electronic device.

[0075] See also Figure 5 As shown, the electronic device 500 of the present application includes a memory 510, a processor 520, and a memory storage data error correction program stored on the memory 510 and executable on the processor 520. When the processor executes the memory storage data error correction program, the aforementioned memory storage data error correction method is implemented.

[0076] It should be pointed out that the above-mentioned explanation of the embodiments and beneficial effects of the method for correcting errors in memory data is also applicable to the electronic device of the embodiment of the present application, and will not be elaborated here in detail to avoid redundancy.

[0077] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0078] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0079] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0080] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0081] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0082] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for correcting errors in memory stored data, characterized in that: Each storage unit of the memory is used to store multi-bit data, and the method comprises: Performing data encoding on a multi-bit data set to obtain target verification data of the multi-bit data set, wherein the multi-bit data set includes a plurality of multi-bit data; Determine actual check data of the multi-bit data set according to a coding coefficient of each of the multi-bit data in a coding process, wherein the coding coefficients of each of the multi-bit data are different; In a case where the actual verification data is different from the target verification data, an error correction operation is performed on the corresponding multi-bit data based on the difference between the actual verification data and the target verification data.

2. The memory storage data error correction method according to claim 1, characterized in that: Performing an error correction operation on the corresponding multi-bit data based on a difference between the actual verification data and the target verification data, comprising: Obtaining a difference between the actual verification data and the target verification data; taking the multi-bit data corresponding to the coding coefficient having the same absolute value as the difference as the multi-bit data to be corrected; An error correction operation is performed on the multi-bit data to be corrected based on the difference.

3. The memory storage data error correction method according to claim 2, characterized in that: Performing an error correction operation on the multi-bit data to be corrected based on the difference, comprising: In the case where the difference is greater than 0, subtracting the multi-bit data to be corrected from a first preset value to perform an error correction operation on the multi-bit data to be corrected; When the difference is less than 0, the multi-bit data to be corrected is summed with a second preset value to perform an error correction operation on the multi-bit data to be corrected.

4. The memory storage data error correction method according to claim 1, characterized in that: Determining actual check data of the multi-bit data set according to a coding coefficient of each of the multi-bit data in a coding process includes: Obtaining the product of each multi-bit data in the multi-bit data set and its coding coefficient; The actual verification data is determined based on the sum of all products.

5. The memory storage data error correction method according to claim 1, characterized in that: The method further comprises: In the case where a plurality of multi-bit data sets are stored in the memory, target verification data of each of the multi-bit data sets is verified based on actual verification data of the plurality of multi-bit data sets and target verification data of the plurality of multi-bit data sets.

6. The memory storage data error correction method according to claim 5, characterized in that: The target check data of the plurality of multi-bit data sets are stored in a single-bit memory.

7. The memory storage data error correction method according to claim 1, characterized in that: The method further comprises: In the case where the actual verification data is identical to the target verification data, no error correction operation is required.

8. A memory storage data error correction device, characterized in that: Each storage unit of the memory is used to store multi-bit data, and the device comprises: An acquisition module, configured to perform data encoding on a multi-bit data set to obtain target verification data of the multi-bit data set, wherein the multi-bit data set includes a plurality of multi-bit data; a determination module, configured to determine actual check data of the multi-bit data set according to a coding coefficient of each of the multi-bit data in a coding process, wherein the coding coefficients of each of the multi-bit data are different; An operation module is used to perform an error correction operation on the corresponding multi-bit data based on a difference between the actual verification data and the target verification data when the actual verification data is different from the target verification data.

9. A computer-readable storage medium, characterized in that: A memory storage data error correction program is stored thereon, and when the memory storage data error correction program is executed by a processor, a memory storage data error correction method according to any one of claims 1-7 is implemented.

10. An electronic device, characterized in that: The invention comprises a memory, a processor and a memory storage data error correction program stored in the memory and executable on the processor. When the processor executes the memory storage data error correction program, the memory storage data error correction method according to any one of claims 1 to 7 is implemented.

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