A dynamic current sharing layout design method and system for multi-chip parallel power modules

Abstract

The present invention belongs to the field of power semiconductor devices and discloses a dynamic current sharing layout design method and system for multi-chip parallel power modules. The method includes two aspects: main power circuit layout and wiring, and drive circuit layout and wiring. The main power circuit is designed with vertical commutation, and the parallel chip source and drain are designed as an integrated design, which can make the chip quasi-common source inductance consistent and integrated, which is conducive to the dynamic current sharing of multiple gallium nitride chips in parallel. The drive circuit wiring is designed with vertical commutation and perpendicular to the main power circuit, so the mutual inductance of the power circuit to the drive circuit is basically zero, which is conducive to the dynamic current sharing of gallium nitride chips in parallel. When the above design is met and the gate terminals and Kelvin source terminals of the four chips are symmetrical about the symmetry axis of the main power circuit, the mutual inductance of the main power circuit to the wiring driving each chip gate is equal, and the mutual inductance of the main power circuit to the wiring driving each chip Kelvin source is also equal, which can achieve excellent dynamic current sharing effect of multiple gallium nitride chips in parallel.

Description

Technical Field

[0001] The present invention belongs to, but is not limited to, the technical field of power semiconductor devices, and in particular relates to a dynamic current sharing layout design method and system for a multi-chip parallel power module. Background Art

[0002] In the field of power electronics, power semiconductor devices are core components for efficient power conversion and control. Third-generation wide-bandgap semiconductor materials, silicon carbide (SiC) and gallium nitride (GaN), have revolutionized converter performance with their exceptional electrical properties. GaN, in particular, exhibits superior electron mobility due to its unique two-dimensional electron gas structure. This translates to faster switching speeds for GaN devices, improving converter response and efficiency. Furthermore, GaN devices offer low switching losses and greater efficiency in high-frequency applications, contributing to smaller and lighter passive components, which is particularly important in space-constrained applications. GaN devices are already penetrating multiple industries, including data centers and electric vehicles, operating in systems with power levels of 10kW to 100kW and higher. However, the immaturity of GaN chip manufacturing processes limits the effective area and current capacity of individual chips. Currently, the most mature technology is 650V planar GaN, with maximum currents per chip reaching 150A for GaNsystems and 200A for Visic. Therefore, multiple chips are usually packaged in parallel to obtain a high-current power module to meet the application needs of high-power occasions.

[0003] Improper layout design of multi-chip GaN power modules can lead to uneven dynamic current distribution. This uneven dynamic current distribution causes inconsistent chip switching losses, which in turn leads to inconsistent junction temperatures among paralleled chips. This in turn leads to uneven performance degradation rates and thermal-mechanical stresses among the paralleled chips, ultimately significantly reducing module reliability and service life. Therefore, dynamic current sharing design for multi-chip parallel GaN power modules is crucial.

[0004] To address the dynamic current sharing issue of multi-chip parallel GaN power modules, Cheng Jun and others from GaN Systems established an equivalent circuit for parallel GaN chips and performed a segmented analysis of the turn-on and turn-off processes. They pointed out that the inconsistency of the self-inductance of the drive circuit has little effect on current sharing, while the mutual inductance of the power circuit to the drive circuit and the quasi-common source inductance seriously affect the gate voltage in the di / dt phase, thereby affecting the dynamic current sharing of multi-chip parallel GaN. They also provided design recommendations for minimizing and equalizing the quasi-common source inductance and the mutual inductance of the power circuit to the drive circuit.

[0005] In terms of power circuit design, the current commercial GaN parallel modules use a planar commutation structure, and the source layout of the parallel chips is seriously inconsistent, resulting in poor dynamic current sharing of the modules. In terms of drive circuit design, when a single driver chip is used to drive parallel GaN chips, a symmetrical and consistent drive circuit design method is adopted, such as Figure 1 As shown. (a) (b) are discrete device design schemes, in which (a) the driver chip is placed on one side, and the drive signal wiring first reaches the middle of the four chips, and then extends to both sides, driving two GaN chips each, making the two sides symmetrical. (b) The driver chip is in the middle of the four parallel GaN chips, and extends to both sides, driving two GaN chips each, and the two sides are completely symmetrical. Li B et al. proposed a hybrid packaging form to realize a double-sided heat dissipation parallel GaN module, but still placed the driver chip in the middle of the four parallel GaN chips, extending to both sides, driving two GaN chips each, and the two sides are completely symmetrical. In addition, when performing a double-sided heat dissipation design, it is necessary to add a gasket to highly match the driver chip and the GaN chip.

[0006] In view of the above analysis, the technical problems that need to be solved urgently in the existing technology are:

[0007] There is no complete design guidance and theoretical analysis for the layout design of planar GaN multi-chip parallel dynamic current sharing modules. It is urgent to analyze the impact of layout and wiring on the dynamic current sharing of GaN multi-chip parallel modules and provide a complete set of dynamic current sharing layout design theories and guidance for multi-chip parallel GaN power modules. Summary of the Invention

[0008] In response to the problems existing in the prior art and the unique symmetrical dual-gate structure of planar GaN, the present invention provides a dynamic current sharing layout design method and system for a multi-chip parallel power module.

[0009] The present invention is implemented as follows: a dynamic current sharing layout design method for a multi-chip parallel power module, characterized in that the method includes two aspects: main power circuit layout and wiring and drive circuit layout and wiring.

[0010] Furthermore, the main power circuit layout and wiring design principles are as follows:

[0011] The four GaN chips connected in parallel at each switch position are named die1 to die4, and are placed side by side in a "hand-in-hand" manner;

[0012] The half-bridge module power chip layout and wiring and decoupling capacitors are constructed into a vertical commutation structure;

[0013] The source and drain of the parallel chips are interconnected nearby while meeting the insulation requirements, and the source and drain layout and wiring of multiple parallel chips are integrated into a whole.

[0014] Furthermore, the layout and wiring of the driving circuit are designed according to the following principles:

[0015] The right gate g1 of die1 is interconnected with the left gate g2 of die2 and led out. The right gate g3 of die3 is interconnected with the left gate g4 of die4 and led out. The two lead-out terminals are symmetrical about the symmetry axis of the main power circuit.

[0016] The source of die1 closest to the right gate g1 leads to the Kelvin source ks1; the source of die2 closest to the left gate g2 leads to the Kelvin source ks2; the source of die3 closest to the right gate g3 leads to the Kelvin source ks3; the source of die4 closest to the left gate g4 leads to the Kelvin source ks4, ks1-ks2 and ks3-ks4 are symmetrical about the symmetry axis of the main power circuit;

[0017] The driver chip to the chip gate is horizontally wired while meeting the insulation requirements, connecting the two gate leads in sequence. The chip Kelvin source lead is horizontally wired and connected to the ground potential of the driver circuit in sequence, and overlaps with the horizontal wiring from the driver chip to the chip gate, forming a vertical commutation structure.

[0018] Another object of the present invention is to provide a dynamic current sharing layout design system for multi-chip parallel GaN power modules, the system specifically comprising:

[0019] Main power circuit design module, used for layout and wiring of the main power circuit;

[0020] Drive circuit design module, used for layout and wiring of the drive circuit;

[0021] Heat dissipation module, used for designing the heat dissipation performance of the module.

[0022] In combination with the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solutions to be protected by the present invention are as follows:

[0023] First, the gallium nitride multi-chip parallel connection solution proposed in the present invention is simple in design, and the power circuit and the drive circuit are integrated into a vertical commutation design, which has a significant current sharing effect and is easy to design.

[0024] The present invention separates the drive circuit and the power circuit horizontally. The power circuit part only contains the GaN chip and a gasket with the same thickness as the chip, and does not contain other drive circuit components with inconsistent thickness. When the ceramic substrate is welded on the top of the chip, compared with the existing gallium nitride parallel module that designs the drive circuit above the power circuit, the present invention avoids the problem of height matching between the GaN chip and the driver chip, and also removes the gasket on the top of the gallium nitride chip, further reducing thermal resistance and improving the heat dissipation performance of the module.

[0025] The present invention analyzes the mechanism of dynamic current sharing of multiple GaN chips in parallel from the perspective of magnetic field, and provides a theoretical explanation for the significant current sharing effect of the multi-chip parallel solution proposed by the present invention.

[0026] Second, the technical effects of the present invention are also reflected in the following important aspects:

[0027] (1) The technical solution of the present invention solves a technical problem that people have long been eager to solve but have never been able to solve successfully:

[0028] The multi-chip parallel GaN module dynamic current sharing solution proposed in this invention has a great significance in power circuit layout.

[0029] In terms of the drive circuit, an integrated symmetrical vertical commutation layout design perpendicular to the power circuit is adopted, making the mutual inductance of the power circuit to the drive circuit close to zero, and achieving basically consistent mutual inductance of the power circuit to each part of the drive circuit of the four chips, solving the problem of uneven current distribution caused by inconsistent influence of the power circuit on each drive circuit during the rising and falling stages of the switching process.

[0030] Based on the above technical solutions of the present invention, the minimization and homogenization of the quasi-common source proposed by predecessors are realized.

[0031] The design requirements for multi-chip parallel GaN power modules with mutual inductance of the pole inductance and the power circuit to the drive circuit solve the technical problems that people have always wanted to solve but have never been able to successfully solve.

[0032] (2) The expected benefits and commercial value of the technical solution of the present invention after transformation are:

[0033] The technical solution of the present invention can be applied to a module with four planar gallium nitride chips connected in parallel.

[0034] The current maximum current is achieved by connecting four GaNsystems GaN chips in parallel, each rated at 650 V and 150 A. The module's rated current is 600 A, with a maximum power rating of 390 kW. This module can be used in applications with power levels of 10 kW to 250 kW and above, such as servers, onboard chargers, and electric vehicle main drive inverters, further enhancing the performance of high-power inverters. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1The present invention provides a design scheme for existing GaN multi-chip parallel drive circuits, including: (a) a symmetrical design with four GaN discrete devices connected in parallel and the drive circuit placed on one side of the power circuit; (b) a symmetrical design with four GaN discrete devices connected in parallel and the drive circuit placed in the middle of the power circuit; and (c) a symmetrical design with four GaN chips connected in parallel and the drive circuit placed in the middle of the power circuit for a double-sided heat dissipation GaN module.

[0036] Figure 2 Commercial planar gallium nitride with two symmetrical gate electrodes provided by an embodiment of the present invention, (a) VisIC, (b) Infineon, (c) Yunga Semiconductor.

[0037] Figure 3 This is the main power circuit layout and wiring design provided by an embodiment of the present invention: (a) front view, (b) side view;

[0038] Figure 4 The driving circuit layout and wiring design provided by the embodiment of the present invention;

[0039] Figure 5 The overall design of the gallium nitride multi-chip parallel double-sided heat dissipation module provided by the embodiment of the present invention;

[0040] Figure 6 This is a schematic diagram of the flexible printed circuit board (FPC) of a multi-chip parallel gallium nitride half-bridge module provided by an embodiment of the present invention, including (a) the upper tube drive circuit, (b) the lower tube drive circuit, and (c) the main power circuit.

[0041] Figure 7 Layout design diagram of a GaN multi-chip parallel FPC according to an embodiment of the present invention, (a) top view, (b) bottom view;

[0042] Figure 8 1. Main-DPC layout design diagram provided by an embodiment of the present invention, (a) top view, (b) bottom view;

[0043] Figure 9 Schematic diagram of the up-DPC layout provided by an embodiment of the present invention, (a) top view, (b) bottom view;

[0044] Figure 10 This is a 28mm*28mm*10mm heat sink design provided by an embodiment of the present invention, (a) top view, (b) bottom right view;

[0045] Figure 11 This is an equivalent circuit diagram of a quasi-common source inductor with an integrated vertical commutation structure provided by an embodiment of the present invention;

[0046] Figure 12(a) a structural diagram of a horizontal commutation module and (b) a quasi-common source inductor equivalent circuit diagram of a horizontal commutation module provided by an embodiment of the present invention;

[0047] Figure 13 This is a vertical commutation magnetic field distribution diagram of the power circuit of the gallium nitride multi-chip parallel module provided by an embodiment of the present invention;

[0048] Figure 14 This is a diagram of the magnetic field distribution and mutual inductance extraction generated by the power circuit on the drive circuit provided by an embodiment of the present invention;

[0049] Figure 15 is a system module diagram provided by an embodiment of the present invention;

[0050] Figure 16 LTspice simulation results provided by an embodiment of the present invention: (a) multi-pulse waveform, (b) turn-on waveform (left) and turn-off waveform (right) when the on-current is 15A, and (c) turn-on waveform (left) and turn-off waveform (right) when the on-current is 40A.

[0051] Figure 17 This is the steady-state result of solid-fluid heat transfer simulation in COMSOL of the multi-chip parallel gallium nitride power module of the present invention provided by an embodiment of the present invention;

[0052] Figure 18 These are physical modules provided by the embodiments of the present invention, (a) a pulse experiment module, (b) a continuous experiment module;

[0053] Figure 19 (a) multi-pulse experimental waveform, (b) turn-on transient waveform, and (c) turn-off transient waveform provided by the embodiment of the present invention;

[0054] Figure 20 (a) 300V / 50A continuous test waveform and (b) module steady-state operating temperature distribution provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0056] The embodiment of the present invention is based on the fact that the inconsistency of the self-inductance value of the driving circuit has little effect on the current sharing, and minimizes and equalizes the multi-chip quasi-common source inductance and the mutual inductance of the power circuit to the driving circuit. The multi-chip GaN parallel design suggestion is for planar gallium nitride with two symmetrical gates such as Figure 2, provides a dynamic current sharing layout design method for multi-chip parallel power modules, which mainly includes two aspects: main power circuit layout and wiring and drive circuit layout and wiring, and is analyzed using four chips in parallel.

[0057] First, the following design principles are proposed for the layout and wiring of the main power circuit:

[0058] The four GaN chips connected in parallel at each switch position are named die1 to die4, and are placed side by side in a "hand-in-hand" manner;

[0059] The half-bridge module power chip layout and wiring and decoupling capacitors are constructed into a vertical commutation structure;

[0060] The source and drain electrodes of parallel chips are interconnected as close together as possible while meeting insulation requirements. The source and drain electrodes of multiple parallel chips are laid out and wired as a single unit. This integrated layout can integrate the quasi-source inductors of multiple chips, eliminating the circulating current of the quasi-common source inductor and reducing its impact on the dynamic current sharing of multiple parallel chips.

[0061] Secondly, the following design principles are proposed for the layout and wiring of the drive circuit:

[0062] like Figure 4 The right gate g1 of die1 and the left gate g2 of die2 are interconnected and led out; the right gate g3 of die3 and the left gate g4 of die4 are interconnected and led out, and the two lead-out ends are symmetrical about the symmetry axis of the main power circuit.

[0063] like Figure 4 The source of die1 closest to the right gate g1 leads to the Kelvin source ks1; the source of die2 closest to the left gate g2 leads to the Kelvin source ks2; the source of die3 closest to the right gate g3 leads to the Kelvin source ks3; the source of die4 closest to the left gate g4 leads to the Kelvin source ks4. ks1-ks2 and ks3-ks4 are symmetrical about the symmetry axis of the main power circuit. The physical connection between the Kelvin source and the power source is only Figure 4 Introduction point.

[0064] The driver chip to the chip gate is wired horizontally while meeting insulation requirements, and the two gate leads are connected in sequence. The chip Kelvin source lead is horizontally wired and connected to the driver circuit ground potential in sequence, and overlaps with the horizontal wiring from the driver chip to the chip gate, forming a vertical commutation structure. The advantages are: ① the vertical commutation formed by the driver circuit results in low self-inductance; ② the mutual inductance of the power circuit to the four chip driver circuits is basically equal and close to 0. ③ the mutual inductance of each part of the power circuit to the four chip driver circuits is equal, and the current sharing effect is significant. (Theoretical analysis from the magnetic field perspective will be given later)

[0065] Based on the layout and wiring design principles proposed in the present invention, taking the gallium nitride chip model GS-065-060-2-D2 with a rated voltage of 650V and a rated current of 60A as an example, a hybrid double-sided packaging solution using a flexible printed circuit (FPC) and a direct-plated copper (DPC) substrate is used. The dynamic current-sharing layout design method and processing scheme for the parallel connection of multi-chip GaN power modules proposed in the present invention are described in detail.

[0066] Dynamic current sharing layout design structure framework for multi-chip parallel GaN power modules:

[0067] The main power circuit is constructed with two layers of FPC and DPC. Figure 7 As shown in the left figure, the GaN chip pads are designed to be arranged in a "hand-in-hand" pattern on the upper copper layer of the FPC. The source and drain pads of the GaN chip are connected as a whole according to the electrical relationship and pad shape using copper plating. The upper copper layer and the lower copper layer of the FPC are connected through vias at the GaN chip pad position. The lower copper layer performs RDL on the GaN source and drain. Figure 7 The right picture shows the corresponding position of the copper on the main-DPC being welded. Figure 8 In the left figure, in addition, DPC designs the busbar and output terminal connections based on electrical connection and insulation considerations: DC+, DC-, and AC. The DC+ busbar (and DC- as well) is connected through DPC vias to form a vertical commutation structure, such as Figure 8 Right picture.

[0068] The driver circuit is designed with FPC, and the components used in the driver circuit are packaged with SMD. The components used in the driver circuit are packaged with SMD, and the pads are designed on the top. The driver chip and peripheral circuits are located on the left side of the GaN chip. According to the driver loop layout design guidelines in Section 2, the layout from the driver to the four GaN gates and the layout from the four GaN Kelvin sources to the driver ground are placed on the top and bottom copper layers of the FPC respectively. In addition, Figure 8 On the left, the top copper layer of the main DPC corresponding to the FPC driving position is connected to the ground potential to form a shielding layer to reduce the electromagnetic interference of the main power circuit magnetic field on the driving circuit.

[0069] In addition, it is necessary to design a gasket, a heat dissipation substrate (up-DPC), a heat sink, and a positioning pad. The gasket is the same thickness as the chip and is used to connect the chip source and the chip heat dissipation top surface, achieving equal potential between the chip substrate surface and the source, while also playing a role in balancing and supporting the up-DPC. The up-DPC acts as an insulator, and the heat sink can be soldered to its top surface. The FPC has positioning pads to facilitate alignment when soldering to the main DPC. The assembly diagram of the module is shown below. Figure 5As shown, the GaN chip, spacer, and driver circuit are soldered to the top of the FPC, and the bottom of the FPC is soldered to the top of the main DPC. The GaN chip and the top of the spacer are soldered to the bottom of the upper PCB, and the heat sink is soldered to the bottom of the main PCB and the top of the upper PCB. Finally, a cooling fan is mounted on the heat sink.

[0070] Specific steps for dynamic current sharing layout design of multi-chip parallel GaN power modules:

[0071] Step 1: Design the GS-065-060-2-D2 gallium nitride die schematic library and package library in Altium Designer.

[0072] Step 2: Design the flexible printed circuit (FPC) schematic in Altium Designer. This design will build a GaN half-bridge power module. The flexible printed circuit (FPC) contains the power GaN chip and its drive circuit. Each switch position of the half-bridge uses four GaN chips in parallel, and the upper and lower switches are driven by a driver chip respectively. The drive circuit design uses the solution selection and design recommended by GaNsystems' "GN001 Application Guide Design with GaN Enhancementmode HEMT". The schematic design is as follows Figure 6 Shown: (a) upper tube drive circuit, (b) lower tube drive circuit, (c) main power circuit.

[0073] Step 3: Design the GaN chip layout and routing within the flexible printed circuit (FPC) in Altium Designer. A two-layer FPC structure is used. The GaN chip pads are located on the upper copper layer of the FPC. Vias connect the upper and lower copper layers, which then serve as RDL connections to the main DPC. The four chips at each switch position are arranged in a straight line, "hand in hand," with the upper and lower switches aligned and positioned appropriately. Copper cladding is used to connect the GaN chip's source and drain pads, consistent with the electrical relationship and pad geometry.

[0074] Step 4: Design the driver layout and routing for the flexible printed circuit (FPC) in Altium Designer. The components used in the driver circuit are packaged in SMD form factors, with pads located on the top surface. The driver chip and peripheral circuitry are laid out according to the recommendations in the "GN001 Application Guide Design with GaN Enhancement-mode HEMTs" and placed on the left (or right) side of the GaN chip. The right gate g1 of die1 is interconnected with the left gate g2 of die2 and led out; the right gate g3 of die3 is interconnected with the left gate g4 of die4 and led out, with the two leads symmetrically about the axis of symmetry of the main power circuit. The gate routing for the drive signal to each chip is copper-plated from the driver resistor to the two leads, laid out on the lower copper layer. The source of die1, closest to the right gate g1, leads to Kelvin source ks1; the source of die2, closest to the left gate g2, leads to Kelvin source ks2; the source of die3, closest to the right gate g3, leads to Kelvin source ks3; the source of die4, closest to the left gate g4, leads to Kelvin source ks4. ks1-ks2 and ks3-ks4 are symmetrical about the main power loop's axis of symmetry. The Kelvin source routing from the drive ground to each chip is copper-plated sequentially from the drive ground to the four lead-out points, laid out on the upper copper layer, overlapping with the gate routing from the drive signal to each chip.

[0075] Steps 1-4 complete the design of the flexible circuit board (FPC). The flexible circuit board (FPC) layout design is as follows Figure 7 As shown, the top surface houses the GaN chip and driver, while the bottom surface features the RDLs for the GaN chip's source and drain. Pads 1-7 are located on the bottom surface, along with the RDL pads, for soldering and securing the flexible printed circuit (FPC) to the main DPC.

[0076] Step 5: Design the main-DPC required for the main power circuit in SolidWorks. Use a DPC with a Cu / ALN / Cu 0.3mm / 0.635mm / 0.3mm structure. Design the copper layer on the main-DPC surface according to the flexible circuit board (FPC) layout and chip RDL distribution designed in steps 1-4. Figure 8 The D and S on the upper side of the DPC are the RDL soldering points for the chip on the flexible printed circuit (FPC). The DPC design incorporates busbars and output terminal connections (DC+, DC-, and AC) based on electrical connectivity, insulation considerations, and chip placement. The left copper layer is connected to ground potential at the bottom of the driver circuit, forming a shield to mitigate electromagnetic interference from the main power circuit's magnetic field on the left-hand drive circuit. The DC+ busbar (which can also be DC-, with the busbar terminal position adjusted simultaneously) is connected via DPC vias to form a vertical commutation structure.

[0077] Step 6: Design the chip top connection up-DPC in solidworks. Use Cu / ALN / Cu 0.3mm / 0.635mm / 0.3mm structure DPC. Figure 9 As shown, the top heat sink serves the following functions: 1. Connecting the chip source to the heat sink through a gasket, achieving equal potential between the chip heat sink and the source; 2. Isolation, allowing the heat sink to be soldered to the other side of the DPC.

[0078] Step 7: Design a gasket. The gasket is 0.27mm, which is basically consistent with the thickness of the chip. It is used to connect the chip source and the heat dissipation surface, and at the same time plays a role in balancing and supporting the DPC.

[0079] Step 8: Design the radiator according to the position and space of the upper and lower pipes of the half-bridge, such as Figure 10 This case is designed with a 28mm*28mm*10mm radiator and 2.5mm studs on the radiator, which is suitable for installing a 30mm*30mm small fan.

[0080] The actual processing steps of multi-chip parallel dynamic current sharing GaN power module are as follows:

[0081] Step 1: Prepare the designed flexible circuit board (FPC), main-DPC, up-DPC, GaN chip, decoupling capacitors and devices required for the drive circuit according to the design steps.

[0082] Step 2: The chip, gasket and flexible circuit board (FPC) are reflow soldered using Sn99Cu0.7Ag0.3 solder paste at 227℃.

[0083] Step 3: Place the flexible printed circuit board (FPC) on the main-DPC, the up-DPC on top of the chip, and the heat sinks on the top and bottom. Decoupling capacitors and terminals are also placed on the main-DPC, and the driver circuit components are placed on the flexible printed circuit board (FPC). Reflow soldering is performed using Sn63Pb37 solder paste at 183°C.

[0084] Step 4: Glue filling: Use silicone gel (Nusil-R2188) to fill the gap between the upper and lower DPCs to enhance the insulation of the module.

[0085] Step 5: Install other external components such as pillars, small fans, etc.

[0086] Analysis of the current sharing mechanism of the dynamic current sharing layout design method for multi-chip parallel power modules proposed in this invention:

[0087] 1. The power drain and source of the parallel GaN chips are integrated and form a vertical commutation structure. The current path of each chip is the same and can be regarded as a whole. Figure 3, the Kelvin source is set on the source closest to the extraction gate, such as Figure 4 The ks1, ks2, ks3, and ks4 of the four chips are not physically connected to the power source. Therefore, the quasi-common source inductors of the four chips can be regarded as a whole, such as Figure 11 Medium L cs , which solves the problem of inconsistent quasi-common source inductance in horizontal commutation structure, such as Figure 12 .

[0088] 2. The power circuit forms a vertical commutation structure, and the drive circuit forms a vertical commutation structure. The drive circuit and the power circuit are physically decoupled and located above the power circuit, and the commutation paths are perpendicular to each other, such as Figure 3 and 4 .

[0089] 3. During the switching process, the switch tube commutates, and the commutation current flows through the vertical commutation formed by the power circuit and the decoupling capacitor. The upper and lower conductors flow through the commutation current of equal magnitude and opposite direction. The internal magnetic fields of the parallel plane conductors increase each other, and the external magnetic fields of the parallel plane conductors cancel each other. At the same time, the magnetic field forms a closed loop. The front view of the power vertical commutation circuit and the magnetic field distribution are shown as follows: Figure 13 shown.

[0090] 4. Select points a, b, and c on the upper side of the power circuit. Point c is located on the axis of symmetry, and points a and b are symmetrical about point c. The magnetic field at each point is the integral of the magnetic field at that point due to a unit current in a parallel plane conductor.

[0091] 5. When the commutation current is uniformly distributed horizontally in the conductor, the magnetic field strength at point c is horizontal. Points a and b have horizontal and vertical components. Points a and b are symmetrical about the axis of symmetry. The horizontal magnetic field strength is equal in magnitude and direction. Figure 13 middle , , the magnetic field strength in the vertical direction is equal in magnitude and opposite in direction. Figure 13 middle , Due to the edge effect, the magnetic field intensity is stronger at the edge of the power circuit.

[0092] 6. The drive circuit is designed above the main power circuit. The horizontal magnetic field strength does not pass through the drive circuit, but the vertical magnetic field passes through the drive circuit. The drive circuit design proposed by the present invention has a schematic diagram of the vertical magnetic field strength of the layout and wiring from the driver chip to the chip gate and the Kelvin source to the driver ground. Figure 14 The magnetic fields that the driver chip-to-chip gate wiring and the Kelvin source-to-driver ground wiring pass through are equal in magnitude and opposite in direction (the starting direction of the wiring changes).

[0093] 7. Biot-Savart Law: , The mutual inductance of the power circuit to the drive circuit is: .

[0094] 8. The magnetic flux passing through the driver chip to the chip gate wiring increases as the wiring extends from left to right, and reaches its maximum when it reaches the symmetry axis. The magnetic flux decreases as it extends to the right beyond the symmetry axis, and the magnetic flux is equal at the position symmetrical to the symmetry axis. This is because the area symmetrical to the symmetry axis is Figure 14 The magnetic field integral within the circled region symmetrical about the axis of symmetry is zero. The magnetic flux distribution from the Kelvin source to the driver ground is similar, but in the opposite direction. Therefore, the total magnetic flux generated by the main circuit commutation through the driver loop (the driver resistor to chip gate wiring and the Kelvin source to driver ground wiring) is essentially zero.

[0095] 9. Based on the above analysis, the design proposed by the present invention ensures that the mutual inductance of the main power circuit to each of the four chip driver circuits is equal. The mutual inductance of the vertical commutation power circuit to the driver chip-to-chip gate wiring increases from the edge to the center and is equal at locations symmetrical about the symmetry axis. The mutual inductance of the vertical commutation power circuit to the Kelvin source-to-driver ground wiring increases from the edge to the center and is equal at locations symmetrical about the symmetry axis. The mutual inductances of the two components are opposite in sign, and their sum is essentially zero.

[0096] 10. The driver loop layout was routed from the left side of the power loop to the right side, with 31 points uniformly selected as gate and Kelvin source lead-out points. Ansys simulation was used to extract the partial inductances between the power loop and driver to the chip gate, and between the power loop and Kelvin source to the driver ground. As shown in Figure 14, the mutual inductances are essentially equal along the symmetrical axes, and the sum of the two is close to zero, confirming the theoretical analysis above.

[0097] Conclusion: The vertical commutation of the main power circuit and the integrated source and drain design of the parallel chips make the quasi-common source inductance of the chips consistent and integrated, which is conducive to dynamic current sharing of multiple GaN chips in parallel. When the drive circuit wiring is vertically commutated and designed perpendicular to the main power circuit, the mutual inductance of the power circuit to the drive circuit is basically zero, which is conducive to dynamic current sharing of GaN chips in parallel. When the above design is met and the drive terminal and Kelvin source terminal are symmetrical about the symmetry axis of the main power circuit, the mutual inductance of the main power circuit to the drive-to-chip gate wiring and the mutual inductance of the Kelvin source-to-drive ground wiring are equal, which can achieve excellent dynamic current sharing effect of multiple GaN chips in parallel.

[0098] like Figure 15 As shown, an embodiment of the present invention provides a dynamic current sharing layout design system for multi-chip parallel GaN power modules, including:

[0099] Main power circuit design module, used for layout and wiring of the main power circuit;

[0100] The drive circuit design module is used for layout and routing of the drive circuit.

[0101] Heat dissipation module, used for heat dissipation design of the module.

[0102] According to the method described in the present invention, a multi-chip parallel GaN power module is designed using a gallium nitride chip with a rated voltage of 650V, a rated current of 60A, and model GS-065-060-2-D2, and the dynamic current sharing effect is verified.

[0103] The design module was imported into Ansys Q3D software and the inductance and mutual inductance were extracted. Table 1 lists the extracted values ​​of the main power loop and the lower drive loop, where L gx is the value of the gate inductance from the positive electrode of the drive power decoupling capacitor to the GaN chip x, L sx is the inductance from the chip x Kelvin source to the negative electrode of the driver power decoupling capacitor, L p is the inductance of the main power supply loop. The bold data on the diagonal of the table are self-inductance values, and the other data are mutual inductance values.

[0104] The parasitic inductances in Table 1 are imported into LTspice to construct an equivalent simulation circuit. The simulation results are shown in Figure 1. Figure 16 As shown in Figure 2, the on-state current of the four GaN chips connected in parallel is equal. There is some dynamic current non-uniformity in the turn-on and turn-off transients. g = 10Ω, the maximum turn-on transient current unevenness is 1.35 A, and the maximum turn-off transient current unevenness is 0.78 A. In addition, the current unevenness is basically independent of the magnitude of the turn-on current.

[0105] The designed module was imported into Comsol software for thermal resistance extraction. The thermal resistance from the GaN chip to the top copper layer of the up-DPC was 0.16K / W, the thermal resistance from the GaN chip to the bottom copper layer of the main-DPC was 0.62K / W, and the double-sided heat dissipation thermal resistance was 0.144K / W. A solid-fluid heat transfer simulation of a multi-chip parallel GaN power module was also performed. The loss per chip was 15W. Two small fans with an air intake of 10CFM were used, and the maximum module temperature was 75.5°C. Figure 17 .

[0106] Figure 18 The left picture shows the actual module. The up-DPC and heat sink are not soldered. A 4mm thick spacer is used to raise the flexible printed circuit board (FPC) so that the Rogowski coil can be placed in the hole. The current flowing through each chip is measured to verify the current sharing effect. The pulse experiment waveform is as follows Figure 19As shown in Figure 19(a), the currents of the four chips are equal in the on-state. Figure 19(b) shows the transient waveforms during turn-on and turn-off. The transient currents of the four chips are essentially the same, and the experimental waveforms are consistent with the simulated waveforms. The maximum unequal currents during turn-on and turn-off transients are also close to the simulation results, at 1.3 A and 0.84 A, respectively.

[0107] A complete hybrid double-sided GaN power module with DPC and FPC cooling was fabricated using the process steps proposed in this invention; the module is shown in the right image of Figure 18. At this point, the current of each chip cannot be measured; only the total current output by the parallel chips can be measured. The left image of Figure 20 shows the voltage and current waveforms during continuous operation at a 300 V bus voltage, 50 A current amplitude, a purely inductive load, and a 245 kHz output frequency. The right image of Figure 20 shows the temperature distribution of the module during steady-state operation under double-sided forced air cooling conditions. The highest temperature occurs between the two DPC layers and the isolated power supply, with the surface temperature of the upper DPC layer reaching 54.1°C, demonstrating the module's ability to operate continuously.

[0108] Table 1: Extracted values ​​of self-inductance and mutual inductance of the designed multi-chip parallel GaN power module Unit: nH

[0109]

[0110] It should be noted that the embodiments of the present invention can be implemented by hardware, software, or a combination of software and hardware. The hardware portion can be implemented using dedicated logic; the software portion can be stored in a memory and executed by an appropriate instruction execution system, such as a microprocessor or dedicated design hardware. Those skilled in the art will appreciate that the above-mentioned devices and methods can be implemented using computer-executable instructions and / or contained in processor control code, for example, such as a carrier medium such as a disk, CD or DVD-ROM, a programmable memory such as a read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The devices and modules of the present invention can be implemented by hardware circuits such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., can also be implemented by software executed by various types of processors, or can be implemented by a combination of the above-mentioned hardware circuits and software, such as firmware.

[0111] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with this technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered by the scope of protection of the present invention.

Claims

1. A dynamic current sharing layout design method for a multi-chip parallel power module, characterized in that: The following steps are involved: 1) Main power circuit layout and wiring design: When planar GaN chips are connected in parallel, they are placed side by side in a "hand-in-hand" pattern to form a symmetrical layout. The power circuit layout of the half-bridge module adopts a vertical commutation structure; The source and drain of the parallel chips are interconnected nearby while meeting the insulation requirements, and the source and drain layout and wiring of multiple parallel chips are integrated into an integrated whole; 2) Drive circuit layout and wiring design: For the four chips connected in parallel, Chip 1 and Chip 2 are "hand in hand" and lead out to the gate, while Chip 3 and Chip 4 are "hand in hand" and lead out to the gate, and the two lead-out terminals are symmetrical about the symmetry axis of the main power circuit; the Kelvin source lead-out terminals of the four chips are selected to be the source closest to the gate lead-out terminal of each chip, and are basically symmetrical about the symmetry axis; The drive signal wiring is carried out horizontally under the condition of meeting the insulation requirements, connecting the chip gate lead-out terminals in sequence, and ensuring that the gate wiring is symmetrical about the symmetry axis of the main power circuit; The Kelvin source lead-out wiring is horizontally connected to the ground potential of the driving circuit and overlaps with the driving signal wiring up and down to form a vertical commutation structure to reduce the self-inductance value of the driving circuit and make the mutual inductance of the power circuit to the driving circuit close to zero.

2. The method according to claim 1, characterized in that The main power circuit layout design includes: The integrated design of vertical commutation in the power circuit ensures that the drain and source circuits and layout of each parallel chip are exactly the same. Therefore, the quasi-common source inductors are identical and integrated, eliminating the circulating current between the quasi-common source inductors and reducing the impact on the gate voltage and dynamic current.

3. The method according to claim 1, characterized in that The drive circuit layout design includes: The drive circuit is horizontally separated from the power circuit, with the drive circuit placed on the left or right side of the power circuit. The power circuit only contains the GaN power chip and a gasket of the same height, without other components of varying heights. Therefore, when soldering the power chip to the ceramic substrate, there is no need to match the height of the chip. The top of the chip can be directly soldered to the bottom of the ceramic substrate, reducing thermal resistance. The signal wiring from the driver chip to the chip gate and the wiring from the Kelvin source to the driving ground form a vertical commutation structure, and are perpendicular to the power loop, so the mutual inductance between the power loop and the driver loop is 0; when the chip gate lead-out end is symmetrical about the symmetry axis of the power loop, the partial mutual inductance of the power loop and the driving signal line of each chip is equal; when the Kelvin source is symmetrical about the symmetry axis, the partial mutual inductance of the power loop and the Kelvin source to the driving ground wiring of each chip is equal; the mutual inductance of the power loop to each part of the driving loop of each chip can be made equal, and excellent dynamic current sharing characteristics can be achieved.

4. The method according to claim 1, wherein The layout of the main power circuit and the drive circuit can adopt a hybrid packaging solution combining a Cu / AlN / Cu direct copper plating DPC substrate and a flexible circuit board FPC, wherein: The main power circuit uses DPC substrate and FPC for busbar connection and power chip layout connection; The drive circuit is laid out on the FPC, and the FPC is welded above the main power circuit to form a sandwich structure with double-sided heat dissipation.

5. The method according to claim 1, wherein The main power circuit can be constructed using two layers of FPC and DPC. The GaN chip pads are designed to be arranged "hand in hand" on the upper copper layer of the FPC. The source and drain pads of the GaN chip are connected as a whole using copper cladding according to the electrical relationship and pad shape. The upper and lower copper layers of the FPC are connected through vias at the GaN chip pad positions. The lower copper layer performs RDL on the GaN source and drain and is welded to the corresponding positions of the main-DPC upper copper layer. The main-DPC busbar and output terminals are designed based on electrical connection and insulation, and are connected through vias to form a vertical commutation structure.

6. The method according to claim 1, characterized in that The drive circuit can be designed on the FPC. The components used in the drive circuit adopt SMD packaging, with the pads designed on the top. The drive chip and peripheral circuits are located on the left side of the gallium nitride chip. The top copper layer of the main DPC corresponding to the FPC driving position is connected to the ground potential to form a shielding layer to reduce the electromagnetic interference of the main power circuit magnetic field on the driving circuit.

7. A dynamic current sharing design system for multi-chip parallel power modules, characterized in that: The system includes: The main power circuit module includes multiple planar GaN chips placed side by side in a "hand-in-hand" arrangement and interconnected via a vertical commutation structure to form an integrated layout. This layout ensures that the quasi-source inductance of each chip is essentially consistent, reducing the impact of the quasi-common source inductance circulating current on the current sharing. Drive circuit module: includes the drive chip and peripheral circuits on the FPC. The drive signal wiring and the chip Kelvin source terminal wiring are horizontally connected in sequence to form a vertical commutation structure. The drive circuit wiring and the main power circuit wiring are arranged perpendicular to each other. Heat dissipation module: includes a gasket, a heat dissipation substrate up-DPC and a heat sink. The gasket has the same thickness as the chip and is used to connect the chip source and the chip heat dissipation top surface, achieving equipotential between the substrate surface and the source on the chip, while also balancing and supporting the up-DPC. The up-DPC acts as an insulator and is welded to the heat dissipation surface of the GaN chip, with the heat sink welded on the other side. The main-DPC and up-DPC form a sandwich structure to achieve double-sided heat dissipation of the module.

8. The system according to claim 7, characterized in that The main power circuit module further comprises: Decoupling capacitors are used to minimize parasitic inductance in the power loop in the vertical commutation structure and to ensure the consistency of the current path; The busbar terminals, including DC+, DC- and AC output terminals, are arranged on the DPC substrate, and the DC+ or DC- vias are connected to form a vertical commutation path.

9. The system according to claim 7, wherein: The layout design of the drive circuit module is as follows: The drive signal wiring and the Kelvin source wiring overlap in the vertical commutation structure, and the magnetic field cancellation effect is used to make the total mutual inductance of the power circuit to the drive circuit close to zero; The signal wiring from the driver chip to the chip gate and the wiring from the chip Kelvin source to the driver ground are symmetrically distributed about the symmetry axis of the main power loop, ensuring that the mutual inductance value of each part of the power loop to each chip driver loop is equal, thereby achieving a significant dynamic current sharing effect.

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