Signal processing circuit of target simulator carried on UUV platform

Abstract

The invention belongs to the technical field of underwater acoustic signal processing, and particularly relates to a signal processing circuit of a target simulator carried on a UUV platform. Comprising an analog circuit adopting an analog receiver; the analog circuit comprises a signal amplification circuit, a signal filter circuit and a gain control circuit; the signal amplification circuit comprises a primary amplification circuit and a final amplification circuit; the signal filtering circuit comprises a fourth-order low-pass filter and a fourth-order high-pass filter; the gain control circuit is composed of a secondary amplification circuit and an analog switch. The analog switch is connected with the secondary amplification circuit; the digital circuit comprises a DSP (Digital Signal Processor), a data acquisition circuit, a data forwarding circuit, a data storage circuit, a serial port communication circuit and a power supply conversion module; the invention mainly solves the problems of power supply source, bandwidth, sampling rate and other parameters, input noise influence and circuit power.

Description

Technical Field

[0001] The invention belongs to the technical field of underwater acoustic signal processing, and in particular relates to a signal processing circuit of a target simulator carried on a UUV platform. Background Art

[0002] In the process of the development of sonar technology and sonar equipment, computer technology and signal processing technology have also been continuously developed, which laid the foundation for the emergence of target simulators. Foreign countries' research on sonar target simulator equipment is relatively early, and it has become relatively mature today. Sonar target simulator equipment with various functions has been widely used. Since the 1980s, my country's research on target simulators has also been continuously deepened. At the beginning, it was only at the level of mathematical modeling and theoretical analysis, but with the development of signal processing technology and the improvement of hardware technology, my country's research on target simulators has also developed into the physical level. The main function of the target simulator is to simulate the echo signal of the sonar, but due to different application backgrounds, different units have also developed different target simulators.

[0003] The signal processing circuit of the traditional target simulator has the following main disadvantages:

[0004] (1) Input power is unstable;

[0005] (2) The receiver bandwidth and sampling rate cannot meet the requirements of most scenarios;

[0006] (3) The equivalent input noise of the receiver is too large;

[0007] (4) The signal processing circuit consumes too much power. Summary of the invention

[0008] The purpose of the present invention is to provide a signal processing circuit for a target simulator mounted on a UUV platform, which mainly solves the above-mentioned power supply source problem, bandwidth, sampling rate and other parameter problems, input noise influence problem and circuit power problem.

[0009] In order to solve the above technical problems, the present invention provides a signal processing circuit of a target simulator mounted on a UUV platform, comprising:

[0010] The analog circuit adopts an analog receiver; the analog circuit includes a signal amplifying circuit, a signal filtering circuit and a gain control circuit; the signal amplifying circuit includes a primary amplifying circuit and a final amplifying circuit; the signal filtering circuit includes a fourth-order low-pass filter and a fourth-order high-pass filter; the gain control circuit is composed of a secondary amplifying circuit and an analog switch; the primary amplifying circuit is connected to the secondary amplifying circuit, the fourth-order low-pass filter, the fourth-order high-pass filter and the final amplifying circuit in sequence, and the analog switch is connected to the secondary amplifying circuit;

[0011] The digital circuit includes a DSP processor, a data acquisition circuit, a data forwarding circuit, a data storage circuit, a serial communication circuit and a power conversion module; the DSP processor is respectively connected to the data acquisition circuit, the data forwarding circuit, the data storage circuit and the serial communication circuit, and the power conversion module supplies power to the signal processing circuit as a whole.

[0012] Preferably, the primary amplifier circuit includes: a resistor R1, a resistor R4, a resistor R12, a resistor R41, a resistor R46, an operational amplifier N3A, a capacitor C1, a capacitor C3, a capacitor C10, a capacitor C11 and a capacitor C16; the in-phase input terminal of the operational amplifier N3A is connected to the grounded resistor R41 and one end of the capacitor C10, and the other end of the capacitor C10 is the INP terminal; the inverting input terminal of the operational amplifier N3A is connected to the grounded resistor R4 and one end of the resistor R12, the other end of the resistor R12 is connected to the output terminal of the operational amplifier N3A, the positive power supply terminal of the operational amplifier N3A is connected to one end of the resistor R46, the capacitor C11 and the capacitor C16, the other end of the resistor R46 is connected to the power supply +5V, and the other ends of the capacitor C11 and the capacitor C16 are grounded; the negative power supply terminal of the operational amplifier N3A is connected to one end of the resistor R1, the capacitor C1 and the capacitor C3, the other end of the resistor R1 is connected to the power supply -5V, and the other ends of the capacitor C1 and the capacitor C3 are grounded.

[0013] Preferably, the final amplifier circuit uses a connected reverse amplifier circuit and a first-stage emitter-follower circuit as the last stage of the analog receiver; the final amplifier circuit includes: an operational amplifier U10A, an operational amplifier U10B, a resistor R60, a resistor R72, a resistor R73, a resistor R81, a resistor R82, a capacitor C84 and a capacitor C126; the in-phase input terminal of the operational amplifier U10A is connected to the grounded resistor R82, the inverting input terminal of the operational amplifier U10A is connected to the resistor R73 and one end of the resistor R72, and the other end of the resistor R72 is connected to the grounded resistor R82. The positive power supply terminal of the operational amplifier U10A is connected to the output terminal of the operational amplifier U10A and the non-inverting input terminal of the operational amplifier U10B; the positive power supply terminal of the operational amplifier U10A is connected to the resistor R81 and one end of the capacitor C126, the other end of the resistor R81 is connected to the power supply +5V, and the other end of the capacitor C126 is grounded; the negative power supply terminal of the operational amplifier U10A is connected to the resistor R60 and one end of the capacitor C84, the other end of the resistor R60 is connected to the power supply -5V, and the other end of the capacitor C84 is grounded; the inverting input terminal of the operational amplifier U10B is connected to the output terminal of the operational amplifier U10B.

[0014] Preferably, the gain control circuit includes: an operational amplifier N3B, a resistor R13, a resistor R27, a resistor R42, a resistor R43, a resistor R50, a resistor R51, a capacitor C17, a capacitor C18, a capacitor C27, a capacitor C83 and an analog switch U6 (MAX319ESA type); the in-phase input terminal of the operational amplifier N3B is connected to the grounded resistor R13, the inverting input terminal of the operational amplifier N3B is connected to one end of the resistor R42 and the resistor R43, the other ends of the resistor R42 and the resistor R43 are respectively connected to the NO terminal and the NC terminal of the analog switch U6, and the output terminal of the operational amplifier N3B is connected to the grounded resistor R13. The analog switch U6 is connected to the COM terminal, the IN terminal of the analog switch U6 is connected to CTR1, the VL terminal of the analog switch U6 is connected to the power supply +5V, the V+ terminal of the analog switch U6 is connected to the resistor R50 and one end of the capacitor C17 and the capacitor C27, the other end of the resistor R50 is connected to the power supply +5V, the other ends of the capacitors C17 and C27 are grounded, the V- terminal of the analog switch U6 is connected to the resistor R51 and one end of the capacitor C18 and the capacitor C83, the other end of the resistor R51 is connected to the power supply -5V, and the other ends of the capacitors C18 and C83 are grounded.

[0015] Preferably, the fourth-order low-pass filter is constructed by combining two single-op-amp second-order low-pass filters; the fourth-order low-pass filter includes: an op amp U7A, an op amp U7B, a resistor R7, a resistor R15, a resistor R17, a resistor R36, a resistor R40, a resistor R44, a resistor R48, a resistor R49, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C8, a capacitor C12, a capacitor C13 and a capacitor C14; the in-phase input terminal of the op amp U7A is connected to the grounded capacitor C12 and one end of the resistor R17, the other end of the resistor R17 is connected to one end of the resistor R15 and one end of the capacitor C5 and the capacitor C6, the other ends of the capacitor C5 and the capacitor C6 are connected to the output terminal of the op amp U7A, the resistor R36 and One end of the resistor R48 and the other end of the resistor R48 are connected to the inverting input terminal of the operational amplifier U7A, the positive power supply terminal of the operational amplifier U7A is connected to the resistor R7 and the grounded capacitor C4, the other end of the resistor R7 is connected to the power supply +5V, the negative power supply terminal of the operational amplifier U7A is connected to the resistor R44 and the grounded capacitor C13, and the other end of the resistor R44 is connected to the power supply -5V; the other end of the resistor R36 is connected to the capacitor C8 and one end of the resistor R40, the other end of the resistor R40 is connected to the grounded capacitor C14 and the non-inverting input terminal of the operational amplifier U7B, the inverting input terminal of the operational amplifier U7B is connected to one end of the resistor R49, and the other end of the resistor R49 is connected to the output terminal of the operational amplifier U7B and the other end of the capacitor C8.

[0016] Preferably, the fourth-order high-pass filter is constructed by combining two single-op-amp second-order high-pass filters; the fourth-order high-pass filter includes: an op amp U9A, an op amp U9B, a resistor R58, a resistor R61, a resistor R62, a resistor R74, a resistor R75, a resistor R77, a resistor R79, a resistor R83, a resistor R84, a capacitor C119, a capacitor C120, a capacitor C89, a capacitor C121, a capacitor C122 and a capacitor C124; the in-phase input terminal of the op amp U9A is connected to the grounded resistor R74 and one end of the capacitor C120, and the other end of the capacitor C120 is connected to one end of the capacitor C119 and the resistor R58, one end of the resistor R83, one end of the capacitor C121 and one end of the capacitor C122, and one end of the resistor R61 and the output end of the operational amplifier U9A, the other end of the resistor R83 is connected to the inverting input end of the operational amplifier U9A, the positive power supply end of the operational amplifier U9A is connected to the resistor R62 and the grounded capacitor C89, the other end of the resistor R62 is connected to the power supply +5V, the negative power supply end of the operational amplifier U7A is connected to the resistor R79 and the grounded capacitor C124, and the other end of the resistor R79 is connected to the power supply -5V; the other end of the resistor R61 is connected to one end of the resistor R84 and the output end of the operational amplifier U9B, the other end of the resistor R84 is connected to the inverting input end of the operational amplifier U9B, the other end of the capacitor C122 is connected to one end of the resistor R75 and the non-inverting input end of the operational amplifier U9B, and the other end of the resistor R75 is connected to the grounded resistor R77.

[0017] Preferably, the data acquisition circuit is mainly composed of a 16-bit data A / D chip, which collects the analog signal of the analog receiver; the data forwarding circuit is mainly composed of a D / A chip; the A / D chip and the D / A chip adopt a serial frame synchronization interface mode, are externally connected to the McBSP of the DSP processor, and the crystal oscillator is connected to the CPLD, and two clocks of the same frequency are separated in the CPLD and provided to the A / D chip and the D / A chip respectively, SCLK is the clock provided by the DSP processor to the D / A chip for data transmission, and the DSP processor inputs 24-bit data to the D / A chip at this clock frequency.

[0018] Preferably, the output end of the data forwarding circuit also includes an output signal adjustment circuit, which includes: an operational amplifier U12A, an operational amplifier U12B, a resistor R87, a resistor R88, a capacitor C140, a capacitor C141, an isolation transformer L8 and an isolation transformer L9; the in-phase input end of the operational amplifier U12A is connected to one end of the resistor R87 and the grounded capacitor C140, the other end of the resistor R87 is connected to the output signal DA1 of the D / A chip, the inverting input end of the operational amplifier U12A is connected to the output end of the operational amplifier U12A and 1 end of the primary coil of the isolation transformer L8, the positive power supply end of the operational amplifier U12A is connected to the power supply +5V, the negative power supply end of the operational amplifier U12A is grounded, and the primary coil of the isolation transformer L8 is grounded. Two ends of the secondary coil are grounded, and the three ends of the secondary coil of the isolation transformer L8 are the output end DA_OUT1 of the output signal adjustment circuit, and the four ends of the secondary coil of the isolation transformer L8 are grounded; the in-phase input end of the operational amplifier U12B is connected to one end of the resistor R88 and the grounded capacitor C141, and the other end of the resistor R88 is connected to the output signal DA2 of the D / A chip, the inverting input end of the operational amplifier U12B is connected to the output end of the operational amplifier U12B and one end of the primary coil of the isolation transformer L9, and the two ends of the primary coil of the isolation transformer L9 are grounded, and the three ends of the secondary coil of the isolation transformer L9 are the output end DA_OUT2 of the output signal adjustment circuit, and the four ends of the secondary coil of the isolation transformer L9 are grounded.

[0019] The present invention also provides a target simulator mounted on a UUV platform, using the signal processing circuit of the target simulator mounted on the UUV platform as described above, comprising:

[0020] UUV master control;

[0021] A target simulator is connected to the UUV main control; the target simulator is composed of a transducer, an analog circuit, a transmitter and a digital circuit; wherein the transducer is composed of a receiving hydrophone, a medium-low frequency transducer and a high-frequency transducer; and the transmitter is composed of a medium-low frequency transmitter and a high-frequency transmitter;

[0022] UUV battery, which provides power to the entire device;

[0023] The host computer is connected to the UUV main control and the digital circuit control respectively.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] 1) Receiver bandwidth: 2kHz-30kHz.

[0026] 2) Receiver equivalent input noise: less than 55dB.

[0027] 3) Sampling rate: 150kHz.

[0028] 4) Total power consumption of signal processing circuit: less than 4W. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a block diagram of the target simulator of the present invention.

[0030] Figure 2 It is a structural block diagram of the target simulator receiver of the present invention.

[0031] Figure 3 It is a structural diagram of the primary amplifier circuit of the present invention.

[0032] Figure 4 It is a structural diagram of the final stage amplifier circuit of the present invention.

[0033] Figure 5 It is a structural diagram of the gain control circuit of the present invention.

[0034] Figure 6 It is the basic structure diagram of the second-order low-pass filter of the present invention.

[0035] Figure 7 It is a structural diagram of a 4th-order low-pass filter of the present invention.

[0036] Figure 8 It is the basic structure diagram of the second-order high-pass filter of the present invention.

[0037] Fig. 9 It is the basic structure diagram of the 4th order high pass filter of the present invention.

[0038] Fig.10 It is a structural block diagram of the digital part of the present invention.

[0039] Fig.11 It is a partial connection principle diagram of the data acquisition circuit of the present invention.

[0040] Fig.12 It is a partial connection principle diagram of the data forwarding circuit of the present invention.

[0041] Fig.13 This is the output signal arrangement circuit diagram of the present invention.

[0042] Fig.14 It is a connection schematic diagram of the data storage circuit of the present invention.

[0043] Fig.15 It is a schematic diagram of the serial-to-parallel conversion connection of the present invention. DETAILED DESCRIPTION

[0044] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0045] like Figure 1 As shown, an embodiment of the present invention provides a target simulator mounted on a UUV platform. The target simulator is mounted on the UUV platform, so the entire device includes a UUV main control part and a target simulator part, and the entire device is powered by a UUV battery. The target simulator part is composed of a receiving hydrophone, an analog receiver, a digital circuit, a transmitter, a medium and low frequency transducer, and a high frequency transducer. The analog receiver and the digital circuit are drawn on a PCB, so they are collectively referred to as a signal processing circuit. The present invention mainly designs the signal processing circuit of the target simulator.

[0046] Analog circuit design: The signal received by the hydrophone of the target simulator is usually in the microvolt or millivolt level. Such a tiny electrical signal, coupled with the influence of system self-noise and ocean environmental noise, will make it difficult for the target simulator system to detect active sonar signals. Therefore, a low-noise and low-power analog receiver is necessary for the target simulator system.

[0047] The analog receiver mainly includes signal amplification circuit, signal filtering circuit, gain control circuit and isolated power supply. The primary amplification circuit is used to amplify the tiny signal received by the hydrophone; the secondary amplification circuit is a gain control circuit to meet the requirements of different working distances of the target simulator; the signal filtering circuit is used to filter out the noise and interference signals outside the frequency band after the signal is amplified; the signal will be attenuated after passing through the filter, so the final amplification circuit is added; at the same time, a transmitter-follower circuit is added to improve the load capacity of the analog receiver. The structure of the analog receiver is as follows: Figure 2 shown.

[0048] Signal amplifier circuit: The primary amplifier circuit is the first stage of the receiver, which directly amplifies the signal received by the hydrophone. Therefore, the amplifier circuit needs to have a small self-noise to improve the signal-to-noise ratio of the channel. ADA4841 is a standard low-noise operational amplifier. Since the receiver needs to match the impedance of the hydrophone, a 1kΩ resistor is connected in parallel to the circuit. The specific structure is as follows: Figure 3 shown.

[0049] The final amplifier circuit uses a reverse amplifier circuit plus a first-stage emitter-follower circuit, which is the last stage of the receiver. The specific structure is as follows Figure 4 shown.

[0050] Gain control circuit: The gain control circuit is constructed by the secondary amplifier circuit and the analog switch. The specific structure is as follows Figure 5 shown.

[0051] Signal filtering circuit: For the amplitude-frequency characteristics, we always hope that the passband is smooth enough and the transition band is steep enough. This requires a filter with a high enough order, but a high-order filter will also bring other problems, such as self-excited oscillation. After comprehensive engineering indicators and actual capabilities, a combination of a 4th-order low-pass filter and a 4th-order high-pass filter is designed to build a bandpass filter. The 4th-order low-pass filter is built by combining two single op amp 2nd-order low-pass filters. The basic structure of a single op amp 2nd-order low-pass filter is as follows: Figure 6 shown.

[0052] The actual structure diagram of the 4th order low pass filter is as follows Figure 7 The design of the high-pass filter is similar to that of the low-pass filter. A 4th-order high-pass filter is constructed by combining two single op amp 2nd-order high-pass filters. The basic structure of a single op amp 2nd-order high-pass filter is shown in Figure 8 The actual structure of the 4th-order high-pass filter is shown in Fig. 9 shown.

[0053] Digital circuit design: The digital circuit part of the target simulator mainly includes data acquisition circuit, data forwarding circuit, data storage circuit, serial communication circuit and power module. The structural block diagram is as follows Fig.10 shown.

[0054] Data acquisition circuit: Since the processor can only operate on digital signals, a data acquisition circuit is designed. The data acquisition circuit is mainly composed of an A / D chip to collect the analog signal of the receiver. In order to ensure the accuracy of the digital signal and facilitate the processor operation, an A / D chip with a sampling accuracy of 16 bits is selected. According to the peripheral limitations of the DSP, the chip needs to support a serial frame synchronization interface and a sampling rate of 150kHz.

[0055] Due to the limitation of DSP external interface, A / D and D / A adopt serial frame synchronization interface mode and are connected to McBSP of DSP. In addition, the clocks of A / D and D / A must be consistent, so the crystal oscillator is connected to CPLD, and two clocks of the same frequency are divided in CPLD to provide A / D and D / A respectively. CS and RD pins are chip select and read control respectively, which are enabled only when they are low. These two pins are always grounded to keep chip select and read enable. The falling edge of BUSY signal indicates that the current sampling conversion is completed, so this signal can be used as the data frame synchronization signal for DSP to read. When the falling edge of BUSY pin arrives, DSP starts to read the data currently collected by A / D. SCLK is the data reading clock provided by DSP. When BUSY, CS and RD are all low, SDOUT pin collects 16-bit data with the serial output of SCLK clock. Therefore, the A / D is a 4-wire structure, and CNVST, BUSY, SCLK and SDOUT pins are connected to FSX, FSR, CLKR and DR pins in McBSP module in DSP respectively. Schematic diagram Fig.11 shown.

[0056] Data forwarding circuit: Since the transducer needs an analog signal to drive, the digital signal processed by DSP needs to be converted into an analog signal for forwarding. The data forwarding circuit is mainly composed of a D / A chip. D / A is configured as a slave device of DSP, SCLK is the clock provided by DSP for D / A data transmission, and DSP inputs 24-bit data to D / A at this clock frequency. The schematic diagram is shown in the figure below. Fig.12 shown.

[0057] Due to quantization, the signal output by D / A is in a step-like shape, so a simple RC low-pass filter is added to the output of D / A, and a transmitter-follower circuit is added. Since the output of D / A is directly connected to the transmitter, it will cause certain interference to the digital circuit, so an isolation transformer is added after the transmitter-follower circuit. These parts are collectively referred to as the output signal adjustment circuit, and the structure is as follows Fig.13 shown.

[0058] Data storage circuit: When reading FLASH data, the CLK clock frequency is uninterrupted, but when the McBSP module in the DSP is in the clock stop mode, the CLK clock is intermittent between each frame of data. For the compatibility issue between the McBSP clock stop mode and the SPI interface, a 5-wire structure is used, and the function of the HOLD pin of FLASH is utilized to realize data transmission. In the SPI device, the HOLD pin is a waiting pin. The SPI device allows the master device to pause it during operation, that is, when the chip select CS is low, the HOLD pin is also low. At this time, FLASH is paused. When the HOLD pin becomes high, FLASH resumes operation. Therefore, when operating FLASH, you only need to input a low level to the HOLD pin in the middle of each frame of data. In this way, the clock CLK is equivalent to no interruption for FLASH, so it can work normally. The signal input to the HOLD pin is provided by the CPLD, and is mainly realized by the chip select signal provided by the DSP and the logical operation of the GPIO. The connection diagram of the data storage circuit is as follows Fig.14 shown.

[0059] Serial communication circuit: The target simulator requires two serial ports. The DSP has a total of three multi-channel buffered serial ports McBSP, which are connected to A / D, D / A, and FLASH respectively. Therefore, in order to realize the functions of the two serial ports, a serial-to-parallel conversion chip is needed. And the serial-to-parallel conversion chip supports FIFO function, which can improve the working efficiency of DSP. Since the external memory interface of DSP cannot output the chip select signal of 4 channels, the address line of the external memory interface can be used to realize the chip select of 4 channels through combinational logic. The combinational logic is implemented by CPLD, and the CPLD is used to realize the inversion of TL16C754 interrupt signal to achieve compatibility with DSP interrupt. Other address lines and data lines TL16C754 are connected to DSP accordingly. The serial-to-parallel conversion connection diagram is as follows Fig.15 shown.

[0060] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A signal processing circuit for a target simulator mounted on a UUV platform, characterized in that: include: The analog circuit adopts an analog receiver; the analog circuit includes a signal amplifying circuit, a signal filtering circuit and a gain control circuit; the signal amplifying circuit includes a primary amplifying circuit and a final amplifying circuit; the signal filtering circuit includes a fourth-order low-pass filter and a fourth-order high-pass filter; the gain control circuit is composed of a secondary amplifying circuit and an analog switch; the primary amplifying circuit is connected to the secondary amplifying circuit, the fourth-order low-pass filter, the fourth-order high-pass filter and the final amplifying circuit in sequence, and the analog switch is connected to the secondary amplifying circuit; The digital circuit includes a DSP processor, a data acquisition circuit, a data forwarding circuit, a data storage circuit, a serial communication circuit and a power conversion module; the DSP processor is respectively connected to the data acquisition circuit, the data forwarding circuit, the data storage circuit and the serial communication circuit, and the power conversion module supplies power to the signal processing circuit as a whole.

2. The signal processing circuit of the target simulator mounted on the UUV platform as claimed in claim 1, characterized in that: The primary amplifier circuit includes: a resistor R1, a resistor R4, a resistor R12, a resistor R41, a resistor R46, an operational amplifier N3A, a capacitor C1, a capacitor C3, a capacitor C10, a capacitor C11 and a capacitor C16; the in-phase input terminal of the operational amplifier N3A is connected to the grounded resistor R41 and one end of the capacitor C10, and the other end of the capacitor C10 is the INP terminal; the inverting input terminal of the operational amplifier N3A is connected to the grounded resistor R4 and one end of the resistor R12, the other end of the resistor R12 is connected to the output terminal of the operational amplifier N3A, the positive power supply terminal of the operational amplifier N3A is connected to the resistor R46, one end of the capacitor C11 and the capacitor C16, the other end of the resistor R46 is connected to the power supply +5V, and the other ends of the capacitor C11 and the capacitor C16 are grounded; the negative power supply terminal of the operational amplifier N3A is connected to the resistor R1, the capacitor C1 and one end of the capacitor C3, the other end of the resistor R1 is connected to the power supply -5V, and the other ends of the capacitor C1 and the capacitor C3 are grounded.

3. The signal processing circuit of the target simulator mounted on the UUV platform as claimed in claim 1, characterized in that: The final amplifier circuit adopts a connected reverse amplifier circuit and a first-stage emitter-follower circuit as the last stage of the analog receiver; the final amplifier circuit includes: an operational amplifier U10A, an operational amplifier U10B, a resistor R60, a resistor R72, a resistor R73, a resistor R81, a resistor R82, a capacitor C84 and a capacitor C126; the in-phase input terminal of the operational amplifier U10A is connected to the grounded resistor R82, the inverting input terminal of the operational amplifier U10A is connected to the resistor R73 and one end of the resistor R72, and the other end of the resistor R72 is connected to the operational amplifier U10A. The output end of the operational amplifier U10A and the non-inverting input end of the operational amplifier U10B; the positive power supply end of the operational amplifier U10A is connected to the resistor R81 and one end of the capacitor C126, the other end of the resistor R81 is connected to the power supply +5V, and the other end of the capacitor C126 is grounded; the negative power supply end of the operational amplifier U10A is connected to the resistor R60 and one end of the capacitor C84, the other end of the resistor R60 is connected to the power supply -5V, and the other end of the capacitor C84 is grounded; the inverting input end of the operational amplifier U10B is connected to the output end of the operational amplifier U10B.

4. The signal processing circuit of a target simulator mounted on a UUV platform as claimed in claim 1, characterized in that: The gain control circuit includes: an operational amplifier N3B, a resistor R13, a resistor R27, a resistor R42, a resistor R43, a resistor R50, a resistor R51, a capacitor C17, a capacitor C18, a capacitor C27, a capacitor C83 and an analog switch U6; the non-inverting input terminal of the operational amplifier N3B is connected to the grounded resistor R13, the inverting input terminal of the operational amplifier N3B is connected to one end of the resistor R42 and the resistor R43, the other ends of the resistor R42 and the resistor R43 are respectively connected to the NO terminal and the NC terminal of the analog switch U6, and the output terminal of the operational amplifier N3B is connected to the analog switch U6. 6, the IN terminal of the analog switch U6 is connected to CTR1, the VL terminal of the analog switch U6 is connected to the power supply +5V, the V+ terminal of the analog switch U6 is connected to the resistor R50 and one end of the capacitor C17 and the capacitor C27, the other end of the resistor R50 is connected to the power supply +5V, the other ends of the capacitors C17 and C27 are grounded, the V- terminal of the analog switch U6 is connected to the resistor R51 and one end of the capacitor C18 and the capacitor C83, the other end of the resistor R51 is connected to the power supply -5V, and the other ends of the capacitors C18 and C83 are grounded.

5. The signal processing circuit of the target simulator mounted on a UUV platform as claimed in claim 1, characterized in that: The fourth-order low-pass filter is constructed by combining two single-op-amp second-order low-pass filters; the fourth-order low-pass filter includes: op amp U7A, op amp U7B, resistor R7, resistor R15, resistor R17, resistor R36, resistor R40, resistor R44, resistor R48, resistor R49, capacitor C4, capacitor C5, capacitor C6, capacitor C8, capacitor C12, capacitor C13 and capacitor C14; the in-phase input end of the op amp U7A is connected to the grounded capacitor C12 and one end of the resistor R17, the other end of the resistor R17 is connected to one end of the resistor R15 and one end of the capacitor C5 and capacitor C6, the other ends of the capacitor C5 and capacitor C6 are connected to the output end of the op amp U7A, the resistor R36 and the resistor One end of the resistor R48, the other end of the resistor R48 is connected to the inverting input terminal of the operational amplifier U7A, the positive power supply terminal of the operational amplifier U7A is connected to the resistor R7 and the grounded capacitor C4, the other end of the resistor R7 is connected to the power supply +5V, the negative power supply terminal of the operational amplifier U7A is connected to the resistor R44 and the grounded capacitor C13, and the other end of the resistor R44 is connected to the power supply -5V; the other end of the resistor R36 is connected to the capacitor C8 and one end of the resistor R40, the other end of the resistor R40 is connected to the grounded capacitor C14 and the non-inverting input terminal of the operational amplifier U7B, the inverting input terminal of the operational amplifier U7B is connected to one end of the resistor R49, and the other end of the resistor R49 is connected to the output terminal of the operational amplifier U7B and the other end of the capacitor C8.

6. The signal processing circuit of the target simulator mounted on a UUV platform as claimed in claim 1, characterized in that: The fourth-order high-pass filter is constructed by combining two single-amp second-order high-pass filters; the fourth-order high-pass filter includes: an op amp U9A, an op amp U9B, a resistor R58, a resistor R61, a resistor R62, a resistor R74, a resistor R75, a resistor R77, a resistor R79, a resistor R83, a resistor R84, a capacitor C119, a capacitor C120, a capacitor C89, a capacitor C121, a capacitor C122 and a capacitor C124; the in-phase input end of the op amp U9A is connected to the grounded resistor R74 and one end of the capacitor C120, and the other end of the capacitor C120 is connected to one end of the capacitor C119 and the resistor R58, one end of the resistor R83, one end of the capacitor C121 and one end of the capacitor C122, one end of the resistor R61 and and the output end of the operational amplifier U9A, the other end of the resistor R83 is connected to the inverting input end of the operational amplifier U9A, the positive power supply end of the operational amplifier U9A is connected to the resistor R62 and the grounded capacitor C89, the other end of the resistor R62 is connected to the power supply +5V, the negative power supply end of the operational amplifier U7A is connected to the resistor R79 and the grounded capacitor C124, and the other end of the resistor R79 is connected to the power supply -5V; the other end of the resistor R61 is connected to one end of the resistor R84 and the output end of the operational amplifier U9B, the other end of the resistor R84 is connected to the inverting input end of the operational amplifier U9B, the other end of the capacitor C122 is connected to one end of the resistor R75 and the non-inverting input end of the operational amplifier U9B, and the other end of the resistor R75 is connected to the grounded resistor R77.

7. The signal processing circuit of the target simulator mounted on a UUV platform as claimed in claim 1, characterized in that: The data acquisition circuit is mainly composed of a 16-bit data A / D chip, which collects the analog signal of the analog receiver; the data forwarding circuit is mainly composed of a D / A chip; the A / D chip and the D / A chip adopt a serial frame synchronization interface mode, which are externally connected to the McBSP of the DSP processor, and the crystal oscillator is connected to the CPLD, and two clocks of the same frequency are separated in the CPLD and provided to the A / D chip and the D / A chip respectively. SCLK is the clock provided by the DSP processor to the D / A chip for data transmission, and the DSP processor inputs 24-bit data to the D / A chip at this clock frequency.

8. The signal processing circuit of the target simulator mounted on the UUV platform as claimed in claim 7, characterized in that: The output end of the data forwarding circuit also includes an output signal adjustment circuit, which includes: an operational amplifier U12A, an operational amplifier U12B, a resistor R87, a resistor R88, a capacitor C140, a capacitor C141, an isolation transformer L8 and an isolation transformer L9; the in-phase input end of the operational amplifier U12A is connected to one end of the resistor R87 and the grounded capacitor C140, the other end of the resistor R87 is connected to the output signal DA1 of the D / A chip, the inverting input end of the operational amplifier U12A is connected to the output end of the operational amplifier U12A and one end of the primary coil of the isolation transformer L8, the positive power supply end of the operational amplifier U12A is connected to the power supply +5V, the negative power supply end of the operational amplifier U12A is grounded, and the primary line of the isolation transformer L8 is grounded. The 2 ends of the secondary coil are grounded, the 3 ends of the secondary coil of the isolation transformer L8 are the output end DA_OUT1 of the output signal adjustment circuit, and the 4 ends of the secondary coil of the isolation transformer L8 are grounded; the in-phase input end of the operational amplifier U12B is connected to one end of the resistor R88 and the grounded capacitor C141, the other end of the resistor R88 is connected to the output signal DA2 of the D / A chip, the inverting input end of the operational amplifier U12B is connected to the output end of the operational amplifier U12B and 1 end of the primary coil of the isolation transformer L9, the 2 ends of the primary coil of the isolation transformer L9 are grounded, the 3 ends of the secondary coil of the isolation transformer L9 are the output end DA_OUT2 of the output signal adjustment circuit, and the 4 ends of the secondary coil of the isolation transformer L9 are grounded.

9. A target simulator mounted on a UUV platform, using a signal processing circuit of a target simulator mounted on a UUV platform as claimed in any one of claims 1 to 8, characterized in that: include:. UUV master control; A target simulator is connected to the UUV main control; the target simulator is composed of a transducer, an analog circuit, a transmitter and a digital circuit; wherein the transducer is composed of a receiving hydrophone, a medium-low frequency transducer and a high-frequency transducer; and the transmitter is composed of a medium-low frequency transmitter and a high-frequency transmitter; UUV battery, which provides power to the entire device; The host computer is connected to the UUV main control and the digital circuit control respectively.

Images