Display control chip, display control method and electronic equipment
By using dynamically adjustable buffer capacity and capacity-based operation decisions in the display control chip, the screen abnormality caused by tight video data cache resources is solved, and efficient cache utilization and stable video transmission are achieved.
Patent Information
- Application Number
- CN202411776815.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-04-22
AI Technical Summary
As the video data size and bit width increase, the cache storage space required by the system also increases, resulting in tight cache resources and prone to abnormal display screen problems.
A display control chip is provided that caches video data through a storage module, and determines whether to perform an operation based on the writeable and readable capacity of the buffer before writing and reading operations through the control module. The amount of data for the write and read operations is less than the amount of data for one video frame, and the capacity of the buffer may be of any size, not limited to the integer frame size.
It improves the utilization rate of cache space, occupies less resources, and ensures the stable transmission of video data, reducing the problem of abnormal display screens.
Smart Images
Figure CN119865660A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of display technology, and in particular to a display control chip, a display control method, and an electronic device. Background Art
[0002] With the rapid popularization of mobile Internet technology, people have higher and higher requirements for the smoothness of streaming media playback such as audio and video. Common display devices generally use random access memory (RAM) to cache video data to ensure normal playback of video images.
[0003] However, as the size and bit width of video data increase, the cache storage space required by the system increases, cache resources become more scarce, and problems such as display screen abnormalities are more likely to occur. Summary of the invention
[0004] In view of this, embodiments of the present application provide a display control chip, a display control method, and an electronic device.
[0005] On the one hand, an embodiment of the present application provides a display control chip, including:
[0006] A storage module, comprising a buffer for caching video data; wherein the cache space of the buffer is of any size;
[0007] A control module coupled to the storage module; the control module is configured to: perform a write operation to write the video data into the buffer; determine whether to perform the write operation based on the writable capacity of the buffer before performing each write operation; wherein the amount of data written by the write operation is less than the amount of data of one video frame; perform multiple read operations to read the video data of one video frame from the buffer; determine whether to perform the read operation of the next frame based on the readable capacity of the buffer;
[0008] The processing module is configured to determine a picture to be displayed based on the video data read by the reading operation.
[0009] In some embodiments, the control module is further configured to: set the capacity of the buffer to a non-integer multiple of the data amount of the one video frame.
[0010] In some embodiments, before performing each write operation, determining whether to perform the write operation based on the writable capacity of the buffer includes:
[0011] Before executing each write operation, determining whether the writable capacity of the buffer is greater than a first threshold; wherein the first threshold is determined based on a rate ratio of the write operation to the read operation;
[0012] When the writable capacity of the buffer is greater than the first threshold, performing the write operation;
[0013] When the writable capacity of the buffer is less than or equal to the first threshold, the video data of the video frame corresponding to the current write operation is discarded.
[0014] In some embodiments, the control module is further configured to:
[0015] After completing each of the write operations, determining whether all of the video data corresponding to the video frame has been written into the buffer;
[0016] When all the video data corresponding to the video frame has been written into the buffer, updating the reserved writing address to the current writing address;
[0017] In a case where the video data corresponding to the video frame is not all written into the buffer, determining whether the writable capacity of the buffer is greater than the first threshold;
[0018] When the writable capacity of the buffer is less than or equal to the first threshold, the video data of the video frame corresponding to the current write operation is discarded, and the current write address is updated to the reserved write address.
[0019] In some embodiments, the control module is specifically configured to: after completing the reading operation of the video data of each of the video frames, determine whether to perform the reading operation of the next frame based on the readable capacity of the buffer; wherein the amount of data read by the reading operation is less than the amount of data of one of the video frames.
[0020] In some embodiments, performing multiple read operations to read the video data of a video frame from the buffer includes:
[0021] Performing a read operation to read the video data cached in the storage space corresponding to the current read address from the buffer;
[0022] After completing the reading operation of the video data of each video frame, determining whether to continue to perform the reading operation based on the readable capacity of the buffer includes:
[0023] After completing the reading operation of the video data of each video frame, determining whether the readable capacity of the buffer is greater than a second threshold; wherein the second threshold is determined based on a rate ratio of the write operation to the read operation;
[0024] When the readable capacity of the buffer is greater than the second threshold, the reserved read address is updated to the current read address, and the next read operation is continued;
[0025] When the readable capacity of the buffer is less than or equal to the second threshold, the current read address is updated to the reserved read address to repeatedly read the video data of the current video frame.
[0026] On the other hand, an embodiment of the present application further provides a display control method, including:
[0027] Performing a write operation to write the video data into a buffer; wherein the cache space of the buffer is of any size; and the amount of data written by the write operation is less than the amount of data of a video frame;
[0028] Before executing each write operation, determining whether to execute the write operation based on the writable capacity of the buffer;
[0029] Performing multiple read operations to read the video data of a video frame from the buffer; determining whether to perform the read operation of the next frame based on the readable capacity of the buffer;
[0030] A picture to be displayed is determined based on the video data read by the reading operation.
[0031] In some embodiments, the capacity of the buffer is set to a non-integer multiple of the data amount of one of the video frames.
[0032] In some embodiments, before performing each write operation, determining whether to perform the write operation based on the writable capacity of the buffer includes:
[0033] Before executing each write operation, determining whether the writable capacity of the buffer is greater than a first threshold; wherein the first threshold is determined based on a rate ratio of the write operation to the read operation;
[0034] When the writable capacity of the buffer is greater than the first threshold, performing the write operation;
[0035] When the writable capacity of the buffer is less than or equal to the first threshold, the video data of the video frame corresponding to the current write operation is discarded.
[0036] In some embodiments, after completing each of the write operations, determining whether all of the video data corresponding to the video frame has been written into the buffer;
[0037] When all the video data corresponding to the video frame has been written into the buffer, updating the reserved writing address to the current writing address;
[0038] In a case where the video data corresponding to the video frame is not all written into the buffer, determining whether the writable capacity of the buffer is greater than the first threshold;
[0039] When the writable capacity of the buffer is less than or equal to the first threshold, the video data of the video frame corresponding to the current write operation is discarded, and the current write address is updated to the reserved write address.
[0040] In some embodiments, after completing the reading operation of the video data of each video frame, it is determined whether to perform the reading operation of the next frame based on the readable capacity of the buffer; wherein the amount of data read by the reading operation is less than the amount of data of one video frame.
[0041] In some embodiments, performing multiple read operations to read the video data of a video frame from the buffer includes:
[0042] Performing a read operation to read the video data cached in the storage space corresponding to the current read address from the buffer;
[0043] After completing the reading operation of the video data of each video frame, determining whether to continue to perform the reading operation based on the readable capacity of the buffer includes:
[0044] After completing the reading operation of the video data of each video frame, determining whether the readable capacity of the buffer is greater than a second threshold; wherein the second threshold is determined based on a rate ratio of the write operation to the read operation;
[0045] When the readable capacity of the buffer is greater than the second threshold, the reserved read address is updated to the current read address, and the next read operation is continued;
[0046] When the readable capacity of the buffer is less than or equal to the second threshold, the current read address is updated to the reserved read address to repeatedly read the video data of the current video frame.
[0047] On the other hand, an embodiment of the present application further provides an electronic device, comprising: a display control chip according to any one of the above embodiments, wherein the display control chip is used to implement access to video data.
[0048] In the embodiment of the present application, the control module determines whether to execute the write operation based on the writable capacity of the buffer before executing each write operation, and the amount of data written in each write operation is less than the amount of data of a video frame. In this way, on the one hand, the video data is continuously written in the buffer with a data amount less than one frame, so that the cache space of the buffer can be of any size and is no longer limited to the size of an integer frame, thereby improving the utilization rate of the cache space and occupying less resources; on the other hand, by judging whether the writable capacity of the buffer is sufficient to determine whether to execute the write operation, the stable transmission of the video data can be guaranteed and the problem of abnormal display screen can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0049] Figure 1 A schematic diagram of a display control chip provided in an embodiment of the present application;
[0050] Figure 2 A schematic diagram of a storage space of a storage module in a display control chip provided in an embodiment of the present application;
[0051] Figure 3 A schematic diagram of a current write address of a buffer in a display control chip provided in an embodiment of the present application;
[0052] Figure 4 A flowchart of a control module executing a write operation in a display control chip provided in an embodiment of the present application;
[0053] Figure 5 A flowchart of a control module executing a read operation in a display control chip provided in an embodiment of the present application;
[0054] Figure 6 A schematic diagram of a current read address of a buffer in a display control chip provided in an embodiment of the present application;
[0055] Figure 7 A flow chart of a display control method provided in an embodiment of the present application;
[0056] Figure 8 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0057] The following will be combined with the embodiments of the present application and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0058] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.
[0059] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0060] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.
[0061] The data access technology based on dynamic random access memory (DRAM) (hereinafter referred to as frame buffer technology) is used in multiple industries, multiple chips and multiple applications. The method is to write to DRAM based on the AXI bus, and DRAM has enough space to cache data, and then read the data through the AXI bus. In audio and video related application scenarios such as TVs, monitors, and set-top boxes, frame buffer technology is also often needed. Unlike other industries, in the application of display control chips, there are the following related application constraints: First, under normal application, any frame rate ratio can be achieved to play the picture, and the picture is normal, and there must be no abnormal frame loss, stuttering, tearing, etc.; second, when the system has an abnormality, such as bandwidth problems, timing abnormalities, etc., when the abnormality is restored, all modules such as the bus, read direct memory access (RDMA), and write direct memory access (WDMA) can be restored, and the picture is normal; third, combined with the specification requirements of different chips, for example, when the size and bit width of the video image are getting larger and larger, the system needs to use more and more caches. When the DRAM storage space is insufficient, the above application requirements can still be met.
[0062] In some embodiments, when the chip includes a smooth switching function and there is a frame delay, DRAM needs to be used for caching. At the same time, in order to ensure that the correct settings are applied to the correct video frame, at least 1 frame of data needs to be cached in the DRAM. For traditional methods, at least 2 frames need to be cached, plus the frame currently being written, the cache space needs to cache at least 3 frames of data. When the DRAM space is insufficient (such as less than 3 frames), this function will not work properly.
[0063] like Figure 1 As shown, an embodiment of the present application provides a display control chip 100, including: a storage module 110, including a buffer for caching video data; wherein the cache space of the buffer is of any size; a control module 120, coupled to the storage module 110; the control module 120 is configured to: perform a write operation to write the video data into the buffer; before performing each write operation, determine whether to perform the write operation based on the writable capacity of the buffer; wherein the amount of data written by the write operation is less than the amount of data of a video frame; perform multiple read operations to read video data of a video frame from the buffer; based on the readable capacity of the buffer, determine whether to perform a read operation for the next frame; a processing module 130, configured to: determine a picture to be displayed based on the video data read by the read operation.
[0064] In the embodiment of the present application, the display control chip 100 can be used in various display devices, including but not limited to televisions, monitors, set-top boxes, projectors, etc. The display control chip 100 includes a storage module 110 , a control module 120 and a processing module 130 . Among them, the storage module 110 can be a volatile memory, including but not limited to static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate (DDR) synchronous dynamic random access memory, enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), direct RAM bus random access memory (DRRAM), etc.; the storage module 110 can also be a non-volatile memory, including but not limited to read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM) and so on. Memory), Electrically Erasable Programmable Read-Only Memory (EEPROM), ferromagnetic random access memory (FRAM), Flash Memory, etc. Here, the storage module 110 is described as DDR.The control module 120 may include any suitable logic device, such as an application specific integrated circuit (ASIC), a DSP, a programmable logic device (PLD), a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a general processor, a controller, a microcontroller (MCU), a microprocessor, etc. Here, the control module 120 is taken as a direct memory access (DMA) controller as an example for description.
[0065] The storage module 110 can be used to cache video data and temporarily store firmware, programs, etc. to be executed by the display control chip 100. The buffer, writable capacity, and readable capacity in the storage module 110 can be referred to Figure 2 Understand. The control module 120 is used to write video data into the buffer in the storage module 110, and read video data from the buffer of the storage module 110. Specifically, for the video data corresponding to a video frame, the control module 120 can write in multiple times to write the video data of a video frame into the buffer, that is, the amount of data written in each write operation is less than the amount of data of a video frame. Before performing each write operation, the control module 120 will determine whether to perform the write operation based on the remaining writable capacity in the buffer. For example, a threshold value of the remaining storage capacity of the buffer can be set. When the writable capacity is less than the threshold value, the control module 120 will not perform the next write operation. When the writable capacity is greater than the threshold value, the control module 120 performs the next write operation. For another example, in the case where the storage space size of the buffer is constantly adjusted and changed (such as the storage resources of the entire storage module 110 are allocated in real time according to the tasks performed by the display control chip 100), a preset ratio of the writable capacity to the total capacity of the buffer can be set, and the control module 120 determines whether to perform the next write operation based on the preset ratio.
[0066] The control module 120 is also used to perform a read operation to read video data from the buffer. It should be noted that for the video data of a video frame, the control module 120 will read it multiple times, that is, the amount of data read in each read operation is less than the amount of data of a video frame. However, the control module 120 needs to completely read all the video data corresponding to an entire video frame to ensure the integrity of the displayed image and avoid problems such as screen tearing, faults, and flickering. The control module 120 will also determine whether to perform a read operation for the next frame based on the readable capacity of the buffer. The specific method for determining the readable capacity can refer to the content related to the above-mentioned write operation, which will not be repeated here.
[0067] The processing module 130 is used to determine the picture to be displayed according to the video data read by the reading operation. In some embodiments, the processing module 130 can perform certain processing on the read video data to adapt to display screens and display devices with different parameter specifications.
[0068] In this way, on the one hand, the video data is continuously written into the buffer in a data amount less than one frame, so that the cache space of the buffer can be of any size and is no longer limited to an integer frame size, thereby improving the utilization of the cache space and occupying less resources; on the other hand, by judging whether the writable capacity of the buffer is sufficient to determine whether to perform a write operation, the stable transmission of video data can be guaranteed and the problem of abnormal display images can be reduced.
[0069] In some embodiments, the control module 120 is further configured to set the capacity of the buffer to a non-integer multiple of the data volume of one video frame.
[0070] In the embodiment of the present application, since the control module 120 determines whether to perform the write operation based on the writable capacity before each write operation, the capacity of the buffer can be a non-integer frame size, and it can also ensure that the display screen is normal when the system abnormality is recovered. For example, considering the frame delay, the capacity of the buffer can be set to the size of 1.5 frames to 3 frames of video data.
[0071] In some embodiments, before performing each write operation, determining whether to perform the write operation is based on the writable capacity of the buffer, including: before performing each write operation, determining whether the writable capacity of the buffer is greater than a first threshold; wherein the first threshold is determined based on a rate ratio of write operations to read operations; performing the write operation when the writable capacity of the buffer is greater than the first threshold; and discarding video data of the video frame corresponding to the current write operation when the writable capacity of the buffer is less than or equal to the first threshold.
[0072] In the embodiment of the present application, the control module 120 compares the writable capacity of the buffer with the size of the first threshold before executing each write operation. For example, the control module 120 can implement this function through a comparator. If the writable capacity is greater than the first threshold, the control module 120 executes the write operation; if the writable capacity is less than or equal to the first threshold, the control module 120 discards (Drop) the video data of the entire video frame corresponding to this write operation. It can be understood that the discarded video data here includes the video data to be written in this write operation, the video data of the video frame corresponding to this write operation that has been written into the buffer, and the video data of the video frame corresponding to this write operation that has not been written into the buffer.
[0073] The first threshold value may be determined by the control module 120 or other modules in the display control chip 100 based on the rate ratio of the write operation to the read operation. In some embodiments, the rate ratio of the write operation to the read operation may be determined by the transmission frame rate of the input end of the display control chip and the display frame rate of the display device coupled to the display control chip. It should be noted that for different input end devices and display devices, the rate ratio of the write operation to the read operation is different, and the display control chip 100 may set different first threshold values based on different rate ratios.
[0074] In some embodiments, the control module 120 is further configured to: when the rate ratio of write operations to read operations is greater than 1, set the first threshold to be greater than a first preset value; when the rate ratio of write operations to read operations is less than 1, set the first threshold to be less than the first preset value.
[0075] In an embodiment of the present application, the reference rate ratio (e.g., 1:1) of the write operation and the read operation in the display control chip 100 can be determined based on empirical data, a large number of tests and simulations, and the first threshold value corresponding to the appropriate first preset value under the reference rate ratio is determined. That is to say, the first preset value is used as the first threshold value under the reference rate ratio to ensure the stable transmission of video data and the normal display of the screen. In this way, when the rate ratio of the write operation to the read operation is greater than the reference rate ratio (fast writing and slow reading), the control module 120 can adjust the first threshold value to be greater than the first preset value, so it is easier to trigger the discarding of video frames during the process of writing video data, so that the read operation can "keep up" with the write operation; on the contrary, when the rate ratio of the write operation to the read operation is less than the reference rate ratio (slow writing and fast reading), the control module 120 can adjust the first threshold value to be less than the first preset value.
[0076] In some embodiments, Figure 3 and Figure 4As shown, a write operation is performed to write video data into a buffer, including: performing a write operation to write the video data into a storage space corresponding to a current write address waddr in the buffer, and updating the address to be written waddr_nxt based on the current write address waddr (step S102); the control module 120 is also configured to: determine whether the address to be written waddr_nxt is greater than or equal to the end address base1 (step S103); when the address to be written waddr_nxt is greater than or equal to the end address base1, update the current write address waddr to the starting address base0 (step S104); wherein the buffer is a storage space between the starting address base0 and the end address base1; when the address to be written waddr_nxt is less than the end address base1, update the current write address waddr to the address to be written waddr_nxt (step S105).
[0077] In the examples of this application, refer to Figure 3 , the buffer of the storage module 110 includes a storage space between the starting address base0 and the ending address base1, and the write address corresponding to the write operation cycles between the starting address base0 and the ending address base1. Figure 4 , the control module 120 performs a write operation to write the video data into the storage space corresponding to the current write address waddr, and updates the address waddr_nxt to be written corresponding to the next write operation to the current write address waddr plus the burst length stride. For example, the burst length stride here can be the AXI burst length. Next, the control module 120 compares the address waddr_nxt to be written and the end address base1. If the address waddr_nxt to be written is greater than or equal to the end address base1, the current write address waddr is updated to the starting address base0, that is, the next write operation is written from the starting address base0 again; if the address waddr_nxt to be written is less than the end address base1, the current write address waddr is updated to the address waddr_nxt to be written, that is, the next write operation continues to write from the address waddr_nxt to be written.
[0078] In some embodiments, Figure 4As shown, the control module 120 is also configured to: after completing each write operation, determine whether the video data corresponding to the video frame has been completely written into the buffer (step S106); if the video data corresponding to the video frame has been completely written into the buffer, update the reserved write address waddr_keep to the current write address waddr (step S107); if the video data corresponding to the video frame has not been completely written into the buffer, determine whether the writable capacity of the buffer is greater than a first threshold (step S101); if the writable capacity of the buffer is less than or equal to the first threshold, discard the video data of the video frame corresponding to this write operation, and update the current write address waddr to the reserved write address waddr_keep (step S108).
[0079] In the embodiment of the present application, the control module 120 can also use the reserved write address waddr_keep to ensure that after discarding the written video frame data, the next write operation can continue to write from the end address corresponding to the last written video frame. Figure 4 After completing each write operation, if the control module 120 determines that all video data corresponding to a video frame have been written into the buffer, the reserved write address waddr_keep is updated to the current write address waddr, that is, the end address corresponding to the video frame after the writing is completed is recorded. If the control module 120 determines that all video data corresponding to a video frame have not been written into the buffer, it continues to determine whether the writable capacity is greater than the first threshold. In the case that the writable capacity of the buffer is less than or equal to the first threshold, the video data of the video frame corresponding to this write operation is discarded, and the current write address waddr is updated to the reserved write address waddr_keep, so that after discarding the written video frame data, the next write operation can continue to write from the end address corresponding to the last written video frame.
[0080] In some embodiments, the control module 120 is further configured to: when the writable capacity of the buffer is less than or equal to the first threshold, write the video data corresponding to the next write operation into the portion of the buffer where the video data has been cached.
[0081] In the embodiment of the present application, the control module 120 can also perform an overwrite write operation when the writable capacity is less than or equal to the first threshold. It is understandable that the display control chip 100 can perform an overwrite write operation or discard the operation of writing video frame data according to actual usage and needs. Compared with the operation of discarding the operation of writing video frame data, the overwrite write operation does not need to discard data, and only needs to change the address pointer position to perform the next write operation, and the response speed is faster.
[0082] In some embodiments, the control module 120 is specifically configured to: after completing the video data reading operation of each video frame, determine whether to perform the next frame reading operation based on the readable capacity of the buffer; wherein the amount of data read by the reading operation is less than the amount of data of a video frame.
[0083] In the embodiment of the present application, the control module 120 needs to completely read all the video data corresponding to an entire video frame to ensure the integrity of the displayed image and avoid problems such as image tearing, faulting, flickering, etc. Therefore, the control module 120 will determine whether the readable capacity is sufficient for the next reading operation only after completing the reading operation of the video data of a video frame.
[0084] In some embodiments, Figure 5 and Figure 6 As shown, multiple read operations are performed to read video data of a video frame from a buffer, including: performing a read operation to read video data cached in a storage space corresponding to a current read address raddr from the buffer (step S201); after completing the read operation of the video data of each video frame, determining whether to continue to perform the read operation based on the readable capacity of the buffer, including: after completing the read operation of the video data of each video frame, judging whether the readable capacity of the buffer is greater than a second threshold (step S206); wherein the second threshold is determined based on a rate ratio of a write operation to a read operation; when the readable capacity of the buffer is greater than the second threshold, updating the reserved read address raddr_keep to the current read address raddr, and continuing to perform the next read operation (step S207); when the readable capacity of the buffer is less than or equal to the second threshold, updating the current read address raddr to the reserved read address raddr_keep to repeatedly read the video data of the current video frame (step S208).
[0085] In the examples of this application, refer to Figure 6 , the buffer of the storage module 110 includes a storage space between the starting address base0 and the ending address base1, and the read address corresponding to the read operation cycles between the starting address base0 and the ending address base1. Specifically, Figure 5As shown, after completing the read operation of each video frame, the control module 120 compares the readable capacity of the buffer with the size of the second threshold. For example, the control module 120 can implement this function through a comparator. If the readable capacity is greater than the second threshold, the control module 120 updates the reserved read address raddr_keep to the current read address raddr, that is, records the starting address of the next video frame to be read, and performs the next read operation; if the readable capacity is less than or equal to the second threshold, the control module 120 updates the current read address raddr to the reserved read address raddr_keep, that is, reads again from the starting address of the current video frame to repeatedly read the current video frame.
[0086] The second threshold value may be determined by the control module 120 or other modules in the display control chip 100 based on the rate ratio of the write operation to the read operation. It should be noted that for different input devices and display devices, the rate ratio of the write operation to the read operation is different, and the display control chip 100 may set different second threshold values based on different rate ratios.
[0087] In some embodiments, the control module 120 is further configured to: when the rate ratio of write operations to read operations is greater than 1, set the second threshold to be less than a second preset value; when the rate ratio of write operations to read operations is less than 1, set the second threshold to be greater than the second preset value.
[0088] In the embodiment of the present application, the reference rate ratio (e.g., 1:1) of the write operation and the read operation in the display control chip 100 can be determined based on empirical data, a large number of tests and simulations, and the appropriate second preset value corresponding to the second threshold value under the reference rate ratio is determined. That is to say, the second preset value is used as the second threshold value under the reference rate ratio, which can ensure the stable transmission of video data and the normal display screen. In this way, when the rate ratio of the write operation to the read operation is less than the reference rate ratio (slow writing and fast reading), the control module 120 can adjust the second threshold value to be greater than the second preset value, so it is easier to trigger repeated reading of video frames in the process of reading video data, so as to leave more time for the write operation and leave sufficient data for the subsequent read operation; on the contrary, when the rate ratio of the write operation to the read operation is greater than the reference rate ratio (fast writing and slow reading), the control module 120 can adjust the second threshold value to be less than the second preset value.
[0089] In some embodiments, Figure 5 and Figure 6As shown, the control module 120 is also configured to: perform a read operation to read the video data cached in the storage space corresponding to the current read address raddr from the buffer, and update the address to be read raddr_nxt based on the current read address raddr (step S201); determine whether the address to be read raddr_nxt is greater than or equal to the end address base1 (step S202); when the address to be read raddr_nxt is greater than or equal to the end address base1, update the current read address raddr to the starting address base0 (step S203); wherein the buffer is the storage space between the starting address base0 and the end address base1; when the address to be read raddr_nxt is less than the end address base1, update the current read address raddr to the address to be read raddr_nxt (step S204).
[0090] In the embodiment of the present application, the read address corresponding to the read operation cycles between the starting address base0 and the ending address base1. The specific operation method can refer to the relevant embodiment of the above-mentioned write operation, which will not be repeated here.
[0091] In some embodiments, Figure 5 As shown, the control module 120 is also configured to: after completing each read operation, determine whether the video data corresponding to the video frame has been read out from the buffer in full (step S205); if the video data corresponding to the video frame has been read out from the buffer in full, determine whether the readable capacity of the buffer is greater than a second threshold value (step S206); if the video data corresponding to the video frame has not been read out from the buffer in full, continue to perform the next read operation (step S201).
[0092] In some embodiments, the control module 120 is further configured to: when the readable capacity of the buffer is less than or equal to the second threshold, suspend the next read operation and instruct the processing module 130 to perform data filling based on the read video data to determine the picture to be displayed.
[0093] In an embodiment of the present application, when the readable capacity is less than or equal to the second threshold, the processing module 130 can perform data filling based on the video data that has been read to determine the screen to be displayed corresponding to the video frame that has not been fully read. Here, data filling can be achieved through various algorithms, machine learning, deep learning, etc.
[0094] In some embodiments, the control module can configure an appropriate first threshold, a second threshold, and a total cache space of the buffer based on the rate ratio of write operations and read operations, thereby ensuring that the input and output video data are correct and stable, and ensuring that the displayed image does not have abnormal phenomena such as faults, flickering, and tearing.
[0095] Based on the same inventive concept, the embodiment of the present application also provides a display control method, such as Figure 7 As shown, the method includes:
[0096] Step S301: Before executing each write operation, determine whether to execute the write operation based on the writable capacity of the buffer;
[0097] Step S302, performing a write operation to write the video data into a buffer; wherein the cache space of the buffer is of any size; and the amount of data written by the write operation is less than the amount of data of a video frame;
[0098] Step S303, performing multiple read operations to read video data of a video frame from the buffer; based on the readable capacity of the buffer, determining whether to perform a read operation for the next frame;
[0099] Step S304: determine the picture to be displayed based on the video data read by the reading operation.
[0100] It should be understood that Figure 7 The steps shown in the operations are not exclusive, and other steps may be performed before, after, or between any steps in the operations shown.
[0101] In this way, on the one hand, the video data is continuously written into the buffer in a data amount less than one frame, so that the cache space of the buffer can be of any size and is no longer limited to an integer frame size, thereby improving the utilization of the cache space and occupying less resources; on the other hand, by judging whether the writable capacity of the buffer is sufficient to determine whether to perform a write operation, the stable transmission of video data can be guaranteed and the problem of abnormal display images can be reduced.
[0102] In some embodiments, the capacity of the buffer is set to a non-integer multiple of the data amount of one video frame.
[0103] In some embodiments, before performing each write operation, determining whether to perform the write operation is based on the writable capacity of the buffer, including: before performing each write operation, determining whether the writable capacity of the buffer is greater than a first threshold; wherein the first threshold is determined based on a rate ratio of write operations to read operations; performing the write operation when the writable capacity of the buffer is greater than the first threshold; and discarding video data of the video frame corresponding to the current write operation when the writable capacity of the buffer is less than or equal to the first threshold.
[0104] In some embodiments, the method further includes: when the rate ratio of write operation to read operation is greater than 1, setting the first threshold to be greater than a first preset value; when the rate ratio of write operation to read operation is less than 1, setting the first threshold to be less than the first preset value.
[0105] In some embodiments, a write operation is performed to write video data into a buffer, including: performing a write operation to write the video data into a storage space corresponding to a current write address in the buffer, and updating the address to be written based on the current write address; the method also includes: determining whether the address to be written is greater than or equal to a closing address; if the address to be written is greater than or equal to the closing address, updating the current write address to a starting address; wherein the buffer is a storage space between the starting address and the closing address; if the address to be written is less than the closing address, updating the current write address to the address to be written.
[0106] In some embodiments, after completing each write operation, it is determined whether the video data corresponding to the video frame has been completely written into the buffer; if the video data corresponding to the video frame has been completely written into the buffer, the reserved write address is updated to the current write address; if the video data corresponding to the video frame has not been completely written into the buffer, it is determined whether the writable capacity of the buffer is greater than a first threshold; if the writable capacity of the buffer is less than or equal to the first threshold, the video data of the video frame corresponding to this write operation is discarded, and the current write address is updated to the reserved write address.
[0107] In some embodiments, the method further includes: when the writable capacity of the buffer is less than or equal to a first threshold, writing the video data corresponding to the next write operation to a portion of the buffer where the video data has been cached.
[0108] In some embodiments, after completing the video data reading operation of each video frame, it is determined whether to perform the next frame reading operation based on the readable capacity of the buffer; wherein the amount of data read by the reading operation is less than the amount of data of one video frame.
[0109] In some embodiments, multiple read operations are performed to read video data of a video frame from a buffer, including: performing a read operation to read video data cached in a storage space corresponding to a current read address from the buffer; after completing the read operation of the video data of each video frame, determining whether to continue to perform the read operation based on the readable capacity of the buffer, including: after completing the read operation of the video data of each video frame, determining whether the readable capacity of the buffer is greater than a second threshold; wherein the second threshold is determined based on a rate ratio of write operations to read operations; in a case where the readable capacity of the buffer is greater than the second threshold, updating the reserved read address to the current read address, and continuing to perform the next read operation; in a case where the readable capacity of the buffer is less than or equal to the second threshold, updating the current read address to the reserved read address to repeatedly read the video data of the current video frame.
[0110] In some embodiments, the method further includes: when the rate ratio of write operations to read operations is greater than 1, setting the second threshold to be less than a second preset value; when the rate ratio of write operations to read operations is less than 1, setting the second threshold to be greater than the second preset value.
[0111] In some embodiments, the method further includes: performing a read operation to read video data cached in a storage space corresponding to a current read address from a buffer, and updating an address to be read based on the current read address; determining whether the address to be read is greater than or equal to a cut-off address; if the address to be read is greater than or equal to the cut-off address, updating the current read address to a starting address; wherein the buffer is a storage space between the starting address and the cut-off address; if the address to be read is less than the cut-off address, updating the current read address to the address to be read.
[0112] In some embodiments, the method further includes: after completing each read operation, determining whether the video data corresponding to the video frame has been completely read out from the buffer; if the video data corresponding to the video frame has been completely read out from the buffer, determining whether the readable capacity of the buffer is greater than a second threshold; if the video data corresponding to the video frame has not been completely read out from the buffer, continuing to perform the next read operation.
[0113] In some embodiments, the method further includes: when the readable capacity of the buffer is less than or equal to a second threshold, pausing the next read operation, and performing data filling based on the read video data to determine the picture to be displayed.
[0114] Based on the same inventive concept, the present application also provides an electronic device, such as Figure 8 As shown, it includes any display control chip in the above embodiments, and the display control chip is used to access video data. Exemplarily, the electronic device 200 includes a display control chip 100 and a display panel 201, and the display control chip 100 is used to control the display panel 201 to display a corresponding picture according to the received video data.
[0115] It should be noted that the display control chip and display control method provided in the present application can also be applied to other streaming media devices, such as caching and reading audio data frames.
[0116] The display control chip and display control method provided by the present application can ensure the correctness of data transmission and screen display under any rate ratio of write operation and read operation. For example, when the storage space of the buffer is less than or equal to 2 frames, after certain calculations and timing settings, reading and writing with arbitrary frame rate conversion can also be realized. When the storage space of the buffer is greater than 2 frames, while realizing reading and writing with arbitrary frame rate conversion, it can also support smooth switching function and greatly reduce the phenomenon of discarding and repeated reading of written data.
[0117] In addition, the display control chip and display control method provided by the present application also have the advantages of simple logic, convenient application, strong robustness, high reliability, high cache space utilization, low resource occupation, and strong self-recovery ability under various abnormal situations (such as insufficient bandwidth).
[0118] The various embodiments / implementations provided in this application can be combined with each other without causing any contradiction.
[0119] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A display control chip, characterized in that: The display control chip comprises: A storage module, comprising a buffer for caching video data; wherein the cache space of the buffer is of any size; A control module coupled to the storage module; the control module is configured to: perform a write operation to write the video data into the buffer; determine whether to perform the write operation based on the writable capacity of the buffer before performing each write operation; wherein the amount of data written by the write operation is less than the amount of data of one video frame; perform multiple read operations to read the video data of one video frame from the buffer; determine whether to perform the read operation of the next frame based on the readable capacity of the buffer; The processing module is configured to determine a picture to be displayed based on the video data read by the reading operation.
2. The display control chip according to claim 1, characterized in that: The control module is further configured to set the capacity of the buffer to a non-integer multiple of the data volume of the one video frame.
3. The display control chip according to claim 1, characterized in that: The step of determining whether to execute the write operation based on the writable capacity of the buffer before executing each write operation comprises: Before executing each write operation, determining whether the writable capacity of the buffer is greater than a first threshold; wherein the first threshold is determined based on a rate ratio of the write operation to the read operation; When the writable capacity of the buffer is greater than the first threshold, performing the write operation; When the writable capacity of the buffer is less than or equal to the first threshold, the video data of the video frame corresponding to the current write operation is discarded.
4. The display control chip according to claim 3, characterized in that: The control module is further configured to: After completing each of the write operations, determining whether all of the video data corresponding to the video frame has been written into the buffer; When all the video data corresponding to the video frame has been written into the buffer, updating the reserved writing address to the current writing address; In a case where the video data corresponding to the video frame is not all written into the buffer, determining whether the writable capacity of the buffer is greater than the first threshold; When the writable capacity of the buffer is less than or equal to the first threshold, the video data of the video frame corresponding to the current write operation is discarded, and the current write address is updated to the reserved write address.
5. The display control chip according to claim 1, characterized in that: The control module is specifically configured to: after completing the reading operation of the video data of each video frame, determine whether to perform the reading operation of the next frame based on the readable capacity of the buffer; wherein the amount of data read by the reading operation is less than the amount of data of one video frame.
6. The display control chip according to claim 5, characterized in that: The performing multiple read operations to read the video data of a video frame from the buffer includes: Performing a read operation to read the video data cached in the storage space corresponding to the current read address from the buffer; After completing the reading operation of the video data of each video frame, determining whether to continue to perform the reading operation based on the readable capacity of the buffer includes: After completing the reading operation of the video data of each video frame, determining whether the readable capacity of the buffer is greater than a second threshold; wherein the second threshold is determined based on a rate ratio of the write operation to the read operation; When the readable capacity of the buffer is greater than the second threshold, the reserved read address is updated to the current read address, and the next read operation is continued; When the readable capacity of the buffer is less than or equal to the second threshold, the current read address is updated to the reserved read address to repeatedly read the video data of the current video frame.
7. A display control method, characterized in that: The display control method comprises: Performing a write operation to write the video data into a buffer; wherein the cache space of the buffer is of any size; and the amount of data written by the write operation is less than the amount of data of a video frame; Before executing each write operation, determining whether to execute the write operation based on the writable capacity of the buffer; Performing multiple read operations to read the video data of a video frame from the buffer; determining whether to perform the read operation of the next frame based on the readable capacity of the buffer; A picture to be displayed is determined based on the video data read by the reading operation.
8. The method according to claim 7, characterized in that The method further includes: setting the capacity of the buffer to a non-integer multiple of the data volume of one video frame.
9. The method according to claim 7, characterized in that: The step of determining whether to execute the write operation based on the writable capacity of the buffer before executing each write operation comprises: Before executing each write operation, determining whether the writable capacity of the buffer is greater than a first threshold; wherein the first threshold is determined based on a rate ratio of the write operation to the read operation; When the writable capacity of the buffer is greater than the first threshold, performing the write operation; When the writable capacity of the buffer is less than or equal to the first threshold, the video data of the video frame corresponding to the current write operation is discarded.
10. The method according to claim 9, characterized in that The method further comprises: After completing each of the write operations, determining whether all of the video data corresponding to the video frame has been written into the buffer; When all the video data corresponding to the video frame has been written into the buffer, updating the reserved writing address to the current writing address; In a case where the video data corresponding to the video frame is not all written into the buffer, determining whether the writable capacity of the buffer is greater than the first threshold; When the writable capacity of the buffer is less than or equal to the first threshold, the video data of the video frame corresponding to the current write operation is discarded, and the current write address is updated to the reserved write address.
11. The method according to claim 7, characterized in that The method further comprises: After completing the reading operation of the video data of each video frame, determining whether to perform the reading operation of the next frame is performed based on the readable capacity of the buffer; wherein the amount of data read by the reading operation is less than the amount of data of one video frame.
12. The method according to claim 11, characterized in that The performing multiple read operations to read the video data of a video frame from the buffer includes: Performing a read operation to read the video data cached in the storage space corresponding to the current read address from the buffer; After completing the reading operation of the video data of each video frame, determining whether to continue to perform the reading operation based on the readable capacity of the buffer includes: After completing the reading operation of the video data of each video frame, determining whether the readable capacity of the buffer is greater than a second threshold; wherein the second threshold is determined based on a rate ratio of the write operation to the read operation; When the readable capacity of the buffer is greater than the second threshold, the reserved read address is updated to the current read address, and the next read operation is continued; When the readable capacity of the buffer is less than or equal to the second threshold, the current read address is updated to the reserved read address to repeatedly read the video data of the current video frame.
13. An electronic device, characterized in that: include: The display control chip according to any one of claims 1 to 6, wherein the display control chip is used to implement access to video data.