Complementary metal oxide semiconductor (CMOS) detector read-out device with chopping and read-out method

Abstract

The invention relates to the fields of aerospace, geological exploration, low-light detection and the like, in particular to a CMOS (complementary metal oxide semiconductor) detector reading device with chopping, which comprises a photoelectric conversion unit, a pixel reading unit and an image reading unit. The photoelectric conversion unit includes a plurality of photodiodes. The pixel reading units are in one-to-one correspondence with the photodiodes and read the pixel electric signals of the corresponding pixels. And the image reading unit reads each pixel electric signal from the plurality of pixel reading units and outputs a whole image electric signal. In the pixel read-out unit, an integral unit obtains an original electric signal from a photodiode, firstly performs chopping processing, then performs integration, and performs chopping processing on the output again. And after filtering by the filtering unit, the sampling unit performs correlated double sampling to obtain a difference voltage, and the difference voltage is output as a pixel electric signal through the output driving unit. The invention also comprises a method. Circuit noise is eliminated through chopping processing, the bandwidth range of signals capable of being processed is enlarged, and signal burrs introduced by chopping processing are eliminated through the correlated double-sampling circuit.

Description

Technical Field

[0001] The invention relates to the fields of aerospace, geological exploration and low-light detection, and in particular to a CMOS detector readout device with chopping and a readout method. Background Art

[0002] With the advancement of science and technology and the continuous development of modern society, the requirements for the detection of tiny light signals are becoming higher and higher. In recent years, CMOS image sensor technology has shown strong advantages in the field of optical sensors, and the performance and performance indicators of low-noise photodetectors have also been continuously improved. In the field of low-light detection, noise has further become a key factor restricting the improvement of photodetector performance. Therefore, it is necessary to improve the readout circuit structure and reduce circuit noise.

[0003] Modern CMOS integrated circuit technology is increasingly developing in the direction of improving the performance of digital circuits, which makes analog signal processing in digital environments have to face the challenges brought by the reduction of power supply voltage and the increase of noise voltage and offset voltage. Taking the typical 0.35μm CMOS process as an example, its operating voltage has been reduced to 3.3V, while the noise corner frequency of typical size MOS tubes is generally greater than 100k Hz, and the input offset voltage is also in the mV order. With the rapid development of integrated circuit technology, an important development trend of sensor technology is to realize the integration of sensor readout circuits, and even to realize the single-chip integration of microsensors and sensor readout circuits. For microsensors, since their output signals are mainly at the low-frequency end and the signal amplitude is very small, the increase of offset and low-frequency noise brought by CMOS technology poses a huge challenge to the design of microsensor readout circuits. The continuous development of modern society has higher and higher requirements for the detection of tiny light signals. Therefore, in the design of CMOS image sensor readout circuits, it is very important to suppress and eliminate the noise of the readout circuit and improve the signal-to-noise ratio.

[0004] The electronic noise of the device in the readout circuit can be divided into three categories according to the generation mechanism: the first is the inherent noise of the device, such as the thermal noise and 1 / f noise of the MOS tube; the second is the noise caused by the circuit structure and working mode, such as channel charge injection, clock feedthrough, KTC noise, etc.; the third is the spatial noise caused by process manufacturing errors, such as fixed pattern noise. These noises will be transmitted to the next level step by step, reducing the signal-to-noise ratio and limiting the dynamic range of the output, so noise processing is necessary for the design of the readout circuit. CTIA is one of the most widely used photodetector readout circuits. In recent years, research on CTIA noise reduction has never stopped, mainly including the processing of KTC noise and 1 / f noise. At present, the KTC noise of the readout circuit can be significantly suppressed by using the correlated double sampling technology, but the substantial reduction of 1 / f noise is more achieved by process means. Summary of the invention

[0005] The purpose of the present invention is to provide a CMOS detector readout device and a readout method with chopping, which mainly solves the problems existing in the above-mentioned prior art. It reduces the 1 / f noise of the CTIA core amplifier from the circuit aspect through the relevant principles of chopping technology, so as to further improve the signal-to-noise ratio of the readout circuit under the existing process conditions, thereby optimizing the performance indicators of the photodetector.

[0006] In order to achieve the above-mentioned object, the technical solution adopted by the present invention is to provide a CMOS detector readout device with chopping, characterized in that it comprises a photoelectric conversion unit, a pixel readout unit and an image readout unit;

[0007] The photoelectric conversion unit includes a plurality of photodiodes, each of which corresponds to a pixel; the pixel readout unit corresponds to the photodiodes one by one, and reads the pixel electrical signal corresponding to the pixel; the image readout unit reads each pixel electrical signal from the plurality of pixel readout units, and outputs the entire image electrical signal;

[0008] The pixel readout unit includes an integration unit, a filtering unit, a sampling unit and an output driving unit; the integration unit is connected to the photodiode, obtains an original electrical signal from the photodiode, performs a chopping process on the original electrical signal, and then performs an integration process on the original electrical signal to obtain an integrated output signal; the integration unit performs a chopping process on the integrated output signal again, and then performs filtering on the integrated output signal by the filtering unit, and then uses the signal as the input of the sampling unit; the sampling unit samples the difference voltage at different time points to obtain a sampling output signal, and outputs the sampled output signal as the pixel electrical signal through the output driving unit.

[0009] Further, the integration unit comprises an integration capacitor, an operational amplifier module, a bias module, an input chopping module and an output chopping module;

[0010] The integral capacitor is connected across the input and output ends of the operational amplifier module; the bias module is a current source, connected to the operational amplifier module, and provides the bias current required for the operational amplifier module during operation; the input chopping module is arranged before the input end of the operational amplifier module, and the output chopping module is arranged after the output end of the operational amplifier module, and performs chopping processing on the input signal and the integral output signal of the operational amplifier module.

[0011] Furthermore, the operational amplifier module is a capacitive transimpedance amplifier, which adopts a folded common-source and common-gate structure, and includes a common-source level sub-module and a common-gate level sub-module; the common-source level sub-module is connected to the input end, converts the input signal into an intermediate signal, and then inputs it into the common-gate level sub-module; the common-gate level sub-module forms the amplified integral output signal under the control of the intermediate signal; the input chopping module is arranged before the common-source level sub-module to perform chopping processing on the input signal; the output chopping module is arranged after the output of the common-gate level sub-module to perform chopping processing on the integral output signal.

[0012] Furthermore, the input chopping module and the output chopping module include a first input terminal, a second input terminal, a first output terminal, a second output terminal, and four groups of CMOS devices with the same channel length; the CMOS devices meet dynamic element matching conditions and are controlled by a clock signal; when the clock signal is high, the first input terminal is connected to the first output terminal, and the second input terminal is connected to the second output terminal; when the clock signal is low, the first input terminal is connected to the second output terminal, and the second input terminal is connected to the first output terminal.

[0013] Furthermore, the filtering unit is an RC low-pass filter; the cut-off frequency of the RC low-pass filter is less than the chopping frequency of the integration unit.

[0014] Further, the sampling unit is a correlated double sampling circuit, comprising a reset switch, a first sampling switch, a second sampling switch, a first sampling capacitor and a second sampling capacitor; when the reset switch is turned on, the second sampling capacitor is discharged; the first sampling switch is connected to a reference voltage, and the first sampling capacitor is charged with the reference voltage; the second sampling switch is connected to the filtering unit, and the second sampling capacitor is charged with the filtered integrated output signal; the voltage difference between the second sampling capacitor and the first sampling capacitor is used as the sampling output signal.

[0015] Further, the driving output unit is a unity gain buffer;

[0016] Furthermore, the image readout unit includes a shift register; the image readout unit is sequentially connected to different pixel readout units, reads the pixel electrical signals of different pixels, inputs them into the shift register, and is finally read out as a whole to form the entire image electrical signal.

[0017] The invention also discloses a readout method using the above-mentioned CMOS detector readout device with chopping, characterized in that it comprises the steps of:

[0018] Step S1, initializing the photoelectric conversion unit, the pixel readout unit and the image readout unit;

[0019] Step S2, the photoelectric conversion unit transmits the original electrical signal to the pixel readout unit;

[0020] Step S3, each of the pixel readout units outputs a single pixel electrical signal;

[0021] Step S4, the image readout unit reads each pixel electrical signal from the plurality of pixel readout units in sequence, and outputs the entire image electrical signal after splicing; if the next frame of image needs to be generated, jump to step S3.

[0022] Furthermore, in step S3, the steps are included:

[0023] Step S31, resetting the integration unit and the sampling unit;

[0024] Step S32, the sampling unit starts working and performs the first sampling on the reference voltage;

[0025] Step S33, the integration unit starts to work and chops the original electrical signal;

[0026] Step S34, the integration unit outputs an integration output signal;

[0027] Step S35, the integration unit chops the integration output signal;

[0028] Step S36, using the filtering unit to perform low-pass filtering on the integrated output signal;

[0029] Step S37, the sampling unit performs a second sampling on the filtered integrated output signal;

[0030] Step S38: the sampling unit outputs the pixel electrical signal.

[0031] In view of the above technical features, compared with the prior art, the present invention has the following notable features:

[0032] 1. The input chopping module and the output chopping module in the CMOS detector readout device with chopping of the present invention adopt the method of low-resistance node chopping and dynamic element matching, which can increase the bandwidth range of the processable signal without significantly deteriorating the input equivalent offset voltage.

[0033] 2. The output of the integration unit with chopping processing function in the CMOS detector with chopping of the present invention is optimized as a single-ended output circuit. When the common-mode output level of the circuit is offset, the change of the branch current can be affected by the change of the self-bias voltage, thereby forming a negative feedback effect on the common-mode output level, without the need to design an additional common-mode feedback circuit.

[0034] 3. The two choppers in the output chopper module of the integration unit with chopping processing function in the CMOS detector with chopping of the present invention dynamically switch the two PMOS tubes in the current mirror of the operational amplifier module, and use the dynamic element matching method to further reduce the current mismatch of the current mirror.

[0035] 4. The sampling unit in the CMOS detector readout device with chopping of the present invention can eliminate the correlated noise of the circuit and the voltage glitches introduced by the preceding input chopping module and the output chopping module in the chopping process at the same time through the timing design of the correlated double sampling circuit.

[0036] 5. The sampling unit in the CMOS detector readout device with chopping of the present invention uses two simple capacitors as sampling circuits to obtain the differential integrated voltage at two time points, eliminating the need for a subtractor and saving layout area.

[0037] 6. The design of the CMOS detector readout device with chopping in the present invention is manufactured using a 5V 0.5mm standard CMOS process, which is a mature manufacturing process, thus facilitating on-chip integrated design. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a system block diagram of a preferred embodiment of the CMOS detector readout device with chopping of the present invention;

[0039] Figure 2 It is a system block diagram of a pixel readout unit in a preferred embodiment of a CMOS detector readout device with chopping according to the present invention;

[0040] Figure 3 It is a circuit diagram of an integration unit and a filtering unit in a preferred embodiment of a CMOS detector readout device with chopping of the present invention;

[0041] Figure 4 It is a circuit diagram of an input chopping module and an output chopping module in an integration unit in a preferred embodiment of a CMOS detector readout device with chopping of the present invention;

[0042] Figure 5 It is a circuit diagram of a sampling unit in a preferred embodiment of a CMOS detector readout device with chopping according to the present invention;

[0043] Figure 6 It is a working timing diagram of a preferred embodiment of the CMOS detector readout device with chopping of the present invention;

[0044] Figure 7 is a method flow chart of a preferred embodiment of a readout method using a CMOS detector readout device with chopping according to the present invention;

[0045] Figure 8 It is a flow chart of a method for converting pixel electrical signals by a pixel readout unit in a preferred embodiment of a readout method using a CMOS detector readout device with chopping in the present invention.

[0046] In the figure: 100-photoelectric conversion unit, 200-pixel readout unit, 300-image readout unit;

[0047] 101-photodiode;

[0048] 210-integrating unit, 220-filtering unit, 230-sampling unit, 240-output driving unit;

[0049] 211 - integration capacitor, 212 - operational amplifier module, 213 - bias module, 214 - input chopping module, 215 - output chopping module. DETAILED DESCRIPTION

[0050] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0051] See also Figures 1 to 5 The present invention discloses a CMOS detector readout device with chopping. As shown in the figure, a preferred embodiment thereof includes a photoelectric conversion unit 100, a pixel readout unit 200 and an image readout unit 300.

[0052] Among them, the photoelectric conversion unit 100 is used to convert the optical signal into an electrical signal, and it is composed of a plurality of photodiodes 101. Each photodiode 101 corresponds to a pixel. The electrical signals of all the photodiodes 101 are spliced ​​together to form a photoelectric conversion image. The pixel readout unit 200 corresponds to the photodiode 101 one by one, reads the original electrical signal of a single photodiode 101, and obtains the pixel electrical signal after processing. The image readout unit 300 is responsible for sequentially obtaining the pixel electrical signal corresponding to each pixel from all the pixel readout units 200, and splicing it into an image electrical signal corresponding to the complete image. The key component in the image readout unit 300 is the shift register, which controls the bus switch to read out each pixel one by one. Under the control of the shift register, the image readout unit 300 is sequentially connected to each pixel readout unit 200, and the pixel electrical signal corresponding to each pixel is stored in the shift register. Before reading in a new pixel electrical signal each time, the pixel electrical signal that has been read out is shifted, thereby leaving space to store the new pixel electrical signal. Finally, all pixel electrical signals are read out from the shift register in full at one time to obtain the electrical signals of the entire image.

[0053] In the present invention, the structure of the pixel readout unit 200 is mainly optimized. The pixel readout unit 200 is composed of an integration unit 210, a filtering unit 220, a sampling unit 230 and an output driving unit 240. The integration unit 210 is connected to the photodiode 101 (PD), obtains the original electrical signal from the photodiode 101 (PD), integrates the original electrical signal, and obtains an integrated output signal. At the input and output ends of the integration unit 210, the signal input to the integration unit 210 and the signal output from the integration unit 210 are both chopped. In this way, the original electrical signal undergoes two chopping processes when entering and exiting the integration unit 210, and the frequency jumps back to the original low-frequency band. However, the noise signal generated inside the integration unit 210 is only chopped once at the output end and is switched to the high-frequency band. Therefore, the filtering unit 220 connected after the integration unit 210 is used to filter out the electrical signal in the high-frequency band, thereby removing the noise signal generated inside the integration unit 210, and only outputting the integrated output signal generated based on the original electrical signal. The integrated output signal after filtering by the filter unit 220 is input to the sampling unit 230. The filter unit 220 is a resistor-capacitor low-pass filter, which is composed of C1 and R1. Its cut-off frequency is less than the chopping frequency of the chopping process in the integration unit 210, so that the high-frequency signal that has only undergone one chopping can be filtered out. In the filter unit 220, a compensation capacitor C2 is also set, and the size is 1pF. The purpose of the sampling unit 230 is to sample and hold. It reads and holds the integrated output signal according to the preset sampling frequency, so that the image readout unit 300 can read the output of all pixel readout units 200 in succession within a period of time. The sampling unit 230 itself obtains the sampled output signal by sampling the difference voltage at different time points, thereby further eliminating the signal offset inherent in the system. The output signal of the sampling unit 230 is amplified by the output drive unit 240 and used as the pixel electrical signal of the current sampling unit 230. The specific implementation of the drive output unit 240 is a unit gain buffer, which can realize lossless difference signal reading.

[0054] The integration unit 210 is composed of an integration capacitor 211, an operational amplifier module 212, a bias module 213, an input chopping module 214 and an output chopping module 215. The core component of the integration unit 210 is the operational amplifier module 212, which is a capacitive transimpedance amplifier and adopts a folded common source and common gate structure. The operational amplifier module 212 and the integration capacitor 211 are combined, that is, the integration capacitor 211 is connected between the input and output ends of the operational amplifier module 212, so as to complete the voltage integration operation using the electrical characteristics of the integration capacitor itself. The integration capacitor 211 is Cint, and its size is 500fF. The integration starting voltage is provided by a voltage source Vdc, which is connected to the input of the integration unit 210 and is set to 1V. The normal operation of the operational amplifier module 212 requires external bias current. The bias module 213 is a module that completes this work. It is a current source, which is composed of MOS tubes PM6, PM7, PM8, NM5, NM6, NM7, NM8 and NM9. Its output is connected to the operational amplifier module 212 to provide the bias current required for the operational amplifier module 212 to work. The input chopping module 214 and the output chopping module 215 are newly added designs of the present invention, which are used to filter the internal thermal noise of the operational amplifier module 212. The input chopping module 214 is arranged before the input end of the operational amplifier module 212, and the output chopping module 215 is arranged after the output end of the operational amplifier module 212. The input chopping module 214 performs chopping processing on all input signals (original electrical signals), and the output chopping module 215 performs chopping processing on all output signals (processed original electrical signals and noise signals).

[0055] The operational amplifier module 212 is further subdivided into a common source submodule and a common gate submodule. The common source submodule is composed of MOS tubes PM1, PM2, and PM3. Among them, PM1 and PM2 are connected to the input end to convert the input signal into an intermediate signal. The common gate submodule is composed of MOS tubes PM4, PM5, NM1, NM2, NM3, and NM4. The common gate submodule is controlled by the intermediate signal output by PM1 and PM2, and its output is the amplified integral output signal. The output of the input chopping module is connected to the gates of PM1 and PM2 in the common source submodule to complete the chopping process of the input signal. There are two output chopping modules, which are respectively connected to the source and drain of NM1 and NM2 in the common gate submodule to chop the integral output signal. The integration unit 210 includes a reset switch reset. When the switch reset is closed, Cint is short-circuited and the charge is reset, which is the initial stage of the integration unit 210. When the switch reset is disconnected, the integration unit 210 starts to work, and the current generated by the photodiode 101 (PD) causes the charge to be accumulated on Cint, generating a linearly rising voltage at the output end, which is output to the next stage sampling unit 230 after passing through the filtering unit 220 (low-pass filtering structure).

[0056] The input chopping module 214 and the output chopping module 215 have the same internal structure, including a first input terminal INP, a second input terminal INN, a first output terminal OP, and a second output terminal ON, and four groups of CMOS devices with the same channel length. Among them, the ratio of the PMOS channel width to the NMOS channel width is 2.5 to 1. The CMOS device meets the dynamic element matching condition and is controlled by paired clock signals clk and clkb. Clk and clkb are opposite square wave signals, with a high level of 5V, a low level of 0V, a duty cycle of 50%, and a cycle of 40kHz. When the clock signal clk is high, the first input terminal INP and the first output terminal OP are turned on, and the second input terminal INN and the second output terminal ON are turned on. When the clock signal clk is low, the first input terminal INP is connected to the second output terminal ON, and the second input terminal INN is connected to the first output terminal OP. The principle of chopping is that when the signal passes through the input chopping module 214 or the output chopping module 215, a 40kHz frequency domain modulation is achieved. For the integration unit 210, the input voltage signal will be chopped by an even number of times (twice), and the low-frequency noise (1 / f noise) generated by the self circuit will be chopped by an odd number of times (once). According to the principle of chopper frequency modulation, the signal chopped by an even number of times will return to the base frequency, but the signal chopped by an odd number of times will be at a high frequency (40kHz). Therefore, the signal and the noise are separated in the frequency domain. After low-frequency filtering by the filtering unit 220, the noise at the high frequency is filtered out to achieve a noise reduction effect.

[0057] The sampling unit 230 is a correlated double sampling circuit, which samples the difference voltage at two time points on the integral curve to achieve FPN noise removal. It includes a first sampling switch S1, a second sampling switch S2, a reset switch S3, a first sampling capacitor C1 and a second sampling capacitor C2. The structure is simple and easy to control. A unit gain buffer is connected at the back to achieve lossless difference signal readout. The first sampling switch S1, the second sampling switch S2 and the reset switch S3 operate in a certain timing sequence to complete the double sampling and holding action. When the reset switch S3 is turned on, the second sampling capacitor C1 is discharged. The first sampling switch S1 is connected to the reference voltage Vref, and the reference voltage Vref is used to charge the first sampling capacitor C1. The input IN end of the second sampling switch S2 is connected to the filtering unit 220, and the filtered integral output signal is read to charge the second sampling capacitor C2.

[0058] Please Figures 1 to 5 Based on the combination Figure 6As shown in the figure, a preferred embodiment of a CMOS detector readout device with chopping of the present invention realizes the integration, sampling and noise reduction of the signal within one sampling cycle by controlling the timing of the operational amplifier module 212, the input chopping module 214, the output chopping module 215 and the sampling unit 230 in the integration unit 210, and obtains a low-noise voltage output result. Specifically, the Choppr signal is the clock signal of the input chopping module 214 and the output chopping module 215, which changes with a cycle of 25 microseconds (40kHz). The integration unit 210 enters the working state after being reset by the CTIA_reset signal. The sampling unit 230 is reset under the control of CDS_reset. In the sampling unit 230, the CDS1 signal controls the first sampling switch S1, the CDS2 signal controls the second sampling switch S2, and the CDS_reset signal controls the reset switch S3. The reset signal CDS_reset first turns on the reset switch S3, then uses the first sampling switch S1 to turn on Vref for the first sampling, and then uses the second sampling switch S2 to sample the integrated output signal. After the first sampling switch S1 and the second sampling switch S2 are turned on together for a period of time, the voltage difference between the second sampling capacitor C2 and the first sampling capacitor C1 is obtained as the sampling output signal of the sampling unit 230. DFF_clk is used to control the shift register action in the image readout unit 300, and the cycle is 80 microseconds. DFF_in varies according to the different pixel electrical signals.

[0059] The noise measurement results of this embodiment are as follows. At a chopping frequency of 40 kHz, the output noise of the integration unit with chopping is 87.9 μVrms. In comparison, the output noise of the chopper-free CTIA with the same process is 158.6 μVrms. The introduction of chopping technology reduces the RMS noise of the chip test by 44.58%.

[0060] See also Figure 7 The present invention also discloses a readout method using the above-mentioned CMOS detector readout device with chopping, a preferred embodiment of which comprises the steps of:

[0061] Step S100, initializing a CMOS detector readout device with chopping.

[0062] After the device is powered on, the photoelectric conversion unit, the pixel readout unit and the image readout unit complete initialization under the action of the synchronization signal.

[0063] Step S200: the photoelectric conversion unit samples the optical signal.

[0064] The photodiodes in the photoelectric conversion unit generate original electrical signals under the stimulation of the light signal. Each photodiode transmits the original electrical signal it generates to the corresponding pixel readout unit.

[0065] In step S300 , the pixel readout unit generates a pixel electrical signal.

[0066] Each pixel readout unit generates a pixel electrical signal based on the original electrical signal. Before each new pixel electrical signal is generated, the pixel readout unit is reset once to clear the pixel electrical signal outputted last time.

[0067] Step S400: the image reading unit outputs the entire image electrical signal.

[0068] The image readout unit uses a shift register to sequentially read pixel electrical signals from each pixel readout unit constituting the entire image, and outputs the entire image electrical signal after sequential splicing as an output of one frame. If the next frame of image needs to be generated, jump to step S300.

[0069] See also Figure 8 In the above-mentioned readout method using the CMOS detector readout device with chopping, when the pixel readout unit generates the pixel electrical signal (i.e., in step 300), the sub-steps are included:

[0070] Step S301, the pixel readout unit is reset.

[0071] Before generating a new pixel electrical signal each time, the integration unit and the sampling unit are reset.

[0072] Step S302: the sampling unit performs sampling for the first time.

[0073] The sampling unit performs the first sampling in the double sampling process with respect to the reference voltage.

[0074] Step S303: the integration unit processes the input signal.

[0075] The integration unit performs chopping processing on the read original electrical signal at its input end.

[0076] Step S304: the integration unit completes the integration operation.

[0077] The integration unit utilizes the integration unit and the operational amplifier module to perform integration operation on the original electrical signal and form an integrated output signal.

[0078] Step S305: the integration unit processes the output signal.

[0079] The integration unit performs chopping processing on the integrated output signal, thereby returning the information from the original electrical signal to the base frequency through an even number of chopping, while the internally generated noise signal is moved to a high frequency by an odd number of chopping.

[0080] Step S306, filtering out high frequency noise signals.

[0081] The filtering unit uses a low-pass RC filter to perform low-pass filtering on the integrated output signal, thereby filtering out high-frequency noise signals.

[0082] Step S307: the sampling unit performs sampling for the second time.

[0083] The sampling unit performs the second sampling in the double sampling process on the filtered integrated output signal.

[0084] Step S308: the sampling unit outputs the pixel electrical signal.

[0085] After the double sampling is completed, the sampling unit subtracts the voltages of the two samples and outputs a pixel electrical signal.

[0086] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A CMOS detector readout device with chopping, characterized in that: It includes a photoelectric conversion unit, a pixel readout unit and an image readout unit; The photoelectric conversion unit includes a plurality of photodiodes, each of which corresponds to a pixel; the pixel readout unit corresponds to the photodiodes one by one, and reads the pixel electrical signal corresponding to the pixel; the image readout unit reads each pixel electrical signal from the plurality of pixel readout units, and outputs the entire image electrical signal; The pixel readout unit comprises an integration unit, a filtering unit, a sampling unit and an output driving unit; The integration unit is connected to the photodiode, obtains the original electrical signal from the photodiode, performs chopping processing on the original electrical signal and then performs integration processing to obtain an integrated output signal; the integration unit performs chopping processing on the integrated output signal again, and then filters it through the filtering unit as the input of the sampling unit; the sampling unit samples the difference voltage at different time points to obtain a sampling output signal, and outputs it as the pixel electrical signal through the output driving unit.

2. The CMOS detector readout device with chopping as claimed in claim 1, characterized in that: The integration unit comprises an integration capacitor, an operational amplifier module, a bias module, an input chopping module and an output chopping module; The integral capacitor is connected across the input and output ends of the operational amplifier module; the bias module is a current source, connected to the operational amplifier module, and provides the bias current required for the operational amplifier module during operation; the input chopping module is arranged before the input end of the operational amplifier module, and the output chopping module is arranged after the output end of the operational amplifier module, and performs chopping processing on the input signal and the integral output signal of the operational amplifier module.

3. The CMOS detector readout device with chopping as claimed in claim 2, characterized in that: The operational amplifier module is a capacitive transimpedance amplifier, which adopts a folded common-source and common-gate structure and includes a common-source submodule and a common-gate submodule; the common-source submodule is connected to the input end, and after converting the input signal into an intermediate signal, the intermediate signal is input into the common-gate submodule; The common-gate submodule forms the amplified integral output signal under the control of the intermediate signal; the input chopping module is arranged before the common-source submodule to perform chopping processing on the input signal; the output chopping module is arranged after the output of the common-gate submodule to perform chopping processing on the integral output signal.

4. The CMOS detector readout device with chopping as claimed in claim 2, characterized in that: The input chopping module and the output chopping module include a first input terminal, a second input terminal, a first output terminal, a second output terminal, and four groups of CMOS devices with the same channel length; the CMOS devices meet the dynamic element matching conditions and are controlled by a clock signal; when the clock signal is high, the first input terminal is connected to the first output terminal, and the second input terminal is connected to the second output terminal; When the clock signal is low, the first input terminal is connected to the second output terminal, and the second input terminal is connected to the first output terminal.

5. The CMOS detector readout device with chopping as claimed in claim 1, characterized in that: The filtering unit is an RC low-pass filter; the cut-off frequency of the RC low-pass filter is less than the chopping frequency of the integration unit.

6. The CMOS detector readout device with chopping as claimed in claim 1, characterized in that: The sampling unit is a correlated double sampling circuit, comprising a reset switch, a first sampling switch, a second sampling switch, a first sampling capacitor and a second sampling capacitor; when the reset switch is turned on, the second sampling capacitor is discharged; the first sampling switch is connected to a reference voltage, and the first sampling capacitor is charged with the reference voltage; the second sampling switch is connected to the filtering unit, and the second sampling capacitor is charged with the filtered integrated output signal; the voltage difference between the second sampling capacitor and the first sampling capacitor is used as the sampling output signal.

7. The CMOS detector readout device with chopping as claimed in claim 1, characterized in that: The driving output unit is a unity gain buffer.

8. The CMOS detector readout device with chopping as claimed in claim 1, characterized in that: The image readout unit comprises a shift register; the image readout unit is sequentially connected to different pixel readout units, reads the pixel electrical signals of different pixels, inputs them into the shift register, and is finally read out as a whole to form the entire image electrical signal.

9. A readout method using the CMOS detector readout device with chopping as claimed in claim 1, characterized in that: Contains steps: Step S1, initializing the photoelectric conversion unit, the pixel readout unit and the image readout unit; Step S2, the photoelectric conversion unit transmits the original electrical signal to the pixel readout unit; Step S3, each of the pixel readout units outputs a single pixel electrical signal; Step S4, the image readout unit reads each pixel electrical signal from the plurality of pixel readout units in sequence, and outputs the entire image electrical signal after splicing; if the next frame of image needs to be generated, jump to step S3.

10. The readout method using a CMOS detector readout device with chopping as claimed in claim 9, characterized in that: In step S3, the steps are included: Step S31, resetting the integration unit and the sampling unit; Step S32, the sampling unit starts working and performs the first sampling on the reference voltage; Step S33, the integration unit starts to work and chops the original electrical signal; Step S34, the integration unit outputs an integration output signal; Step S35, the integration unit chops the integration output signal; Step S36, using the filtering unit to perform low-pass filtering on the integrated output signal; Step S37, the sampling unit performs a second sampling on the filtered integrated output signal; Step S38: the sampling unit outputs the pixel electrical signal.

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