Preparation method of ferroelectric memory

Abstract

The present disclosure provides a method for preparing a ferroelectric memory, comprising epitaxially growing a water-soluble sacrificial layer, a first ferroelectric layer, a conductive layer, and a second ferroelectric layer on a first substrate in sequence; bonding an adhesion layer to a supporting layer, and adhering the supporting layer to the second ferroelectric layer via the adhesion layer to obtain a first composite structure; immersing the first composite structure in deionized water to remove the water-soluble sacrificial layer and the first substrate to obtain a second composite structure; transferring the second composite structure so that the first ferroelectric layer contacts a metal layer of a transistor, and immersing the second composite structure in a first organic solvent to remove the adhesion layer and the supporting layer, thereby exposing the second ferroelectric layer; and preparing a connecting electrode on the second ferroelectric layer, and connecting the connecting electrode through the second ferroelectric layer to the conductive layer to obtain a ferroelectric memory.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor memory, and more particularly, to a method for preparing a ferroelectric memory. Background Art

[0002] With the advent of the era of artificial intelligence and big data, the "memory wall" problem in semiconductor memory integrated circuits urgently needs to be addressed. Ferroelectric memory, with its advantages such as a wide operating temperature range, fast read / write speeds, fatigue resistance, low power consumption, and radiation resistance, has attracted widespread attention. Ferroelectric memory stores data based on the orientation of electric domains in ferroelectric thin films. Under the influence of an external electric field or force field, the flipping of these domains enables the conversion of binary "1" and "0" data. Currently, ferroelectric memory comes in three main forms: ferroelectric random access memory (FeRAM), ferroelectric field-effect transistors (FeFETs), and ferroelectric tunnel junctions (FTJs).

[0003] The primary advantage of ferroelectric random access memory (FeRAM) lies in its compatibility with mature CMOS processes. However, its destructive charge-based readout makes scaling difficult. Ferroelectric field-effect transistors (FeFETs) offer a nondestructive resistive readout method, but suffer from poor stability. Ferroelectric tunnel junctions (FTJs) offer advantages such as high-density data storage, lossless readout, fast read / write speeds, and low energy consumption. However, the primary challenge lies in integrating epitaxial single-crystal oxide ferroelectric tunnel junction devices with silicon-based circuits. Summary of the Invention

[0004] To solve at least one of the technical problems in the prior art, an embodiment of the present disclosure provides a method for preparing a ferroelectric memory, which can accurately transfer a second composite structure to a metal layer of a transistor.

[0005] An embodiment of the present disclosure provides a method for preparing a ferroelectric memory, comprising: epitaxially growing a water-soluble sacrificial layer, a first ferroelectric layer, a conductive layer, and a second ferroelectric layer on a first substrate in sequence; bonding an adhesion layer to a supporting layer, and adhering the supporting layer to the second ferroelectric layer through the adhesion layer to obtain a first composite structure; immersing the first composite structure in deionized water to remove the water-soluble sacrificial layer and the first substrate to obtain a second composite structure; transferring the second composite structure so that the first ferroelectric layer contacts the metal layer of the transistor, and immersing the second composite structure in a first organic solvent to remove the adhesion layer and the supporting layer, thereby exposing the second ferroelectric layer; preparing a connecting electrode on the second ferroelectric layer, and connecting the connecting electrode through the second ferroelectric layer to the conductive layer to obtain the ferroelectric memory.

[0006] According to some embodiments of the present disclosure, before sequentially epitaxially growing a water-soluble sacrificial layer, a first ferroelectric layer, a conductive layer, and a second ferroelectric layer on a first substrate, the method includes: cleaning the surface of the first substrate with a second organic solvent; etching the cleaned first substrate, and annealing the substrate in an oxygen pressure environment, so that an atomic-level step surface is formed on the surface of the first substrate.

[0007] According to some embodiments of the present disclosure, in the above annealing process, the annealing temperature is 900° C. to 1000° C., and the annealing time is 30 min to 60 min.

[0008] According to some embodiments of the present disclosure, the material of the water-soluble sacrificial layer is strontium aluminate; the materials of the first ferroelectric layer and the second ferroelectric layer are any one of the following: barium titanate, bismuth ferrite and lead zirconate titanate; the material of the conductive layer is any one of the following: lanthanum strontium manganese oxide, strontium ruthenate, lanthanum strontium cobalt oxide and lanthanum calcium manganese oxide.

[0009] According to some embodiments of the present disclosure, the water-soluble sacrificial layer, the first ferroelectric layer, the conductive layer and the second ferroelectric layer are epitaxially grown in sequence on the first substrate through a pulsed laser deposition process.

[0010] According to some embodiments of the present disclosure, the growth conditions of the water-soluble sacrificial layer are as follows: the growth temperature of the water-soluble sacrificial layer is 700°C to 750°C, the oxygen pressure is 1×10 -6 Torr~5×10 -5 Torr, the energy density of the laser is 1.2 J / cm 2 ~2.2J / cm 2 , the laser frequency is 1Hz~5Hz.

[0011] According to some embodiments of the present disclosure, the growth conditions of the first ferroelectric layer and the second ferroelectric layer are as follows: the growth temperature of the first ferroelectric layer and the second ferroelectric layer is 650° C. to 750° C., the oxygen pressure is 1×10 -4 Torr ~1×10 -2 Torr, the energy density of the laser is 0.3J / cm 2 ~1.2J / cm 2 , the laser frequency is 1Hz~5Hz.

[0012] According to some embodiments of the present disclosure, the growth conditions of the conductive layer are as follows: the growth temperature of the conductive layer is 650°C to 750°C, the oxygen pressure is 1×10 -5 Torr~1×10 -2 Torr, the energy density of the laser is 0.3J / cm 2 ~0.8J / cm 2, the laser frequency is 1Hz~5Hz.

[0013] According to some embodiments of the present disclosure, the above-mentioned bonding of the adhesive layer to the support layer includes: adhering the above-mentioned adhesive layer to the surface of the above-mentioned support layer to obtain a flexible support structure; placing the above-mentioned flexible support structure in a temperature environment of 90°C for treatment to enhance the adhesion between the above-mentioned adhesive layer and the above-mentioned support layer.

[0014] According to some embodiments of the present disclosure, the above-mentioned transistor is prepared by the following steps: patterning the single crystal silicon on the surface of the second substrate; preparing a drain and a source on both sides of the patterned single crystal silicon; growing a first dielectric layer on the patterned single crystal silicon, the drain and the source; preparing a gate on the first dielectric layer and above the patterned single crystal silicon; growing a second dielectric layer on the gate and the first dielectric layer; etching the first dielectric layer and the second dielectric layer to form a through hole above the source; depositing metal on the second dielectric layer and in the through hole, and patterning the metal to form the metal layer.

[0015] According to a method for preparing a ferroelectric memory according to an embodiment of the present disclosure, a water-soluble sacrificial layer, a first ferroelectric layer, a conductive layer and a second ferroelectric layer are epitaxially grown in sequence on a first substrate, an adhesion layer is bonded to a supporting layer, and the supporting layer is adhered to the second ferroelectric layer through the adhesion layer to obtain a first composite structure, the first composite structure is immersed in deionized water, and the water-soluble sacrificial layer and the first substrate are removed in a water-soluble manner to obtain a second composite structure. Compared with the method of etching the sacrificial layer using an acidic or alkaline solution, the second composite structure has the advantages of safety, environmental protection, low cost and simple operation. The second composite structure is transferred so that the first ferroelectric layer contacts the metal layer of the transistor and is immersed in a first organic solvent, the adhesion layer and the supporting layer are removed to expose the second ferroelectric layer, a connecting electrode is prepared on the second ferroelectric layer, and the connecting electrode is connected to the conductive layer through the second ferroelectric layer to obtain a ferroelectric memory. The preparation method of the ferroelectric memory can accurately transfer the second composite structure to the metal layer of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a flow chart of a method for preparing a ferroelectric memory according to an exemplary embodiment of the present disclosure;

[0017] Figure 2 is a schematic diagram of a manufacturing process of a ferroelectric memory according to an exemplary embodiment of the present disclosure;

[0018] Figure 3 is a circuit diagram of a ferroelectric memory according to an exemplary embodiment of the present disclosure;

[0019] Figure 4 is a pictorial diagram of a ferroelectric memory according to an exemplary embodiment of the present disclosure;

[0020] Figure 5 is a flow chart of a method for manufacturing a transistor according to an exemplary embodiment of the present disclosure;

[0021] Figure 6 Schematic diagram of a transistor manufacturing process according to an exemplary embodiment of the present disclosure.

[0022] In the drawings, the meanings of the reference numerals are as follows:

[0023] 100. Ferroelectric memory;

[0024] 1. a first substrate;

[0025] 2. Water-soluble sacrificial layer;

[0026] 3. First ferroelectric layer;

[0027] 4. Conductive layer;

[0028] 5. Second ferroelectric layer;

[0029] 6. Adhesion layer;

[0030] 7. Support layer;

[0031] 8. Metal layer;

[0032] 9. Connect the electrodes;

[0033] 10. Back bottom;

[0034] 11. Insulation layer;

[0035] 12. Monocrystalline silicon;

[0036] 13. Drain;

[0037] 14. Source;

[0038] 15. First dielectric layer;

[0039] 16. Gate;

[0040] 17. Second dielectric layer;

[0041] 18. Through hole. DETAILED DESCRIPTION

[0042] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0043] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0044] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0045] When expressions such as “at least one of A, B, and C, etc.” are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, “a system having at least one of A, B, and C” should include but is not limited to systems having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, and C, etc.). When expressions such as “at least one of A, B, or C, etc.” are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, “a system having at least one of A, B, or C” should include but is not limited to systems having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, and C, etc.).

[0046] In order to solve the problem of integration of epitaxial single crystal oxide ferroelectric tunnel junction devices and silicon-based circuits, according to the inventive concept of one aspect of the present disclosure, a water-soluble sacrificial layer, a first ferroelectric layer, a conductive layer and a second ferroelectric layer are epitaxially grown in sequence on a first substrate, an adhesion layer is bonded to a supporting layer, and the supporting layer is adhered to the second ferroelectric layer through the adhesion layer to obtain a first composite structure, the first composite structure is immersed in deionized water, and the water-soluble sacrificial layer and the first substrate are removed in a water-soluble manner to obtain a second composite structure. Compared with the method of etching the sacrificial layer using an acidic or alkaline solution, the second composite structure has the advantages of safety, environmental protection, low cost and simple operation. The second composite structure is transferred so that the first ferroelectric layer contacts the metal layer of the transistor and is immersed in a first organic solvent. The adhesion layer and the supporting layer are removed to expose the second ferroelectric layer, a connecting electrode is prepared on the second ferroelectric layer, and the connecting electrode is connected to the conductive layer through the second ferroelectric layer to obtain a ferroelectric memory. The preparation method of the ferroelectric memory can accurately transfer the second composite structure to the metal layer of the transistor.

[0047] Figure 1 is a flow chart of a method for preparing a ferroelectric memory according to an exemplary embodiment of the present disclosure, Figure 2 It is a schematic diagram of a manufacturing process of a ferroelectric memory according to an illustrative embodiment of the present disclosure.

[0048] According to an embodiment of the present disclosure, a method for preparing a ferroelectric memory 100 is provided, such as Figure 1 and Figure 2 As shown, the process includes the following steps S1 to S5.

[0049] Step S1: Figure 2 Figure (a) and Figure 2 As shown in FIG. 2( b ), a water-soluble sacrificial layer 2 , a first ferroelectric layer 3 , a conductive layer 4 and a second ferroelectric layer 5 are epitaxially grown in sequence on a first substrate 1 .

[0050] According to an embodiment of the present disclosure, the material of the first substrate 1 may be single crystal perovskite oxide, for example, strontium titanate SrTiO3 (001), and the size of the first substrate 1 is 5 mm×5 mm.

[0051] Step S2: Figure 2 As shown in FIG. 5( c ), the adhesion layer 6 is bonded to the support layer 7 , and the support layer 7 is adhered to the second ferroelectric layer 5 through the adhesion layer 6 , thereby obtaining a first composite structure.

[0052] Step S3: Figure 2 As shown in FIG. 5( d ), the first composite structure is immersed in deionized water to remove the water-soluble sacrificial layer 2 and the first substrate 1 , thereby obtaining a second composite structure.

[0053] According to an embodiment of the present disclosure, the first composite structure is immersed in deionized water for 12 hours to 24 hours to remove the water-soluble sacrificial layer 2 and the first substrate 1 to obtain a second composite structure. The second composite structure is a multi-film composite structure of a first ferroelectric layer 3, a conductive layer 4 and a second ferroelectric layer 5 supported by an adhesion layer 6 and a support layer 7.

[0054] Step S4: Figure 2 As shown in FIG. 5( e ), the second composite structure is transferred so that the first ferroelectric layer 3 contacts the metal layer 8 of the transistor, and is immersed in a first organic solvent to remove the adhesion layer 6 and the support layer 7 , thereby exposing the second ferroelectric layer 5 .

[0055] In an exemplary embodiment, deionized water is applied to the surface of the metal layer 8 of the transistor, and the multi-layer composite structure of the adhesion layer 6 and the first ferroelectric layer 3, the conductive layer 4, and the second ferroelectric layer 5 bonded to the adhesion layer 6 is removed from the support layer 7 and transferred to the metal layer 8 of the transistor through the first ferroelectric layer 3. The surface tension of water is used to spread the adhesion layer 6 and the multi-layer composite structure of the first ferroelectric layer 3, the conductive layer 4, and the second ferroelectric layer 5 bonded to the adhesion layer 6, thereby completing the van der Waals contact between the first ferroelectric layer 3 and the metal layer 8 of the transistor. The conductive layer 4, the first ferroelectric layer 3, and the metal layer 8 of the transistor form a ferroelectric tunnel junction. The entire structure is then placed on a hot plate and heated at 50°C to 60°C for 0.5 to 1 hour to achieve a good lamination effect. The temperature is then raised to 90°C to 100°C and heated for 10 to 20 minutes to remove residual moisture.

[0056] According to an embodiment of the present disclosure, the entire structure is immersed in a first organic solvent for 6 to 12 hours. The first organic solvent may be anisole solution to remove the adhesion layer 6 , thereby exposing the second ferroelectric layer 5 .

[0057] Step S5: Figure 2 Figure (f) and Figure 6 As shown in FIG. 1 (h), a connection electrode 9 is formed on the second ferroelectric layer 5 and is connected to the conductive layer 4 through the second ferroelectric layer 5 to obtain a ferroelectric memory 100 .

[0058] According to an embodiment of the present disclosure, the surface of the second ferroelectric layer 5 is cleaned using acetone, ethanol, and deionized water. A photoresist is spin-coated on the surface of the second ferroelectric layer 5, exposed and developed, and a metal is deposited by electron beam evaporation or magnetron sputtering. For example, gold can be selected, and the thickness of the metal is 30 nm to 100 nm. The photoresist and the metal film on the surface of the photoresist are then removed to form a connecting electrode 9. An ultrasonic aluminum wire bonding machine is used to connect the connecting electrode 9 to the conductive layer 4. The connecting electrode 9 is used to read the tunneling current, ultimately forming a complete ferroelectric tunnel junction non-volatile memory with a "1 Transistor-1 Resistance (1T-1R)" structure.

[0059] According to an embodiment of the present disclosure, a water-soluble sacrificial layer 2, a first ferroelectric layer 3, a conductive layer 4 and a second ferroelectric layer 5 are epitaxially grown in sequence on a first substrate 1, an adhesion layer 6 is bonded to a supporting layer 7, and the supporting layer 7 is adhered to the second ferroelectric layer 5 through the adhesion layer 6 to obtain a first composite structure, the first composite structure is immersed in deionized water, and the water-soluble sacrificial layer 2 and the first substrate 1 are removed in a water-soluble manner to obtain a second composite structure, which has the advantages of safety, environmental protection, low cost and simple operation compared to the method of etching the sacrificial layer using an acidic or alkaline solution, the second composite structure is transferred so that the first ferroelectric layer 3 contacts the metal layer 8 of the transistor, and is immersed in a first organic solvent, the adhesion layer 6 and the supporting layer 7 are removed, thereby exposing the second ferroelectric layer 5, a connecting electrode 9 is prepared on the second ferroelectric layer 5, and the connecting electrode 9 is connected to the conductive layer 4 through the second ferroelectric layer 5 to obtain a ferroelectric memory 100, and the preparation method of the ferroelectric memory 100 can accurately transfer the second composite structure to the metal layer 8 of the transistor.

[0060] Figure 3 is a circuit diagram of a ferroelectric memory according to an exemplary embodiment of the present disclosure.

[0061] According to the embodiments of the present disclosure, Figure 3 As shown, the drain 13 of the transistor is electrically connected to the bit line (BL), and the gate 16 of the transistor is electrically connected to the word line (WL). The word line is used to control the connection between the ferroelectric memory 100 and the bit line. The bit line is used to read and write the ferroelectric memory 100. One end of the ferroelectric memory 100 is electrically connected to the source 14 of the transistor, and the other end of the ferroelectric memory 100 is electrically connected to the plate line (PL), which is grounded.

[0062] Figure 4 is a pictorial diagram of a ferroelectric memory according to an exemplary embodiment of the present disclosure.

[0063] According to the embodiments of the present disclosure, Figure 4 As shown, Figure 4A ferroelectric memory 100 is shown in a dotted box. Since the ferroelectric tunnel junction is a transparent stacked film, Figure 4 The transistor directly below the ferroelectric tunnel junction can be seen in the figure.

[0064] According to an embodiment of the present disclosure, before epitaxially growing a water-soluble sacrificial layer 2, a first ferroelectric layer 3, a conductive layer 4 and a second ferroelectric layer 5 in sequence on a first substrate 1, the surface of the first substrate 1 is cleaned with a second organic solvent, the cleaned first substrate 1 is etched, and annealing is performed in an oxygen pressure environment, so that an atomic-level step surface is formed on the surface of the first substrate 1.

[0065] According to the embodiment of the present disclosure, the first substrate 1 needs to be pre-treated before epitaxially growing the water-soluble sacrificial layer 2, the first ferroelectric layer 3, the conductive layer 4, and the second ferroelectric layer 5 on the first substrate 1. First, the surface of the first substrate 1 is cleaned with a second organic solvent, such as acetone and ethanol. The cleaned first substrate 1 is etched with BOE for 50s to 55s, and the etching time is 5×10 -6 Torr~1×10 -4 Annealing is performed in an oxygen pressure environment of 0.1 Torr, so that a flat atomic-level step surface is formed on the surface of the first substrate 1 .

[0066] According to an embodiment of the present disclosure, in the annealing process, the annealing temperature is 900° C. to 1000° C., and the annealing time is 30 min to 60 min.

[0067] According to the embodiment of the present disclosure, the material of the water-soluble sacrificial layer 2 is strontium aluminate (Sr3Al2O6). The materials of the first ferroelectric layer 3 and the second ferroelectric layer 5 are both perovskite oxides, which can be any of the following: barium titanate (BaTiO3), bismuth ferrite (BiFeO3) and lead zirconate titanate (PZT). The material of the conductive layer 4 is a perovskite metal oxide, which can be any of the following: lanthanum strontium manganese oxide (La 0.7 Sr 0.3 MnO3), strontium ruthenate (SrRuO3), lanthanum strontium cobalt oxide (La 0.5 Sr 0.5 CoO3 and lanthanum calcium manganese oxide (La 0.8 Ca 0.2 MnO3) etc.

[0068] According to an embodiment of the present disclosure, a water-soluble sacrificial layer 2 , a first ferroelectric layer 3 , a conductive layer 4 and a second ferroelectric layer 5 are epitaxially grown in sequence on a first substrate 1 by a pulsed laser deposition (PLD) process.

[0069] According to an embodiment of the present disclosure, a water-soluble sacrificial layer 2, a first ferroelectric layer 3, a conductive layer 4, and a second ferroelectric layer 5 are epitaxially grown in sequence on a first substrate 1 through a pulsed laser deposition process (PLD), which enables precise epitaxial growth of a single-crystal thin film with a thickness of nanometers, reduces roughness, and improves the uniformity of the film.

[0070] According to the embodiment of the present disclosure, the growth conditions of the water-soluble sacrificial layer 2 are as follows: the growth temperature of the water-soluble sacrificial layer 2 is 700° C. to 750° C., the oxygen pressure is 1×10 -6 Torr~5×10 -5 Torr, the energy density of the laser is 1.2 J / cm 2 ~2.2J / cm 2 , the laser frequency is 1Hz~5Hz.

[0071] According to an embodiment of the present disclosure, the thickness of the water-soluble sacrificial layer 2 is 8 nm to 10 nm.

[0072] According to the embodiment of the present disclosure, the water-soluble sacrificial layer 2 epitaxially grown under the above growth conditions does not damage the first substrate 1 , which is beneficial for maintaining the integrity and performance of the first substrate 1 .

[0073] According to the embodiment of the present disclosure, the growth conditions of the first ferroelectric layer 3 and the second ferroelectric layer 5 are as follows: the growth temperature of the first ferroelectric layer 3 and the second ferroelectric layer 5 is 650° C. to 750° C., the oxygen pressure is 1×10 -4 Torr~1×10 -2 Torr, the energy density of the laser is 0.3J / cm 2 ~1.2J / cm 2 , the laser frequency is 1Hz~5Hz.

[0074] According to an embodiment of the present disclosure, the thickness of the first ferroelectric layer 3 and the second ferroelectric layer 5 are both 2 nm to 4 nm. The first ferroelectric layer 3 and the second ferroelectric layer 5 have the same film thickness.

[0075] According to the embodiments of the present disclosure, the first ferroelectric layer 3 and the second ferroelectric layer 5 epitaxially grown under the above-mentioned growth conditions have a better electric domain structure and a lower defect density, which can improve the dielectric properties and ferroelectric properties of the first ferroelectric layer 3 and the second ferroelectric layer 5.

[0076] According to the embodiment of the present disclosure, the growth conditions of the conductive layer 4 are as follows: the growth temperature of the conductive layer 4 is 650°C to 750°C, the oxygen pressure is 1×10 -5 Torr~1×10 -2 Torr, the energy density of the laser is 0.3J / cm 2 ~0.8J / cm 2, the laser frequency is 1Hz~5Hz.

[0077] According to an embodiment of the present disclosure, the thickness of the conductive layer 4 is 10 nm to 50 nm.

[0078] According to an embodiment of the present disclosure, after the second ferroelectric layer 5 is grown, the first substrate 1 on which the water-soluble sacrificial layer 2, the first ferroelectric layer 3, the conductive layer 4 and the second ferroelectric layer 5 are epitaxially grown is placed in an environment of 650°C to 750°C and an oxygen pressure of 0.1 Torr to 1 Torr for in-situ annealing for 1h to 2h.

[0079] According to an embodiment of the present disclosure, bonding the adhesive layer 6 to the support layer 7 includes adhering the adhesive layer 6 to the surface of the support layer 7 to obtain a flexible support structure, and then placing the flexible support structure in a temperature environment of 90°C for treatment to enhance the adhesion between the adhesive layer 6 and the support layer 7.

[0080] According to an embodiment of the present disclosure, support layer 7 is made of an organic flexible material, such as polydimethylsiloxane (PDMS), and has a thickness of 0.5 mm to 1 mm. Adhesion layer 6 is made of an organic flexible material, such as polypropylene carbonate (PPC), and has a thickness of 0.1 mm to 0.2 mm.

[0081] According to an embodiment of the present disclosure, the support layer 7 is first placed on a clean and smooth platform, such as a glass sheet, to facilitate the subsequent transfer of the support layer 7, with the flat and smooth surface of the support layer 7 facing upward, and the adhesive layer 6 is adhered to the surface of the support layer 7 to obtain a flexible support structure. The flexible support structure is then placed on a hot plate and treated in a temperature environment of 90°C for 10 minutes to 15 minutes to enhance the adhesion between the adhesive layer 6 and the support layer 7. The flexible support structure makes the subsequent transfer of the multi-layer composite structure of the first ferroelectric layer 3, the conductive layer 4 and the second ferroelectric layer 5 more convenient.

[0082] According to an embodiment of the present disclosure, a flexible support structure is bonded to the second ferroelectric layer 5 to obtain a first composite structure, and then the first composite structure is placed on a hot plate and treated in a temperature environment of 90°C for 10 minutes to 15 minutes to enhance the adhesion between the adhesive layer 6 of the flexible support structure and the second ferroelectric layer 5.

[0083] Figure 5 is a flow chart of a method for preparing a transistor according to an exemplary embodiment of the present disclosure, Figure 6 Schematic diagram of a transistor manufacturing process according to an exemplary embodiment of the present disclosure.

[0084] According to the embodiments of the present disclosure, Figure 5and Figure 6 As shown, the transistor is prepared through the following steps S6 to S12.

[0085] Step S6: Figure 6 As shown in FIG. 1( a ), the single crystal silicon 12 on the surface of the second substrate is patterned.

[0086] According to an embodiment of the present disclosure, the second substrate (P-type SOI) includes a backing 10, an insulating layer 11, and single-crystal silicon 12. The insulating layer 11 can be made of silicon dioxide (SiO2). The single-crystal silicon 12 is doped with P-type silicon, i.e., silicon doped with a trivalent element (e.g., boron B). The single-crystal silicon 12 is cleaned using acetone, ethanol, and deionized water. A photoresist is then spin-coated on the surface of the single-crystal silicon 12, exposed and developed, and etched using RIE to complete the patterning process, leaving the insulating layer 11 and backing 10. The thickness of the single-crystal silicon 12 is approximately 200 nm to 400 nm.

[0087] Step S7: Figure 6 As shown in FIG. 5( b ), a drain electrode 13 and a source electrode 14 are respectively prepared on both sides of the patterned single crystal silicon 12 .

[0088] According to an embodiment of the present disclosure, the insulating layer 11 and the surface of the patterned single-crystal silicon 12 are cleaned using acetone, ethanol, and deionized water. A photoresist is spin-coated on both sides of the patterned single-crystal silicon 12, exposed and developed, and metal, such as titanium (approximately 10 nm to 20 nm thick) and gold (approximately 30 nm to 50 nm thick), is deposited on both sides of the patterned single-crystal silicon 12 using electron beam evaporation or magnetron sputtering. The photoresist and the metal film on the surface of the photoresist are then removed to form the drain 13 and source 14 of the transistor, respectively.

[0089] Step S8: Figure 6 As shown in FIG. 5( c ), a first dielectric layer 15 is grown on the patterned single crystal silicon 12 , the drain 13 and the source 14 .

[0090] According to an embodiment of the present disclosure, acetone, ethanol, and deionized water are used to clean the surfaces of the patterned single crystal silicon 12, the drain 13, and the source 14. Then, an atomic layer deposition (ALD) process is used to grow a first dielectric layer 15 on the patterned single crystal silicon 12, the drain 13, and the source 14 to cover the patterned single crystal silicon 12, the drain 13, and the source 14. The thickness of the first dielectric layer 15 is 10 nm to 30 nm, and the material of the first dielectric layer 15 can be aluminum oxide.

[0091] Step S9: Figure 6As shown in FIG. 5( d ), a gate 16 is formed on the first dielectric layer 15 and above the patterned single crystal silicon 12 .

[0092] According to an embodiment of the present disclosure, the surface of the first dielectric layer 15 is cleaned using acetone, ethanol, and deionized water. A photoresist is spin-coated on the surface of the first dielectric layer 15, exposed and developed, and a metal is deposited on the first dielectric layer 15 and above the patterned single crystal silicon 12 by electron beam evaporation or magnetron sputtering. The metal is, for example, titanium (with a thickness of approximately 10 nm to 20 nm) or gold (with a thickness of approximately 30 nm to 50 nm). The photoresist and the metal film on the surface of the photoresist are then removed to form the gate 16 of the transistor.

[0093] Step S10: Figure 6 As shown in FIG. 8( e ), a second dielectric layer 17 is grown on the gate 16 and the first dielectric layer 15 .

[0094] According to an embodiment of the present disclosure, the surfaces of the gate 16 and the first dielectric layer 15 are cleaned using acetone, ethanol, and deionized water, and a second dielectric layer 17 is grown on the gate 16 and the first dielectric layer 15 by a plasma enhanced chemical vapor deposition (PECVD) process to cover the gate 16 and the first dielectric layer 15. The material of the second dielectric layer 17 can be silicon oxide, and the thickness of the second dielectric layer 17 is 1 μm to 5 μm.

[0095] Step S11: Figure 6 As shown in FIG. 5( f ), the first dielectric layer 15 and the second dielectric layer 17 are etched to form a through hole 18 above the source electrode 14 .

[0096] According to an embodiment of the present disclosure, the surface of the second dielectric layer 17 is cleaned using acetone, ethanol, and deionized water, photoresist is spin-coated on the surface of the second dielectric layer 17, exposed and developed, and the first dielectric layer 15 and the second dielectric layer 17 are etched using BOE to form a through hole 18 above the source electrode 14.

[0097] Step S12: Figure 6 As shown in FIG. 8( g ), metal is deposited on the second dielectric layer 17 and in the through hole 18 , and the metal is patterned to form a metal layer 8 .

[0098] According to an embodiment of the present disclosure, metal is deposited on the second dielectric layer 17 and within the through-hole 18 via electron beam evaporation or magnetron sputtering, filling the through-hole 18 and planarizing the layer using chemical mechanical polishing (CMP). A photoresist is spin-coated on the surface of the second dielectric layer 17, exposed and developed, and metal, such as platinum or silver, is deposited to a thickness of approximately 30 nm to 50 nm via electron beam evaporation or magnetron sputtering. The photoresist and the metal film on the photoresist surface are then removed to form a metal layer 8 in contact with the ferroelectric tunnel junction film, completing the transistor fabrication process.

[0099] Those skilled in the art will appreciate that various combinations and / or combinations of features described in the various embodiments and / or claims of this disclosure may be made, even if such combinations and / or combinations are not explicitly described in this disclosure. In particular, various combinations and / or combinations of features described in the various embodiments and / or claims of this disclosure may be made, without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0100] It should also be noted that directional terms such as "upper," "lower," "front," "back," "left," and "right" mentioned in the embodiments are merely references to the directions in the accompanying drawings and are not intended to limit the scope of protection of the present disclosure. Throughout the drawings, identical elements are represented by identical or similar reference numerals. Conventional structures or configurations are omitted where they may cause confusion in understanding the present disclosure, and the shapes and dimensions of the components in the drawings do not reflect actual size or proportion, but are merely illustrative of the embodiments of the present disclosure.

[0101] Unless otherwise indicated, the numerical parameters in this specification and the appended claims are approximate and can vary depending on the desired properties obtained through the content of the present disclosure. Specifically, all numbers used in the specification and claims to express composition amounts, reaction conditions, etc. should be understood to be modified by the term "about" in all cases. Generally, the meaning of the expression is to include variations of ±10% in some embodiments, ±5% in some embodiments, ±1% in some embodiments, and ±0.5% in some embodiments from the specific amount.

[0102] The use of ordinal numbers such as "first," "second," and "third" in the specification and claims to modify corresponding elements does not in itself mean that the elements have any ordinal number, nor does it represent the order of one element relative to another or the order in the manufacturing method. The use of such ordinal numbers is only used to clearly distinguish one element with a certain name from another element with the same name.

[0103] Furthermore, unless specifically described or required to occur sequentially, the order of the steps is not limited to the order listed above and may be varied or rearranged based on desired design requirements. Furthermore, the above embodiments may be mixed and matched with each other or with other embodiments based on design and reliability considerations. That is, the technical features of different embodiments may be freely combined to form more embodiments.

[0104] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method for preparing a ferroelectric memory, comprising: epitaxially growing a water-soluble sacrificial layer, a first ferroelectric layer, a conductive layer, and a second ferroelectric layer on a first substrate in sequence; bonding an adhesive layer to a support layer, and adhering the support layer to the second ferroelectric layer via the adhesive layer to obtain a first composite structure; immersing the first composite structure in deionized water to remove the water-soluble sacrificial layer and the first substrate to obtain a second composite structure; Transferring the second composite structure so that the first ferroelectric layer contacts the metal layer of the transistor, and immersing the composite structure in a first organic solvent, removing the adhesion layer and the support layer to expose the second ferroelectric layer, and connecting the metal layer of the transistor to the source of the transistor through the metal in the through hole; A connecting electrode is prepared on the second ferroelectric layer, and the connecting electrode is connected to the conductive layer through the second ferroelectric layer to obtain the ferroelectric memory.

2. The preparation method according to claim 1, wherein Before sequentially epitaxially growing a water-soluble sacrificial layer, a first ferroelectric layer, a conductive layer, and a second ferroelectric layer on a first substrate, the method includes: cleaning the surface of the first substrate using a second organic solvent; The cleaned first substrate is etched and annealed in an oxygen pressure environment, so that an atomic-level step surface is formed on the surface of the first substrate.

3. The preparation method according to claim 2, wherein In the annealing treatment, the annealing temperature is 900° C. to 1000° C., and the annealing time is 30 min to 60 min.

4. The preparation method according to claim 1, wherein The material of the water-soluble sacrificial layer is strontium aluminate; The materials of the first ferroelectric layer and the second ferroelectric layer are any one of the following: barium titanate, bismuth ferrite and lead zirconate titanate; The material of the conductive layer is any one of the following: lanthanum strontium manganese oxide, strontium ruthenate, lanthanum strontium cobalt oxide and lanthanum calcium manganese oxide.

5. The preparation method according to claim 1, wherein The water-soluble sacrificial layer, the first ferroelectric layer, the conductive layer and the second ferroelectric layer are epitaxially grown in sequence on the first substrate by a pulsed laser deposition process.

6. The preparation method according to claim 5, wherein The growth conditions of the water-soluble sacrificial layer are as follows: the growth temperature of the water-soluble sacrificial layer is 700°C to 750°C, the oxygen pressure is 1×10 -6 Torr~5×10 -5 Torr, the energy density of the laser is 1.2 J / cm 2 ~2.2J / cm 2 , the laser frequency is 1Hz~5Hz.

7. The preparation method according to claim 5, wherein The growth conditions of the first ferroelectric layer and the second ferroelectric layer are as follows: the growth temperature of the first ferroelectric layer and the second ferroelectric layer is 650° C. to 750° C., the oxygen pressure is 1×10 - 4 Torr ~1×10 -2 Torr, the energy density of the laser is 0.3J / cm 2 ~1.2J / cm 2 , the laser frequency is 1Hz~5Hz.

8. The preparation method according to claim 5, wherein The growth conditions of the conductive layer are as follows: the growth temperature of the conductive layer is 650°C to 750°C, the oxygen pressure is 1×10 -5 Torr~1×10 -2 Torr, the energy density of the laser is 0.3J / cm 2 ~0.8J / cm 2 , the laser frequency is 1Hz~5Hz.

9. The preparation method according to claim 1, wherein The step of bonding the adhesive layer to the support layer comprises: Laminating the adhesive layer to the surface of the support layer to obtain a flexible support structure; The flexible support structure is placed in a temperature environment of 90° C. for treatment to enhance the adhesion between the adhesive layer and the support layer.

10. The preparation method according to claim 1, wherein The transistor is prepared by the following steps: performing patterning on the single crystal silicon on the surface of the second substrate; A drain electrode and a source electrode are respectively prepared on both sides of the patterned single crystal silicon; growing a first dielectric layer on the patterned single crystal silicon, the drain electrode, and the source electrode; forming a gate on the first dielectric layer and above the patterned single crystal silicon; growing a second dielectric layer on the gate and the first dielectric layer; Etching the first dielectric layer and the second dielectric layer to form a through hole above the source electrode; Metal is deposited on the second dielectric layer and in the through hole, and the metal is patterned to form the metal layer.

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