Process for improving cell density of double-groove MOSFET (metal-oxide-semiconductor field effect transistor)

Abstract

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a process for improving the cellular density of a double-groove MOSFET (Metal Oxide Semiconductor Field Effect Transistor), which comprises the following steps of: etching the surface of an N substrate by adopting an extreme ultraviolet lithography technology to form grooves; two grid electrodes G1 and one grid electrode G0 are deposited in a groove of a single MOS cell; a P well layer, an N well layer and a P + layer are formed between the grid G1 and the grid G0 and between the grids G1 of the adjacent MOS cells through ion implantation; and a polycrystalline silicon nanowire which is vertical to the surface of the substrate and grows inside the groove is used as a grid electrode. According to the invention, the plurality of grids are arranged in the trench, so that the intensity of an electric field applied to the trench can be dispersed, the phenomenon of electric field concentration in a local area is reduced, the long-term reliability and stability of the device are improved, the vertical space of the trench is fully utilized by adopting the multi-grid design, the higher integration level is realized, and the reliability of the device is improved. And the performance is improved under the condition that the chip area is not obviously increased.

Description

Technical Field

[0001] The invention relates to the technical field of MOS semiconductors, and in particular to a process for improving the cell density of double-trench MOSFETs. Background Art

[0002] The main purpose of the process of increasing the cell density of the dual trench MOSFET is to add more MOSFET units within a limited chip area to improve the overall performance of the device. This usually involves optimizing the design and manufacturing process of the trench to ensure high precision and high quality while minimizing the space occupied by each unit.

[0003] The existing patent discloses a process for improving the cell density of trench MOSFET and trench MOSFET (publication number CN117650181A), which belongs to the field of semiconductor technology. The trench MOSFET includes a filling conductive layer having a protrusion and / or a depression on at least one of the two lateral sides. The technology disclosed in the patent has the following defects: 1) The introduced protrusions and depressions may change the strength and thermal stability of the filled conductive layer, especially when subjected to external stress, which may affect the overall performance of the device.

[0004] 2) The patent experimentally compares the changes in spatial gaps under different designs, but more data support is needed for the reliability and durability of this new structure under long-term working conditions. Summary of the invention

[0005] The main technical problem solved by the present invention is to provide a process for improving the cell density of double trench MOSFET, thereby solving the problems in the above-mentioned background technology.

[0006] To solve the above technical problems, according to one aspect of the present invention, more specifically, a process for improving the cell density of a double trench MOSFET comprises the following steps: S1, using extreme ultraviolet lithography technology to etch a groove on the surface of the N substrate; S2, two gates G1 and one gate G0 are deposited in the trench of a single MOS cell; S3, forming a P well layer, an N well layer and a P+ layer between the gate G1 and the gate G0, and between the gates G1 of adjacent MOS cells by ion implantation; S4, and using polysilicon nanowires grown vertically to the substrate surface inside the trench as gates; S5. After completing the double trench structure and performing surface passivation treatment, the electrical performance of the MOSFET device is tested.

[0007] Furthermore, the specific steps in steps S2 to S3 are: 1) After the groove surface is oxidized, polysilicon and photoresist are deposited; 2) Photolithography is performed inside the groove to form two gates G1 and one gate G0; 3) After ion implantation, oxidation is performed and the photoresist is covered; 4) At this time, the covering photoresist is photolithographically processed to form a gate oxide layer on the gate G1 and the gate G0.

[0008] Furthermore, in the process of photolithography to form two gates G1 and one gate G0 inside the groove, it is necessary to keep the oxide layer covering the N substrate layer before the ion implantation step can be performed.

[0009] Furthermore, in step S4, the gate G1 serves as the polysilicon nanowire on one side, and the gate G0 serves as the polysilicon nanowire on the other side.

[0010] Furthermore, in step S5, whether the electrical performance of the MOSFET device meets the standard is determined based on the resistance between the source and the drain when the MOSFET device is fully turned on, the maximum voltage that can be tolerated between the drain and the source when the gate is grounded, and the thermal resistance, which are: In the formula, Indicates the condition coefficient for the MOSFET device to meet the electrical performance standards. It represents the resistance between the source and drain when the MOSFET device is fully turned on. It indicates the maximum voltage that the drain and source can withstand when the gate is grounded. Indicates the thermal resistance of the MOSFET device.

[0011] Furthermore, the thermal resistance of the MOSFET device is calculated based on the temperature change of the MOSFET device from one measurement point to another measurement point, and the heat power transferred between the two points. Then: In the formula, Indicates the thermal resistance of the MOSFET device. It represents the temperature change of the MOSFET device from one measurement point to another. Represents the heat power transferred between the two points.

[0012] Furthermore, when When , it means that the electrical performance of the tested MOSFET device meets the use requirements; when When , it means that the electrical performance of the tested MOSFET device does not meet the use requirements.

[0013] Furthermore, in the step S5, during the source electrode deposition process, the gate G1 and the gate G0 need to be covered with photoresist, and after the photoresist is photolithographically processed, the N substrate layer needs to be exposed to the outside so that metal can be deposited to form the source electrode.

[0014] The present invention provides a process for improving the cell density of a double trench MOSFET. Compared with the prior art, the method has the following effects: 1. The present invention increases the effective width of the channel by arranging multiple gates in the same trench, so that more current can flow through the same area, thereby improving the current density. In addition, multiple gates help to distribute the current more evenly, reduce the formation of hot spots, and improve the overall thermal performance of the device.

[0015] 2. The present invention can directly realize single exposure of these fine features through extreme ultraviolet lithography technology, which simplifies the manufacturing process and reduces potential sources of errors.

[0016] 3. The present invention can help disperse the electric field strength applied to the channel by deploying multiple gates in the groove, reduce the electric field concentration phenomenon in local areas, thereby improving the long-term reliability and stability of the device. In addition, this multi-gate design fully utilizes the vertical space of the groove, achieves higher integration, and improves performance without significantly increasing the chip area.

[0017] 4. The present invention can quickly and simply determine whether the electrical performance of the MOSFET device meets the standard through the resistance between the source and the drain when the MOSFET device is fully turned on, the maximum voltage that the drain and the source can withstand when the gate is grounded, and the thermal resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a process flow chart of the MOSFET structure in the present invention; Figure 2 It is a schematic diagram of the planar structure of the present invention; Figure 3 It is a schematic diagram of the distribution of MOS cells and gates G1 and G0 in the present invention. DETAILED DESCRIPTION

[0019] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] Example 1 like Figure 1 - 3, according to one aspect of the present invention, a process for improving the cell density of a double trench MOSFET is provided, comprising the following steps: Step 1: Use extreme ultraviolet lithography to etch grooves on the surface of the N substrate. In traditional photolithography, in order to achieve smaller feature sizes, multiple patterning techniques (such as double or quadruple patterning) are usually required, which increases process complexity and cost. Extreme ultraviolet lithography can directly achieve single exposure of these small features, simplifying the manufacturing process and reducing potential sources of error.

[0021] Step 2: Deposit two gates G1 and one gate G0 in the trench of a single MOS cell. By setting multiple gates in the same trench, the effective width of the channel is increased, so that more current can flow through the same area, thereby increasing the current density, and multiple gates help to distribute the current more evenly, reduce the formation of hot spots, and improve the overall thermal performance of the device.

[0022] Deploying multiple gates in the trench can help disperse the electric field strength applied to the channel and reduce the electric field concentration in local areas, thereby improving the long-term reliability and stability of the device. This multi-gate design makes full use of the vertical space of the trench, achieves higher integration, and improves performance without significantly increasing the chip area.

[0023] Step 3: Form a P-well layer, an N-well layer and a P+ layer between the gate G1 and the gate G0 and between the gates G1 of adjacent MOS cells by ion implantation.

[0024] Step 4: A polysilicon nanowire grown vertically to the substrate surface is used as a gate inside the trench, wherein the gate G1 is used as the polysilicon nanowire on one side, and the gate G0 is used as the polysilicon nanowire on the other side.

[0025] Step 5: After the double trench structure is completed and the surface is passivated, the electrical performance of the MOSFET device is tested. During the source electrode deposition process, the gate G1 and the gate G0 need to be covered with photoresist. After the photoresist is photolithographically processed, the N substrate layer needs to be exposed to the outside before the metal can be deposited to form the source electrode.

[0026] In this embodiment, the specific steps in steps 2 to 3 are: 1. After the groove surface is oxidized, polysilicon and photoresist are deposited.

[0027] 2. Photolithography is performed inside the groove to form two gates G1 and one gate G0; and in the process of photolithography to form two gates G1 and one gate G0 inside the groove, it is necessary to retain the oxide layer covering the N substrate layer before the ion implantation step can be performed.

[0028] 3. After ion implantation, oxidation is performed and the photoresist is covered.

[0029] 4. At this time, the covering photoresist is photolithographically processed to form a gate oxide layer on the gate G1 and the gate G0.

[0030] Example 2 like Figure 2 As shown in the figure, the electrical performance of the MOSFET device is determined based on the resistance between the source and the drain when the MOSFET device is fully turned on, the maximum voltage that the drain and the source can withstand when the gate is grounded, and the thermal resistance. In the formula, Indicates the condition coefficient for the MOSFET device to meet the electrical performance standards. It represents the resistance between the source and drain when the MOSFET device is fully turned on. It indicates the maximum voltage that the drain and source can withstand when the gate is grounded. Indicates the thermal resistance of the MOSFET device.

[0031] The thermal resistance of the MOSFET device is calculated based on the temperature change of the MOSFET device from one measurement point to another, and the heat power transferred between the two points. Then: In the formula, Indicates the thermal resistance of the MOSFET device. It represents the temperature change of the MOSFET device from one measurement point to another. Represents the heat power transferred between the two points.

[0032] The thermal resistance of the collected MOSFET device is calculated. The temperature change of the MOSFET device from one measurement point to another is obtained. (Unit: °C). The heat transfer power between the two points is (Unit: W). Then we have: From the above calculation, we can know that the thermal resistance of MOSFET device is (Unit: °C / W). Then, when calculating the conditional coefficients for the collected MOSFET devices, the resistance between the source and the drain when the MOSFET device is fully turned on is (Unit: mΩ). When the gate is grounded, the maximum voltage between the drain and the source can withstand is (unit V). Then we have: It can be known from the above calculation that the electrical performance of the tested MOSFET device meets the use requirements.

[0033] Example 3 When determining whether the electrical performance of a MOSFET device meets the standard based on the resistance between the source and the drain when the MOSFET device is fully turned on, the maximum voltage that the drain and the source can withstand when the gate is grounded, and the thermal resistance, after comparing multiple sets of data samples, we have: Table 1 Some implementation parameters and usage standards of MOSFET devices From the data in Table 1 above, we can know that when the sample tends to infinity, there will be a dividing line that determines whether the MOSFET device meets the use requirements by the condition coefficient w, that is, when When , it means that the electrical performance of the tested MOSFET device meets the use requirements.

[0034] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A process for increasing the cell density of a double trench MOSFET, characterized in that: The following steps are involved: S1, using extreme ultraviolet lithography technology to etch a groove on the surface of the N substrate; S2, two gates G1 and one gate G0 are deposited in the trench of a single MOS cell; S3, forming a P well layer, an N well layer and a P+ layer between the gate G1 and the gate G0, and between the gates G1 of adjacent MOS cells by ion implantation; S4, and using polysilicon nanowires grown vertically to the substrate surface inside the trench as gates; S5. After completing the double trench structure and performing surface passivation treatment, the electrical performance of the MOSFET device is tested.

2. The process for increasing the cell density of a dual trench MOSFET according to claim 1, characterized in that: The specific steps in steps S2 to S3 are: 1) After the groove surface is oxidized, polysilicon and photoresist are deposited; 2) Photolithography is performed inside the groove to form two gates G1 and one gate G0; 3) After ion implantation, oxidation is performed and the photoresist is covered; 4) At this time, the covering photoresist is photolithographically processed to form a gate oxide layer on the gate G1 and the gate G0.

3. The process for increasing the cell density of a dual trench MOSFET according to claim 2, characterized in that: In the process of photolithography to form two gates G1 and one gate G0 inside the groove, it is necessary to keep the oxide layer covering the N substrate layer before the ion implantation step can be performed.

4. The process for increasing the cell density of a dual trench MOSFET according to claim 1, characterized in that: In the step S4, the gate G1 serves as the polysilicon nanowire on one side, and the gate G0 serves as the polysilicon nanowire on the other side.

5. The process for increasing the cell density of a dual trench MOSFET according to claim 1, characterized in that: The step S5 determines whether the electrical performance of the MOSFET device meets the standard according to the resistance between the source and the drain when the MOSFET device is fully turned on, the maximum voltage that the drain and the source can withstand when the gate is grounded, and the thermal resistance, which includes: In the formula, Indicates the condition coefficient for the MOSFET device to meet the electrical performance standards. It represents the resistance between the source and drain when the MOSFET device is fully turned on. It indicates the maximum voltage that the drain and source can withstand when the gate is grounded. Indicates the thermal resistance of the MOSFET device.

6. The process for increasing the cell density of a dual trench MOSFET according to claim 5, characterized in that: The thermal resistance of the MOSFET device is calculated based on the temperature change of the MOSFET device from one measurement point to another, and the heat power transferred between the two points. Then: In the formula, Indicates the thermal resistance of the MOSFET device. It represents the temperature change of the MOSFET device from one measurement point to another. Represents the heat power transferred between the two points.

7. The process for increasing the cell density of a dual trench MOSFET according to claim 5, characterized in that: when When , it means that the electrical performance of the tested MOSFET device meets the use requirements; when When , it means that the electrical performance of the tested MOSFET device does not meet the use requirements.

8. The process for increasing the cell density of a dual trench MOSFET according to claim 1, characterized in that: In the step S5, during the source electrode deposition process, the gate G1 and the gate G0 need to be covered with photoresist. After the photoresist is photolithographically processed, the N substrate layer needs to be exposed to the outside so that metal can be deposited to form the source electrode.

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