Semiconductor switching device for implementing edge terminal structure
By setting the doping profile of the concentric ring segment in the edge termination structure of the semiconductor switching device, the distribution of the charge carriers smoothly, the reliability failure problem caused by the electric field peak is solved, and the effect of improving breakdown voltage and reliability is achieved.
Patent Information
- Application Number
- CN202411451588.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-20
- Filing Date
- 2024-10-17
- Publication Date
- 2025-04-22
AI Technical Summary
The existing semiconductor switching devices have electric field peaks in the edge termination structure, resulting in reliability failure and it is difficult to effectively increase the breakdown voltage (VBR).
By providing a series of spaced concentric ring segments in the edge termination structure of the semiconductor switching device, the doping profiles of these ring segments are used to smoothly diffuse in the lateral direction, thereby obtaining a similar charge carrier distribution (VLD) profile within each ring, reducing the electric field peak.
This technology effectively reduces the electric field peak, improves breakdown voltage (VBR) and reliability, and shows higher reliability under conditions such as high humidity and cosmic ray events.
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Figure CN119866040A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor switching device implementing an edge termination structure. Background Art
[0002] The edge termination structure is intended to confine or terminate the electric field within a minimum length or a given length of the terminal to increase the breakdown voltage (VBR) of the semiconductor switching device. In particular, the edge termination structure is intended to minimize the electric field peaks, which are often the cause of reliability failures of the device. However, depending on the doping profile and configuration, the electric field during the blocking state of the edge termination structure may still consist of a maximum value and may therefore still be the cause of reliability failures.
[0003] It is therefore an object of the present disclosure to provide an improved semiconductor switching device with an edge termination structure having improved VBR and reliability. Summary of the invention
[0004] According to a first example of the present disclosure, a semiconductor switching device implementing an edge termination structure is provided. The semiconductor switching device includes a semiconductor die, the semiconductor die is formed by a first region doped with a first type of charge carriers, and a top section having a central region and a peripheral region surrounding the central region. At least one junction is provided in the central region of the semiconductor die, the junction being formed between a second region doped with a second type of charge carriers different from the first type of charge carriers, wherein the second region is adjacent to the first region.
[0005] Furthermore, an edge termination structure is disposed in the edge region and surrounds the central region. The edge termination structure is configured to prevent voltage breakdown during operation of the semiconductor switching device and is composed of at least one ring structure disposed at an edge of the first region.
[0006] At least one ring structure is comprised of a series of spaced apart concentric ring segments disposed in the first region, each ring segment being doped with charge carriers of the second type and spaced apart at intervals doped with charge carriers of the first type.
[0007] Therefore, by replacing each wide ring of the current implementation with multiple narrow sub-rings arranged concentrically with each other, the injection (doping) profile of the relevant charge carriers is smoothly spread in the lateral direction, and the resulting electric field as a function of doping is smoothed to obtain the advantages of a VLD-like profile within each ring. Therefore, any electric field peaks that occur within the spacing of the individual junctions of the ring segments are further reduced, and thereby improve VBR and reliability.
[0008] It should be noted that the first type of charge carriers may be N-type carriers and the second type of charge carriers may be P-type carriers. However, the opposite configuration in which the first type of charge carriers are P-type carriers and the second type of charge carriers are N-type carriers is also suitable for achieving the desired effects of smoothing the electric field peaks and improving VBR and reliability.
[0009] In one example, the second region is formed as a well in the first region. Thus, such a device can be manufactured in a logical sequence of manufacturing steps.
[0010] In an advantageous example, the number of sub-ring segments is in the range of 3-10, particularly 3-8, and more particularly 3-5.
[0011] In particular, the lateral width of the sub-ring segment may be in the range of 3-10 μm, in particular 3-6 μm, and preferably 4 μm.
[0012] Likewise, the spacing between adjacent sub-ring segments may be in the range of 4-10 μm, preferably 6-10 μm.
[0013] In a further advantageous example, the termination structure comprises a metal field plate element on top of the main ring segments extending to the spacing between the main ring segments.The metal FP structure may increase reliability in case of suboptimal charge shielding by the passivation layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The present disclosure will now be discussed with reference to the accompanying drawings, in which is shown:
[0015] Figure 1A A semiconductor switching device implementing an edge termination structure according to the prior art;
[0016] Figure 1B A field plate edge termination structure according to an example of the present disclosure;
[0017] Figure 1C Figure 1B A detailed view of an instance of
[0018] Figure 2 Figure 1B and Figure 1C A top view of an example of;
[0019] Figure 3 Improved breakdown voltage (VBR) of field plate termination examples according to the present disclosure compared to the prior art;
[0020] Figure 4 A Figure 1A Overview of the electric field distribution of the standard structure at 1200V;
[0021] Figure 4 B is the electric field distribution profile of the example of the present disclosure at 1200V. DETAILED DESCRIPTION
[0022] For proper understanding of the present disclosure, in the following detailed description, corresponding elements or components of the present disclosure will be denoted by the same reference numerals in the drawings.
[0023] Throughout the following detailed description, it should be understood that the first type of charge carrier is an N-type carrier and the second type of charge carrier is logically a P-type carrier. However, the opposite configuration in which the first type of charge carrier is a P-type carrier and the second type of charge carrier is an N-type carrier is also applicable to all examples described in this application, because both configurations (NP or PN) achieve the desired effects of the present disclosure.
[0024] As outlined in the background section of this application, the edge termination structure is intended to confine or terminate the electric field within a minimum length or within a given length of the terminal to increase the breakdown voltage (VBR) of the semiconductor switching device. In particular, the edge termination structure is intended to minimize the electric field peaks, which are often the cause of reliability failures of the device.
[0025] exist Figure 1A Detailed examples as known in the prior art are described in detail in the accompanying drawings. Reference numeral 10 denotes a semiconductor switching device, but its function or mode of operation is not further detailed. Device 10 is formed by a semiconductor die 11. Die 11 is formed by a first region doped with a first type of charge carriers. For the sake of clarity and explanation of the present disclosure, it is assumed that the first type of charge carriers are N-type charge carriers.
[0026] The semiconductor switching device 10 has a central region denoted by reference numeral 10 y and a peripheral region surrounding the central region 10 y , wherein the peripheral region is denoted by reference numeral 10 z .
[0027] Although not relevant to a correct understanding of the present disclosure, the central region 10y of the semiconductor die 11 may be provided with a junction, typically formed by a second region doped with a second type of charge carriers different from the first type of charge carriers, wherein the second region is adjacent to the first region or is above the first region or is on top of the first region.
[0028] Reference numeral 13 may denote an edge termination structure disposed in the edge region 10z and surrounding the central region 10y of the semiconductor die 11. The edge termination structure 13 is configured to prevent voltage breakdown during operation of the semiconductor switching device 10 and is composed of at least one ring structure 13 disposed in a first region doped with a first type of charge carriers, which are P-type charge carriers in this example. Each ring structure 13 may be electrically connected to a metal field plate element 14, which is placed on top of the ring structure 13.
[0029] An insulating layer 15 is provided between the metal plate element 14 and the semiconductor surface. Reference numeral 16 denotes a polyamide moisture insulator, which covers the semiconductor die surface and the metal field plate element 14 in an isolating manner. Reference numeral 12 may denote an electrode to which a bias voltage is applied.
[0030] Figure 1B (Attached with its Figure 1C Detailed view CC) in FIG. 1 shows an example of an improved semiconductor switching device with an edge termination structure that exhibits improved VBR and reliability.
[0031] exist Figure 1B and in Figure 1C In the detailed enlarged image CC, from Figure 1A The corresponding technical features obtained are indicated by similar reference numerals. Figure 1B and Figure 1C In FIG. 1 , an example of a semiconductor switching device according to the present disclosure is indicated by reference numeral 100. It is formed of a semiconductor die 111 having a first region doped with a first type of charge carriers, which may be P-type or N-type.
[0032] The central region of the semiconductor switching device 100 is denoted as 100y, and the peripheral region surrounding the central region 100y is denoted as 100z. Likewise, the central region 100y of the semiconductor die 111 may be provided with a junction, which is typically formed by a second region doped with a second type of charge carriers different from the first type of charge carriers, wherein the second region is adjacent to the first region.
[0033] The edge termination structure 113 of the present disclosure is disposed in the edge region 100z and surrounds the central region 100y of the semiconductor die 111 in a similar manner as in the prior art. The edge termination structure 113 according to the present disclosure also prevents voltage breakdown during operation of the semiconductor switch device 100.
[0034] In contrast to the edge termination structure 13 of the prior art, according to the present disclosure, the edge termination structure 113 is formed as a ring structure consisting of a series of spaced-apart concentric ring segments. Each individual concentric ring segment is referenced by 1131-..-1133-..-113 n Indicates. Individual concentrically oriented ring segments 113 n are present in the first region and are each doped with charge carriers of the second type. Figure 1C As seen in more detail in FIG. 1 , the individual concentrically oriented ring segments 113 n The spacing is 120. See also Figure 2 Top view of .
[0035] By using a plurality of narrow ring segments 113 arranged concentrically with each other in the semiconductor die structure 111 n Instead of Figure 1A In the prior art, the doping profile of the relevant charge carriers is diffused in the lateral direction and deeper into the semiconductor device, thus as seen in the direction from the central area 100y towards its peripheral area 100z, towards the outer periphery 100z of the semiconductor switching device 100. The resulting electric field as a function of doping is smoothed to obtain the advantages of a VLD-like profile within the ring. Therefore, the large electric field peaks that occur within the wide spacing between the rings 13 are further reduced, and thereby the VBR and reliability of the semiconductor switching device 100 according to the present disclosure are improved.
[0036] exist Figure 4 The above-mentioned favorable effect on the electric field is shown in Figures 4A and 4B, showing Figure 1A The standard structure and Figure 1B The electric field distribution profile E of the example of the present disclosure, both at 1200V. Figure 4 In B, as in Figure 1A Compared to the known prior art device 10 depicted in , the generated electric field E is diffuse across the semiconductor die structure 111 .
[0037] Through a plurality of narrow ring segments 113 n The configuration of the edge termination structure 113 results in an increase in VBR, such as Figure 3 As shown, the voltage increases from 1348 V to 1500 V, which is considered to be an improvement of about 150 V (= 10%) compared to the prior art example (also depicted in the same figure). 12 and 1.5×10 13 An overall improvement in VBR was observed with an implant dose of 1.54 N·m2 / s.
[0038] The reliability of the new configuration of the present disclosure, i.e., using multiple narrow ring segments 113 according to the present disclosure nInstead of a single wide ring 13 as in the prior art, it is also expected to be better. In case of high humidity and cosmic ray events, as well as suboptimal passivation of external charges, the semiconductor switching device 100 according to the present disclosure becomes robust because sensitive high electric field peaks are pushed away from the surface and their amplitude is reduced.
[0039] Due to the multiple concentric ring segments 113 n This doping profile caused by the FP structure ( Figure 1B and Figure 1C ) during the blocking state is composed of the concentric ring segments 113 n The maximum value of the gap 120 between the concentric ring segments 113 n It also includes another maximum in the large gaps between the rings 113.
[0040] In the FP example, the known single p-implanted ring structure 13 is divided into 3-5 separate concentric ring segments 113 n Alternatively, the ring segment 113 n The width of the concentric ring segments 113 is about 3-10 μm, and the width of the spacing 120 is 4-10 μm. n Become partially interspersed, and diffuse the doping uniformly in the ring section 113 n internal.
[0041] Likewise, each ring structure 113 can be electrically connected to a metal field plate element 114, which is placed on top of the ring structure 113. In more detail, each metal field plate element 114 can be disposed on the spaced concentric ring segments 113. n The contact section is indicated by reference numeral 117, and is specifically described in more detail in Figure 1C .
[0042] Similarly, an insulating layer 115 is provided between the metal plate element 114 and the semiconductor die 111 (the first region doped with the first type of charge carriers). The metal plate structure 114 can increase reliability in the case of suboptimal charge shielding of the passivation layer. In addition, reference numeral 116 denotes a passivation layer covering the insulating layer 115 and the associated metal field plate element 114. Likewise, reference numeral 112 can denote electrodes for contact implants and applied bias.
[0043] In one example, the second region is formed as a well in the first region. Thus, such a device can be manufactured in a logical sequence of manufacturing steps.
[0044] In an advantageous example, the ring segment 113 nThe number n is in the range of 3-10, particularly 3-8, and more particularly 3-5.
[0045] In particular, the ring segment 113 n The lateral width of may be in the range of 3-10 μm, in particular 3-6 μm, and preferably 4 μm.
[0046] Likewise, the adjacent ring segment 113 n The spacing 120 therebetween may be in the range of 4-10 μm, preferably 6-10 μm.
[0047] Various aspects of the invention are set out in the accompanying independent claims. Combinations of features from the dependent claims and / or the independent claim may be combined as appropriate and not just as set out in the claims.
[0048] The scope of the present disclosure includes any new feature or combination of features disclosed therein, whether explicitly or implicitly, or any generalization thereof, whether or not it relates to the claimed invention or mitigates any or all of the problems solved by the invention. The applicant hereby gives notice that new claims may be formulated to such features during the prosecution of the present application or of any such further application derived therefrom. In particular, with reference to the appended claims, features from dependent claims may be combined with features of the independent claims, and features from the respective independent claims may be combined in any appropriate manner and not merely in the specific combinations recited in the claims.
[0049] Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment may also be provided separately or in any suitable subcombination.
[0050] The term "comprising" does not exclude other elements or steps and the term "a" or "an" does not exclude a plurality. Reference signs in the claims should not be construed as limiting the scope of the claims.
[0051] List of reference symbols used
[0052] 10 According to the semiconductor switching device of the prior art
[0053] 10y Central Area
[0054] 10z Outer area
[0055] 11 Semiconductor die structure
[0056] 12 Electrodes
[0057] 13 Edge terminal structure
[0058] 14 Metal Field Plate Components
[0059] 15 Insulation layer
[0060] 16 Field shielding plate
[0061] 100 The semiconductor switch device according to the present disclosure
[0062] 100y Central Area
[0063] 100z Outer area
[0064] 1111 Semiconductor die structure
[0065] 112 Electrode
[0066] 113 According to the edge terminal structure of the present disclosure
[0067] 113 n Spaced concentric ring segments
[0068] 114 Metal Field Plate Element
[0069] 115 Insulation layer
[0070] 116 Field Shield
[0071] 117 concentric ring segments electrically connected to the field shield 120 spacing or pitch
Claims
1. A semiconductor switch device implementing an edge terminal structure, the semiconductor switch device comprising: a semiconductor die formed of a first region doped with charge carriers of a first type and having a central region and a peripheral region surrounding the central region, at least one junction, the at least one junction being arranged in the central region of the semiconductor die, the junction forming a second region doped with a second type of charge carriers different from the first type of charge carriers, wherein the second region adjoins the first region, an edge termination structure disposed in an edge region and surrounding the central region and configured to prevent voltage breakdown during operation of the semiconductor switching device, the edge termination structure consisting of at least one ring structure disposed in the first region, wherein The at least one ring structure is comprised of a series of spaced apart concentric ring segments disposed in the first region, each ring segment being doped with charge carriers of the second type and being spaced apart at intervals doped with charge carriers of the first type. 2 . The semiconductor switching device of claim 1 , wherein the first type of charge carriers are N-type carriers and the second type of charge carriers are P-type carriers. 3 . The semiconductor switching device of claim 1 , wherein the first type of charge carriers are P-type carriers and the second type of charge carriers are N-type carriers.
4. A semiconductor switching device according to any one or more of claims 1-3, wherein the second region is formed as a well in the first region.
5. A semiconductor switching device according to any one or more of claims 1-3, wherein the first region and the second region are formed as layers, wherein the first region layer extends over the second region layer.
6. The semiconductor switching device according to any one or more of claims 1-5, wherein the number of ring segments is in the range of 3-10, in particular 3-8, and more in particular 3-5.
7. A semiconductor switching device according to any one or more of claims 1-6, wherein the lateral width of the ring segment is in the range of 3-10 μm, in particular 3-6 μm, and preferably 4 μm.
8. A semiconductor switching device according to any one or more of claims 1-7, wherein the spacing between adjacent ring segments is in the range of 4-10 μm, preferably 6-10 μm.