Manufacturing method of integrated semiconductor device

Abstract

The invention discloses a manufacturing method of an integrated semiconductor device, and belongs to the technical field of semiconductors, and the manufacturing method comprises the steps: providing a substrate which comprises a high-voltage region, a medium-voltage region and a low-voltage region; forming a high-voltage gate dielectric layer on the substrate; forming well regions in the high-voltage region and the medium-voltage region; removing the high-voltage gate dielectric layer on the medium-voltage region and the low-voltage region; forming a medium-voltage gate dielectric layer on the medium-voltage region and the low-voltage region; sequentially forming a first protection layer and a second protection layer on the medium-voltage gate dielectric layer and the high-voltage gate dielectric layer, wherein the first protection layer and the second protection layer have an etching selection ratio; forming a well region in the low-voltage region; removing the second protection layer and the first protection layer; removing the medium-voltage gate dielectric layer on the low-voltage region; and forming a low-voltage gate dielectric layer on the low-voltage region. According to the manufacturing method of the integrated semiconductor device provided by the invention, the quality of the medium-voltage gate dielectric layer can be improved, and the yield of the semiconductor device can be improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, and in particular relates to a method for manufacturing an integrated semiconductor device. Background Art

[0002] Integrated semiconductor devices are manufactured by integrating multiple types of devices together. For example, transistors of different voltages and types are prepared on the same substrate, and different transistors are isolated by shallow trench isolation structures. By manufacturing different semiconductor devices on the same substrate, the manufacturing efficiency of semiconductor devices can be improved and the integration of semiconductor devices can be improved. However, in the manufacturing process of different semiconductor devices, the threshold voltage of semiconductor devices is different, and it is necessary to meet the use of high-frequency circuits and low-power circuits. Among them, the thickness stability requirements of the medium-voltage gate dielectric layer in the manufacturing process of medium-voltage transistors are extremely important, which will directly affect the manufacturing yield. During the manufacturing process, sometimes multiple ion implantations are added according to the customized design requirements of different devices, thereby forcing the corresponding wet photoresist layer removal process to be added, resulting in the final thickness of the medium-voltage gate dielectric layer being difficult to control. Summary of the invention

[0003] The object of the present invention is to provide a manufacturing method for an integrated semiconductor device, which can simplify the manufacturing process of the integrated semiconductor device and, after forming a medium-voltage gate dielectric layer, can avoid damage and loss to the medium-voltage gate dielectric layer during multiple ion implantations and photoresist layer removal processes according to the customized requirements of the semiconductor device, thereby improving the quality of the medium-voltage gate dielectric layer, improving the yield of the semiconductor device, and reducing the impact on ion implantation.

[0004] In order to solve the above technical problems, the present invention provides a method for manufacturing an integrated semiconductor device, comprising: Providing a substrate, wherein the substrate comprises a high-pressure region, a medium-pressure region and a low-pressure region; forming a high voltage gate dielectric layer on the substrate; Using the high-voltage gate dielectric layer as an ion implantation buffer layer, forming well regions in the high-voltage region and the medium-voltage region; Removing the high-voltage gate dielectric layer on the medium-voltage region and the low-voltage region; forming a medium-voltage gate dielectric layer on the medium-voltage region and the low-voltage region; Sequentially forming a first protective layer and a second protective layer on the medium voltage gate dielectric layer and the high voltage gate dielectric layer, wherein the first protective layer and the second protective layer have an etching selectivity ratio; forming a well region in the low pressure region; removing the second protective layer and the first protective layer; removing the medium voltage gate dielectric layer on the low voltage area; and A low-voltage gate dielectric layer is formed on the low-voltage region.

[0005] In one embodiment of the present invention, the first protective layer includes a silicon nitride layer, and the thickness of the first protective layer is 15Å~25Å.

[0006] In one embodiment of the present invention, the second protective layer includes a polysilicon layer, and the thickness of the second protective layer is 40Å~50Å.

[0007] In one embodiment of the present invention, the manufacturing method further includes: forming a first pattern photoresist layer on the second protective layer, wherein the first pattern photoresist layer exposes the low-voltage N region on the low-voltage area; Using the first patterned photoresist layer as a mask, the second protective layer, the first protective layer and the medium-voltage gate dielectric layer as an ion implantation buffer layer to perform ion implantation to form a well region in the low-voltage N region; removing the first pattern photoresist layer by wet etching; forming a second pattern photoresist layer on the second protective layer, wherein the second pattern photoresist layer exposes the low-voltage P region on the low-voltage area; Using the second patterned photoresist layer as a mask, the second protective layer, the first protective layer and the medium-voltage gate dielectric layer as an ion implantation buffer layer to perform ion implantation to form a well region in the low-voltage P region; The second pattern photoresist layer is removed by wet etching.

[0008] In one embodiment of the present invention, the etching solution for removing the first pattern photoresist layer and / or the second pattern photoresist layer is at least one of SPM etching solution and SC1 etching solution.

[0009] In one embodiment of the present invention, the SPM etching solution or the SC1 etching solution does not etch the second protective layer.

[0010] In one embodiment of the present invention, when a well region is formed in the low-voltage region, at the same ion injection concentration, the injection energy when the second protective layer, the first protective layer and the medium-voltage gate dielectric layer are used as ion injection buffer layers is increased by 1% to 2.5% relative to the injection energy when the medium-voltage gate dielectric layer is used as the ion injection buffer layer.

[0011] In one embodiment of the present invention, the second protective layer is removed by wet etching using a first etching solution, wherein the first etching solution is a mixed solution of hydrofluoric acid and nitric acid, and the volume ratio of the hydrofluoric acid to the nitric acid is, for example, 1:40-1:60.

[0012] In one embodiment of the present invention, the first protective layer is removed by wet etching using a second etching solution, and the second etching solution is phosphoric acid, the mass fraction of the phosphoric acid is 86%-95%, and the etching temperature is 150°C-165°C.

[0013] In one embodiment of the present invention, the thickness of the high-voltage gate dielectric layer is greater than the thickness of the medium-voltage gate dielectric layer, and the thickness of the medium-voltage gate dielectric layer is greater than the thickness of the low-voltage gate dielectric layer.

[0014] In summary, the present invention provides a method for manufacturing an integrated semiconductor device. By improving the method for manufacturing an integrated semiconductor device, the unexpected technical effect of the present invention is that after forming a medium-voltage gate dielectric layer, according to the customized requirements of the semiconductor device, during multiple ion implantations and photoresist layer removal processes, damage and loss to the medium-voltage gate dielectric layer can be avoided, thereby improving the quality of the medium-voltage gate dielectric layer and improving the yield of the semiconductor device. The thickness of the first protective layer and the second protective layer can be reduced to reduce the impact on ion implantation. The first protective layer and the second protective layer can be removed independently to further avoid damage to the medium-voltage gate dielectric layer, further improving the stability and yield of the semiconductor device. The process compatibility can be improved, thereby improving production efficiency and reducing costs, the doping concentration can be accurately controlled, and the well area in the low-voltage area can be protected, leakage current can be reduced, and the reliability of the device can be improved.

[0015] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0017] Figure 1 The present invention is intended to form a patterned photoresist layer on a substrate to locate the position of a shallow trench isolation structure in one embodiment.

[0018] Figure 2 Schematic diagram of forming a shallow trench isolation structure and a high-voltage gate dielectric layer in one embodiment.

[0019] Figure 3 FIG. 1 is a schematic diagram of forming a well region in a high-pressure region and a medium-pressure region in one embodiment.

[0020] Figure 4 Schematic diagram of a medium-voltage gate dielectric layer, a first protective layer, and a second protective layer formed in one embodiment.

[0021] Figure 5 FIG. 4 is a schematic diagram of forming a first patterned photoresist layer and a fifth well region in one embodiment.

[0022] Figure 6 FIG. 4 is a schematic diagram of forming a second patterned photoresist layer and a sixth well region in one embodiment.

[0023] Figure 7 FIG. 1 is a schematic diagram of an embodiment after the second pattern photoresist layer is removed.

[0024] Figure 8 This is a schematic diagram after the second protective layer is removed in one embodiment.

[0025] Fig. 9 This is a schematic diagram after the first protective layer is removed in one embodiment.

[0026] Fig.10 Schematic diagram of etching rates of a medium-voltage gate dielectric layer, a first protective layer, and a second protective layer by various etching solutions in one embodiment.

[0027] Fig.11 FIG. 4 is a schematic diagram of forming a low-voltage gate dielectric layer in an embodiment.

[0028] Fig.12 FIG. 4 is a schematic diagram of forming a gate structure in an embodiment.

[0029] Fig.13 FIG. 4 is a schematic diagram of forming a lightly doped region in an embodiment.

[0030] Fig.14 FIG. 4 is a schematic diagram of forming a heavily doped region in an embodiment.

[0031] Fig.15 FIG. 4 is a schematic diagram of an integrated semiconductor device in an embodiment.

[0032] Description of labels: 10. substrate; 11. pad oxide layer; 12. pad nitride layer; 13. patterned photoresist layer; 131. opening; 14. shallow trench isolation structure; 15. high voltage gate dielectric layer; 16. medium voltage gate dielectric layer; 17. first protective layer; 18. second protective layer; 19. first patterned photoresist layer; 191. first recess; 20. second patterned photoresist layer; 201. second recess; 21. low voltage gate dielectric layer; 22. gate structure; 23. sidewall structure; 101. first well region; 102. first well region The second well region; 103, the third well region; 104, the fourth well region; 105, the fifth well region; 106, the sixth well region; 111, the first lightly doped region; 112, the second lightly doped region; 113, the third lightly doped region; 114, the fourth lightly doped region; 115, the fifth lightly doped region; 116, the sixth lightly doped region; 121, the first heavily doped region; 122, the second heavily doped region; 123, the third heavily doped region; 124, the fourth heavily doped region; 125, the fifth heavily doped region; 126, the sixth heavily doped region. DETAILED DESCRIPTION

[0033] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0035] In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0036] The present invention provides a method for manufacturing an integrated semiconductor device, which can prepare semiconductor devices with different functions in different regions of the same substrate, and each semiconductor device has excellent performance and can simultaneously meet the use requirements of high-frequency circuits and low-power circuits. The method for manufacturing an integrated semiconductor device provided by the present invention is simple in manufacturing method, highly controllable, and can reduce production costs, and can be used to manufacture semiconductor devices with different needs.

[0037] See also Figure 1 As shown, in one embodiment of the present invention, a substrate 10 is first provided, and the substrate 10 can be any material suitable for formation, such as a silicon wafer, a germanium substrate, silicon germanium, silicon on insulator, or silicon stacked on insulator, etc. The present invention does not limit the type and thickness of the substrate 10. In this embodiment, the substrate 10 is, for example, a silicon wafer, and the substrate 10 is, for example, a P-type silicon wafer.

[0038] See also Figure 1 As shown, in one embodiment of the present invention, a pad oxide layer 11 is formed on a substrate 10, and the pad oxide layer 11 is, for example, a material such as dense silicon oxide, and the pad oxide layer 11 can be prepared, for example, by thermal oxidation, in-situ steam growth (ISSG) or chemical vapor deposition (CVD) and other methods. A pad nitride layer 12 is formed on the pad oxide layer 11, and the pad nitride layer 12 is, for example, a silicon nitride layer, and the pad nitride layer 12 is formed, for example, by chemical vapor deposition and other methods. In the process of forming a shallow trench isolation structure, the pad oxide layer 11 can improve the stress between the substrate 10 and the pad nitride layer 12, and at the same time, it can protect the substrate 10 during the shallow trench etching process to prevent the substrate 10 from being damaged by high-energy ions. A patterned photoresist layer 13 is formed on the pad nitride layer 12 . A plurality of openings 131 are disposed on the patterned photoresist layer 13 . The openings 131 are used to define the positions of the shallow trench isolation structures. The openings 131 are, for example, equidistantly distributed. The openings 131 expose the pad nitride layer 12 .

[0039] See also Figure 1 to Figure 2As shown, in one embodiment of the present invention, after forming a patterned photoresist layer 13, the patterned photoresist layer 13 is used as a mask, and etching is performed in the direction of the substrate 10, for example, by dry etching, to remove the pad nitride layer 12, the pad oxide layer 11 and part of the substrate 10 exposed by the opening 131, so as to form a shallow trench. The etching gas, for example, includes one or a mixture of chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6) or hydrogen bromide (HBr), etc. After forming the shallow trench, for example, a liner oxide layer (not shown in the figure) is formed in the shallow trench by thermal oxidation to repair the etching damage in the process of forming the shallow trench and reduce the leakage of the integrated semiconductor device. An isolation medium is deposited in the shallow trench, for example, by high density plasma chemical vapor deposition (HDP-CVD) or high aspect ratio chemical vapor deposition (HARP-CVD), and the isolation medium is, for example, an insulating material such as silicon oxide. After the isolation medium is deposited, the isolation medium and the pad nitride layer 12 are planarized, for example, by chemical mechanical polishing (CMP) and other processes, and the pad nitride layer 12 is removed, for example, by wet etching, to form a shallow trench isolation structure 14, and a step is formed between the shallow trench isolation structure 14 and the pad oxide layer 11 on both sides, and the height of the step is selected according to the manufacturing requirements. For example, the pad oxide layer 11 is removed by wet etching, and part of the isolation medium is removed at the same time, and the step between the shallow trench isolation structure 14 and the pad oxide layer 11 on both sides is transferred to between the shallow trench isolation structure 14 and the substrate 10.

[0040] See also Figure 2As shown, in one embodiment of the present invention, after forming the shallow trench isolation structure 14, the shallow trench isolation structure 14 divides the substrate 10 into multiple regions, such as a high voltage region, a medium voltage region, and a low voltage region. In each region, for example, at least one positive channel metal oxide semiconductor field effect transistor (PMOS) and at least one negative channel metal oxide semiconductor field effect transistor (NMOS) are set, and the region where the PMOS transistor is formed is defined as a P region, and the region where the NMOS transistor is formed is defined as an N region. In this embodiment, for example, taking the example of dividing the substrate 10 into a high voltage N region (HVN), a high voltage P region (HVP), a medium voltage N region (MVN), a medium voltage P region (MVP), a low voltage N region (LVN), and a low voltage P region (LVP) distributed in sequence, the manufacturing method of the semiconductor device is described. After removing the pad oxide layer, a high-voltage gate dielectric layer 15 is formed on the substrate 10, wherein the high-voltage gate dielectric layer 15 is, for example, a silicon oxide layer, and the high-voltage gate dielectric layer 15 can be formed, for example, by a wet oxygen oxidation method. In the present embodiment, the thickness of the high-voltage gate dielectric layer 15 is, for example, 50nm to 120nm. In the present application, the relative height of the high-voltage gate dielectric layer 15 and the shallow trench isolation structure 14 is not specifically limited in the present application. In the present embodiment, for the sake of simplicity of the picture, the height of the high-voltage gate dielectric layer 15 shown in the accompanying drawings is consistent with that of the shallow trench isolation structure 14, but it does not represent the relationship between the heights in the actual manufacturing process. By simultaneously arranging transistors of different types and operating voltages on the same substrate 10, and isolating adjacent transistors by shallow trench isolation structures, production efficiency can be improved and production costs can be reduced.

[0041] See also Figures 2 to 3As shown, in one embodiment of the present invention, after forming the high-voltage gate dielectric layer 15, a photoresist layer (not shown in the figure) is formed on the substrate 10, and the photoresist layer is used as a mask and the high-voltage gate dielectric layer 15 is used as an ion implantation buffer layer to perform ion implantation on the substrate 10 to form a well region, and after forming a well region, the photoresist layer is removed to form a new photoresist layer, and ion implantation is performed again. In this embodiment, a doping region with a higher concentration than that of the substrate 10 is implanted with high implantation energy, and a first well region 101 is formed in the high-voltage N region, and a second well region 102 is formed in the high-voltage P region, wherein the ions implanted in the first well region 101 are, for example, P-type ions such as boron (B) or gallium (Ga), and the ions implanted in the second well region 102 are, for example, N-type impurities such as phosphorus (P), arsenic (As) or antimony (Sb), and the implantation amounts of the first well region 101 and the second well region 102 are, for example, equal. A third well region 103 is formed in the medium voltage N region, and a fourth well region 104 is formed in the medium voltage P region, wherein the ions injected into the third well region 103 are, for example, P-type ions such as boron or gallium, and the ions injected into the fourth well region 104 are, for example, N-type impurities such as phosphorus, arsenic or antimony, and the injection amounts of the third well region 103 and the fourth well region 104 are, for example, equal, or less than the injection amounts of the first well region 101 and the second well region 102. When forming well regions in the high voltage region and the low voltage region, the high voltage gate dielectric layer is used as an ion injection buffer layer, but the thickness of the high voltage gate dielectric layer is relatively large, and the partial loss of the thickness of the high voltage gate dielectric layer has little effect on the high voltage device.

[0042] See also Figure 3 to Figure 4 As shown, in one embodiment of the present invention, after forming well regions in the high-voltage region and the medium-voltage region, the high-voltage gate dielectric layer 15 on the medium-voltage region and the low-voltage region is removed. Specifically, a photoresist layer (not shown in the figure) is formed on the high-voltage region and the shallow trench isolation structure 14 on both sides. Using the photoresist layer as a mask, the high-voltage gate dielectric layer 15 on the medium-voltage region and the low-voltage region is removed by dry etching or wet etching. At the same time, part of the isolation dielectric in the shallow trench isolation structure 14 on the medium-voltage region and the low-voltage region is also etched. After etching, the shallow trench isolation structure 14 is still higher than the substrate 10.

[0043] See also Figure 4As shown, in one embodiment of the present invention, after removing the high-voltage gate dielectric layer 15 on the medium-voltage region and the low-voltage region, a medium-voltage gate dielectric layer 16 is formed on the substrate 10 in the medium-voltage region and the low-voltage region, and the medium-voltage gate dielectric layer 16 is, for example, a silicon oxide layer. In this embodiment, the medium-voltage gate dielectric layer 16 is obtained, for example, by a combination of one or more methods such as an in-situ water vapor growth method, chemical vapor deposition, or hydrothermal oxidation method, and the thickness of the medium-voltage gate dielectric layer 16 is, for example, 15nm~25nm. In one embodiment of the present invention, the medium-voltage gate dielectric layer 16 is formed, for example, by combining an in-situ water vapor growth method and chemical vapor deposition, so as to improve the contact performance of the interface between the medium-voltage gate dielectric layer 16 and the substrate 10, and improve the compactness and quality of the medium-voltage gate dielectric layer 16. After forming the medium voltage gate dielectric layer 16, a first protective layer 17 and a second protective layer 18 are sequentially formed on the high voltage gate dielectric layer 15 and the medium voltage gate dielectric layer 16, and the first protective layer 17 and the medium voltage gate dielectric layer 16 have an etching selectivity ratio, and the first protective layer 17 and the second protective layer 18 have an etching selectivity ratio.

[0044] See also Figure 4 As shown, in one embodiment of the present invention, the first protective layer 17 includes, for example, a silicon nitride layer, and the first protective layer 17 is obtained, for example, by methods such as low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The second protective layer 18 includes, for example, a polysilicon layer, and the second protective layer 18 is obtained, for example, by methods such as low pressure chemical vapor deposition. In this embodiment, the thickness of the first protective layer 17 is, for example, 15Å~25Å, and the thickness of the second protective layer 18 is, for example, 40Å~50Å. By controlling the thickness of the first protective layer 17 and the second protective layer 18, the total thickness of the protective layer can be reduced, thereby reducing the subsequent impact on ion implantation and improving the stability of the process. At the same time, the materials of the first protective layer 17 and the second protective layer 18 are selected to improve the etching selectivity of the adjacent medium-voltage gate dielectric layer 16, the first protective layer 17 and the second protective layer 18. In the subsequent multiple ion implantation processes and the photoresist removal process, damage and loss of the medium-voltage gate dielectric layer 16 can be avoided, and the quality and thickness stability of the medium-voltage gate dielectric layer 16 can be improved, thereby improving the yield of semiconductor devices.

[0045] See also Figures 4 to 5As shown, in one embodiment of the present invention, after forming the second protective layer 18, a first pattern photoresist layer 19 is formed on the second protective layer 18, and a first recess 191 is provided on the first pattern photoresist layer 19, and the first recess 191, for example, exposes the second protective layer 18 on the low-voltage N region. Using the first pattern photoresist layer 19 as a mask, and using the protective layer and the medium-voltage gate dielectric layer 16 as an ion implantation buffer layer, ion implantation is performed to form a fifth well region 105. The ions implanted into the fifth well region 105 are, for example, P-type ions such as boron or gallium. In this embodiment, when forming the fifth well region 105, the implantation energy is, for example, 405KeV~410KeV, and the implanted ion concentration is, for example, 3×10 13 atoms / cm 2 ~3.6×10 13 atoms / cm 2 When no protective layer is provided on the intermediate voltage gate dielectric layer 16, when the fifth well region is formed, the ion concentration injected is, for example, 3×10 13 atoms / cm 2 ~3.6×10 13 atoms / cm 2 Therefore, providing a protective layer on the medium voltage gate dielectric layer 16 has little effect on ion implantation, thereby improving the stability of the process.

[0046] See also Figures 5 and 6 As shown, in one embodiment of the present invention, after the fifth well region 105 is formed, the first pattern photoresist layer 19 is removed, for example, by wet etching, and the wet etching solution, such as sulfuric acid peroxide mixture (SPM) etching solution or standard clean 1 (SC1), can avoid the loss of the second protective layer 18 when removing the first pattern photoresist layer 19, wherein the SPM etching solution is a mixed solution of sulfuric acid and hydrogen peroxide (H2O2), and the SC1 etching solution is a mixed solution of deionized water, hydrogen peroxide and ammonium hydroxide (NH4OH). After removing the first pattern photoresist layer 19, a second pattern photoresist layer 20 is formed on the second protective layer 18, and a second recess 201 is provided on the second pattern photoresist layer 20, and the second recess 201, for example, exposes the second protective layer 18 on the low-voltage P region. The second pattern photoresist layer 20 is used as a mask, and the protective layer and the medium voltage gate dielectric layer 16 are used as an ion implantation buffer layer to perform ion implantation to form a sixth well region 106. The ions implanted into the sixth well region 106 are, for example, N-type impurities such as phosphorus, arsenic, or antimony. In this embodiment, when forming the sixth well region 106, the implantation energy is, for example, 405 KeV to 410 KeV, and the implanted ion concentration is, for example, 3×10 13 atoms / cm 2 ~3.6×10 13atoms / cm 2 When no protective layer is provided on the intermediate voltage gate dielectric layer 16, when the sixth well region is formed, the ion concentration injected is, for example, 3×10 13 atoms / cm 2 ~3.6×10 13 atoms / cm 2 , the injection energy is 400KeV. Therefore, providing a protective layer in the medium-voltage gate dielectric layer 16 has basically no effect on ion injection, so as to improve the stability of the process. In the present embodiment, the injection amounts in the sixth well region 106 and the fifth well region 105 are, for example, equal, and for example, less than the injection amounts in the third well region 103 and the fourth well region 104. That is, after the protective layer is formed, ion injection is performed. For example, when a well region is formed in a low-pressure area, under the same ion concentration, the injection energy when the second protective layer, the first protective layer and the medium-voltage gate dielectric layer are used as ion injection buffer layers is increased by 1% to 2.5% relative to the injection energy when the medium-voltage gate dielectric layer is used as an ion injection buffer layer, which basically does not affect the ion injection process.

[0047] See also Figure 6 to Figure 7 As shown, in one embodiment of the present invention, after the sixth well region 106 is formed, the second pattern photoresist layer 20 is removed, for example, by wet etching, and the wet etching solution, such as SPM etching solution or SC1 etching solution, can avoid the loss of the second protective layer 18 when removing the second pattern photoresist layer 20. By using the medium-voltage gate dielectric layer 16 as an ion implantation buffer layer in the well region of the low-voltage area, the process compatibility is improved, thereby improving production efficiency and reducing costs, and the doping concentration can be accurately controlled, and the well region of the low-voltage area is protected, the leakage current is reduced, and the reliability of the device is improved.

[0048] See also Figures 7 to 9 As shown, in one embodiment of the present invention, after removing the second pattern photoresist layer, the second protective layer 18 and the first protective layer 17 are removed in sequence. The second protective layer 18 is removed by wet etching using a first etching solution, for example, and the first etching solution is, for example, a mixed solution of hydrofluoric acid and nitric acid, the volume ratio of hydrofluoric acid to nitric acid is, for example, 1:40 to 1:60, the mass fraction of hydrofluoric acid is, for example, 35% to 47%, and the mass fraction of nitric acid is, for example, 60% to 70%. In this embodiment, the first etching solution is, for example, 40% hydrofluoric acid and 65% nitric acid mixed at a volume ratio of 1:50. During the etching process, the first etching solution does not react with silicon nitride. Therefore, in the process of removing the second protective layer 18, the first protective layer 17 is not lost, thereby ensuring the integrity of the first protective layer 17.

[0049] See also Figures 8 to 9As shown, in one embodiment of the present invention, after removing the second protective layer 18, the first protective layer 17 is removed. The first protective layer 17 is removed by wet etching using, for example, a second etching solution, and the second etching solution is, for example, hot phosphoric acid, the mass fraction of phosphoric acid is, for example, 86% to 95%, and the etching temperature is, for example, 150°C to 165°C. During the etching process, the second etching solution does not react with silicon oxide, so that in the process of removing the first protective layer 17, the medium-voltage gate dielectric layer 16 is not lost, ensuring the integrity of the medium-voltage gate dielectric layer 16, thereby improving the stability and yield of the semiconductor device.

[0050] See also Figure 8 and Fig.10 As shown, in one embodiment of the present invention, different etching solutions have different etching rates for the medium-voltage gate dielectric layer 16, the first protective layer 17, and the second protective layer 18. Among them, the SPM etching solution or the SC1 etching solution does not etch polysilicon, the SPM etching solution can etch silicon nitride, and the SC1 etching solution can nitride silicon and silicon oxide, that is, the etching solution that removes the pattern photoresist layer does not etch the second protective layer. The first etching solution, which is a mixture of hydrofluoric acid and nitric acid, has a very fast etching rate for the second protective layer 18, and will also etch silicon oxide, but basically does not etch silicon nitride. The second etching solution, phosphoric acid, can etch silicon nitride, but does not etch silicon oxide and polysilicon. Therefore, in the present application, the first protective layer 17 and the second protective layer 18 are formed on the medium-voltage gate dielectric layer 16. After ion implantation, in the process of removing the photoresist layer, the etching of the second protective layer 18 can be avoided, and the etching of the protective layer due to the removal of too many photoresist layers can be avoided, and the damage of the medium-voltage gate dielectric layer 16 can be further avoided. Therefore, after forming the medium voltage gate dielectric layer 16, multiple ion implantations can be performed according to the customized requirements of the semiconductor device, for example, using the medium voltage gate dielectric layer 16 as an ion implantation buffer layer. During the multiple ion implantations and photoresist layer removal processes, damage and loss to the medium voltage gate dielectric layer 16 can be avoided, thereby improving the quality of the medium voltage gate dielectric layer 16 and the yield of the semiconductor device. The first protective layer 17 and the second protective layer 18 can be removed independently, further avoiding damage to the medium voltage gate dielectric layer 16 and improving the yield. By using a high etching selectivity, the thickness of the first protective layer 17 and the second protective layer 18 can be reduced, reducing the impact on ion implantation.

[0051] See also Fig. 9 and Fig.11As shown, in one embodiment of the present invention, after removing the first protective layer, the medium-voltage gate dielectric layer 16 on the low-voltage area is removed. Specifically, a photoresist layer (not shown in the figure) is formed on the high-voltage area, the medium-voltage area, and the shallow trench isolation structure 14 in the high-voltage area and the medium-voltage area. The photoresist layer exposes the low-voltage area. Using the photoresist layer as a mask, the medium-voltage gate dielectric layer 16 on the low-voltage area is removed by dry etching or wet etching. At the same time, part of the isolation dielectric in the shallow trench isolation structure 14 on the low-voltage area is also etched. After etching, the shallow trench isolation structure 14 is still higher than the substrate 10.

[0052] See also Fig.11 As shown, in one embodiment of the present invention, after removing the medium-voltage gate dielectric layer 16 on the low-voltage area, a low-voltage gate dielectric layer 21 is formed on the substrate 10 in the low-voltage area, and the low-voltage gate dielectric layer 21 is, for example, a silicon oxide layer. In this embodiment, the low-voltage gate dielectric layer 21 is obtained, for example, by a dry thermal oxidation method, a wet thermal oxidation method, or an in-situ water vapor growth method. In this embodiment, the thickness of the low-voltage gate dielectric layer 21 is, for example, 10Å~20Å, that is, the thickness of the high-voltage gate dielectric layer 15 is greater than the thickness of the medium-voltage gate dielectric layer 16, and the thickness of the medium-voltage gate dielectric layer 16 is greater than the thickness of the low-voltage gate dielectric layer 21, so as to meet the manufacturing requirements of semiconductor devices with different threshold voltages.

[0053] See also Figure 11 to Figure 12 As shown, in one embodiment of the present invention, after forming the low-voltage gate dielectric layer 21, a gate structure 22 is formed on the gate dielectric layer. Specifically, a gate material layer (not shown in the figure) is formed on the substrate 10, and the gate material layer covers the shallow trench isolation structure 14, the high-voltage gate dielectric layer 15, the medium-voltage gate dielectric layer 16 and the low-voltage gate dielectric layer 21. Among them, the gate material layer is, for example, polysilicon, and the polysilicon can be doped or undoped as needed. Then a photoresist layer (not shown in the figure) is formed on the gate material layer to locate the position of the gate structure. Using the photoresist layer as a mask, for example, by wet etching, dry etching or a combination of wet etching and dry etching, the gate material layer exposed by the photoresist layer is removed to form a plurality of gate structures 22. The gate structures 22 are respectively located on the high-voltage N region (HVN), the high-voltage P region (HVP), the medium-voltage N region (MVN), the medium-voltage P region (MVP), the low-voltage N region (LVN) and the low-voltage P region (LVP).

[0054] See also Figure 12 to Figure 13As shown, in one embodiment of the present invention, after forming the gate structure 22, lightly doped regions are formed in the substrate 10 on both sides of the gate structure 22. The lightly doped regions, for example, include a first lightly doped region 111, a second lightly doped region 112, a third lightly doped region 113, a fourth lightly doped region 114, a fifth lightly doped region 115, and a sixth lightly doped region 116, and the first lightly doped region 111 is arranged in the high-voltage N region, and the doping type is N-type doping, the second lightly doped region 112 is arranged in the high-voltage P region, and the doping type is P-type doping, the third lightly doped region 113 is arranged in the medium-voltage N region, and the doping type is N-type doping, the fourth lightly doped region 114 is arranged in the medium-voltage P region, and the doping type is P-type doping, the fifth lightly doped region 115 is arranged in the low-voltage N region, and the doping type is N-type doping, and the sixth lightly doped region 116 is arranged in the low-voltage P region, and the doping type is P-type doping. The present application does not limit the doping concentrations of the first lightly doped region 111, the second lightly doped region 112, the third lightly doped region 113, the fourth lightly doped region 114, the fifth lightly doped region 115, and the sixth lightly doped region 116, which are set according to the device manufacturing requirements. In the process of forming the lightly doped region, a gate dielectric layer is provided on the substrate, which can reduce the damage of the injected energy to the substrate and improve the reliability and performance of the device.

[0055] See also Figure 13 to Figure 14 As shown, in one embodiment of the present invention, after forming the lightly doped region, a sidewall structure 23 is formed on both sides of the gate structure 22, wherein the sidewall structure 23 is, for example, a single-layer structure or a stacked structure. In this embodiment, the sidewall structure 23 includes, for example, a stack of silicon oxide and silicon nitride to ensure the stability of the sidewall structure. Specifically, a sidewall dielectric layer (not shown in the figure) is formed on the substrate 10, the sidewall dielectric layer covers the gate structure 22, the substrate 10 and the shallow trench isolation structure 14, and the material of the sidewall dielectric layer is, for example, a stack of silicon oxide and silicon nitride. After the sidewall dielectric layer is formed, for example, an etching process such as dry etching can be used to remove the sidewall dielectric layer and part of the gate dielectric layer on the gate structure and part of the substrate 10, and part of the sidewall dielectric layer on both sides of the gate structure is retained to form the sidewall structure 23, and the height of the sidewall structure 23 is the same as the height of the gate structure. In this embodiment, the shape of the sidewall structure 23 is, for example, an arc shape, and in other embodiments, the sidewall structure 23 can be selected in any shape.

[0056] See also Figure 14 to Figure 15As shown, in one embodiment of the present invention, after the spacer structure 23 is formed, heavy doping is formed in the substrate 10 on both sides of the gate structure, and the heavy doping region is, for example, aligned with the side of the spacer structure 23 away from the gate structure 22. The heavily doped region, for example, includes a first heavily doped region 121, a second heavily doped region 122, a third heavily doped region 123, a fourth heavily doped region 124, a fifth heavily doped region 125, and a sixth heavily doped region 126, and the first heavily doped region 121 is set in the high-voltage N region, and the doping type is N-type doping, the second heavily doped region 122 is set in the high-voltage P region, and the doping type is P-type doping, the third heavily doped region 123 is set in the medium-voltage N region, and the doping type is N-type doping, the fourth heavily doped region 124 is set in the medium-voltage P region, and the doping type is P-type doping, the fifth heavily doped region 125 is set in the low-voltage N region, and the doping type is N-type doping, and the sixth heavily doped region 126 is set in the low-voltage P region, and the doping type is P-type doping. The present application does not limit the doping concentrations of the first heavily doped region 121, the second heavily doped region 122, the third heavily doped region 123, the fourth heavily doped region 124, the fifth heavily doped region 125, and the sixth heavily doped region 126, which are set according to the device manufacturing requirements. After the heavily doped regions are formed, the interlayer dielectric layer, the metal connection structure, and the metal layer can be manufactured, which will not be elaborated here.

[0057] In summary, the present invention provides a method for manufacturing an integrated semiconductor device. By improving the method for manufacturing an integrated semiconductor device, the unexpected technical effect of the present invention is that after forming a medium-voltage gate dielectric layer, according to the customized requirements of the semiconductor device, during multiple ion implantations and photoresist layer removal processes, damage and loss to the medium-voltage gate dielectric layer can be avoided, thereby improving the quality of the medium-voltage gate dielectric layer and improving the yield of the semiconductor device. The thickness of the first protective layer and the second protective layer can be reduced to reduce the impact on ion implantation. The first protective layer and the second protective layer can be removed independently to further avoid damage to the medium-voltage gate dielectric layer, further improving the stability and yield of the semiconductor device. The process compatibility can be improved, thereby improving production efficiency and reducing costs, the doping concentration can be accurately controlled, and the well area in the low-voltage area can be protected, leakage current can be reduced, and the reliability of the device can be improved.

[0058] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing an integrated semiconductor device, characterized in that: include: Providing a substrate, wherein the substrate comprises a high-pressure region, a medium-pressure region and a low-pressure region; forming a high voltage gate dielectric layer on the substrate; Using the high-voltage gate dielectric layer as an ion implantation buffer layer, forming well regions in the high-voltage region and the medium-voltage region; Removing the high-voltage gate dielectric layer on the medium-voltage region and the low-voltage region; forming a medium-voltage gate dielectric layer on the medium-voltage region and the low-voltage region; Sequentially forming a first protective layer and a second protective layer on the medium voltage gate dielectric layer and the high voltage gate dielectric layer, wherein the first protective layer and the second protective layer have an etching selectivity ratio; forming a well region in the low pressure region; removing the second protective layer and the first protective layer; Removing the medium voltage gate dielectric layer on the low voltage area; as well as A low-voltage gate dielectric layer is formed on the low-voltage region.

2. The method for manufacturing an integrated semiconductor device according to claim 1, characterized in that: The first protective layer includes a silicon nitride layer, and the thickness of the first protective layer is 15Å~25Å.

3. The method for manufacturing an integrated semiconductor device according to claim 1, characterized in that: The second protective layer includes a polysilicon layer, and the thickness of the second protective layer is 40Å~50Å.

4. The method for manufacturing an integrated semiconductor device according to claim 1, characterized in that: The manufacturing method further comprises: forming a first pattern photoresist layer on the second protective layer, wherein the first pattern photoresist layer exposes the low-voltage N region on the low-voltage area; Using the first patterned photoresist layer as a mask, the second protective layer, the first protective layer and the medium-voltage gate dielectric layer as an ion implantation buffer layer to perform ion implantation to form a well region in the low-voltage N region; removing the first pattern photoresist layer by wet etching; forming a second pattern photoresist layer on the second protective layer, wherein the second pattern photoresist layer exposes the low-voltage P region on the low-voltage area; Using the second patterned photoresist layer as a mask, the second protective layer, the first protective layer and the medium-voltage gate dielectric layer as an ion implantation buffer layer to perform ion implantation to form a well region in the low-voltage P region; The second pattern photoresist layer is removed by wet etching.

5. The method for manufacturing an integrated semiconductor device according to claim 4, characterized in that: The etching solution for removing the first pattern photoresist layer and / or the second pattern photoresist layer is at least one of SPM etching solution and SC1 etching solution.

6. The method for manufacturing an integrated semiconductor device according to claim 5, characterized in that: The SPM etching solution or the SC1 etching solution does not etch the second protective layer.

7. The method for manufacturing an integrated semiconductor device according to claim 4, characterized in that: When a well region is formed in the low-voltage region, at the same ion injection concentration, the injection energy when the second protective layer, the first protective layer and the medium-voltage gate dielectric layer are used as ion injection buffer layers is increased by 1% to 2.5% relative to the injection energy when the medium-voltage gate dielectric layer is used as the ion injection buffer layer.

8. The method for manufacturing an integrated semiconductor device according to claim 1, characterized in that: The second protective layer is removed by wet etching using a first etching solution, wherein the first etching solution is a mixed solution of hydrofluoric acid and nitric acid, and the volume ratio of the hydrofluoric acid to the nitric acid is, for example, 1:40-1:

60.

9. The method for manufacturing an integrated semiconductor device according to claim 1, characterized in that: The first protective layer is removed by wet etching using a second etching solution, and the second etching solution is phosphoric acid, the mass fraction of the phosphoric acid is 86%-95%, and the etching temperature is 150°C-165°C.

10. The method for manufacturing an integrated semiconductor device according to claim 1, characterized in that: The thickness of the high-voltage gate dielectric layer is greater than the thickness of the medium-voltage gate dielectric layer, and the thickness of the medium-voltage gate dielectric layer is greater than the thickness of the low-voltage gate dielectric layer.

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