Light-induced degradation resistant back contact battery, manufacturing method thereof and photovoltaic module

Abstract

The invention provides a light-induced degradation resistant back contact battery and a manufacturing method thereof, and a photovoltaic module, and relates to the technical field of back contact batteries, the battery comprises a silicon wafer, a first semiconductor layer and a second semiconductor layer; the silicon wafer has a front surface and a back surface; the first semiconductor layers and the second semiconductor layers are alternately arranged on the back surface of the silicon wafer; a second tunneling oxide layer, a hydrogenated amorphous silicon layer, a third tunneling oxide layer and a silicon nitride layer are sequentially laid on the front surface of the silicon wafer; the thickness of the second tunneling oxide layer is 1-3nm, the thickness of the third tunneling oxide layer is 1.5-3nm, and the hydrogen content of the hydrogenated amorphous silicon layer is 1e < 19 >-1e < 21 > cm <-3 >. The structure of the oxide layer, the hydrogenated amorphous silicon layer, the oxide layer and the silicon nitride layer is used, a double-oxide-layer structure is introduced to serve as a barrier layer for hydrogen dissipation, hydrogen can be effectively prevented from diffusing towards bulk silicon and overflowing outwards under the photo-thermal condition, meanwhile, the passivation level is not affected due to the excellent passivation effect of the tunneling oxide layer, and the service life of the device is prolonged. The efficient back contact solar cell capable of resisting light-induced degradation is realized.

Description

Technical Field

[0001] The present application relates to the technical field of back-contact cells, and in particular to a back-contact cell resistant to photo-induced degradation, a manufacturing method thereof, and a photovoltaic module. Background Art

[0002] In the prior art, there are two main methods for preparing the front structure of a back-contact battery using a tubular device.

[0003] The first method is to use tubular ALD and PECVD to prepare an aluminum oxide passivation layer and a silicon nitride anti-reflection layer; the second method is to directly use tubular PECVD to prepare a hydrogenated amorphous silicon passivation layer and a silicon nitride anti-reflection layer.

[0004] Compared with the two methods, the structure of using tubular PECVD to prepare hydrogenated amorphous silicon passivation layer and silicon nitride anti-reflection layer has significant advantages in equipment cost. However, compared with the structure of aluminum oxide passivation layer and silicon nitride anti-reflection layer, the structure of hydrogenated amorphous silicon passivation layer and silicon nitride anti-reflection layer has serious attenuation in the light induced attenuation (LID) test.

[0005] The main reason for the above situation is that in order to ensure the passivation level, the hydrogen content in the hydrogenated amorphous silicon passivation layer is relatively high. Under the photothermal conditions prepared using tubular PECVD, the hydrogen in the hydrogenated amorphous silicon passivation layer will diffuse into the bulk silicon and overflow outward, resulting in a serious decrease in the passivation effect.

[0006] The Chinese patent with patent number CN118398679A discloses a combined passivated back contact cell with specific passivation on the light-receiving surface and its preparation and application, including a silicon substrate, a first semiconductor layer and a second semiconductor layer alternately arranged on the back of the silicon substrate, and also including a second tunneling oxide layer, an ultra-thin amorphous silicon layer and an anti-reflection layer arranged in sequence on the light-receiving surface of the silicon substrate. The thickness of the ultra-thin amorphous silicon layer is 0.5-3nm, and the ratio of the thickness of the second tunneling oxide layer to the ultra-thin amorphous silicon layer is 0.15-1:1.

[0007] However, the patent still has the following points to be improved: In order to improve the light transmittance, the patent uses an ultra-thin amorphous silicon layer, and sets a tunnel oxide layer between the ultra-thin amorphous silicon layer and the light-receiving surface of the silicon substrate. However, under high temperature conditions, because the thickness of the ultra-thin amorphous silicon layer is small, it is easier for hydrogen to overflow to the silicon substrate and the outside. Although a tunnel oxide layer is set to block the diffusion of hydrogen to the bulk silicon, there is still a situation where hydrogen will overflow, but the patent does not take this technical problem into consideration.

[0008] The Chinese patent with patent number CN118825140B discloses a method for manufacturing a multi-layer tunneling oxidation passivated back-contact battery and a back-contact battery, including depositing a first oxide layer, a second oxide layer and an oxygen-doped amorphous silicon layer in sequence on the front side of a silicon wafer to form a passivation layer, and then depositing an anti-reflection layer; the first oxide layer is formed by air thermal oxidation deposition by heating the air without vacuuming, and the second oxide layer is formed by tubular PECVD deposition in a vacuum state and with nitrous oxide introduced, the thickness ratio of the first oxide layer to the second oxide layer is controlled to be 1:(0.6-3.4), the thickness of the first oxide layer is 0.6-1.2nm, and the ratio of the sum of the thickness of the first oxide layer and the second oxide layer to the thickness of the oxygen-doped amorphous silicon layer is 1:(0.3-10.8).

[0009] The patent has the following points for improvement: In order to improve the passivation level of the tunnel oxide layer, the patent combines thermal oxidation and tubular PECVD nitrous oxide oxidation. Although it mentions the thickness ratio of the oxide layer and the oxygen-doped amorphous silicon layer, its essential purpose is to improve the density of the tunnel oxide layer through a special tunnel oxide layer deposition method, thereby improving the passivation level. However, the density of the tunnel oxide layer has no significant effect on the escape of hydrogen, so the invention patent still has the situation of hydrogen escaping outward, and the invention patent does not take into account the technical problem of light-induced attenuation.

[0010] Therefore, there is an urgent need to provide a back contact battery to solve the above technical problems.

[0011] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0012] In view of this, the purpose of the present application is to provide a back-contact cell that is resistant to photo-induced degradation, a method for making the same, and a photovoltaic module, so as to at least solve the problem of serious photo-induced degradation in the prior art structure that uses tubular PECVD to prepare a hydrogenated amorphous silicon passivation layer and a silicon nitride anti-reflection layer. The present application uses a structure of an oxide layer + a hydrogenated amorphous silicon layer + an oxide layer + a silicon nitride layer, and introduces a double oxide layer structure as a barrier layer for hydrogen escape, which can effectively isolate hydrogen from diffusing into the bulk silicon and overflowing outward under photothermal conditions. At the same time, the excellent passivation effect of the tunneling oxide layer ensures that the passivation level will not be affected, thereby realizing a highly efficient and photo-induced degradation-resistant back-contact solar cell.

[0013] In a first aspect, the present application provides a back-contact cell with resistance to light-induced degradation, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer; the silicon wafer has a front side and a back side; the first semiconductor layer and the second semiconductor layer are alternately arranged on the back side of the silicon wafer; a second tunneling oxide layer, a hydrogenated amorphous silicon layer, a third tunneling oxide layer and a silicon nitride layer are sequentially laid on the front side of the silicon wafer; the thickness of the second tunneling oxide layer is 1-3 nm, the thickness of the third tunneling oxide layer is 1.5-3 nm, and the hydrogen content of the hydrogenated amorphous silicon layer is 1e19-1e21 cm -3 .

[0014] In some embodiments, the thickness of the hydrogenated amorphous silicon layer is 7-12 nm.

[0015] In some embodiments, the thickness of the silicon nitride layer is 80-120 nm.

[0016] In some embodiments, the first semiconductor layer includes a first tunneling oxide layer and a first doped silicon layer, the first tunneling oxide layer has a thickness of 1-2 nm, the first doped silicon layer has a thickness of 150-300 nm, and the effective doping concentration of the first doped silicon layer is 1e20-1e21 cm -3 .

[0017] In some embodiments, the second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer, the thickness of the intrinsic amorphous silicon layer is 5-15 nm, the thickness of the second doped silicon layer is 10-35 nm, and the effective doping concentration of the second doped silicon layer is 1e19-4e20 cm -3 .

[0018] In some embodiments, the thickness ratio of the hydrogenated amorphous silicon layer, the first tunnel oxide layer, and the intrinsic amorphous silicon layer is 1:(0.1-0.21):(0.5-1.43).

[0019] In some embodiments, the ratio of the hydrogen content of the hydrogenated amorphous silicon layer, the effective doping concentration of the first doped silicon layer, and the effective doping concentration of the second doped silicon layer is 1:(0.2-50):(0.02-10).

[0020] In some embodiments, a second semiconductor opening region is provided between adjacent first semiconductor layers, and two ends of the second semiconductor layer located in the second semiconductor opening region extend toward a surface of the adjacent first semiconductor layer by a preset distance and overlap with the surface to form an overlapping region.

[0021] In some embodiments, the back-contact cell resistant to photo-induced degradation also includes a conductive film layer, which is laid on the first semiconductor layer and the second semiconductor layer. The thickness of the conductive film layer is 40-80nm. The conductive film layer is provided with isolation grooves at each overlapping area, and the width of the isolation grooves is 30-200μm.

[0022] In some embodiments, the back-contact cell resistant to photodegradation further includes a first electrode and a second electrode, which are respectively disposed in a first semiconductor opening region and a second semiconductor opening region; the first semiconductor opening region is disposed in a portion outside the overlapping region on the first semiconductor layer.

[0023] In a second aspect, the present application provides a method for preparing a back-contact cell resistant to light-induced degradation, the preparation method comprising the following steps: S1, provide double-sided polished silicon wafers; S2, depositing a first semiconductor layer and a mask layer on the back side of the silicon wafer; S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region arranged at intervals; S4, removing the first semiconductor layer remaining in the second semiconductor opening region by texturing, and forming a velvet surface on the front side of the silicon wafer and the second semiconductor opening region, and then removing the mask layer outside the second semiconductor opening region on the back side of the silicon wafer during the cleaning process of the velvet surface; S5, using tubular PECVD to sequentially lay a second tunnel oxide layer, a hydrogenated amorphous silicon layer, a third tunnel oxide layer and a silicon nitride layer on the front side of the silicon wafer through chemical reaction; The thickness of the second tunnel oxide layer is 1-3 nm, the thickness of the third tunnel oxide layer is 1.5-3 nm, and the hydrogen content of the hydrogenated amorphous silicon layer is 1e19-1e21 cm -3 ; S6, removing the plating layer deposited on the back side of the silicon wafer in S5 and cleaning the second semiconductor opening area again; S7. Depositing a second semiconductor layer on the back side of the silicon wafer.

[0024] In some embodiments, in S5 , the second tunnel oxide layer is formed by thermal oxidation with oxygen.

[0025] In some embodiments, in S5, the second tunnel oxide layer is formed by using a nitrous oxide plasma glow reaction, and the reaction conditions are: a reaction temperature of 400-450° C., a reaction pressure of 100-3000 mtorr, and a reaction time of 10-120 seconds.

[0026] In some embodiments, in S5, the hydrogenated amorphous silicon layer is formed by chemical reaction of silane, phosphine, hydrogen and carbon dioxide under glow conditions, and the reaction conditions are: reaction temperature of 400-450°C, hydrogen flow rate of 3000-6000sccm, reaction time of 200-500 seconds, and reaction pressure of 800-3000mtorr.

[0027] In some embodiments, in S5, the third tunnel oxide layer is formed by using a nitrous oxide plasma glow reaction, and the reaction conditions are: a reaction temperature of 400-450° C., a reaction pressure of 100-3000 mtorr, and a reaction time of 30-120 seconds.

[0028] In some embodiments, in S5 , the silicon nitride layer is formed by chemical reaction of silane and ammonia under glow conditions.

[0029] In some embodiments, the preparation method further comprises: S8, performing a second etching opening on the second semiconductor layer to form first semiconductor opening regions that are alternately arranged with and spaced from the second semiconductor opening regions; S9, depositing a conductive film layer on the back surface obtained in S8; S10, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; S11 , forming a first electrode and a second electrode in the first semiconductor opening region and the second semiconductor opening region respectively.

[0030] In a third aspect, the present application also provides a photovoltaic module, which includes the aforementioned back-contact cell resistant to photodegradation.

[0031] The beneficial effects that this application can achieve are: 1. Compared with the prior art that directly uses tubular PECVD equipment to prepare hydrogenated amorphous silicon passivation layer and silicon nitride anti-reflection layer, the present application uses a structure of oxide layer + amorphous silicon + oxide layer + silicon nitride, and introduces a double oxide layer structure as a barrier layer for hydrogen escape, which can effectively isolate hydrogen from diffusing into bulk silicon and overflowing outward under photothermal conditions. At the same time, the excellent passivation effect of the tunneling oxide layer ensures that the passivation level will not be affected.

[0032] 2. The prior art (CN118398679A) adopts a structure of a single-layer tunneling oxide layer + an ultra-thin amorphous silicon layer. Under high temperature conditions, the single-layer tunneling oxide layer cannot prevent the hydrogen from overflowing. The present application adopts an amorphous silicon layer of normal thickness, which can reduce the difficulty of preparation. At the same time, the passivation performance is also better than that of the ultra-thin amorphous silicon layer. The double oxide layer structure can effectively isolate hydrogen from diffusing into the bulk silicon and overflowing outward under photothermal conditions, while avoiding affecting the passivation level. At the same time, the present application also found that setting a tunneling oxide layer on the outside of the amorphous silicon layer can reduce the light attenuation of the battery without affecting the performance of the battery itself. Furthermore, subsequent experiments have also proved that the passivation level and the effect of the ultra-thin amorphous silicon layer on anti-photodegradation are not ideal.

[0033] 3. The structure of tunneling oxide layer + amorphous silicon + tunneling oxide layer + silicon nitride used in this application adopts a suitable thickness of the tunneling oxide layer, which can effectively isolate the escape of hydrogen while avoiding affecting the optical performance of the front side of the battery. In addition, the thickness of the tunneling oxide layer of this application is matched with the hydrogen content of the amorphous silicon layer, realizing a high-efficiency and light-induced degradation-resistant back-contact solar cell.

[0034] 4. In the present application, the thickness ratios of the hydrogenated amorphous silicon layer, the first tunnel oxide layer, and the intrinsic amorphous silicon layer have a specific relationship. The hydrogen content of the hydrogenated amorphous silicon layer, the effective doping concentration of the first doped silicon layer, and the effective doping concentration of the second doped silicon layer also have a specific relationship. The parameters on the front and back sides of the present application have a synergistic effect, which is more conducive to improving the passivation effect of the battery, thereby improving the conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 A schematic diagram of the structure of a back contact cell resistant to light-induced degradation in step S1 of Example 1 of the present application is shown; Figure 2 A schematic diagram of the structure of a back contact cell resistant to light-induced degradation in step S2 of Example 1 of the present application is shown; Figure 3 A schematic diagram of the structure of a back contact cell resistant to light-induced degradation in step S3 and step S4 of Example 1 of the present application is shown; Figure 4 A schematic diagram of the structure of a back contact cell resistant to light-induced degradation in step S5 and step S6 of Example 1 of the present application is shown; Figure 5 A schematic diagram of the structure of a back contact cell resistant to light-induced degradation in step S7 and step S8 of Example 1 of the present application is shown; Figure 6 A schematic diagram of the structure of a back contact cell resistant to light-induced degradation in step S9 and step S10 of Example 1 of the present application is shown; Figure 7 A schematic structural diagram of a back-contact cell resistant to photo-induced degradation in step S11 of Example 1 of the present application is shown.

[0037] Description of reference numerals: 1. Silicon wafer; 2. First tunneling oxide layer; 3. N-type doped polysilicon layer; 4. Mask layer; 5. Second tunneling oxide layer; 6. Hydrogenated amorphous silicon layer; 7. Third tunneling oxide layer; 8. Silicon nitride layer; 9. Intrinsic amorphous silicon layer; 10. P-type doped amorphous silicon layer; 11. Conductive film layer. DETAILED DESCRIPTION

[0038] The term "comprising" in the specification and claims of the present application and the drawings is synonymous with "including", "containing" or "characterized by", and is inclusive or open-ended, and does not exclude additional undescribed elements or method steps. "Comprising" is a technical term used in the claim language, meaning that the elements are present, but other elements may also be added and still form a structure or method within the scope of the claim.

[0039] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance. The term "about" in this application means to include a small change (up to + / -10%) from the stated value.

[0040] In the first aspect, the present application provides a back-contact cell that is resistant to photodegradation, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer; the silicon wafer has a front side and a back side; the first semiconductor layer and the second semiconductor layer are alternately arranged on the back side of the silicon wafer; a second tunneling oxide layer, a hydrogenated amorphous silicon layer, a third tunneling oxide layer and a silicon nitride layer are sequentially layered on the front side of the silicon wafer; the thickness of the second tunneling oxide layer is 1-3nm, which can be 1nm, 1.5nm, 2nm, 2.5nm, 3nm and any value therebetween.

[0041] The thickness of the third tunnel oxide layer is 1.5-3 nm, and may be 1.5 nm, 2 nm, 2.5 nm, 3 nm, or any value therebetween.

[0042] The hydrogen content of the hydrogenated amorphous silicon layer is 1e19-1e21cm -3 , which can be 1e19cm -3 、5e19cm -3 , 1e20cm -3 、5e20cm -3 , 1e21cm -3 and any values ​​in between.

[0043] The structure of tunneling oxide layer + amorphous silicon + tunneling oxide layer + silicon nitride used in this application adopts a suitable thickness of the tunneling oxide layer, which can effectively isolate the escape of hydrogen while avoiding affecting the optical performance of the front side of the battery. In addition, the thickness of the tunneling oxide layer of this application is matched with the hydrogen content of the amorphous silicon layer, realizing a high-efficiency and light-induced degradation-resistant back-contact solar cell.

[0044] In some embodiments, the thickness of the hydrogenated amorphous silicon layer is 7-12nm, which can be 7nm, 8nm, 9nm, 10nm, 11nm, 12nm and any value therebetween. Compared with ultra-thin amorphous silicon layers, hydrogenated amorphous silicon layers above 7nm are more easily compatible with existing semiconductor manufacturing processes during the preparation process, and do not require precise control of the thickness of the amorphous silicon layer, which can reduce production costs and complexity. In addition, the present application reasonably sets the thickness of the hydrogenated amorphous silicon layer, which is conducive to balancing the passivation effect and light absorption efficiency of the hydrogenated amorphous silicon layer, thereby improving the battery conversion efficiency.

[0045] In some embodiments, the thickness of the silicon nitride layer is 80-120 nm, and may be 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, and any value therebetween.

[0046] It should be noted that the silicon nitride layer in the present application is an anti-reflection layer. In addition to the silicon nitride layer, other silicon dielectric anti-reflection layers, more specifically silicon oxynitride, silicon oxide, etc., are also within the protection scope of the present application.

[0047] In some embodiments, the first semiconductor layer includes a first tunneling oxide layer and a first doped silicon layer, the first tunneling oxide layer has a thickness of 1-2 nm, the first doped silicon layer has a thickness of 150-300 nm, and the effective doping concentration of the first doped silicon layer is 1e20-1e21 cm -3 The first doped silicon layer is an N-type doped polysilicon layer.

[0048] The present application adopts appropriate thicknesses of the first tunneling oxide layer and the first doped silicon layer, and appropriate effective doping concentration of the first doped silicon layer, which is more conducive to improving the battery conversion efficiency.

[0049] In some embodiments, the second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer, the thickness of the intrinsic amorphous silicon layer is 5-15 nm, the thickness of the second doped silicon layer is 10-35 nm, and the effective doping concentration of the second doped silicon layer is 1e19-4e20 cm -3 The second doped silicon layer is a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer.

[0050] The present application adopts appropriate thicknesses of the second tunneling oxide layer and the second doped silicon layer, and appropriate effective doping concentration of the second doped silicon layer, which is more conducive to improving the battery conversion efficiency.

[0051] In some embodiments, the thickness ratio of the hydrogenated amorphous silicon layer, the first tunnel oxide layer, and the intrinsic amorphous silicon layer is 1:(0.1-0.21):(0.5-1.43).

[0052] In some embodiments, the ratio of the hydrogen content of the hydrogenated amorphous silicon layer, the effective doping concentration of the first doped silicon layer, and the effective doping concentration of the second doped silicon layer is 1:(0.2-50):(0.02-10).

[0053] The thickness ratios of the hydrogenated amorphous silicon layer, the first tunnel oxide layer, and the intrinsic amorphous silicon layer of the present application have a specific relationship. The hydrogen content of the hydrogenated amorphous silicon layer, the effective doping concentration of the first doped silicon layer, and the effective doping concentration of the second doped silicon layer also have a specific relationship. The parameters on the front and back sides of the present application have a synergistic effect, which is more conducive to improving the passivation effect of the battery, thereby improving the conversion efficiency of the battery.

[0054] In some embodiments, a second semiconductor opening region is provided between adjacent first semiconductor layers, and two ends of the second semiconductor layer located in the second semiconductor opening region extend toward a surface of the adjacent first semiconductor layer by a preset distance and overlap with the surface to form an overlapping region.

[0055] In some embodiments, the back-contact cell resistant to photo-induced degradation also includes a conductive film layer, which is laid on the first semiconductor layer and the second semiconductor layer. The thickness of the conductive film layer is 40-80nm. The conductive film layer is provided with isolation grooves at each overlapping area, and the width of the isolation grooves is 30-200μm.

[0056] The conductive film layer is deposited by physical vapor deposition technology (PVD) or activated plasma deposition technology (RPD), and the conductive film layer is an indium oxide-based film doped with tin, zinc, tungsten, titanium, etc., or a zinc oxide-based film doped with aluminum, boron, gallium, etc.

[0057] In some embodiments, the back-contact cell resistant to photodegradation further includes a first electrode and a second electrode, which are respectively disposed in a first semiconductor opening region and a second semiconductor opening region; the first semiconductor opening region is disposed in a portion outside the overlapping region on the first semiconductor layer.

[0058] It is understandable that the first electrode and the second electrode have two polarities, and the polarities of the first electrode and the second electrode are different. The first electrode and the second electrode can be formed by printing silver paste to form a silver paste grid line electrode, electroplating to form a grid line electrode, etc.

[0059] In a second aspect, the present application provides a method for preparing a back-contact cell resistant to light-induced degradation, the preparation method comprising the following steps: S1, provide double-sided polished silicon wafers; The silicon wafer is an N-type single crystal silicon wafer, and the silicon wafer is a CZ single crystal silicon wafer or a cast single crystal silicon wafer.

[0060] S2, depositing a first semiconductor layer and a mask layer on the back side of the silicon wafer; The first semiconductor layer includes a first tunneling oxide layer and a first doped silicon layer, wherein the first doped silicon layer is an N-type doped polysilicon layer. The first semiconductor layer can be formed by tubular PECVD, LPCVD or PVD in-situ doping deposition annealing, preferably tubular PECVD in-situ doping.

[0061] The first tunnel oxide layer is formed by using a nitrous oxide plasma glow reaction, and the reaction conditions are: a reaction temperature of 400-450° C., a reaction pressure of 100-2000 mtorr, and a reaction time of 10-60 seconds.

[0062] The N-type doped polysilicon layer is formed by chemical reaction of silane, phosphine and hydrogen under glow conditions, and the reaction conditions are: reaction temperature of 400-450° C., reaction time of 500-1500 seconds, and reaction pressure of 100-2000 mtorr.

[0063] The thickness of the first tunneling oxide layer is 1-2 nm, the thickness of the first doped silicon layer is 150-300 nm, and the effective doping concentration of the first doped silicon layer is 1e20-1e21 cm -3 The mask layer is at least one of silicon nitride, silicon oxynitride, and silicon oxide, and the thickness of the mask layer is 50-200nm.

[0064] S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region arranged at intervals; The width of the second semiconductor opening region is 0.3-0.6 mm, the etching is laser etching or chemical etching, the laser is ultraviolet or green laser, and the pulse width is less than 100 ns.

[0065] S4, removing the first semiconductor layer remaining in the second semiconductor opening region by texturing, and forming a velvet surface on the front side of the silicon wafer and the second semiconductor opening region, and then removing the mask layer outside the second semiconductor opening region on the back side of the silicon wafer during the cleaning process of the velvet surface; Hydrofluoric acid is used to remove the mask layer.

[0066] S5, using tubular PECVD to sequentially lay a second tunnel oxide layer, a hydrogenated amorphous silicon layer, a third tunnel oxide layer and a silicon nitride layer on the front side of the silicon wafer through chemical reaction; The second tunneling oxide layer is formed by oxygen thermal oxidation or by using a nitrous oxide plasma glow reaction, and the reaction conditions are: a reaction temperature of 400-450° C., a reaction pressure of 100-3000 mtorr, and a reaction time of 10-120 seconds.

[0067] The hydrogenated amorphous silicon layer is formed by chemical reaction of silane, phosphine, hydrogen and carbon dioxide under glow conditions, and the reaction conditions are: reaction temperature of 400-450°C, hydrogen flow rate of 3000-6000sccm, reaction time of 200-500 seconds, and reaction pressure of 800-3000mtorr.

[0068] The third tunnel oxide layer is formed by using a nitrous oxide plasma glow reaction, and the reaction conditions are: a reaction temperature of 400-450° C., a reaction pressure of 100-3000 mtorr, and a reaction time of 30-120 seconds.

[0069] The silicon nitride layer is formed by a chemical reaction of silane and ammonia under glow conditions.

[0070] The thickness of the second tunnel oxide layer is 1-3 nm, the thickness of the third tunnel oxide layer is 1.5-3 nm, and the hydrogen content of the hydrogenated amorphous silicon layer is 1e19-1e21 cm -3 , the thickness of the silicon nitride layer is 80-120nm.

[0071] S6, removing the plating layer deposited on the back side of the silicon wafer in S5 and cleaning the second semiconductor opening area again; S7. Depositing a second semiconductor layer on the back side of the silicon wafer.

[0072] The second semiconductor layer is formed by plasma enhanced chemical vapor deposition (PECVD) technology. The second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer. The thickness of the intrinsic amorphous silicon layer is 5-15nm, the thickness of the second doped silicon layer is 10-35nm, and the effective doping concentration of the second doped silicon layer is 1e19-4e20cm -3 The second doped silicon layer is a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer.

[0073] S8, performing a second etching opening on the second semiconductor layer to form first semiconductor opening regions that are alternately arranged with and spaced from the second semiconductor opening regions; The width of the first semiconductor opening region is 0.1-0.3 mm, the etching is laser etching or chemical etching, the laser is ultraviolet or green laser, and the pulse width is less than 50 ns.

[0074] S9, depositing a conductive film layer on the back surface obtained in S8; The thickness of the conductive film layer is 40-80nm. The conductive film layer is deposited by physical vapor deposition technology (PVD) or activated plasma deposition technology (RPD), and the conductive film layer is an indium oxide-based film doped with tin, zinc, tungsten, titanium, etc., or a zinc oxide-based film doped with aluminum, boron, gallium, etc.

[0075] S10, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; The etching is laser etching or chemical etching, and the width of the isolation groove is 30-200 μm.

[0076] S11 , forming a first electrode and a second electrode in the first semiconductor opening region and the second semiconductor opening region respectively.

[0077] The first electrode and the second electrode can be formed into silver grid electrodes by screen printing process and low temperature sintering, or can be formed by electroplating, preferably by electroplating to form grid line electrodes.

[0078] In a third aspect, the present application also provides a photovoltaic module, which includes the aforementioned back-contact cell resistant to photodegradation.

[0079] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0080] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0081] Example 1 like Figures 1 to 7 As shown, a method for preparing a back contact cell resistant to light-induced degradation comprises the following steps: S1, such as Figure 1 As shown, a double-sided polished silicon wafer 1 is provided, the silicon wafer 1 is an N-type single crystal silicon wafer, and the silicon wafer 1 is a Czochralski single crystal silicon wafer.

[0082] S2, such as Figure 2 As shown, a first semiconductor layer and a mask layer 4 are deposited on the back of a silicon wafer 1; the first semiconductor layer includes a first tunneling oxide layer 2 and an N-type doped polysilicon layer 3. The first semiconductor layer is formed by in-situ doping using tubular PECVD.

[0083] The first tunnel oxide layer 2 is formed by using a nitrous oxide plasma glow reaction, and the reaction conditions are: a reaction temperature of 450° C., a reaction pressure of 1000 mtorr, and a reaction time of 30 seconds.

[0084] The N-type doped polysilicon layer 3 is formed by chemical reaction of silane, phosphine and hydrogen under glow conditions, and the reaction conditions are: reaction temperature of 450° C., reaction time of 1000 seconds and reaction pressure of 1000 mtorr.

[0085] The thickness of the first tunnel oxide layer 2 is 1.5 nm, the thickness of the N-type doped polysilicon layer 3 is 150 nm, and the effective doping concentration of the N-type doped polysilicon layer 3 is 1e20 cm -3 , the mask layer 4 is silicon nitride, and the thickness of the mask layer 4 is 70 nm.

[0086] S3, such as Figure 3 As shown, laser etching is used to perform a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region arranged at intervals; The width S102 of the second semiconductor opening region is 0.4 mm, the laser is an ultraviolet laser, and the pulse width is less than 100 ns.

[0087] S4, such as Figure 3 As shown, the first semiconductor layer remaining in the second semiconductor opening region is removed by texturing, and a texture surface is formed on the front side of the silicon wafer 1 and the second semiconductor opening region. Then, during the cleaning process of the texture surface, hydrofluoric acid is used to remove the mask layer 4 outside the second semiconductor opening region on the back side of the silicon wafer 1. S5, such as Figure 4 As shown, a second tunnel oxide layer 5, a hydrogenated amorphous silicon layer 6, a third tunnel oxide layer 7 and a silicon nitride layer 8 are sequentially laid on the front side of the silicon wafer 1 by chemical reaction using tubular PECVD; The second tunnel oxide layer 5 is formed by using a nitrous oxide plasma glow reaction, and the reaction conditions are: a reaction temperature of 450° C., a reaction pressure of 500 mtorr, and a reaction time of 60 seconds.

[0088] The hydrogenated amorphous silicon layer 6 is formed by chemical reaction of silane, phosphine, hydrogen and carbon dioxide under glow conditions, and the reaction conditions are: reaction temperature of 450° C., hydrogen flow rate of 5000 sccm, reaction time of 300 seconds, and reaction pressure of 1000 mtorr.

[0089] The third tunnel oxide layer 7 is formed by using a nitrous oxide plasma glow reaction, and the reaction conditions are: a reaction temperature of 450° C., a reaction pressure of 2000 mtorr, and a reaction time of 60 seconds.

[0090] The silicon nitride layer 8 is formed by chemical reaction of silane and ammonia under glow conditions.

[0091] The thickness of the second tunnel oxide layer 5 is 2 nm, the thickness of the third tunnel oxide layer 7 is 2.5 nm, and the hydrogen content of the hydrogenated amorphous silicon layer 6 is 5e20 cm -3 The thickness of the hydrogenated amorphous silicon layer 6 is 10 nm, and the thickness of the silicon nitride layer 8 is 120 nm.

[0092] S6, such as Figure 4 As shown, the wrap-around coating produced by deposition on the back side of the silicon wafer 1 in S5 is removed and the second semiconductor opening area is cleaned again; S7, such as Figure 5 As shown, a second semiconductor layer is formed on the back side of the silicon wafer 1 by plasma enhanced chemical vapor deposition (PECVD) technology; The second semiconductor layer includes an intrinsic amorphous silicon layer 9 and a P-type doped amorphous silicon layer 10. The thickness of the intrinsic amorphous silicon layer 9 is 5 nm, the thickness of the P-type doped amorphous silicon layer 10 is 10 nm, and the effective doping concentration of the P-type doped amorphous silicon layer 10 is 1e19 cm -3 .

[0093] S8, such as Figure 5 As shown, laser etching is used to perform a second etching opening on the second semiconductor layer to form a first semiconductor opening region that is alternately arranged with and spaced from the second semiconductor opening region; The width S101 of the first semiconductor opening region is 0.2 mm, the laser is an ultraviolet laser, and the pulse width is less than 50 ns.

[0094] S9, such as Figure 6 As shown, a conductive film layer 11 is deposited on the back surface obtained in S8; The thickness of the conductive film layer 11 is 60 nm. The conductive film layer 11 is deposited by physical vapor deposition (PVD) technology, and the conductive film layer 11 is a tin-doped indium oxide-based thin film.

[0095] S10, such as Figure 6 As shown, laser etching is used to perform a third etching opening on a portion of the conductive film layer 11 located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; The width of the isolation groove is 80 μm.

[0096] S11, such as Figure 7 As shown, a first electrode and a second electrode are respectively formed in the first semiconductor opening region and the second semiconductor opening region by electroplating.

[0097] The thickness ratio of the hydrogenated amorphous silicon layer, the first tunneling oxide layer, and the intrinsic amorphous silicon layer is 1:0.15:0.5.

[0098] The ratio of the hydrogen content of the hydrogenated amorphous silicon layer, the effective doping concentration of the first doped silicon layer, and the effective doping concentration of the second doped silicon layer is 1:0.2:0.02.

[0099] Example 2 The method of Example 1 is referred to, except that the thickness of the second tunnel oxide layer 5 is 1.5 nm. The process parameters that need to be adjusted to meet this condition are: in S5, the reaction time for depositing the second tunnel oxide layer 5 is shortened to 40 seconds.

[0100] The thickness of the third tunnel oxide layer 7 is 2 nm. The process parameters that need to be adjusted to meet this condition are: in S5 , the reaction time for depositing the third tunnel oxide layer 7 is shortened to 30 seconds.

[0101] Example 3 The method of Example 1 is referred to, except that the thickness of the second tunnel oxide layer 5 is 2.5 nm. The process parameters that need to be adjusted to meet this condition are: in S5, the reaction time for depositing the second tunnel oxide layer 5 is increased to 90 seconds.

[0102] The thickness of the third tunnel oxide layer 7 is 3 nm. The process parameters that need to be adjusted to meet this condition are: in S5 , the reaction time for depositing the third tunnel oxide layer 7 is increased to 120 seconds.

[0103] Example 4 The method of Example 1 is followed, except that the hydrogen content of the hydrogenated amorphous silicon layer 6 is 1e21cm -3 The process parameters that need to be adjusted to meet this condition are: in S5, the flow rate of hydrogen gas for depositing the hydrogenated amorphous silicon layer 6 is increased to 6000 sccm.

[0104] Comparative Example 1 The method of Example 1 is referred to, except that in S5, the passivation structure is a conventional hydrogenated amorphous silicon passivation layer and a silicon nitride anti-reflection layer structure, specifically: a hydrogenated amorphous silicon layer and a silicon nitride layer are sequentially deposited on the front side of the silicon wafer by PECVD, the thickness of the hydrogenated amorphous silicon layer is 10 nm, the thickness of the silicon nitride layer is 120 nm, and the effective doping concentration of the hydrogenated amorphous silicon layer is 5e20 cm -3 .

[0105] Comparative Example 2 The method of Example 1 is referred to, except that in S5 , the second tunnel oxide layer 5 is not deposited.

[0106] Comparative Example 3 The method of Example 1 is referred to, except that, in S5 , the third tunnel oxide layer 7 is not deposited.

[0107] Comparative Example 4 The method of Example 1 is referred to, except that in S5, the thickness of the hydrogenated amorphous silicon layer 6 is 2 nm, and it is formed by tubular PECVD at a formation temperature of 450°C. The formation conditions include: introducing silane and hydrogen, the flow ratio of silane to hydrogen is 0.2:1, the process pressure is 300 Pa, the power is 10 kW, and after deposition to a preset thickness, the power is turned off and the gas is evacuated.

[0108] Comparative Example 5 The method of Example 1 is referred to, except that the thickness of the second tunnel oxide layer 5 is 0.5 nm. The process parameters that need to be adjusted to meet this condition are: in S5, the reaction time for depositing the second tunnel oxide layer 5 is shortened to 3 seconds.

[0109] The thickness of the third tunnel oxide layer 7 is 0.5 nm. The process parameters that need to be adjusted to meet this condition are: in S5 , the reaction time for depositing the third tunnel oxide layer 7 is shortened to 2 seconds.

[0110] Comparative Example 6 The method of Example 1 is referred to, except that the thickness of the second tunnel oxide layer 5 is 4 nm. The process parameters that need to be adjusted to meet this condition are: in S5, the reaction time for depositing the second tunnel oxide layer 5 is increased to 200 seconds.

[0111] The thickness of the third tunnel oxide layer 7 is 4 nm. The process parameters that need to be adjusted to meet this condition are: in S5 , the reaction time for depositing the third tunnel oxide layer 7 is increased to 180 seconds.

[0112] Test Case The back contact cells obtained in the above examples and comparative examples were subjected to various performance tests, and the results are shown in Table 1. The specific test method for the LID attenuation performance index can be found in GB / T 6495.11-2016.

[0113] Table 1

[0114] It can be seen from the above results that according to Example 1 and Comparative Example 1, the present application uses a structure of oxide layer + hydrogenated amorphous silicon layer + oxide layer + silicon nitride layer, and introduces a double oxide layer structure as a barrier layer for hydrogen escape, which can effectively isolate hydrogen from diffusing into bulk silicon and overflowing outward under photothermal conditions. At the same time, the excellent passivation effect of the tunneling oxide layer ensures that the passivation level will not be affected, thereby realizing a high-efficiency back-contact solar cell that is resistant to photo-induced degradation.

[0115] Furthermore, according to Example 1 and Comparative Example 2, it can be seen that the second tunneling oxide layer of the present application can effectively isolate hydrogen from diffusing into bulk silicon under photothermal conditions, thereby ensuring the passivation effect of the battery.

[0116] Further, according to Example 1 and Comparative Example 3, the third tunneling oxide layer of the present application can effectively isolate hydrogen from overflowing under photothermal conditions, thereby ensuring the passivation effect of the battery. At the same time, it can be seen that after depositing the third tunneling oxide layer 7, the present application still does not affect the current density, open circuit voltage and battery conversion efficiency of the battery. The third tunneling oxide layer of the present application can reduce the light-induced degradation of the battery without affecting the performance of the battery itself.

[0117] Further, according to Example 1 and Comparative Example 4, it can be seen that the present application reasonably sets the thickness of the hydrogenated amorphous silicon layer, which is conducive to balancing the passivation effect and light absorption efficiency of the hydrogenated amorphous silicon layer, thereby improving the battery conversion efficiency. The reason why the effect of Comparative Example 4 is not good is speculated to be: when the thickness of the hydrogenated amorphous silicon layer is thin, it cannot store enough hydrogen, affecting the level of chemical passivation. At the same time, under high temperature conditions, when the thickness of the hydrogenated amorphous silicon layer is thin, it is easier to produce hydrogen overflow to the silicon substrate and the outside, which makes it decay more seriously in the light-induced attenuation (LID) test.

[0118] Further, according to Example 1 and Comparative Example 5, when the thickness of the second tunnel oxide layer and the third tunnel oxide layer is too thin, the escape of hydrogen in the hydrogenated amorphous silicon layer cannot be isolated, and the passivation effect will still be destroyed. However, the thickness of the tunnel oxide layer of the present application is matched with the hydrogen content of the hydrogenated amorphous silicon layer, realizing a high-efficiency and light-induced degradation-resistant back-contact solar cell.

[0119] Further, according to Example 1 and Comparative Example 6, when the thickness of the second tunnel oxide layer and the third tunnel oxide layer is too thick, it will seriously affect the optical performance of the front side of the cell and reduce the cell conversion efficiency. However, the thickness of the tunnel oxide layer of the present application is matched with the hydrogen content of the hydrogenated amorphous silicon layer, realizing a high-efficiency and light-induced degradation-resistant back-contact solar cell.

[0120] Furthermore, according to Example 1 and Example 2, it can be seen that by adopting the preferred technical solution of the present application, the escape of hydrogen can be further isolated while avoiding affecting the optical performance of the front side of the battery, thereby improving the battery conversion efficiency.

[0121] Furthermore, according to Example 1 and Example 3, it can be seen that by adopting the preferred technical solution of the present application, the escape of hydrogen can be further isolated while avoiding affecting the optical performance of the front side of the battery, thereby improving the battery conversion efficiency.

[0122] Furthermore, according to Example 1 and Example 4, although increasing the hydrogen content of the hydrogenated amorphous silicon layer can improve the passivation performance, the isolation effect of the tunneling oxide layer is limited. By adopting the preferred technical solution of the present application, the escape of hydrogen can be further isolated while avoiding affecting the optical performance of the front side of the battery, thereby improving the battery conversion efficiency.

[0123] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A back contact cell resistant to light-induced degradation, comprising: A silicon wafer having a front side and a back side; A first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are alternately arranged on the back side of the silicon wafer; It is characterized by further comprising: A second tunneling oxide layer, a hydrogenated amorphous silicon layer, a third tunneling oxide layer and a silicon nitride layer are sequentially laid on the front side of the silicon wafer; The thickness of the second tunnel oxide layer is 1-3 nm, the thickness of the third tunnel oxide layer is 1.5-3 nm, and the hydrogen content of the hydrogenated amorphous silicon layer is 1e19-1e21 cm -3 .

2. The back contact cell against light-induced degradation according to claim 1, characterized in that: The thickness of the hydrogenated amorphous silicon layer is 7-12 nm; and / or, The thickness of the silicon nitride layer is 80-120 nm.

3. The back contact cell resistant to light-induced degradation according to claim 1, characterized in that: The first semiconductor layer includes a first tunneling oxide layer and a first doped silicon layer, the first tunneling oxide layer has a thickness of 1-2 nm, the first doped silicon layer has a thickness of 150-300 nm, and the effective doping concentration of the first doped silicon layer is 1e20-1e21 cm -3 ; and / or, The second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer, the thickness of the intrinsic amorphous silicon layer is 5-15 nm, the thickness of the second doped silicon layer is 10-35 nm, and the effective doping concentration of the second doped silicon layer is 1e19-4e20 cm -3 .

4. The back contact cell resistant to light-induced degradation according to claim 3, characterized in that: The thickness ratio of the hydrogenated amorphous silicon layer, the first tunneling oxide layer, and the intrinsic amorphous silicon layer is 1:(0.1-0.21):(0.5-1.43); and / or, The ratio of the hydrogen content of the hydrogenated amorphous silicon layer, the effective doping concentration of the first doped silicon layer, and the effective doping concentration of the second doped silicon layer is 1: (0.2-50): (0.02-10).

5. The back contact cell resistant to light-induced degradation according to claim 1, characterized in that: A second semiconductor opening region is provided between adjacent first semiconductor layers, and two ends of the second semiconductor layer located in the second semiconductor opening region respectively extend toward the surface of the adjacent first semiconductor layer by a preset distance and overlap with it to form an overlapping region.

6. The back contact cell resistant to light-induced degradation according to claim 5, characterized in that: The back contact cell resistant to light-induced degradation further comprises: A conductive film layer, the conductive film layer is laid on the first semiconductor layer and the second semiconductor layer, the thickness of the conductive film layer is 40-80 nm, the conductive film layer is provided with an isolation groove at the position of each overlapping region, and the width of the isolation groove is 30-200 μm; and / or, The back contact cell resistant to light-induced degradation further comprises: A first electrode and a second electrode, wherein the first electrode and the second electrode are respectively disposed in a first semiconductor opening region and a second semiconductor opening region; the first semiconductor opening region is disposed in a portion outside an overlapping region on the first semiconductor layer.

7. A method for preparing a back contact cell resistant to light-induced degradation, characterized in that: The preparation method is used to prepare a back contact cell resistant to light-induced degradation according to any one of claims 1 to 6, and the preparation method comprises the following steps: S1, provide double-sided polished silicon wafers; S2, depositing a first semiconductor layer and a mask layer on the back side of the silicon wafer; S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region arranged at intervals; S4, removing the first semiconductor layer remaining in the second semiconductor opening region by texturing, and forming a velvet surface on the front side of the silicon wafer and the second semiconductor opening region, and then removing the mask layer outside the second semiconductor opening region on the back side of the silicon wafer during the cleaning process of the velvet surface; S5, using tubular PECVD to sequentially lay a second tunnel oxide layer, a hydrogenated amorphous silicon layer, a third tunnel oxide layer and a silicon nitride layer on the front side of the silicon wafer through chemical reaction; The thickness of the second tunnel oxide layer is 1-3 nm, the thickness of the third tunnel oxide layer is 1.5-3 nm, and the hydrogen content of the hydrogenated amorphous silicon layer is 1e19-1e21 cm -3 ; S6, removing the plating layer deposited on the back side of the silicon wafer in S5 and cleaning the second semiconductor opening area again; S7. Depositing a second semiconductor layer on the back side of the silicon wafer.

8. The preparation method according to claim 7, characterized in that: In S5, a second tunnel oxide layer is formed by thermal oxidation with oxygen; and / or, In S5, the second tunnel oxide layer is formed by using a nitrous oxide plasma glow reaction, and the reaction conditions are: a reaction temperature of 400-450°C, a reaction pressure of 100-3000 mtorr, and a reaction time of 10-120 seconds.

9. The preparation method according to claim 7, characterized in that: In S5, the hydrogenated amorphous silicon layer is formed by chemical reaction of silane, phosphine, hydrogen and carbon dioxide under glow conditions, and the reaction conditions are: reaction temperature of 400-450°C, hydrogen flow rate of 3000-6000sccm, reaction time of 200-500 seconds, and reaction pressure of 800-3000mtorr.

10. The preparation method according to claim 7, characterized in that: In S5, the third tunnel oxide layer is formed by using a nitrous oxide plasma glow reaction, and the reaction conditions are: a reaction temperature of 400-450°C, a reaction pressure of 100-3000 mtorr, and a reaction time of 30-120 seconds.

11. The preparation method according to claim 7, characterized in that: In S5, the silicon nitride layer is formed by chemical reaction of silane and ammonia under glow conditions; and / or, The preparation method further comprises: S8, performing a second etching opening on the second semiconductor layer to form first semiconductor opening regions that are alternately arranged with and spaced from the second semiconductor opening regions; S9, depositing a conductive film layer on the back surface obtained in S8; S10, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; S11 , forming a first electrode and a second electrode in the first semiconductor opening region and the second semiconductor opening region respectively.

12. A photovoltaic module, characterized in that: It comprises the back contact cell resistant to light-induced degradation as claimed in any one of claims 1 to 6.

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