Active pixel structure with high conversion gain and low noise and image sensor

Abstract

The invention discloses an active pixel structure with high conversion gain and low noise and an image sensor, the active pixel structure is manufactured based on a P-type silicon substrate, a far-end FD node structure is adopted, P-type light doping is performed between an FD node and a transmission gate TG, and the FD node and the transmission gate TG are isolated; the transmission gate TG adopts a buried channel type transmission gate, a layer of N-type impurities is injected into the P-type substrate below a gate electrode, and a new PN junction is formed in a formed N-type region and the P-type substrate; two depletion regions and a buried trench can be formed under a gate by applying a gate voltage, so that the highest point of potential goes deep into the semiconductor from the surface; during charge transfer, electrons are transferred from the PPD to the FD node through the buried trench. According to the invention, the overlapping capacitance caused by overlapping with the TG can be reduced, so that the FD node capacitance is reduced, and the conversion gain is improved; noise generated by surface defects is reduced, and meanwhile the charge transfer characteristic of pixels is improved.

Description

Technical Field

[0001] The invention relates to the technical field of CMOS image sensor pixels, and in particular to an active pixel structure with high conversion gain and low noise. Background Art

[0002] More than 80% of human information acquisition relies on vision. Low-light image sensors are the core components that expand human visual information acquisition capabilities. In low-light applications such as security monitoring, intelligent driving, aerospace, and seabed surveys, sensitivity is a key indicator that determines the quality of visual information acquisition. Traditional low-light imaging equipment based on photomultiplier tubes is complex and costly, and is not suitable for large-scale promotion. With the continuous development of CMOS process technology, the low-light imaging characteristics of CMOS image sensors have been greatly improved.

[0003] High-sensitivity low-light CMOS image sensors require pixels to have high conversion gain and low noise characteristics. Conventional 4T active pixels introduce a transfer gate (TG) into the pixel to divide the photoelectric conversion into two steps: photosensitivity and "charge-voltage" conversion. High sensitivity can be achieved by reducing the capacitance of the floating diffusion (FD) node and thereby increasing the conversion gain. Figure 1 As shown, the FD node capacitance includes the metal capacitance C M , the overlapping capacitance C1 between the FD node and the reset transistor RST (Reset Transistor), the overlapping capacitance C2 between the FD node and TG, the overlapping capacitance C3 between the FD node and the source follower SF (Source Follower), and the junction capacitance C4 of the FD node; reducing the overlapping area between the FD node and TG can effectively improve the conversion gain of the pixel.

[0004] In addition, for low-light image sensors, the influence of dark current cannot be ignored. The main sources of dark current include: depletion region dark current, surface generated dark current, shallow trench isolation dark current, TG channel dark current, neutral region diffusion dark current, etc. Among them, the TG channel dark current is mainly due to the fact that during the exposure of the pixel, the TG channel area is closely connected to the clamped photodiode area (PPD, Pinned Photodiode), and the electrons thermally generated at the interface between the channel surface and the silicon dioxide may be collected by the PPD electric field.

[0005] Conventional 4T pixel FD nodes and TG will overlap, so the resulting overlap capacitance will increase the FD capacitance and reduce the conversion gain. In addition, when TG is turned on, the maximum potential is located on the semiconductor surface, so the photogenerated electrons will be attracted by the high potential and transfer through the semiconductor surface, that is, the junction of silicon and silicon dioxide. However, there are many defects and interface states on the surface of silicon and silicon dioxide, and the generated photogenerated carriers will be captured and released by the surface defects and interface states, generating a large dark current.

[0006] Therefore, it is of great research value to optimize the FD node capacitance and the dark current in the TG channel region from a design perspective. Summary of the invention

[0007] The purpose of the present invention is to overcome the shortcomings and defects of the prior art and provide an active pixel structure and image sensor with high conversion gain and low noise based on the far-end FD of the buried channel type transmission gate. The active pixel structure can reduce the overlap capacitance between the FD node and the transmission gate TG, improve the conversion gain, and at the same time realize the separation of the charge transfer channel and the surface of the transmission gate TG channel, thereby reducing the dark current in the transmission gate TG channel region.

[0008] One object of the present invention is to provide an active pixel structure with high conversion gain and low noise, which is manufactured based on a P-type silicon substrate, adopts a remote FD node structure, and performs P-type light doping between the FD node and the transmission gate TG to isolate the two.

[0009] Among them, the transmission gate TG adopts a buried channel transmission gate, a layer of N-type impurities is injected into the P substrate under the gate, and a new PN junction is formed between the formed N-type region and the P-type substrate; by applying a gate voltage, two depletion regions and a buried channel can be formed under the gate so that the highest potential point penetrates from the surface into the interior of the semiconductor; during the charge transfer, electrons are transferred from the PPD to the FD node through the buried channel.

[0010] A blocking layer formed by P-type injection is arranged at the connection between the transmission gate TG and the PPD, so that electrons can enter the FD node when the transmission gate TG is turned off.

[0011] The length of the CPX layer extending under the gate is 0.18-0.19 μm.

[0012] Among them, the gate voltage is applied to make the surface of the buried channel transmission gate in a depletion state, and the transmission gate at this time is recorded as the on state; when the transmission gate TG is turned on, the photogenerated electrons in the PPD are attracted by the high potential and transferred through the buried channel to stay away from the junction of the silicon and silicon dioxide surfaces, inhibiting the electrons from being captured or released by surface defects and reducing the dark current; the P-type light doping between the TG and FD nodes blocks the electrons, causing them to gather in the buried channel and cannot be transferred to the FD area.

[0013] Among them, as the gate voltage continues to decrease, the depletion region on the surface of the transmission gate TG and the internal PN junction depletion region become larger and larger until they overlap, the two depletion regions become one, and the buried channel disappears. At this time, the carriers cannot complete the transfer, and the transmission gate is recorded as being in the closed state; applying a negative gate voltage ensures that the potential under the gate is lower than that of the P-type lightly doped region while the buried channel disappears, and at the same time, the voltage of the FD region is high, so that electrons are transferred from PPD to the FD region through TG and the P-type lightly doped region.

[0014] Another object of the present invention is to provide an image sensor comprising the active pixel structure with high conversion gain and low noise.

[0015] The present invention adopts a remote FD structure and performs P-type light doping between the FD node and the TG to isolate the two, thereby reducing the overlapping capacitance caused by overlapping with the TG, thereby reducing the FD node capacitance and improving the conversion gain.

[0016] The present invention is based on a remote FD structure and adopts a buried channel transmission gate. An additional layer of N-type impurities is injected into the P substrate under the gate. The N-type region and the P-type substrate form a new PN junction. By applying a gate voltage, two depletion regions and an N-type conductive channel are formed under the gate. The highest point of the potential penetrates from the surface into the interior of the semiconductor. In this way, during the charge transfer, electrons are transferred from the PPD to the FD node through the N-type conductive channel, thereby staying away from the interface between silicon and silicon dioxide, reducing the noise generated by surface defects, and improving the charge transfer characteristics of the pixel.

[0017] The present invention forms a barrier layer by adding a P-type injection at the connection between TG and PPD, thereby ensuring that electrons can smoothly enter the FD node when the transmission gate TG is turned off.

[0018] Compared with the conventional 4T active pixel structure, the pixel structure of the present invention makes the maximum potential under the transmission gate channel away from the semiconductor surface through double doping, and the photogenerated charge can be transferred from the photodiode to the FD node through the inside of the semiconductor, thereby reducing the dark current. At the same time, the FD node is away from the transmission gate, reducing the FD node capacitance and improving the conversion gain. The combination of the two can improve the signal-to-noise ratio of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the FD node capacitor composition.

[0020] Figure 2 It is a schematic diagram of the active pixel structure with high conversion gain and low noise of the present invention.

[0021] Figure 3 The invention is based on the high conversion gain and low noise active pixel structure AA , Potential distribution diagram;

[0022] Figure 4 It is a schematic diagram of the buried channel at the beginning of the TG of the active pixel structure with high conversion gain and low noise of the present invention.

[0023] Figure 5 This is the PPD-FD potential distribution diagram of the active pixel structure with high conversion gain and low noise at the beginning of TG of the present invention.

[0024] Figure 6 This is a schematic diagram of the buried channel when the TG is turned off for the active pixel structure with high conversion gain and low noise of the present invention.

[0025] Figure 7 It is a PPD-FD potential distribution diagram of the active pixel structure with high conversion gain and low noise when TG is turned off in the present invention. DETAILED DESCRIPTION

[0026] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0027] See also Figure 2 As shown, an embodiment of the present invention provides an active pixel structure with high conversion gain and low noise, which is made based on a P-type silicon substrate. The N-PD region and the clamping layer P+ region together constitute the PPD. The FD node is heavily N-type doped (N+). A remote FD node structure is adopted, and a P-type light doping (P-) is performed between the FD node and the transmission gate TG to isolate the two. By isolating the FD node from the transmission gate TG, the overlap capacitance caused by the overlap with the TG can be reduced, thereby reducing the FD node capacitance and improving the conversion gain.

[0028] The transmission gate TG adopts a buried trench transmission gate, a layer of N-type impurities is injected into the P substrate under the gate, and a new PN junction is formed between the formed N-type region and the P-type substrate; by applying a gate voltage, two depletion regions (the depletion region on the surface of the transmission gate TG and the PN junction depletion region inside the semiconductor) and an N-type conductive channel, i.e., a buried trench, can be formed under the gate, so that the highest potential point penetrates from the surface into the semiconductor, such as Figure 3 As shown in the figure, during the charge transfer, electrons are transferred from the PPD to the FD node through the buried channel, thereby being away from the interface between silicon and silicon dioxide, reducing the noise caused by surface defects, and improving the charge transfer characteristics of the pixel.

[0029] A blocking layer formed by P-type injection is arranged at the connection between the transmission gate TG and PPD, so that electrons can enter the FD node when the transmission gate TG is turned off. By adding a P-type injection at the connection between TG and PPD to form a blocking layer, it can be ensured that when the transmission gate TG is turned off, electrons can smoothly enter the FD node.

[0030] Wherein, the length of the P-type barrier layer extending under the gate is 0.18-0.19 μm.

[0031] The following combination Figures 4 to 7 To illustrate the working principle of the pixel in the embodiment of the present application.

[0032] First, see Figure 4 as well as Figure 5 As shown, in order to ensure that the charge can be smoothly transferred from the internal channel of the semiconductor, the pixel of the embodiment of the present application needs to apply a gate voltage to make the surface of the buried channel type transmission gate in a depleted state, and the transmission gate at this time is recorded as being in an open state. Figure 4 As shown, the x1-x2 region is the surface depletion region, the x2-x3 region is the buried channel conductive channel, and the x3-x5 region is the depletion region formed by the PN junction formed by the N-type doping under the gate and the P-type doping of the substrate. Therefore, when the transmission gate TG is turned on, the photogenerated electrons in the PPD are attracted by the high potential and transferred through the buried channel, which is far away from the junction of the silicon and silicon dioxide surfaces. It can effectively inhibit the electrons from being captured or released by surface defects and reduce the dark current. Because there is a P-type light doping barrier between the TG and FD nodes, the electrons will gather in the buried channel and will not be directly transferred to the FD region. The potential distribution of the charge transfer path at this time is as follows: Figure 5 As shown in the figure, the small circle with a horizontal bar inside represents the electron.

[0033] As the gate voltage continues to decrease, the depletion region on the surface of the transmission gate TG and the PN junction depletion region inside the semiconductor become larger and larger until they begin to overlap and the two depletion regions become one. Figure 6 As shown, x2 and x3 begin to overlap, and the buried channel disappears. At this time, the carrier cannot complete the transfer. The transmission gate is recorded as closed. In order to ensure that the electrons gathered in the buried channel can be smoothly transferred from the inside of the semiconductor to the FD region, a negative gate voltage needs to be applied. When the buried channel disappears, the potential under the gate needs to be lower than that of the P-type lightly doped region. At the same time, the voltage of the FD region must be high enough. The potential distribution of the charge transfer path at this time is as follows: Figure 7 shown.

[0034] In the embodiment of the present application, the length of the P-type blocking layer extending under the gate will affect the charge transfer rate and charge reflux. The longer the blocking layer extends under the gate, the lower the potential of the buried channel will be under the same gate voltage, resulting in a lower potential gradient on the charge transfer path, and thus a lower transfer rate. In addition, as the length of the blocking layer under the gate increases, the weaker potential barrier formed by P-type doping will be more biased toward PD. When the layer transfer gate TG is closed, the electrons flowing back into PD will increase. Therefore, the length of the blocking layer extending under the gate should not be too long. Considering the process implementation, preferably, the length of the blocking layer extending under the gate should not be too short, and the optimal length is 0.18-0.19μm.

[0035] Another object of an embodiment of the present invention is to provide an image sensor including the active pixel structure with high conversion gain and low noise.

[0036] The basic principles and main features of the present invention and the advantages of the present invention are shown and described above. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention.

[0037] Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the claims are included in the present invention.

[0038] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. High conversion gain and low noise active pixel structure, characterized by: It is manufactured based on a P-type silicon substrate and adopts a remote FD node structure. P-type light doping is performed between the FD node and the transmission gate TG to isolate the two.

2. The active pixel structure with high conversion gain and low noise according to claim 1, characterized in that: The transmission gate TG adopts a buried trench transmission gate, and a layer of N-type impurities is injected into the P substrate under the gate, and a new PN junction is formed between the formed N-type region and the P-type substrate; by applying a gate voltage, two depletion regions and a buried trench can be formed under the gate, so that the highest point of potential penetrates from the surface into the interior of the semiconductor; during the charge transfer, electrons are transferred from the PPD to the FD node through the buried trench.

3. The active pixel structure with high conversion gain and low noise according to claim 2, characterized in that: A blocking layer formed by P-type injection is arranged at the connection between the transmission gate TG and the PPD, so that electrons can enter the FD node when the transmission gate TG is turned off.

4. The high conversion gain and low noise active pixel structure according to claim 3, characterized in that: The length of the barrier layer extending under the gate is 0.18-0.19 μm.

5. The active pixel structure with high conversion gain and low noise according to claim 3, characterized in that: Applying gate voltage puts the surface of the buried channel transmission gate in a depletion state, and the transmission gate at this time is recorded as being in the on state; when the transmission gate TG is turned on, the photogenerated electrons in the PPD are attracted by the high potential and transferred through the buried channel to stay away from the interface between the silicon and silicon dioxide surfaces, inhibiting the electrons from being captured or released by surface defects and reducing the dark current; the P-type light doping between the TG and FD nodes blocks the electrons, causing them to gather in the buried channel and unable to be transferred to the FD region.

6. The high conversion gain and low noise active pixel structure according to claim 5, characterized in that: As the gate voltage continues to decrease, the depletion region on the surface of the transmission gate TG and the internal PN junction depletion region become larger and larger until they overlap, the two depletion regions become one, and the buried channel disappears. At this time, the carriers cannot complete the transfer, and the transmission gate is recorded as being in the closed state; applying a negative gate voltage ensures that the potential under the gate is lower than that of the P-type lightly doped region while the buried channel disappears, and at the same time, the voltage in the FD region is high, so that electrons are transferred from PPD to the FD region via TG and the P-type lightly doped region.

7. An image sensor, characterized in that The invention comprises an active pixel structure with high conversion gain and low noise as described in any one of claims 1 to 6.

Images