Solar cell and method for manufacturing solar cell

Abstract

The invention provides a solar cell and a preparation method thereof, and the solar cell comprises an N-type substrate which comprises a first surface and a second surface which are opposite to each other, and the first surface is provided with a P-type region and an N-type region which are spaced from each other; the tunneling dielectric layer, the N-type doping layer, the first intrinsic amorphous silicon layer, the first P-type amorphous silicon layer, the first transparent conducting layer and the first electrode are located in the N-type area, the doping concentration of the N-type doping layer is larger than that of the tunneling dielectric layer, the doping type of the tunneling dielectric layer is the same as that of the N-type doping layer, and the first transparent conducting layer makes contact with the first electrode; the second intrinsic amorphous silicon layer, the second P-type amorphous silicon layer, the second transparent conducting layer and the second electrode are located in the P-type area, and the second electrode is in contact with the second transparent conducting layer and the second P-type amorphous silicon layer; and a passivation layer and an anti-reflection layer on the second surface. The solar cell solves the technical problem of how to improve the efficiency of the solar cell.

Description

Technical Field

[0001] The present application relates to the field of solar cells, and in particular to a solar cell and a method for preparing the solar cell. Background Art

[0002] Back-contact solar cells are a type of high-efficiency solar cells whose light-receiving surface has no main grid lines or even any electrodes. The positive and negative electrodes are arranged on the backlight side of the cell, which can reduce the shading caused by the grid line pattern and effectively increase the light-receiving area of ​​the light-receiving surface of the cell, thereby improving the energy conversion efficiency of the cell. Summary of the invention

[0003] The main purpose of the present application is to provide a solar cell and a method for preparing the solar cell, so as to at least solve the problem of how to improve the efficiency of the solar cell in the prior art.

[0004] According to one aspect of the present application, a method for preparing a solar cell is provided, comprising: an N-type substrate, the N-type substrate comprising a first surface and a second surface opposite to each other, the first surface being provided with a P-type region and an N-type region with an interval; a tunneling dielectric layer, an N-type doping layer, a first intrinsic amorphous silicon layer, a first P-type amorphous silicon layer, a first transparent conductive layer and a first electrode located in the N-type region, wherein the doping concentration of the N-type doping layer is greater than the doping concentration of the tunneling dielectric layer, the tunneling dielectric layer and the N-type doping layer have the same doping type, and the first transparent conductive layer is in contact with the first electrode; a second intrinsic amorphous silicon layer, a second P-type amorphous silicon layer, a second transparent conductive layer and a second electrode located in the P-type region, and the second electrode is in contact with the second transparent conductive layer; a passivation layer and an anti-reflection layer located on the second surface.

[0005] Optionally, the first surface has a plurality of grooves arranged at intervals, and the P-type region is arranged in the grooves.

[0006] Optionally, the tunnel dielectric layer is located on a side of the N-type doped layer close to the first surface and on a side wall of the N-type doped layer.

[0007] Optionally, the first intrinsic amorphous silicon layer includes two intrinsic amorphous silicon portions having a first interval, the first P-type amorphous silicon layer includes two P-type amorphous silicon portions having a second interval, an orthographic projection of the first interval on the N-type substrate and an orthographic projection of the second interval on the N-type substrate overlap, the first transparent conductive layer is located in the first interval, in the second interval, and on a surface of the first P-type amorphous silicon layer away from the N-type substrate, and the first electrode is located on a partial surface of the first transparent conductive layer away from the N-type substrate.

[0008] Optionally, the second transparent conductive layer includes two transparent conductive portions with a third interval, and the second electrode is located in the third interval and on a portion of the surface of the second transparent conductive layer away from the N-type substrate.

[0009] Optionally, the doping concentration of the tunnel dielectric layer is 1E 17 ~1E 19 cm -3 The doping concentration of the N-type doping layer is 1E 19 ~5E 20 cm -3 .

[0010] Optionally, the thickness of the tunnel dielectric layer is in the range of 1 to 3 nm, and the thickness of the N-type doping layer is in the range of 2 to 8 nm.

[0011] According to another aspect of the present application, a method for preparing a solar cell is provided, comprising: providing an N-type substrate, the N-type substrate comprising a first surface and a second surface opposite to each other; forming a first preliminary tunneling dielectric layer on the first surface; printing a doping paste on a portion of the surface of the first preliminary tunneling dielectric layer and performing an annealing treatment to form a preliminary N-type doped layer, and the remaining first preliminary tunneling dielectric layer forms a second preliminary tunneling dielectric layer; forming a protective layer on a side of the N-type doped layer away from the first surface; removing a portion of the protective layer to obtain a preliminary structure having a plurality of spaced grooves, in which the remaining preliminary N-type doped layer forms an N-type doped layer, and the remaining second preliminary tunneling dielectric layer forms a tunneling dielectric layer, and the preliminary structure comprises an N-type region and a P-type region; sequentially forming a first intrinsic amorphous silicon layer, a first P-type amorphous silicon layer, a first transparent conductive layer and a first electrode in the N-type region; sequentially forming a second intrinsic amorphous silicon layer, a second P-type amorphous silicon layer, a second transparent conductive layer and a second electrode in the P-type region; and forming a passivation layer and an anti-reflection layer on the second surface.

[0012] Optionally, the annealing treatment is performed at a temperature of 700-1000°C.

[0013] Optionally, the deposition temperature of the first preliminary tunneling dielectric layer is 600-800°C.

[0014] By applying the technical solution of the present application, a solar cell is provided, comprising: an N-type substrate, the N-type substrate comprising a first surface and a second surface opposite to each other, the first surface being provided with a P-type region and an N-type region with an interval; a tunneling dielectric layer, an N-type doping layer, a first intrinsic amorphous silicon layer, a first P-type amorphous silicon layer, a first transparent conductive layer and a first electrode located in the N-type region, wherein the doping concentration of the N-type doping layer is greater than the doping concentration of the tunneling dielectric layer, the tunneling dielectric layer and the N-type doping layer have the same doping type, and the first transparent conductive layer is in contact with the first electrode; a second intrinsic amorphous silicon layer, a second P-type amorphous silicon layer, a second transparent conductive layer and a second electrode located in the P-type region, the second electrode being in contact with the second transparent conductive layer and the second P-type amorphous silicon layer, respectively; and a passivation layer and an anti-reflection layer located on the second surface. In the N-type region, since the doping concentration of the tunnel dielectric layer is lower than that of the N-type doping layer, the tunnel dielectric layer close to the N-type substrate forms a low-compound dielectric layer, which has good chemical passivation and field passivation effects, and also has certain transmission performance; on the side away from the N-type substrate, since the doping concentration of the N-type doping layer is greater than the doping concentration of the tunnel dielectric layer, a localized heavily doped N-type doping layer is formed, which can improve the electrode contact performance. The P region uses ultra-low-compound amorphous silicon passivation, which has a small surface composite current density and is currently the best P-type passivation material. Combined with the above-mentioned improvement in chemical passivation and field passivation effects, the improvement in electrode contact performance and the reduction in surface composite current density, the efficiency of solar cells can be comprehensively improved, solving the technical problem of how to improve the efficiency of solar cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 A schematic structural diagram of a solar cell provided according to an embodiment of the present application is shown;

[0017] Figure 2 A schematic diagram of a process for preparing a solar cell provided in accordance with an embodiment of the present application is shown;

[0018] Figure 3 A schematic structural diagram of an N-type substrate provided according to an embodiment of the present application is shown;

[0019] Figure 4 Shown in Figure 3 A schematic structural diagram of forming a first preliminary tunnel dielectric layer on the basis of;

[0020] Figure 5 Shown in Figure 4A schematic structural diagram of forming a preliminary N-type doped layer and a second preliminary tunnel dielectric layer on the basis of the present invention;

[0021] Figure 6 Shown in Figure 5 A schematic diagram of a structure in which a protective layer is formed on the basis of

[0022] Figure 7 Shown in Figure 6 A schematic diagram of a structure in which a P-type region and an N-type region are formed on the basis of

[0023] Figure 8 Shown in Figure 7 Structural diagram of velvet making based on the above;

[0024] Fig. 9 Shown in Figure 8 A schematic diagram of a structure in which a passivation layer and an anti-reflection layer are formed on the basis of

[0025] Fig.10 Shown in Fig. 9 A schematic structural diagram of a first intrinsic amorphous silicon layer, a first P-type amorphous silicon layer, a second intrinsic amorphous silicon layer and a second P-type amorphous silicon layer formed on the basis of;

[0026] Fig.11 Shown in Fig.10 A schematic structural diagram of removing a first intrinsic amorphous silicon layer and a first P-type amorphous silicon layer from a part of the N-type region;

[0027] Fig.12 Shown in Fig.11 A schematic structural diagram of forming a first transparent conductive layer and a second transparent conductive layer on the basis of

[0028] Fig.13 Shown in Fig.12 Schematic diagram of the structure of laser isolating P-type area and N-type area based on.

[0029] The above drawings include the following reference numerals:

[0030] 10. N-type substrate; 20. N-type region; 201. tunneling dielectric layer; 202. N-type doped layer; 203. first intrinsic amorphous silicon layer; 204. first P-type amorphous silicon layer; 205. first transparent conductive layer; 206. first electrode; 30. P-type region; 301. second intrinsic amorphous silicon layer; 302. second P-type amorphous silicon layer; 303. second transparent conductive layer; 304. second electrode; 40. passivation layer; 50. anti-reflection layer; 60. first preliminary tunneling dielectric layer; 61. preliminary N-type doped layer; 62. second preliminary tunneling dielectric layer; 63. protective layer; 64. groove; 70. first region; 80. second region. DETAILED DESCRIPTION

[0031] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0032] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] As introduced in the background technology, the problem of how to improve the efficiency of solar cells in the prior art needs to be solved urgently. To solve the above problem, the embodiments of the present application provide a solar cell and a method for preparing a solar cell.

[0035] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0036] Figure 1 Schematic diagram of the structure of a solar cell according to an embodiment of the present application. Figure 1 As shown, including:

[0037] An N-type substrate 10, wherein the N-type substrate 10 comprises a first surface and a second surface opposite to each other, wherein the first surface is provided with a P-type region 30 and an N-type region 20 with an interval;

[0038] Specifically, the N-type substrate 10 is doped with an N-type doping element, and the N-type doping element may be any one of the five group elements such as phosphorus (P), bismuth (Bi), antimony (Sb) or arsenic (As). In some embodiments, the solar cell is a single-sided cell, the second surface is used as a light-receiving surface for receiving incident light, and the first surface is used as a backlight surface. In some embodiments, the solar cell is a double-sided cell, then the first surface and the second surface can both be used as light-receiving surfaces, and can both be used to receive incident light. It can be understood that the backlight surface referred to in the embodiments of the present application can also receive incident light, but the degree of receiving the incident light is weaker than the degree of receiving the incident light by the light-receiving surface, and is therefore defined as the backlight surface. In some embodiments, a velvet process may be performed on at least one of the first surface and the second surface to form a velvet surface, which can enhance the absorption utilization rate of the first surface or the second surface for the incident light. The backlight surface of the solar cell may be a polished surface, that is, the backlight surface is flatter than the light-receiving surface. If the solar cell is a double-sided cell, a velvet surface may be formed on both the light-receiving surface and the backlight surface.

[0039] A tunneling dielectric layer 201, an N-type doped layer 202, a first intrinsic amorphous silicon layer 203, a first P-type amorphous silicon layer 204, a first transparent conductive layer 205 and a first electrode 206 located in the N-type region 20, wherein the doping concentration of the N-type doped layer 202 is greater than the doping concentration of the tunneling dielectric layer 201, the tunneling dielectric layer 201 and the N-type doped layer 202 have the same doping type, and the first transparent conductive layer 205 is in contact with the first electrode 206;

[0040] Specifically, the N-type region 20 forms a high-low junction with the N-type substrate 10. The material of the tunnel dielectric layer may be one or more of silicon oxide, silicon oxynitride and aluminum oxide. Intrinsic amorphous silicon material refers to amorphous (amorphous) silicon material, whose atomic structure is not an orderly arranged lattice structure, but presents a disordered, non-periodic state. The first electrode 206 may be prepared by electroplating, screen printing, physical vapor deposition and sputtering, and laser scribing. The width of the N-type region 20 may range from 200 to 800 μm.

[0041] The second intrinsic amorphous silicon layer 301, the second P-type amorphous silicon layer 302, the second transparent conductive layer 303 and the second electrode 304 are located in the P-type region 30, and the second electrode 304 and the second transparent conductive layer 303;

[0042] Specifically, the P-type region 30 and the N-type substrate 10 form a PN junction. When incident light irradiates the PN junction, the PN junction generates corresponding electron-hole pairs. Under the action of the potential barrier electric field of the PN junction, the electron-hole pairs are separated, and the electrons are driven to the P-type region 30, and the holes are driven to the N-type region 20, generating a photogenerated electric field, thereby generating an electromotive force between the P-type region 30 and the N-type region 20, and outputting a photocurrent. The P-type region 30 is passivated with ultra-low-compound amorphous silicon material prepared at low temperature, and the surface composite current density is less than 1fA / cm 2 . In a specific embodiment, the second intrinsic amorphous silicon layer 301 and the first intrinsic amorphous silicon layer 203 can be formed simultaneously. The second P-type amorphous silicon layer 302 and the first P-type amorphous silicon layer 204 can be formed simultaneously. The second transparent conductive layer can be formed simultaneously with the first transparent conductive layer 205. The second electrode 304 can be prepared by electroplating, screen printing, physical vapor deposition and sputtering, laser scribing, etc. The width of the P-type region 30 can range from 200 to 800 μm.

[0043] A passivation layer 40 and an anti-reflection layer 50 are located on the second surface.

[0044] Specifically, the second passivation layer 40 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the passivation layer 40 may be at least one of silicon oxide and silicon nitride, and the material of the anti-reflection layer 50 may be at least one of aluminum oxide and silicon oxynitride. Using the above materials as the passivation layer 40 and the anti-reflection layer 50 can reduce the surface composite current density to less than 4fA / cm 2 In addition, the preparation process of the passivation layer 40 and the anti-reflection layer 50 is simple and the cost is low.

[0045] Through this embodiment, a solar cell is provided, comprising: an N-type substrate, the N-type substrate comprising a first surface and a second surface opposite to each other, the first surface being provided with a P-type region and an N-type region with an interval; a tunneling dielectric layer, an N-type doping layer, a first intrinsic amorphous silicon layer, a first P-type amorphous silicon layer, a first transparent conductive layer and a first electrode located in the N-type region, wherein the doping concentration of the N-type doping layer is greater than the doping concentration of the tunneling dielectric layer, the tunneling dielectric layer and the N-type doping layer have the same doping type, and the first transparent conductive layer is in contact with the first electrode; a second intrinsic amorphous silicon layer, a second P-type amorphous silicon layer, a second transparent conductive layer and a second electrode located in the P-type region, the second electrode being in contact with the second transparent conductive layer and the second P-type amorphous silicon layer, respectively; and a passivation layer and an anti-reflection layer located on the second surface. In the N-type region, since the doping concentration of the tunnel dielectric layer is lower than that of the N-type doping layer, the tunnel dielectric layer close to the N-type substrate forms a low-compound dielectric layer, which has good chemical passivation and field passivation effects, and also has certain transmission performance; on the side away from the N-type substrate, since the doping concentration of the N-type doping layer is greater than the doping concentration of the tunnel dielectric layer, a localized heavily doped N-type doping layer is formed, which can improve the electrode contact performance. The P region uses ultra-low-compound amorphous silicon passivation, which has a small surface composite current density and is currently the best P-type passivation material. Combined with the above-mentioned improvement in chemical passivation and field passivation effects, the improvement in electrode contact performance and the reduction in surface composite current density, the efficiency of solar cells can be comprehensively improved, solving the technical problem of how to improve the efficiency of solar cells.

[0046] In a specific implementation process, the first surface has a plurality of grooves arranged at intervals, and the P-type region is arranged in the grooves. The above arrangement can further increase the distance between adjacent first electrodes and second electrodes, reduce power loss or short circuit, and further improve the efficiency of the solar cell.

[0047] Specifically, since the P-type region is disposed in the groove, and the number of film layers in the P-type region is less than the number of film layers in the N-type region, in the arrangement direction of the P-type region and the N-type region, the P-type region and the N-type region are not on the same straight line, and the N-type region is farther from the second surface than the P-type region.

[0048] In some embodiments, the tunnel dielectric layer is located on a side of the N-type doped layer close to the first surface and on a sidewall of the N-type doped layer. The tunnel dielectric layer allows majority carriers (electrons) to tunnel into the N-type doped layer while blocking the recombination of minority carriers (holes), thereby achieving selective carrier transmission, thereby greatly reducing the metal contact recombination current and further improving the open circuit voltage and short circuit current of the battery.

[0049] Specifically, the tunnel dielectric layer has a groove, and the N-type doped layer is located in the groove. That is to say, the N-type doped layer is located on a portion of the surface of the tunnel dielectric layer, and the tunnel dielectric layer can realize selective transmission of carriers in a first direction and a second direction, wherein the first direction is the arrangement direction of the P-type region and the N-type region, and the second direction is the thickness direction of the N-type substrate.

[0050] In order to further achieve contact between the first transparent conductive layer and the N-type doped layer, in some embodiments, the first intrinsic amorphous silicon layer includes two intrinsic amorphous silicon portions with a first interval, the first P-type amorphous silicon layer includes two P-type amorphous silicon portions with a second interval, the orthographic projection of the first interval on the N-type substrate and the orthographic projection of the second interval on the N-type substrate overlap, the first transparent conductive layer is located in the first interval, in the second interval, and on the surface of the first P-type amorphous silicon layer away from the N-type substrate, and the first electrode is located on a partial surface of the first transparent conductive layer away from the N-type substrate.

[0051] Specifically, during the preparation of the N-type region, after the first intrinsic amorphous silicon layer and the first P-type amorphous silicon layer are prepared, the first intrinsic amorphous silicon layer and the first P-type amorphous silicon layer are grooved to form a groove, and a first transparent conductive layer is formed in the groove and on the surface of the first P-type amorphous silicon layer away from the first intrinsic amorphous silicon layer.

[0052] In some embodiments, the second transparent conductive layer includes two transparent conductive portions with a third interval, and the second electrode is located in the third interval and on a portion of the surface of the second transparent conductive layer away from the N-type substrate. The above arrangement can achieve contact between the second electrode and the second P-type amorphous silicon layer, further improving the transmission efficiency of the second electrode.

[0053] Specifically, during the preparation of the P-type region, after the second transparent conductive layer is prepared, the second transparent conductive layer can be grooved to form a groove, and a second electrode is formed in the groove and on the surface of the second transparent conductive layer away from the second P-type amorphous silicon layer.

[0054] In some other embodiments, the doping concentration of the tunnel dielectric layer is 1E 17 ~1E 19 cm -3 The doping concentration of the N-type doped layer is 1E 19 ~5E 20 cm -3 The above arrangement can further simultaneously satisfy the low recombination of the tunnel dielectric layer and improve the electrode contact performance of the N-type doped layer.

[0055] Specifically, the doping concentration of the tunnel dielectric layer can be 1E 17 ~1E18 cm -3 , 1E 18 ~1E 19 cm -3 The doping concentration of the N-type doped layer is 1E 19 ~1E 20 cm -3 , 1E 20 ~2E 20 cm -3 , 2E 20 ~3E 20 cm -3 , 3E 20 ~4E 20 cm -3 or 4E 20 ~5E 20 cm -3 .

[0056] In another specific embodiment, the thickness of the tunnel dielectric layer is in the range of 1 to 3 nm, and the thickness of the N-type doped layer is in the range of 2 to 8 nm. The above thickness setting can further provide a thinner tunnel dielectric layer and a thicker N-type doped layer, and the thinner tunnel dielectric layer can further help accelerate the migration and extraction of majority carriers and improve electrical contact performance, and the thicker N-type doped layer can further improve the contact performance of the first electrode.

[0057] Specifically, the thickness of the tunnel dielectric layer may be 1 to 1.5 nm, 1.5 to 2 nm, 2 to 2.5 nm or 2.5 to 3 nm. In practical applications, the thickness of the N-type doped layer may be twice or three times that of the tunnel dielectric layer. The width of the N-type doped layer in the first direction may be in the range of 20 to 80 μm, and the ratio of the maximum width of the N-type doped layer in the first direction to the maximum width of the tunnel dielectric layer in the first direction may be in the range of 1:10 to 2:5.

[0058] The present application also provides a method for preparing a solar cell. Figure 2 As shown, the method for preparing a solar cell comprises the following steps:

[0059] Step S201, providing an N-type substrate, wherein the N-type substrate comprises a first surface and a second surface opposite to each other;

[0060] Specifically, the N-type substrate 10 is doped with an N-type doping element, and the N-type doping element may be any one of the five group elements such as phosphorus (P), bismuth (Bi), antimony (Sb) or arsenic (As). In some embodiments, the solar cell is a single-sided cell, the second surface is used as a light-receiving surface for receiving incident light, and the first surface is used as a backlight surface. In some embodiments, the solar cell is a double-sided cell, then the first surface and the second surface can both be used as light-receiving surfaces, and can both be used to receive incident light. It can be understood that the backlight surface referred to in the embodiments of the present application can also receive incident light, but the degree of receiving the incident light is weaker than the degree of receiving the incident light by the light-receiving surface, and is therefore defined as the backlight surface. In some embodiments, a velvet process may be performed on at least one of the first surface and the second surface to form a velvet surface, which can enhance the absorption utilization rate of the first surface or the second surface for the incident light. The backlight surface of the solar cell may be a polished surface, that is, the backlight surface is flatter than the light-receiving surface. If the solar cell is a double-sided cell, a velvet surface may be formed on both the light-receiving surface and the backlight surface.

[0061] Step S202, forming a first preliminary tunneling dielectric layer on the first surface;

[0062] Specifically, the material of the first preliminary tunnel dielectric layer may be one or more of silicon oxide, silicon oxynitride and aluminum oxide. In practical applications, the first preliminary tunnel dielectric layer may be formed on the first surface and the second surface at the same time.

[0063] Step S203, printing a doping paste on a portion of the surface of the first preliminary tunneling dielectric layer and performing annealing treatment to form a preliminary N-type doping layer, and the remaining first preliminary tunneling dielectric layer forms a second preliminary tunneling dielectric layer;

[0064] Specifically, part of the surface of the first preliminary tunnel dielectric layer is doped to form a preliminary N-type doped layer with a better doping concentration, which can not only improve the contact performance between the N-type doped layer and the first electrode in the contact area, but also ensure the passivation effect of the second preliminary tunnel dielectric layer in the non-contact area.

[0065] Step S204, forming a protective layer on a side of the N-type doped layer away from the first surface;

[0066] Specifically, the material of the protective layer can be one or more of silicon oxide, aluminum oxide and silicon oxynitride. The protective layer is used to protect the morphology of the N-type region from being affected during the subsequent texturing and etching process. A plurality of first regions and a plurality of second regions are arranged on the first surface, and the first regions and the second regions are arranged at intervals.

[0067] Step S205, removing part of the protective layer to obtain a preliminary structure having a plurality of spaced grooves, wherein the remaining preliminary N-type doped layer forms an N-type doped layer, and the remaining second preliminary tunnel dielectric layer forms a tunnel dielectric layer, and the preliminary structure includes an N-type region and a P-type region;

[0068] Specifically, the portion corresponding to the groove is the above-mentioned second region, which is used to subsequently form a P-type region, and the portion corresponding to the ungrooved portion is the above-mentioned first region, which is used to subsequently form an N-type region. In the second direction, the minimum distance between the bottom surface of the groove and the second surface is less than the minimum distance between the tunneling dielectric layer and the second surface. The width of the N-type doped layer in the first direction ranges from 20 to 80 μm. In practical applications, the ratio of the width of the above-mentioned N-type doped layer in the first direction to the width of the preliminary tunneling dielectric layer in the first direction ranges from 1:10 to 2:5. In addition, in the second direction, the ratio of the thickness of the above-mentioned tunneling dielectric layer to the thickness of the N-type doped layer is 1:3 to 1:2.

[0069] Step S206, sequentially forming a first intrinsic amorphous silicon layer, a first P-type amorphous silicon layer, a first transparent conductive layer and a first electrode in the N-type region;

[0070] Step S207, sequentially forming a second intrinsic amorphous silicon layer, a second P-type amorphous silicon layer, a second transparent conductive layer and a second electrode in the P-type region;

[0071] Specifically, the second intrinsic amorphous silicon layer and the first intrinsic amorphous silicon layer can be formed simultaneously. The second P-type amorphous silicon layer and the first P-type amorphous silicon layer can be formed simultaneously. The first electrode and the second electrode can be prepared by electroplating, screen printing, physical vapor deposition and sputtering, laser scribing, etc.

[0072] Step S208 , forming a passivation layer and an anti-reflection layer on the second surface.

[0073] Specifically, the second passivation layer can be a single-layer structure or a multi-layer structure. In some embodiments, the material of the passivation layer can be at least one of silicon oxide and silicon nitride, and the material of the anti-reflection layer can be at least one of aluminum oxide and silicon oxynitride. Using the above materials as the passivation layer and the anti-reflection layer can reduce the surface composite current density to less than 4fA / cm 2 In addition, the preparation process of the passivation layer and the anti-reflection layer is simple and the cost is low.

[0074] Through this embodiment, a method for preparing a solar cell is provided, first, an N-type substrate is provided, the N-type substrate includes a first surface and a second surface opposite to each other; a first preliminary tunneling dielectric layer is formed on the first surface; then, a doping paste is printed on a part of the surface of the first preliminary tunneling dielectric layer and annealed to form a preliminary N-type doping layer, and the remaining first preliminary tunneling dielectric layer forms a second preliminary tunneling dielectric layer; a protective layer is formed on a side of the N-type doping layer away from the first surface; then, part of the protective layer is removed to obtain a preliminary structure with a plurality of spaced grooves, in which the remaining preliminary N-type doping layer forms an N-type doping layer, and the remaining second preliminary tunneling dielectric layer forms a tunneling dielectric layer, and the preliminary structure includes an N-type region and a P-type region; a first intrinsic amorphous silicon layer, a first P-type amorphous silicon layer, a first transparent conductive layer and a first electrode are sequentially formed in the N-type region; finally, a second intrinsic amorphous silicon layer, a second P-type amorphous silicon layer, a second transparent conductive layer and a second electrode are sequentially formed in the P-type region; and a passivation layer and an anti-reflection layer are formed on the second surface. In the N-type region, since the doping concentration of the tunnel dielectric layer is lower than that of the N-type doping layer, the tunnel dielectric layer close to the N-type substrate forms a low-compound dielectric layer, which has good chemical passivation and field passivation effects, and also has certain transmission performance; on the side away from the N-type substrate, since the doping concentration of the N-type doping layer is greater than the doping concentration of the tunnel dielectric layer, a localized heavily doped N-type doping layer is formed, which can improve the electrode contact performance. The P region uses ultra-low-compound amorphous silicon passivation, which has a small surface composite current density and is currently the best P-type passivation material. Combined with the above-mentioned improvement in chemical passivation and field passivation effects, the improvement in electrode contact performance and the reduction in surface composite current density, the efficiency of solar cells can be comprehensively improved, solving the technical problem of how to improve the efficiency of solar cells.

[0075] In order to further prevent the annealing temperature from being too high, causing the N-type doped layer to diffuse into the tunnel dielectric layer and affecting the passivation effect, the temperature of the above annealing treatment is 700-1000°C.

[0076] The deposition temperature of the first preliminary tunnel dielectric layer is 600-800° C. The above temperature setting can further improve the quality of the first preliminary tunnel dielectric layer.

[0077] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the method for preparing a solar cell of the present application is described in detail below in conjunction with specific embodiments.

[0078] This embodiment relates to a specific method for preparing a solar cell. Figure 1 and Figures 3 to 13 As shown, the following steps are included:

[0079] Step S1: Provide a single crystal silicon N-type substrate 10 with a thickness of 150 μm, a resistivity of 5 ohm.cm, and a crystal orientation of <100> , and polish the silicon wafer to obtain Figure 3 The structure shown;

[0080] Step S2: Deposit phosphorus-doped silicon oxide on both the first and second surfaces of the N-type substrate 10 to form a first preliminary tunnel dielectric layer 60 at a deposition temperature of 600-800° C., a thickness of 6 nm, and a doping concentration of 2E 19 cm -3 , and get Figure 4 The structure shown;

[0081] Step S3: Patterning and printing phosphorus paste to form a localized heavily doped N region pattern, and simultaneously performing annealing activation to form a preliminary N-type doping layer 61, and the remaining first preliminary tunneling dielectric layer forms a second preliminary tunneling dielectric layer 62, so as to obtain Figure 5 The structure shown;

[0082] Step S4: A 60 nm protective layer 63 is grown on the surface of the prepared N-type doped layer 61 and the second prepared tunnel dielectric layer 62 away from the N-type substrate 10. The material of the protective layer is silicon oxide, and a plurality of first regions 70 and second regions 80 are arranged on the first surface. The first regions 70 and the second regions 80 are arranged at intervals. Figure 6 The structure shown;

[0083] Step S5: According to the position of the N-region pattern, the laser is applied to the remaining protective layer 63 for ablation, that is, a plurality of second regions 80 are removed to form the groove 64 of the P-type region 30, the remaining second preliminary tunnel dielectric layer 62 forms the tunnel dielectric layer 201 of the N-type region, and the remaining preliminary N-type doping layer 61 forms the N-type doping layer 202 of the N-type region, and the following is obtained: Figure 7 The structure shown;

[0084] Step S6: Perform wet chemical texturing on the second surface to grow a new pyramid morphology. The morphology of the N-type region 20 is not affected under the protection of the protective layer 63. Figure 8 The structure shown;

[0085] Step S7: A 6 nm passivation layer is grown on the second surface by ALD, the material of the passivation layer is aluminum oxide, and then an 80 nm anti-reflection layer is grown on the second surface by PECVD, the material of the anti-reflection layer is silicon nitride, and the following is obtained: Fig. 9 The structure shown;

[0086] Step S8: forming an intrinsic amorphous silicon layer and a P-type amorphous silicon layer in the groove, on the surface of the N-type doped layer 202, and on the surface of the tunnel dielectric layer 201; the intrinsic amorphous silicon layer in the N-type region forms a first intrinsic amorphous silicon layer 203, the P-type amorphous silicon layer in the N-type region forms a first P-type amorphous silicon layer 204, the intrinsic amorphous silicon layer in the P-type region forms a second intrinsic amorphous silicon layer 301, and the P-type amorphous silicon layer in the P-type region forms a second P-type amorphous silicon layer 302, with a thickness of 15 nm, and obtaining the following Fig.10 The structure shown;

[0087] Step S9: The first intrinsic amorphous silicon layer 203 and the first P-type amorphous silicon layer 204 deposited on the surface of the N-type region 20 are etched away by laser, and the Fig.11 The structure shown;

[0088] Step S10: low temperature deposition of a transparent conductive layer with a thickness of 75 nm, the transparent conductive layer in the N-type region forms the first transparent conductive layer 205, and the transparent conductive layer in the P-type region forms the second transparent conductive layer 303, to obtain Fig.12 The structure shown;

[0089] Step S11: Isolate the N-type region 20 and the P-type region 30 by laser scribing to obtain Fig.13 The structure shown;

[0090] Step S12: metallizing the second surface by screen printing or laser transfer to form the first electrode 206 and the second electrode 304, and obtaining Figure 1 The structure shown.

[0091] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0092] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0093] 1) The solar cell of the present application comprises: an N-type substrate, the N-type substrate comprises a first surface and a second surface opposite to each other, the first surface is provided with a P-type region and an N-type region with an interval; a tunneling dielectric layer, an N-type doped layer, a first intrinsic amorphous silicon layer, a first P-type amorphous silicon layer, a first transparent conductive layer and a first electrode located in the N-type region, wherein the doping concentration of the N-type doped layer is greater than the doping concentration of the tunneling dielectric layer, the tunneling dielectric layer and the N-type doped layer have the same doping type, and the first transparent conductive layer is in contact with the first electrode; a second intrinsic amorphous silicon layer, a second P-type amorphous silicon layer, a second transparent conductive layer and a second electrode located in the P-type region, the second electrode being in contact with the second transparent conductive layer and the second P-type amorphous silicon layer respectively; a passivation layer and an anti-reflection layer located on the second surface. In the N-type region, since the doping concentration of the tunnel dielectric layer is lower than that of the N-type doping layer, the tunnel dielectric layer close to the N-type substrate forms a low-compound dielectric layer, which has good chemical passivation and field passivation effects, and also has certain transmission performance; on the side away from the N-type substrate, since the doping concentration of the N-type doping layer is greater than the doping concentration of the tunnel dielectric layer, a localized heavily doped N-type doping layer is formed, which can improve the electrode contact performance. The P region uses ultra-low-compound amorphous silicon passivation, which has a small surface composite current density and is currently the best P-type passivation material. Combined with the above-mentioned improvement in chemical passivation and field passivation effects, the improvement in electrode contact performance and the reduction in surface composite current density, the efficiency of solar cells can be comprehensively improved, solving the technical problem of how to improve the efficiency of solar cells.

[0094] 2) The preparation method of the solar cell of the present application, first, provides an N-type substrate, the N-type substrate includes a first surface and a second surface relative to each other; forms a first preliminary tunneling dielectric layer on the first surface; then, prints a doping paste on a part of the surface of the first preliminary tunneling dielectric layer and performs an annealing treatment to form a preliminary N-type doped layer, and the remaining first preliminary tunneling dielectric layer forms a second preliminary tunneling dielectric layer; forms a protective layer on the side of the N-type doped layer away from the first surface; then removes part of the protective layer to obtain a preliminary structure with a plurality of spaced grooves, in which the remaining preliminary N-type doped layer forms an N-type doped layer, and the remaining second preliminary tunneling dielectric layer forms a tunneling dielectric layer, and the preliminary structure includes an N-type region and a P-type region; forms a first intrinsic amorphous silicon layer, a first P-type amorphous silicon layer, a first transparent conductive layer and a first electrode in the N-type region in sequence; finally, forms a second intrinsic amorphous silicon layer, a second P-type amorphous silicon layer, a second transparent conductive layer and a second electrode in sequence in the P-type region; forms a passivation layer and an anti-reflection layer on the second surface. In the N-type region, since the doping concentration of the tunnel dielectric layer is lower than that of the N-type doping layer, the tunnel dielectric layer close to the N-type substrate forms a low-compound dielectric layer, which has good chemical passivation and field passivation effects, and also has certain transmission performance; on the side away from the N-type substrate, since the doping concentration of the N-type doping layer is greater than the doping concentration of the tunnel dielectric layer, a localized heavily doped N-type doping layer is formed, which can improve the electrode contact performance. The P region uses ultra-low-compound amorphous silicon passivation, which has a small surface composite current density and is currently the best P-type passivation material. Combined with the above-mentioned improvement in chemical passivation and field passivation effects, the improvement in electrode contact performance and the reduction in surface composite current density, the efficiency of solar cells can be comprehensively improved, solving the technical problem of how to improve the efficiency of solar cells.

[0095] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A solar cell, characterized in that: include: An N-type substrate, the N-type substrate comprising a first surface and a second surface opposite to each other, the first surface being provided with a P-type region and an N-type region with an interval; A tunneling dielectric layer, an N-type doped layer, a first intrinsic amorphous silicon layer, a first P-type amorphous silicon layer, a first transparent conductive layer and a first electrode located in the N-type region, wherein the doping concentration of the N-type doped layer is greater than the doping concentration of the tunneling dielectric layer, the tunneling dielectric layer and the N-type doped layer have the same doping type, and the first transparent conductive layer is in contact with the first electrode; A second intrinsic amorphous silicon layer, a second P-type amorphous silicon layer, a second transparent conductive layer and a second electrode located in the P-type region, wherein the second electrode contacts the second transparent conductive layer; A passivation layer and an anti-reflection layer are located on the second surface.

2. The solar cell according to claim 1, characterized in that The first surface has a plurality of grooves arranged at intervals, and the P-type regions are arranged in the grooves.

3. The solar cell according to claim 1, characterized in that The tunnel dielectric layer is located on a side of the N-type doping layer close to the first surface and on a side wall of the N-type doping layer.

4. The solar cell according to claim 1, characterized in that The first intrinsic amorphous silicon layer includes two intrinsic amorphous silicon portions with a first interval, the first P-type amorphous silicon layer includes two P-type amorphous silicon portions with a second interval, the orthographic projection of the first interval on the N-type substrate and the orthographic projection of the second interval on the N-type substrate overlap, the first transparent conductive layer is located in the first interval, in the second interval, and on the surface of the first P-type amorphous silicon layer away from the N-type substrate, and the first electrode is located on a partial surface of the first transparent conductive layer away from the N-type substrate.

5. The solar cell according to claim 1, characterized in that: The second transparent conductive layer includes two transparent conductive portions with a third interval, and the second electrode is located in the third interval and on a portion of the surface of the second transparent conductive layer away from the N-type substrate.

6. The solar cell according to any one of claims 1 to 5, characterized in that: The doping concentration of the tunnel dielectric layer is 1E 17 ~1E 19 cm -3 The doping concentration of the N-type doping layer is 1E 19 ~5E 20 cm -3 .

7. The solar cell according to any one of claims 1 to 5, characterized in that: The thickness of the tunnel dielectric layer is in the range of 1 to 3 nm, and the thickness of the N-type doping layer is in the range of 2 to 8 nm.

8. A method for preparing a solar cell, characterized in that: include: Providing an N-type substrate, the N-type substrate comprising a first surface and a second surface opposite to each other; forming a first preliminary tunneling dielectric layer on the first surface; Printing a doping paste on a portion of the surface of the first preliminary tunneling dielectric layer and performing an annealing treatment to form a preliminary N-type doping layer, and the remaining first preliminary tunneling dielectric layer forms a second preliminary tunneling dielectric layer; forming a protective layer on a side of the N-type doped layer away from the first surface; Removing part of the protective layer to obtain a preliminary structure having a plurality of spaced grooves, wherein the remaining preliminary N-type doped layer forms an N-type doped layer, and the remaining second preliminary tunnel dielectric layer forms a tunnel dielectric layer, the doping concentration of the N-type doped layer is greater than the doping concentration of the tunnel dielectric layer, and the preliminary structure includes an N-type region and a P-type region; In the N-type region, a first intrinsic amorphous silicon layer, a first P-type amorphous silicon layer, a first transparent conductive layer and a first electrode are sequentially formed; In the P-type region, a second intrinsic amorphous silicon layer, a second P-type amorphous silicon layer, a second transparent conductive layer and a second electrode are sequentially formed; A passivation layer and an anti-reflection layer are formed on the second surface.

9. The method for preparing a solar cell according to claim 8, characterized in that: The annealing treatment temperature is 700-1000°C.

10. The method for preparing a solar cell according to claim 8, characterized in that: The deposition temperature of the first preliminary tunneling dielectric layer is 600-800°C.

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