Selector, semiconductor device, and method of manufacturing selector and semiconductor device

Abstract

The invention relates to a selector, a semiconductor device and a method of manufacturing the selector and the semiconductor device. A selector includes: a substrate including carbon; and a dopant that is implanted into the substrate. A method for manufacturing a selector includes: forming a carbon layer; and implanting a dopant into the carbon layer. A semiconductor device includes: a selector pattern including carbon as a substrate and a dopant implanted by an ion implantation process; and a memory pattern disposed at an upper portion or a lower portion of the selector pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0141523, filed on October 20, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to memory circuits or devices and applications thereof in semiconductor devices. Background Art

[0004] Recent demands for miniaturization, low power consumption, high performance, and diversification of electronic devices require semiconductor devices to be configured to store information in a variety of electronic devices such as computers and portable communication devices. Researchers and the industry are studying and developing such semiconductor devices. Among semiconductor devices, some devices can store data by utilizing the property of switching between different resistance states according to the applied voltage or current, such as resistive random access memory (RRAM), phase change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), electric fuses, etc. Summary of the invention

[0005] Embodiments of the present disclosure relate to a selector having excellent electrical and physical characteristics by using carbon as a host of the selector and implanting dopant ions into the carbon, a semiconductor device including the selector, and a method for manufacturing the semiconductor device.

[0006] According to an embodiment of the present disclosure, a selector includes: a substrate including carbon; and a dopant implanted into the substrate.

[0007] According to another embodiment of the present disclosure, a method for manufacturing a selector includes: forming a carbon layer; and implanting a dopant into the carbon layer.

[0008] According to another embodiment of the present disclosure, a semiconductor device includes: a selector pattern including carbon as a base material and a dopant implanted through an ion implantation process; and a memory pattern disposed above or below the selector pattern.

[0009] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming a carbon layer over a substrate; forming a selector layer by implanting dopants through an ion implantation process; forming a memory layer on the upper or lower portion of the selector layer; and forming a storage cell including a memory pattern and a selector pattern by etching the memory layer and the selector layer through an etching process using a mask pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A and Figure 1B A method for manufacturing a selector according to an embodiment of the present disclosure is shown.

[0011] Figure 2A and Figure 2B A semiconductor device according to an embodiment of the present disclosure is shown.

[0012] FIG. 3A to FIG. 3F A method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0013] 4A to 4F A method for manufacturing a semiconductor device according to another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0014] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments may be embodied in different forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In the present disclosure, the same figure numerals refer to the same parts in multiple figures and embodiments of the present disclosure.

[0015] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0016] The drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being on a second layer or on a substrate, it refers not only to the case where the first layer is directly formed on the second layer or the substrate, but also to the case where a third layer exists between the first layer and the second layer or between the first layer and the substrate.

[0017] Figure 1A and Figure 1B A method for manufacturing a selector according to an embodiment of the present disclosure is shown.

[0018] exist Figure 1A and Figure 1B In the embodiment of the present invention, only the method for manufacturing the selector is shown, and the description of the structures other than the selector provided at the upper and lower parts of the selector is omitted.

[0019] Reference Figure 1A , a carbon layer CL can be formed.

[0020] The carbon layer CL may be used as a matrix of a substrate forming a selector. The carbon layer CL may have an amorphous phase that can easily participate in a chemical reaction, and when a dopant such as arsenic (As) is ion-implanted, a new structural bond may be easily formed, and the metallic state of the dopant may be well maintained. Therefore, the ion-implanted dopant can more easily and effectively form a trap site for conductive carriers, thereby effectively realizing the threshold switching operation characteristics of the selector. In addition, since the carbon layer CL has a low density and high thermal conductivity, the selector based on the carbon layer CL may have excellent electrical and physical properties.

[0021] The carbon layer CL may be formed by depositing carbon (C) using a physical deposition method such as a sputtering method.

[0022] According to one embodiment of the present disclosure, the carbon layer CL may include carbon (C) atoms as a main component, and may also include at least one of nitrogen (N) atoms, oxygen (O) atoms, and hydrogen (H) atoms. In an embodiment, at least one of nitrogen (N) atoms, oxygen (O) atoms, and hydrogen (H) atoms may be doped onto the carbon layer CL by performing a carbon (C) deposition process in a gas atmosphere of at least one of nitrogen, oxygen, and hydrogen.

[0023] Reference Figure 1B The selector 10 may be formed by implanting a dopant into the carbon layer CL. For example, ion implantation may be used to implant the dopant into the carbon layer CL.

[0024] The dopant may form a trap site for conductive carriers, thereby allowing the selector 10 to perform a threshold switching operation.

[0025] The dopant may include, for example, at least one of arsenic (As), phosphorus (P), and antimony (Sb).

[0026] According to the present disclosure Figure 1B In the illustrated embodiment, the dopant may be implanted using an ion implantation process, however, the present disclosure may not be limited to the method used to implant the dopant, and other suitable methods may be used without departing from the scope of the present disclosure.

[0027] According to an embodiment of the present disclosure, the thickness of the selector 10 may be the same as the thickness of the carbon layer CL. According to another embodiment of the present disclosure, the thickness of the selector 10 may be less than the thickness of the carbon layer CL. This is because a portion of the upper portion of the carbon layer CL may be lost due to damage that may occur during ion implantation.

[0028] According to an embodiment of the present disclosure, the selector 10 may include amorphous carbon (C) as a main component, and a dopant may be implanted in the selector 10 by an ion implantation process. In addition, in addition to carbon (C), the selector 10 may optionally further include at least one of nitrogen (N), oxygen (O), and hydrogen (H). The dopant may include at least one of arsenic (As), phosphorus (P), and antimony (Sb).

[0029] Unlike conventional doped nitride or oxide based selectors, the selector 10 according to the embodiment of the present disclosure may include carbon (C) in an amorphous phase ready to participate in a chemical reaction as a main component, and a dopant implanted using an ion implantation process. When a dopant such as arsenic (As) is ion implanted, amorphous carbon may form defects and / or vacancies in the selector 10, and the metallic state of the formed dopant may be well maintained, thereby forming a trap site for conductive carriers more easily and more effectively. In an embodiment, the electrical characteristics of the selector 10 may be further improved. In addition, the physical characteristics of the selector 10 may be improved based on the basic characteristics of carbon as a main component. When the selector 10 includes at least one of nitrogen (N), oxygen (O) and hydrogen (H) in addition to carbon (C), carbon and the additional elements may form multiple phases, thereby further increasing the formation of defects and / or vacancies in the selector 10. Therefore, by controlling the degree of defect and / or vacancy formation, the electrical and / or physical characteristics required for the target selector 10 may be achieved.

[0030] The selector 10 according to the embodiment shown in the present disclosure may include carbon (C) as a substrate, and at least one of nitrogen (N), oxygen (O) and hydrogen (H) in addition to carbon (C). Studies have found that adding dopants to the substrate using ion implantation provides the selector 10 with excellent electrical and physical properties.

[0031] The selector 10 according to an embodiment of the present disclosure may be a current regulating layer configured to control the flow of current. For example, the selector 10 may reduce and / or suppress leakage current between storage elements of a semiconductor device. For example, the selector 10 may be formed to have a threshold switching characteristic: when the applied voltage is less than a predetermined threshold, the current hardly flows, and when the applied voltage is equal to or higher than a predetermined threshold, the current increases sharply. The threshold may be referred to as a threshold voltage, and the selector 10 may be implemented as an on state or an off state based on the threshold voltage.

[0032] The selector 10 according to an embodiment of the present disclosure may be implemented as a selector layer of a memory cell having a structure in which a selector layer and a memory layer are stacked at the upper and lower parts of a device, as shown in FIG. Figure 2A and Figure 2B Described in more detail.

[0033] Figure 2A and Figure 2B A semiconductor device according to an embodiment of the present disclosure is shown. To avoid unnecessary repeated description, the Figure 2A and Figure 2B Also in Figure 1A and Figure 1B A detailed description of any constituent elements appearing in.

[0034] Reference Figure 2A and Figure 2B , the semiconductor device according to the embodiment of the present disclosure may have a cross-point structure including a first conductive line 110 formed on a substrate 100 and extending in a first direction (D1), a second conductive line 130 disposed on the first conductive line 110 and extending in a second direction (D2) intersecting the first direction (D1), and a memory cell 120 disposed at a cross-point between the first conductive line 110 and the second conductive line 130. Figure 2A and Figure 2B In the illustrated embodiment, a plurality of memory cells 120, a plurality of first conductive lines 110, and a plurality of second conductive lines 130 are illustrated, wherein the plurality of first conductive lines 110 and the second conductive lines 130 form a plurality of intersections. Figure 2A and Figure 2B In the embodiment of FIG. 1 , it is also shown that the storage unit 120 is disposed at each of a plurality of intersections formed between the first conductive line 110 and the second conductive line 130 .

[0035] The substrate 100 may be any suitable semiconductor substrate. For example, the substrate 100 may include a semiconductor material, such as silicon. At least one structure (not shown) may be formed in the substrate 100. For example, the lower structure may include a driving circuit (not shown) electrically connected to control the first conductive line 110 and / or the second conductive line 130 formed on the substrate 100.

[0036] The first wire 110 and the second wire 130 can be coupled to the memory cell 120 and drive the memory cell 120 by transmitting a voltage or a current to the memory cell 120. The first wire 110 or the second wire 130 can be a word line. For example, the first wire 110 can be a word line, and then the second wire can be a bit line, or vice versa, the first wire 110 can be a bit line, and the second wire can be a word line. Each of the first wire 110 and the second wire 130 can have a single-layer structure. Each of the first wire 110 and the second wire 130 can have a multi-layer structure. Each of the first wire 110 and the second wire 130 can have a single-layer structure or a multi-layer structure, and can include a conductive material. The conductive material can include a metal, a metal nitride, a conductive carbon material, and a combination thereof. For example, each of the first conductive line 110 and the second conductive line 130 may include tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pd), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), or a combination thereof.

[0037] The memory cells 120 may be arranged in a matrix along the first direction (D1) and the second direction (D2) to overlap the intersection area of ​​the first conductive line 110 and the second conductive line 130. The size of each memory cell 120 may be equal to or smaller than the corresponding intersection area of ​​the corresponding pair of first conductive lines 110 and the second conductive line 130. In an embodiment, the size of each memory cell 120 may be larger than the corresponding intersection area of ​​the corresponding pair of first conductive lines 110 and the second conductive line 130.

[0038] The storage unit 120 may have a cylindrical shape. The storage unit 120 may have a square column shape. However, the shape of the storage unit may not be limited thereto.

[0039] Spaces between the first conductive line 110 , the second conductive line 130 , and the memory cell 120 may be filled with a dielectric material (not shown).

[0040] The memory cell 120 may include a stack structure including a selector pattern 122. For example, the memory cell 120 may include a lower electrode 121, a selector pattern 122, an intermediate electrode 123, a memory pattern 124, and an upper electrode 125.

[0041] Figure 2B The selector pattern 122 shown in FIG. 1 may correspond to Figure 1B The selector 10 shown in FIG. Figure 1BSimilar contents to those in the above-mentioned embodiments may be omitted in the embodiment of the present disclosure.

[0042] The lower electrode 121 may be formed as the lowermost portion of the memory cell 120. The lower electrode 121 may be electrically connected to the first conductive line 110, and thus may form a transmission path of current or voltage between the first conductive line 110 and the memory cell 120. The intermediate electrode 123 may be disposed between the selector pattern 122 and the memory pattern 124, and may be used to electrically connect them to each other and physically separate them from each other. The upper electrode 125 may form the uppermost portion of the memory cell 120, and thus may form a transmission path of current or voltage between the second conductive line 130 and the memory cell 120.

[0043] The lower electrode 121, the middle electrode 123 and the upper electrode 125 may have a single-layer structure or a multi-layer structure, including a variety of conductive materials, such as metals, nitrides, silicide-based materials and combinations thereof. For example, the lower electrode 121, the middle electrode 123 and the upper electrode 125 may include tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pd), chromium (Cr), tungsten nitride (WN), tungsten silicide (WSi), titanium silicide (TiSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN) or a combination thereof.

[0044] The lower electrode 121 , the intermediate electrode 123 , and the upper electrode 125 may be formed of the same material or different materials.

[0045] The lower electrode 121 , the intermediate electrode 123 , and the upper electrode 125 may have the same thickness or different thicknesses.

[0046] At least one of the lower electrode 121, the intermediate electrode 123, and the upper electrode 125 may be selectively omitted. For example, when the lower electrode 121 is omitted, the first wire 110 may replace the omitted lower electrode 121 to perform the function of the lower electrode 121. When the upper electrode 125 is omitted, the second wire 130 may replace the omitted upper electrode 125 to perform the function of the upper electrode 125.

[0047] The selector pattern 122 may be a current regulating layer configured to control the flow of current and prevent current leakage that may occur between the memory cells 121 that share the first conductive line 110 or the second conductive line 130. The selector pattern 122 may have a threshold switching characteristic: when the applied voltage is lower than a predetermined threshold, the current hardly flows, and when the applied voltage is equal to or higher than the predetermined threshold, the current increases sharply. The threshold may be referred to as a threshold voltage, and the selector pattern 122 may be implemented as an on state or an off state based on the threshold voltage.

[0048] Unlike a conventional doped nitride or oxide-based selector, the selector pattern 122 may include amorphous carbon (C) as a main component and a dopant implanted by an ion implantation process. In addition, in addition to carbon (C), the selector pattern 122 may further include at least one of nitrogen (N), oxygen (O), and hydrogen (H). The dopant may include at least one of arsenic (As), phosphorus (P), and antimony (Sb).

[0049] The selector pattern 122 may include carbon (C) of an amorphous phase that can easily participate in a chemical reaction as a main component, and may include a dopant implanted by an ion implantation process, thereby forming defects and / or vacancies in the selector pattern 122. Therefore, the metallic state of the dopant can be well maintained, which makes it easier and more effective for them to form trap sites for conductive carriers. This can further improve the electrical characteristics of the selector pattern 122. In addition, due to the basic characteristics of carbon as a main component, the physical characteristics of the selector pattern 122 can be improved. When the selector pattern 122 includes at least one of nitrogen (N), oxygen (O), and hydrogen (H) in addition to carbon (C), carbon (C) and the additional element can form a variety of phases, which can further increase the degree of defects and / or vacancies formed in the selector pattern 122. Therefore, by comprehensively considering the physical and electrical characteristics required for the target selector pattern 122, the degree of defects and / or vacancies formed in the selector pattern 122 can be controlled.

[0050] According to an embodiment of the present disclosure, the selector pattern 122 may include carbon (C) as a substrate, and the selector pattern 122 may also include at least one of nitrogen (N), oxygen (O) and hydrogen (H) in addition to carbon (C), and exhibit excellent electrical and physical properties by implanting dopant ions into the substrate.

[0051] The memory pattern 124 can store different data by switching between different resistance states according to a voltage or current applied via the upper and lower parts. The memory pattern 124 may include materials used in resistive random access memory (RRAM), phase change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), etc., for example, materials with variable resistance characteristics used in RRAM, PRAM, FRAM, MRAM, etc. The memory pattern 124 may include transition metal oxides used in RRAM, PRAM, FRAM, MRAM, etc., metal oxides such as perovskite-based materials, phase change materials such as chalcogenide-based materials, ferroelectric materials, ferromagnetic materials, etc.

[0052] For example, the memory pattern 124 may include a magnetic tunnel junction (MTJ) structure including a free layer having a changeable magnetization direction, a fixed layer having a fixed magnetization direction, and a tunnel barrier layer between the free layer and the fixed layer.

[0053] The free layer may be a layer configured to store different data by having a variable magnetization direction, and it may also be referred to as a storage layer. The free layer may have one of different magnetization directions, or one of different electron spin directions, thereby switching the polarity of the free layer in the MTJ structure and changing the resistance value. According to some embodiments of the present disclosure, when a voltage or current signal (e.g., a drive current equal to or higher than a predetermined threshold) is applied to the MTJ structure, the polarity of the free layer may change or reverse. As the polarity of the free layer changes, the free layer and the fixed layer may have different magnetization directions or different electron spin directions. Therefore, the memory pattern 124 may store different data or represent different data bits. The magnetization direction of the free layer may change between a top-down direction and a bottom-up direction. This change in the magnetization direction of the free layer may be caused by a spin transfer torque generated based on an applied current or voltage.

[0054] The fixed layer may have a fixed magnetization direction that does not change when the magnetization direction of the free layer changes. The fixed layer may also be referred to as a reference layer. According to some embodiments of the present disclosure, the fixed layer may be fixed to a magnetization direction from top to bottom. According to some embodiments of the present disclosure, the fixed layer may be fixed to a magnetization direction from bottom to top.

[0055] The free layer and the fixed layer may have a single layer structure or a multilayer structure including a ferromagnetic material. For example, the free layer and the fixed layer may include an alloy having Fe, Ni or Co as a main component, such as a Fe-Pt alloy, a Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, a Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, a Co-Ni-Pt alloy, a Co-Fe-B alloy, etc., or may include a stacked structure formed of a metal, such as a stacked structure such as Co / Pt, Co / Pd, etc.

[0056] The tunnel barrier layer can realize the tunneling of electrons in both data reading operation and data writing operation. The tunnel barrier layer may include a dielectric oxide, such as MgO, CaO, SrO, TiO, VO, NbO, Al2O3, TiO2, Ta2O5, RuO2, B2O3, etc.

[0057] The memory pattern 124 may have a single-layer structure or may have a multi-layer structure exhibiting variable resistance characteristics by combining two or more layers. However, the embodiments of the present disclosure are not limited thereto, and the memory cell 120 may include other memory layers that can store different data in various ways instead of the memory pattern 124.

[0058] According to an embodiment of the present disclosure, the memory cell 120 may include a lower electrode 121, a selector pattern 122, an intermediate electrode 123, a memory pattern 124, and an upper electrode 125 stacked in sequence. However, the memory cell 120 may be modified in various ways as long as it has data storage characteristics. For example, at least one of the intermediate electrode 123 and the upper electrode 125 may be omitted. In addition, the positions of the selector pattern 122 and the memory pattern 124 may be exchanged with each other. In addition, in addition to the layers 121, 122, 123, 124, and 125, the memory cell 120 may also include one or more layers (not shown) to improve the characteristics of the memory cell 120 or improve the process. For example, it may also include at least one of the lower electrode contact and the upper electrode contact. In addition, for example, the hard mask pattern may be retained.

[0059] The memory cells 120 formed as described above may be arranged spaced apart from each other at regular intervals, and trenches may be formed therebetween. The height-to-width (H / W) aspect ratio of the trenches between the memory cells 120 may be, for example, in the range of about 1:1 to 40:1, or about 10:1 to 40:1, or about 10:1 to 20:1, or about 5:1 to 10:1, or about 10:1 to 15:1, or about 1:1 to 25:1, or about 1:1 to 30:1, or about 1:1 to 35:1, or about 1:1 to 45:1, or about 1:1 to 40:1.

[0060] According to some embodiments of the present disclosure, the sidewalls of the trenches may be substantially perpendicular to the upper surface of the substrate 100. In addition, according to one embodiment of the present disclosure, adjacent trenches may be spaced apart from each other by substantially the same distance. However, according to another embodiment of the present disclosure, the spaces between adjacent trenches may be different.

[0061] Although a cross-point structure having a single memory cell 120 is described in this embodiment of the present disclosure, the cross-point structure may include two or more memory cells 120 stacked in a vertical direction.

[0062] Then, refer to FIG. 3A to FIG. 3F A method for manufacturing a semiconductor device according to an embodiment of the present disclosure is described. In the following description, the lower electrode layer 221A, the selector layer 222A, the intermediate electrode layer 223A, the memory layer 224A, and the upper electrode layer 225A may respectively represent material layers that will be formed into the lower electrode 221, the selector pattern 222, the intermediate electrode 223, the memory pattern 224, and the upper electrode 225 through a patterning process.

[0063] Reference Figure 3A , the first conductive line 210 may be formed on a substrate 200 formed with a predetermined lower structure (not shown). The first conductive line 210 may be formed by forming a conductive layer for forming the first conductive line 210 on the substrate 200, and then etching the conductive layer using a linear mask pattern extending in a first direction (D1). The first conductive line 210 may have a single-layer structure or a multi-layer structure including a conductive material. Non-limiting examples of the conductive material may include metals, metal nitrides, conductive carbon materials, and combinations thereof.

[0064] The lower electrode layer 221A may be formed on the first conductive line 210. The lower electrode layer 221A may have a single-layer structure or a multi-layer structure including various conductive materials such as metal, nitride, silicide-based materials, and combinations thereof.

[0065] Reference Figure 3B , a carbon layer CL may be formed on the lower electrode layer 221A.

[0066] The carbon layer CL can be used as a matrix of a substrate forming a selector. The carbon layer CL can be formed of an amorphous phase that can easily participate in a chemical reaction, and when a dopant such as arsenic (As) is ion-implanted, a new structural bond can be easily formed, and the metallic state of the dopant can be well maintained. Since the ion-implanted dopant is configured to more easily and effectively form a trap site for conductive carriers, the threshold switching operation characteristics of the selector can be effectively realized. In addition, since the carbon layer CL has a low density and high thermal conductivity, the selector based on the carbon layer CL can have excellent electrical and physical properties.

[0067] The carbon layer CL may be formed by depositing carbon (C) through a physical deposition method such as a sputtering method.

[0068] According to an embodiment of the present disclosure, the carbon layer CL may include carbon (C) atoms as a main component, and the carbon layer CL may further include at least one of nitrogen (N) atoms, oxygen (O) atoms, and hydrogen (H) atoms. In an embodiment, by performing a carbon (C) deposition process in a gas atmosphere of at least one of nitrogen, oxygen, and hydrogen, at least one of nitrogen (N) atoms, oxygen (O) atoms, and hydrogen (H) atoms may be doped onto the carbon layer CL.

[0069] Reference Figure 3C , dopants may be implanted into the carbon layer CL to form the selector layer 222A.

[0070] The dopant may form a trap site for conductive carriers, thereby allowing the finally formed selector pattern 222 to perform a threshold switching operation.

[0071] The dopant may include, for example, at least one of arsenic (As), phosphorus (P), and antimony (Sb).

[0072] According to one embodiment of the present disclosure, the dopant may be implanted through an ion implantation process.

[0073] According to one embodiment of the present disclosure, the thickness of the selector layer 222A may be the same as the thickness of the carbon layer CL. According to another embodiment of the present disclosure, the thickness of the selector layer 222A may be less than the thickness of the carbon layer CL. This is because a portion of the upper portion of the carbon layer CL may be lost due to damage that may occur during the ion implantation process.

[0074] Reference Figure 3D , an intermediate electrode layer 223A may be formed on the selector layer 222A. The intermediate electrode layer 223A may have a single-layer structure or a multi-layer structure, including a variety of conductive materials, such as metals, nitrides, silicide-based materials, and combinations thereof.

[0075] The memory layer 224A may be formed on the intermediate electrode layer 223A. The memory layer 224A may be formed of a material used in RRAM, PRAM, FRAM, MRAM, etc., for example, a material having a variable resistance characteristic used in RRAM, PRAM, FRAM, MRAM, etc. According to one embodiment of the present disclosure, the memory layer 224A may include a transition metal oxide used in RRAM, PRAM, FRAM, MRAM, etc., a metal oxide such as a perovskite-based material, a phase change material such as a chalcogenide-based material, a ferroelectric material, a ferromagnetic material, etc. According to another embodiment of the present disclosure, the memory layer 224A may have a magnetic tunnel junction (MTJ) structure including a free layer having a variable magnetization direction, a fixed layer having a fixed magnetization direction, and a tunnel barrier layer between the free layer and the fixed layer.

[0076] The upper electrode layer 225A may be formed on the memory layer 224 A. The upper electrode layer 225A may have a single-layer structure or a multi-layer structure including various conductive materials such as metal, nitride, silicide-based materials, and combinations thereof.

[0077] Reference Figure 3E , a memory cell 220 is shown, in which a lower electrode 221, a selector pattern 222, an intermediate electrode 223, a memory pattern 224 and an upper electrode 225 are sequentially stacked and formed by using a mask pattern as an etching mask and sequentially etching an upper electrode layer 225A, a memory layer 224A, an intermediate electrode layer 223A, a selector layer 222A and a lower electrode layer 221A.

[0078] Reference Figure 3F , the second conductive line 230 may be formed on the upper electrode 225. The second conductive line 230 may be formed by depositing a conductive layer for forming the second conductive line 230 and etching the conductive layer using a line-shaped mask pattern extending in the second direction (D2).

[0079] Through the above process, it can be formed Figure 3F The semiconductor device shown.

[0080] The semiconductor device according to the embodiment of the present disclosure may include a first conductive line 210, a memory cell 220, and a second conductive line 230 sequentially formed over a substrate 200. The memory cell 220 may include a lower electrode 221, a selector pattern 222, an intermediate electrode 223, a memory pattern 224, and an upper electrode 225 sequentially formed.

[0081] Unlike a conventional selector doped with nitride or oxide, the selector pattern 222 may include amorphous carbon (C) as a main component and an ion-implanted dopant. In addition, in addition to carbon (C), the selector pattern 222 may optionally include at least one of nitrogen (N), oxygen (O), and hydrogen (H). The dopant may include at least one of arsenic (As), phosphorus (P), and antimony (Sb).

[0082] The selector pattern 222 may include carbon (C) of an amorphous phase that can easily participate in a chemical reaction as a main component, and when a dopant such as arsenic (As) is ion-implanted, defects and / or vacancies may be formed in the selector pattern 222. Therefore, the metallic state of the dopant can be well maintained, and a trap site for conductive carriers can be formed more easily and effectively. As a result, the electrical characteristics of the selector pattern 222 can be further improved. In addition, due to the basic characteristics of carbon as a main component, the physical characteristics of the selector pattern 222 can be improved. When the selector pattern 222 includes at least one of nitrogen (N), oxygen (O), and hydrogen (H) in addition to carbon (C), carbon (C) and the additional element can form a variety of phases, thereby further increasing the degree of defects and / or vacancies formed in the selector pattern 222. Therefore, the degree of defects and / or vacancies formed in the selector pattern 222 can be controlled by comprehensively considering the physical characteristics and electrical characteristics required by the target selector pattern 222.

[0083] When forming the upper memory pattern 224, the flatness of the selector pattern 222 is very important for stable crystallization of the memory pattern 224. Since the roughness characteristics of the selector pattern 222 according to the embodiment of the present disclosure are improved as the internal carbon and additional elements form various phases, the memory pattern 224 can be more stably crystallized.

[0084] Figure 3F The substrate 200, the first conductive line 210, the memory cell 220, the second conductive line 230, the lower electrode 221, the selector pattern 222, the intermediate electrode 223, the memory pattern 224, and the upper electrode 225 shown in FIG. 2 may correspond to Figure 2B , a substrate 100, a first conductive line 110, a memory cell 120, a second conductive line 130, a lower electrode 121, a selector pattern 122, an intermediate electrode 123, a memory pattern 124, and an upper electrode 125 are shown in FIG.

[0085] According to an embodiment of the present disclosure, the selector pattern 222 may be formed at a lower portion of the memory pattern 224. However, the relative positions of the selector pattern 222 and the memory pattern 224 may be exchanged with each other. 4A to 4F Describe this.

[0086] 4A to 4F A method for manufacturing a semiconductor device according to another embodiment of the present disclosure is shown. The description will focus on Figure 1A and Figure 1B , Figure 2A and Figure 2B as well as FIG. 3A to FIG. 3F In the following description, the lower electrode layer 321A, the selector layer 322A, the intermediate electrode layer 323A, the memory layer 324A, and the upper electrode layer 325A may represent material layers that will be formed into the lower electrode 321, the selector pattern 322, the intermediate electrode 323, the memory pattern 324, and the upper electrode 325 through a patterning process.

[0087] Reference Figure 4A , the first conductive line 310 may be formed on a substrate 300 in which a predetermined lower structure (not shown) is formed. The first conductive line 310 may be formed by forming a conductive layer for forming the first conductive line 210 on the substrate 300 and then etching the conductive layer using a linear mask pattern extending in a first direction (D1).

[0088] The lower electrode layer 321A may be formed on the first conductive line 310. The lower electrode layer 321A may have a single-layer structure or a multi-layer structure including various conductive materials such as metal, nitride, silicide-based materials, and combinations thereof.

[0089] The memory layer 324A may be formed on the lower electrode layer 321 A. The memory layer 324A may be formed of a material used in RRAM, PRAM, FRAM, MRAM, etc., for example, a material having a variable resistance characteristic used in RRAM, PRAM, FRAM, MRAM, etc.

[0090] The intermediate electrode layer 323A may be formed on the memory layer 324 A. The intermediate electrode layer 323A may have a single-layer structure or a multi-layer structure including various conductive materials such as metal, nitride, silicide-based materials, and combinations thereof.

[0091] Reference Figure 4B , a carbon layer CL may be formed on the intermediate electrode layer 323A. The carbon layer CL may be formed by depositing carbon (C) through a physical deposition method such as physical vapor deposition or sputtering.

[0092] According to one embodiment of the present disclosure, the carbon layer CL may include carbon (C) atoms as a main component, and in addition to carbon (C), it may further include at least one of nitrogen (N) atoms, oxygen (O) atoms, and hydrogen (H) atoms. In this case, at least one of nitrogen (N) atoms, oxygen (O) atoms, and hydrogen (H) atoms may be doped onto the carbon layer CL by performing a carbon (C) deposition process in a gas atmosphere of at least one of nitrogen, oxygen, and hydrogen.

[0093] Reference Figure 4C , dopants may be implanted into the carbon layer CL to form the selector layer 322A.

[0094] The dopant may form a trap site for conductive carriers, thereby allowing the finally formed selector pattern 322 to perform a threshold switching operation.

[0095] For example, the dopant may include at least one of arsenic (As), phosphorus (P), and antimony (Sb).

[0096] According to one embodiment of the present disclosure, the dopant may be implanted through an ion implantation process.

[0097] According to one embodiment of the present disclosure, the thickness of the selector layer 322A may be the same as the thickness of the carbon layer CL. According to another embodiment of the present disclosure, the thickness of the selector layer 322A may be less than the thickness of the carbon layer CL. This is because a portion of the upper portion of the carbon layer CL may be lost due to damage that may occur during the ion implantation process.

[0098] Reference Figure 4D , an upper electrode layer 325A may be formed on the selector layer 322A. The upper electrode layer 325A may have a single-layer structure or a multi-layer structure including a variety of conductive materials, such as metals, nitrides, silicide-based materials, and combinations thereof.

[0099] Reference Figure 4E , the upper electrode layer 325A, the selector layer 322A, the intermediate electrode layer 323A, the memory layer 324A, and the lower electrode layer 321A may be sequentially etched by using the mask pattern as an etching barrier. As a result, a memory cell 320 in which the lower electrode 321, the memory pattern 324, the intermediate electrode 323, the selector pattern 322, and the upper electrode 325 are sequentially stacked may be formed.

[0100] Reference Figure 4F , the second conductive line 330 may be formed over the upper electrode 325. The second conductive line 330 may be formed by depositing a conductive layer for forming the second conductive line 330 and etching the conductive layer using a line-shaped mask pattern extending in the second direction (D2).

[0101] Through the above process, it can be formed Figure 4FThe semiconductor device shown in .

[0102] The semiconductor device according to the embodiment of the present disclosure may include a first conductive line 310, a memory cell 320, and a second conductive line 330 sequentially formed over a substrate 300. The memory cell 320 may include a lower electrode 321, a memory pattern 324, an intermediate electrode 323, a selector pattern 322, and an upper electrode 325 sequentially formed.

[0103] Unlike a conventional selector doped with nitride or oxide, the selector pattern 322 may include amorphous carbon (C) as a main component and an ion-implanted dopant. In addition, in addition to carbon (C), the selector pattern 322 may optionally include at least one of nitrogen (N), oxygen (O), and hydrogen (H). The dopant may include at least one of arsenic (As), phosphorus (P), and antimony (Sb).

[0104] The selector pattern 322 according to an embodiment of the present disclosure may include carbon (C), and may also include at least one of nitrogen (N), oxygen (O), and hydrogen (H), and may include a dopant that is ion-implanted, thereby forming defects and / or vacancies due to various phases formed in the selector pattern 322. As a result, the metallic state of the dopant may be well maintained, and a trap site for conductive carriers may be more easily and effectively formed. Therefore, the selector pattern 322 according to an embodiment of the present disclosure may exhibit excellent electrical and physical properties.

[0105] Figure 4F The substrate 300, the first conductive line 310, the memory cell 320, the second conductive line 330, the lower electrode 321, the selector pattern 322, the intermediate electrode 323, the memory pattern 324, and the upper electrode 325 shown in FIG. 3 may correspond to Figure 3F The substrate 200, the first conductive line 210, the memory cell 220, the second conductive line 230, the lower electrode 221, the selector pattern 222, the intermediate electrode 223, the memory pattern 224 and the upper electrode 225 shown in FIG. Figure 2B , a substrate 100, a first conductive line 110, a memory cell 120, a second conductive line 130, a lower electrode 121, a selector pattern 122, an intermediate electrode 123, a memory pattern 124, and an upper electrode 125 are shown in FIG.

[0106] According to an embodiment of the present disclosure, a selector having excellent electrical and physical characteristics by using carbon as a matrix of the selector and implanting dopant ions into the carbon matrix, a semiconductor device including the selector, and a method for manufacturing the semiconductor device are provided.

[0107] Although the embodiments of the present disclosure have been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present disclosure defined in the appended claims. Furthermore, these embodiments may be combined to form additional embodiments.

Claims

1. A selector, comprising: a substrate comprising carbon; and Dopants are implanted into the substrate by an ion implantation process.

2. The selector according to claim 1, further comprising: At least one of nitrogen, oxygen and hydrogen.

3. The selector according to claim 1, wherein: The dopant includes at least one of arsenic As, phosphorus P, and antimony Sb.

4. The selector according to claim 1, wherein: There is a defect or a gap in the selector.

5. The selector according to claim 1, wherein: The carbon is in an amorphous phase.

6. The selector according to claim 1, wherein: The carbon forms the basic framework structure of the selector.

7. A method for manufacturing a selector, the method comprising: Formation of a carbon layer; as well as Dopants are implanted into the carbon layer.

8. The method according to claim 7, wherein: Forming the carbon layer includes a physical deposition process.

9. The method according to claim 7, wherein: Forming the carbon layer is performed in a gas atmosphere of at least one of nitrogen, oxygen, and hydrogen.

10. The method according to claim 7, wherein: Forming the carbon layer is performed to form an amorphous carbon layer.

11. The method according to claim 7, wherein: The dopant includes at least one of arsenic As, phosphorus P, and antimony Sb.

12. The method according to claim 7, wherein: Defects or vacancies are formed in the selector.

13. A semiconductor device comprising: a selector pattern including carbon as a base material and a dopant implanted by an ion implantation process; as well as A memory pattern is provided above or below the selector pattern.

14. The semiconductor device according to claim 13, wherein: The selector pattern is formed to control the flow of current and prevent current leakage between memory cells, and The memory pattern is formed to store different data by switching between different resistance states according to applied voltage or current.

15. The semiconductor device according to claim 13, further comprising at least one of the first electrode, the second electrode and the third electrode, The first electrode is disposed between the selector pattern and the substrate or between the substrate and the memory pattern; the second electrode is disposed between the selector pattern and the memory pattern; and The third electrode is disposed on an upper portion of the memory pattern or an upper portion of the selector pattern.

16. The semiconductor device according to claim 13, wherein: The selector pattern further includes at least one of nitrogen, oxygen, and hydrogen.

17. The semiconductor device according to claim 13, wherein: The dopant includes at least one of arsenic As, phosphorus P, and antimony Sb.

18. The semiconductor device according to claim 13, wherein: There are defects or gaps in the selector pattern.

19. The semiconductor device according to claim 13, wherein: The carbon is in an amorphous phase.

20. The semiconductor device according to claim 13, wherein The carbon forms the basic framework structure of the selector pattern.

21. A method for manufacturing a semiconductor device, the method comprising: forming a carbon layer on the substrate; forming a selector layer by implanting dopants through an ion implantation process; forming a memory layer on an upper portion or a lower portion of the selector layer; as well as A memory cell including a memory pattern and a selector pattern is formed by etching the memory layer and the selector layer through an etching process using a mask pattern.

22. The method according to claim 21, further comprising at least one of the following steps: forming a first electrode layer between the substrate and the selector layer or between the substrate and the memory layer; forming a second electrode layer between the selector layer and the memory layer; as well as A third electrode layer is formed on an upper portion of the memory layer or an upper portion of the selector layer.

23. The method according to claim 21, wherein: Forming the carbon layer includes a physical deposition process.

24. The method according to claim 21, wherein: Forming the carbon layer is performed in a gas atmosphere of at least one of nitrogen, oxygen, and hydrogen.

25. The method according to claim 21, wherein: Forming the carbon layer is performed to form an amorphous carbon layer.

26. The method of claim 21, wherein: The ion implantation process is performed using a dopant including at least one of arsenic As, phosphorus P, and antimony Sb.

27. The method of claim 21, wherein: Defects or vacancies are formed in the selector layer by implanting the dopant.

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