Neural pulse on-chip detection circuit and equipment for electroencephalogram signals

Abstract

The invention discloses a neural pulse on-chip detection circuit and device for electroencephalogram signals, and the circuit comprises an input module which is used for receiving multiple paths of electroencephalogram signals inputted from a serial peripheral interface through time division multiplexing; the pulse recognition module is used for performing pulse detection on the input electroencephalogram signals; the waveform output module is used for recording and outputting waveform data near the pulse point; the input module comprises a serial peripheral interface used for inputting multiple paths of electroencephalogram signals, the input module, the pulse recognition module and the waveform output module are connected in sequence, and the waveform output module is provided with an output interface used for outputting waveform data. The invention aims to solve the problem of time division multiplexing of a calculation circuit caused by resource limitation and frequency difference and the problems of resource management and data synchronization in high-throughput data processing by aiming at the limitation of an existing electroencephalogram signal detection method in the aspects of resource utilization and detection precision. And a pulse detection algorithm realization problem in compromise between precision and hardware overhead is solved.

Description

Technical Field

[0001] The present invention relates to a neural pulse on-chip detection technology and circuit implementation in the field of brain-computer interface, and in particular to a neural pulse on-chip detection circuit and device for electroencephalogram signals. Background Art

[0002] Brain-Computer Interface (BCI) connects the brain to external devices through electrical signals, enabling the brain to directly control computers, robots, prostheses and other devices. This technology provides a new way for rehabilitation, scientific research and technological development. The BCI system includes signal acquisition, processing, pulse detection, classification algorithms and control output. It interprets brain activity and converts it into device instructions to achieve direct control of the brain over the device. BCI has a wide range of applications in many fields. BCI research began in the 1960s. Modern BCI systems can process large amounts of EEG data in real time and provide reliable signal interpretation and control functions. Despite the progress, BCI technology still faces challenges such as improving signal processing accuracy and speed, reducing device size and weight, and increasing system convenience.

[0003] Pulse detection is a crucial part of neural signal processing. Neurons generate pulse signals through discharge. These pulses carry a lot of information and are the main way for the brain to interact with the outside world. Pulse detection identifies these pulses from complex EEG signals and extracts useful information. It involves filtering, amplification, feature extraction and classification, and is ultimately used for analysis or device control. Pulse detection is widely used. In brain-computer interface systems, pulse detection interprets the brain's movement intentions and converts them into instructions to control devices such as prostheses. In neuroscience research, pulse detection analyzes neuronal activity patterns to help understand the working mechanism of the brain. In medical diagnosis, pulse detection monitors and analyzes neural signals to assist in the diagnosis and treatment of neurological diseases. Common pulse detection methods include threshold method, template matching method and machine learning method. The threshold method sets a fixed threshold, and pulses are detected when the signal exceeds the threshold. The method is simple but susceptible to noise. The template matching method detects pulses by matching the signal with a predefined template. It has high accuracy but complex calculations. The machine learning method automatically detects pulses by training models. It processes complex signals but requires a lot of training data and computing resources.

[0004] With the development of brain-computer interface technology, the demand for efficient, real-time and accurate processing of a large number of neural signals is increasing. However, existing detection methods have certain limitations in resource utilization and detection accuracy: (1) The problem of time-division multiplexing of computing circuits caused by resource limitation and frequency difference. In many brain-computer interface systems, the sampling frequency of EEG signals is low, generally only a few thousand hertz, while the operating frequency of customized hardware accelerators can reach several megahertz. This significant frequency difference leads to idleness and waste of computing resources. In order to efficiently utilize these high-frequency computing units, the system needs to be optimized through time-division multiplexing technology. Time-division multiplexing is a method of using the same hardware resources to process different tasks at different times. Through this technology, complex signal processing functions can be implemented with limited hardware resources. However, time-division multiplexing technology also brings new challenges. First, since the same computing unit needs to process different tasks at different times, task scheduling and switching become crucial. If the scheduling is improper, it may lead to processing delays and performance degradation. Second, time-division multiplexing requires that the computing unit has sufficient flexibility to quickly switch and process different types of tasks. (2) Resource management and data synchronization issues in multi-channel high-throughput processing. The brain-computer interface system needs to process a large number of neural signals, so it must have high-throughput processing capabilities. This requires the system to be able to process signals from multiple channels at the same time, which requires the support of multiple parallel inputs and multiple sets of storage logic. Through multiple parallel inputs, the system can simultaneously collect and process signals from different channels to avoid data processing bottlenecks. Multiple sets of storage logic are used to efficiently store and manage a large amount of neural signal data to ensure fast data access and real-time processing. Achieving multiple parallel inputs and multiple sets of storage logic requires overcoming a series of technical challenges. For example, efficient management and scheduling of signals from multiple channels is key, and the real-time and consistency of data must be guaranteed. In addition, the processing capability of the system must be improved without significantly increasing hardware overhead. Multi-channel parallel processing also needs to consider interference and synchronization issues between signals to ensure that the signal of each channel can be processed independently without being affected by other channels. (3) How to achieve high-precision pulse detection under limited hardware resources. Traditional pulse detection methods have two extremes in terms of accuracy and hardware resource usage: high-precision methods require a lot of hardware resources, while low-precision methods are simple but difficult to provide accurate detection results. High-precision pulse detection methods, such as those based on variance calculation, can provide high-precision detection results. However, these methods have high computational complexity and high hardware overhead, and are difficult to implement, especially in resource-constrained systems. In addition, complex algorithms have low missed detection rates and false alarm rates in real-time processing, but are difficult to implement in hardware. On the other hand, low-precision methods, such as simple threshold methods, have low computational complexity and simple hardware implementation, but low detection accuracy and are easily affected by noise. Such detection methods have high missed detection rates and difficult-to-control false alarm rates, and are not suitable for sophisticated signal processing requirements.Therefore, it is necessary to find a pulse detection method that strikes a balance between hardware overhead and detection accuracy. The ideal method should minimize the use of hardware resources while ensuring detection accuracy. Summary of the invention

[0005] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, an on-chip neural pulse detection circuit and device for EEG signals are provided. The present invention aims to address the limitations of existing EEG signal detection methods in terms of resource utilization and detection accuracy, and solve the problems of time-division multiplexing of computing circuits caused by resource limitations and frequency differences, resource management and data synchronization problems in high-throughput data processing, and the problem of implementing a pulse detection algorithm that compromises accuracy and hardware overhead.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A neural pulse on-chip detection circuit for electroencephalogram signals, comprising: An input module, used for receiving multiple EEG signals input from a serial peripheral interface through time division multiplexing; A pulse identification module is used to detect pulses of input EEG signals; A waveform output module is used to record and output waveform data near the pulse point; The input module comprises a serial peripheral interface for inputting multiple channels of EEG signals. The input module, pulse recognition module and waveform output module are connected in sequence. The waveform output module has an output interface for outputting waveform data.

[0007] Optionally, the input module includes a 16-channel SPI engine, 16 single-channel data FIFO buffers, a polling module, a common data FIFO buffer and an extraction module. The EEG signals from each serial peripheral interface are converted from serial data to parallel data by the corresponding SPI engine and then sent to the single-channel data FIFO buffer for buffering. The polling module takes out the buffered EEG signals from each of the 16 single-channel data FIFO buffers in turn and sends them to the common data FIFO buffer. The extraction module sends the 16-channel EEG signals buffered in the common data FIFO buffer to the pulse recognition module.

[0008] Optionally, the input of the SPI engine is 1 bit and the output is 16 bits. The SPI engine includes a shift register. Each 1-bit input signal will be stored in the shift register. When the data stored in the shift register reaches 16 bits, the 16-bit data will be output at one time. Each SPI engine processes the data of 16 channels by time division multiplexing TDM, so that the 16-channel SPI engines can process a total of 256 channels of data to achieve high-throughput data input. Each SPI engine is followed by a first circular shift register for calculating the channel index. The width of the first circular shift register is 8 bits, and the circulation range of the first circular shift register of each SPI engine is different. Whenever the SPI engine outputs a valid signal, the first circular shift register is self-incremented once, and the 16-bit original signal data is combined with the 8-bit data in the first circular shift register to form a 24-bit data output containing channel information.

[0009] Optionally, it also includes an accelerator interface and a microprocessor, the microprocessor is connected to the input module through the accelerator interface for parameter configuration of the input module, the parameter configuration includes route selection configuration and channel number configuration, the route selection configuration is used to select the specified number of routes, so that the SPI engine and the single-channel data FIFO buffer of the corresponding route work, and the polling module also takes data from the single-channel data FIFO buffer of the corresponding route; the channel number configuration refers to configuring the channel selected by the SPI engine and the circular range of the channel index of the first circular shift register, so that the SPI engine sequentially inputs the input data of the selected channel.

[0010] Optionally, the pulse identification module includes an automatic threshold detection module, which includes: a second circular shift register for determining the state of the current channel; a maximum value memory for storing the maximum value of the current window respectively; a minimum value memory for storing the minimum value of the current window respectively; a partial sum memory for storing the partial sum of the current window respectively; an average value memory for storing the average value of the previous window respectively; a range memory for storing the range of the previous window respectively; a standard deviation parameter memory for storing parameters for calculating the standard deviation; a calculation processing unit for performing data calculation, data comparison and determining whether the current signal is a pulse signal; the second circular shift register has three states, when the register value is 0, the current input value is stored in the maximum value memory, the minimum value memory and the partial sum memory, and the register value is increased by 1; when the register value is between 0 and the current window width width, the maximum value, the minimum value memory and the partial sum memory are taken out. The minimum value and partial sum are rewritten after updating, and the register value is increased by 1; when the register value is equal to the current window width width, the range and average value are calculated, written into the range memory and the average value memory respectively, and the register value is set to 0; the second circular shift register, the maximum value memory, the minimum value memory, the partial sum memory, the average value memory and the range memory are directly connected to the input channel index, and the reading and writing of data are controlled by the data valid signal; the input of the standard deviation parameter memory includes the current window width width, and the reading and writing of data are controlled by the data valid signal. When data enters, the calculation processing unit first updates the maximum value, minimum value and partial sum of the current window, and takes out the average value and range of the previous window, and then multiplies the range and the standard deviation parameter related to the window width to obtain an approximate standard deviation, and finally judges whether the current input signal is a pulse signal and outputs it according to the current input signal, the average value, the approximate standard deviation and the input threshold factor P_Value.

[0011] Optionally, the pulse recognition module also includes a fixed threshold detection module, and the output ends of the automatic threshold detection module and the fixed threshold detection module are respectively connected to the input end of a multiplexer MUX controlled by a configured working mode; the fixed threshold detection module includes a comparator, one input of the comparator is a fixed threshold, and the other output is the input EEG signal.

[0012] Optionally, the waveform output module includes: a waveform data memory for storing waveform data; a write address pointer module for specifying a write address; a pulse counter for calculating the number of waveform sampling points; a read address register for storing the value of the write address pointer module so as to find the starting point of the waveform when reading the pulse waveform; a channel FIFO for storing the channel for which the waveform needs to be output; the front end of the waveform data memory is connected to a write port for writing input data, the write address of the write port is determined by the sum of the channel index and the value of the write address pointer module, and the write enable of the write port is controlled by a data valid signal; the write address pointer module is a circular shift register, and the write address has two ranges: 0 to Length-1 and Length to 2*Length-1, where Length is the number of sampling points of a complete waveform. The circular shift register will cycle between the two ranges after completing the waveform storage of a channel. After receiving the pulse signal, the pulse counter sets the counter value to 2*Length / 3. Whenever valid data is input, the counter value is reduced by 1. When the counter value is reduced to 0, the loop range of the write address pointer module is switched, and the value of the current write address pointer module is saved in the read address register, and the current number of channels is output to the channel FIFO. The non-empty signal of the channel FIFO is connected to the read enable signal of the waveform data storage. When the channel FIFO is not empty, the waveform data is read from the waveform data storage according to the number of channels of the channel FIFO and the value of the read address register and output through the AXI interface.

[0013] Optionally, the accelerator interface is also connected to the pulse recognition module and the waveform output module respectively for parameter configuration of the pulse recognition module and the waveform output module, including: configuring the working mode for the multiplexer MUX of the pulse recognition module to select the output of the automatic threshold detection module or the fixed threshold detection module, the current window width width stored in the register of the automatic threshold detection module, the threshold factor P_Value, and the fixed threshold in the fixed threshold detection module; configuring the sampling frequency of the input signal for the waveform output module, and the sampling frequency of the input signal is used to control the number of data points of the waveform recorded when the waveform is output.

[0014] In addition, the present invention also provides an EEG signal detection device, including a detection electrode assembly and a neural pulse on-chip detection circuit, the detection electrode assembly includes detection electrodes of multiple channels, the detection electrodes of multiple channels are respectively connected to the input ends of the neural pulse on-chip detection circuit, and the neural pulse on-chip detection circuit is the aforementioned neural pulse on-chip detection circuit for EEG signals.

[0015] Optionally, the output end of the on-chip neural pulse detection circuit is connected to a computer device.

[0016] Compared with the prior art, the present invention mainly has the following advantages: 1. In order to solve the problem of time-division multiplexing of computing circuits caused by resource limitations and frequency differences, the present invention adopts an improved time-division multiplexing method to ensure efficient processing of EEG signals under limited resources. By optimizing task scheduling and improving the flexibility of computing units, the present invention not only improves the performance of the system, but also reduces processing delays, ensuring efficient processing and real-time response of EEG signals.

[0017] 2. In order to solve the resource management and data synchronization problems in multi-channel high-throughput processing, the present invention adopts an optimized multi-channel parallel input and multiple sets of storage logic design, and realizes efficient data processing and storage management through advanced scheduling algorithms and storage management strategies. This design not only improves the processing capability of the system, but also ensures the real-time and consistency of the data, effectively solving various technical problems in multi-channel high-throughput processing.

[0018] 3. In order to solve the problem of achieving high-precision pulse detection under limited hardware resources, the present invention adopts an optimized pulse detection algorithm, which improves the detection accuracy on the basis of hardware friendliness. The specific implementation includes the following aspects: (1) Simplified calculation: Reduce the demand for hardware resources through approximate calculation methods, such as using approximate values ​​of square roots and logarithms. (2) Optimized algorithm: Adopt a hybrid detection algorithm to combine the low-complexity threshold method with the high-precision statistical method to reduce the overall calculation complexity. (3) Hardware design optimization: Through parallel processing and pipeline technology, improve computing efficiency and reduce missed detection rate and false alarm rate. This compromise detection method is not only more friendly in hardware implementation, but also excels in the missed detection and false alarm probability of signal detection and estimation, and can achieve efficient and accurate pulse detection under limited hardware resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the structure of the neural pulse on-chip detection circuit in an embodiment of the present invention.

[0020] Figure 2 Schematic diagram of the structure of the front end part of the input module in an embodiment of the present invention.

[0021] Figure 3 Schematic diagram of the structure of the back-end part of the input module in the embodiment of the present invention.

[0022] Figure 4 Schematic diagram of the structure of the pulse identification module in an embodiment of the present invention.

[0023] Figure 5 Schematic diagram of the structure of the waveform output module in an embodiment of the present invention.

[0024] Figure 6Schematic diagram of the working process of the on-chip neural pulse detection circuit in an embodiment of the present invention.

[0025] Legend: 1. Input module; 11. SPI engine; 12. Single-channel data FIFO buffer; 13. Polling module; 14. Public data FIFO buffer; 15. Retrieval module; 16. First circular shift register; 2. Pulse recognition module; 21. Automatic threshold detection module; 211. Second circular shift register; 212. Maximum value memory; 213. Minimum value memory; 214. Memory; 215. Average value memory; 216. Range memory; 217. Standard deviation parameter memory; 22. Fixed threshold detection module; 221. Comparator; 23. Multiplexer MUX; 3. Waveform output module; 31. Waveform data memory; 32. Write address pointer; 33. Pulse counter; 34. Read address register; 35. Channel FIFO; 4. Accelerator interface; 5. Microprocessor. DETAILED DESCRIPTION

[0026] like Figure 1 As shown, a neural pulse on-chip detection circuit for electroencephalogram signals includes: Input module 1, used for receiving multiple EEG signals input from a serial peripheral interface through time division multiplexing; Pulse identification module 2, used for pulse detection of input EEG signals; The waveform output module 3 is used to record and output the waveform data near the pulse point; The input module 1 includes a serial peripheral interface for inputting multiple EEG signals. The input module 1, the pulse recognition module 2 and the waveform output module 3 are connected in sequence. The waveform output module 3 has an output interface for outputting waveform data. Through the collaborative work of the above modules, the EEG signal pulse detection chip can efficiently and accurately detect and output the pulse information of the EEG signal, and is suitable for various EEG signal processing applications.

[0027] like Figure 1 , Figure 2 and Figure 3As shown, the input module 1 includes 16 SPI (serial peripheral interface) engines 11, 16 single-channel data FIFO (first-in first-out) buffers 12, a polling module 13, a common data FIFO buffer 14 and a fetching module 15. The EEG signals from each serial peripheral interface are converted from serial data to parallel data by the corresponding SPI engine 11 and then sent to the single-channel data FIFO buffer 12 for buffering. The polling module 13 takes the buffered EEG signals from each of the 16 single-channel data FIFO buffers 12 in turn and sends them to the common data FIFO buffer 14. The fetching module 15 sends the 16 EEG signals buffered in the common data FIFO buffer 14 to the pulse recognition module 2.

[0028] The SPI engine 11 is responsible for decoding the received SPI signal and restoring it to the original signal. Figure 2 As shown, the input of the SPI engine 11 is 1 bit and the output is 16 bits. The SPI engine 11 includes a shift register. Each 1-bit input signal will be stored in the shift register. When the data stored in the shift register reaches 16 bits, the 16-bit data will be output at one time. Each SPI engine 11 processes the data of 16 channels by time division multiplexing TDM, so that the 16-channel SPI engines 11 can process a total of 256 channels of data to achieve high-throughput data input. Each SPI engine 11 is followed by a first circular shift register 16 for calculating the channel index. The width of the first circular shift register 16 is 8 bits, and the circulation range of the first circular shift register 16 of each SPI engine 11 is different (such as Figure 2 As shown, for example, for the circular shift register of the 0th SPI, its cycle range is 0-15). Whenever the SPI engine 11 outputs a valid signal, the first circular shift register 16 is self-incremented once, and the 16-bit original signal data is combined with the 8-bit data in the first circular shift register 16 to form a 24-bit data output containing channel information, so that the encoded signals of each channel are sent to the pulse identification module 2 in sequence for further processing.

[0029] like Figure 2 As shown, the 24-bit data signal containing the channel information then enters the single-channel data FIFO buffer 12. The empty signal (empty signal) in the single-channel data FIFO buffer 12 is connected to the polling module 13. When the polling module 13 detects a non-empty signal in the single-channel data FIFO buffer 12, it will take out the signal in the single-channel data FIFO buffer 12 for the next step of processing. This design ensures the continuity and stability of data processing.

[0030] The fetching module 15 is responsible for extracting the data of 256 channels from the FIFO, outputting 24-bit data including channel information, and outputting valid signals of different modes according to the configured working mode, so as to facilitate further processing by the subsequent pulse identification module.

[0031] Through the collaborative work of the SPI engine 11, the single-channel data FIFO buffer 12, a polling module 13, a common data FIFO buffer 14, and a fetching module 15, the input module 1 can efficiently receive and process multi-channel EEG signal data, providing a reliable data basis for subsequent pulse recognition and waveform output. This design not only realizes high-throughput data input, but also ensures the accuracy and stability of signal processing. The input module 1 solves the needs of high-throughput data processing and multiple sets of storage logic through multi-channel parallel input and effective data management, ensuring that the system has efficient and real-time performance when processing a large number of EEG signals.

[0032] This design improves the efficiency and flexibility of data transmission and ensures the accuracy and reliability of subsequent processing. Figure 1 As shown, the circuit of this embodiment also includes an accelerator interface 4 and a microprocessor 5. The microprocessor 5 is connected to the input module 1 through the accelerator interface 4 to perform parameter configuration on the input module 1. The parameter configuration includes a route selection configuration and a channel number configuration. The route selection configuration is used to select the specified number of routes, so that the SPI engine 11 and the single-channel data FIFO buffer 12 of the corresponding route work, and the polling module 13 also takes data from the single-channel data FIFO buffer 12 of the corresponding route; the channel number configuration refers to configuring the channel selected by the SPI engine 11 and the cyclic range of the channel index of the first cyclic shift register 16, so that the SPI engine 11 sequentially inputs the input data of the selected channel.

[0033] In addition, the accelerator interface 4 of this embodiment is also connected to the pulse identification module 2 and the waveform output module 3 respectively to configure parameters of the pulse identification module 2 and the waveform output module 3 .

[0034] like Figure 4 As shown, the pulse identification module 2 includes an automatic threshold detection module 21, which divides the signal into several time windows by performing window processing on the EEG signal. The mean and standard deviation of the signal in each window are obtained by calculation. This submodule includes a comparison unit for comparing the mean and standard deviation in the window with the original amplitude of the signal to determine whether there is a pulse signal. The automatic threshold detection algorithm can dynamically adjust the threshold to adapt to the change of the signal and improve the accuracy and robustness of pulse detection.

[0035] The automatic threshold detection module 21 is designed to automatically adjust the detection threshold according to the dynamic changes of the input signal to adapt to signals of different amplitudes and frequencies. The design of the automatic threshold detection module 21 enables it to work effectively in an environment where the signal amplitude and frequency vary greatly. Its adaptive adjustment mechanism ensures detection sensitivity and accuracy, and is suitable for various complex signal processing applications. Figure 4 As shown, the automatic threshold detection module 21 includes: The second circular shift register 211 is used to determine the state of the current channel; A maximum value memory 212, used to store the maximum value of the current window respectively; A minimum value memory 213, used to store the minimum value of the current window respectively; Partial sum memory 214, used to store partial sums of the current window respectively; An average value memory 215, used to store the average value of the previous window respectively; A range memory 216, used to store the range of the previous window respectively; A standard deviation parameter memory 217, used to store parameters for calculating standard deviation; A calculation processing unit, used to perform data calculation, data comparison and determine whether the current signal is a pulse signal, such operations include but are not limited to: calculating partial sum, average value, range, difference between input signal and average value, approximate standard deviation, and comparing current input data with maximum value and minimum value, and determining whether the current signal is a pulse signal; The second circular shift register 211 has three states. When the register value is 0, the current input value is stored in the maximum value memory 212, the minimum value memory 213 and the partial sum memory 214, and the register value is increased by 1; when the register value is between 0 and the current window width width, the maximum value, the minimum value and the partial sum are taken out from the maximum value memory 212, the minimum value memory 213 and the partial sum memory 214, updated and rewritten, and the register value is increased by 1; when the register value is equal to the current window width width, the range and the average value are calculated, written into the range memory 216 and the average value memory 215 respectively, and the register value is set to 0; the second circular shift register 211, the maximum value memory 212, the minimum value memory 213 and the partial sum memory 214 are The memory 213, the partial sum memory 214, the average value memory 215 and the range memory 216 are all directly connected to the input channel index, and the reading and writing of data are controlled by the data valid signal; the input of the standard deviation parameter memory 217 includes the window width width, and the reading and writing of data are controlled by the data valid signal. When data enters, the calculation processing unit first updates the maximum value, minimum value and partial sum of the current window, and takes out the average value and range of the previous window, and then multiplies the range with the standard deviation parameter related to the window width to obtain an approximate standard deviation, and finally judges whether the current input signal is a pulse signal and outputs it according to the current input signal, the average value, the approximate standard deviation and the input threshold factor P_Value. In this embodiment, the calculation processing unit includes: Mean calculation unit: responsible for calculating the mean of the input signal within a specific time window. The mean calculation unit is implemented using an accumulator and a divider, and calculates the real-time mean through continuously updated input data.

[0036] Standard deviation calculation unit: responsible for calculating the standard deviation of the input signal within a specific time window. The standard deviation calculation unit uses a comparator and a subtractor to calculate the approximate standard deviation of the input signal in real time.

[0037] Dynamic threshold adjustment unit: Automatically adjust the detection threshold according to the calculation results of the mean and standard deviation. The dynamic threshold adjustment unit is implemented through weighted operations and comparators to ensure that the detection threshold can adapt to changes in the input signal.

[0038] Signal comparator: compares the real-time input signal with the dynamically adjusted threshold to determine whether the signal is a pulse. The signal comparator is implemented based on hardware logic and has the characteristics of high speed and high precision.

[0039] The function expression for calculating the mean value by the mean calculation unit is as follows: , (1) In the above formula, is the mean, is the window width, is the kth input signal.

[0040] The mean of the first width-1 points is set to 0, that is, avg[0] to avg[width-2] are all 0. Starting from avg[width−1], the first valid mean data calculation begins. The mean calculation will be continuously updated as the window slides. Each calculation takes the mean of all points in the current window to obtain accurate mean data.

[0041] In general, the function expression for calculating the standard deviation is as follows: , (2) In the above formula, is the standard deviation, is the mean, is the window width, is the kth input signal. In order to reduce resource consumption, the standard deviation calculation unit in this embodiment uses the following approximate formula to calculate the standard deviation: , (3) In the above formula, is the standard deviation, is the window width, is the ith input signal, For the window The formula can approximately calculate the standard deviation within a window of length width.

[0042] The function expression of the dynamic threshold adjustment unit automatically adjusting the detection threshold according to the calculation results of the mean and standard deviation is: , (4) in, is the current input signal, and are the mean and standard deviation of the previous window, respectively, and the threshold factor is an adjustable parameter. When the above inequality holds, it is considered that the current input signal is the pulse point. In order to calculate the current point The corresponding mean and standard deviation , needs to be calculated based on the data of the previous window. Assuming the window width is width, the window slides once every width points. The specific sliding method is as follows: First window: arrive ; Second window: arrive ; The third window: arrive ; Through this sliding window method, the mean and standard deviation can be calculated in each window, thereby realizing real-time pulse detection of the input signal and improving the sensitivity and accuracy of detection.

[0043] The automatic threshold detection method part shows in detail the calculation process of the mean and approximate standard deviation. When valid data enters the pulse identification module, the value of the channel status register will change. The value of the channel status register varies from 0 to width. When the channel register value is 0, the current input data is directly written into the maximum value memory 212, the minimum value memory 213 and the partial sum memory 214; when the channel register value is 1 to width-1, the values ​​of the maximum value memory 212, the minimum value memory 213 and the partial sum memory 214 are first taken out, the new input data is compared with the maximum value and the minimum value, and the maximum value and the minimum value in the maximum value memory 212 and the minimum value memory 213 are updated. At the same time, the new input data is added to the value of the partial sum memory 214 and stored in the partial sum memory 214; when the channel status register value is width, the data range of the current window is calculated and stored in the range memory 216, and the partial sum is calculated and divided by width to obtain the mean value, and stored in the average value memory 215. The read and write addresses of all memories and the address of the channel status register are the channel index of the current input. When the mean and range have not been calculated for the first width-1 points, the mean and range of the previous window will not be taken out from the mean value memory and the range memory for output; in other cases, the mean and range are taken out according to the output channel index and output to the pulse detection part. After the mean and range calculation is completed, the input of the pulse identification part includes input data, mean value, range, window width and threshold factor . Pulse signal detection requires calculation of 1 / Since the calculation is complex and the width range is 1 to 64, the standard deviation parameter memory 217 is used to store 1 / After receiving width, the corresponding data is directly taken out from the standard deviation parameter memory 217 for calculation. When equation (4) is satisfied, the signal is considered to be a pulse. In the positive and negative pulse detection mode: If , it is considered to be a positive pulse; if , it is considered to be a negative pulse. This design effectively improves the accuracy of pulse detection and system efficiency.

[0044] like Figure 1 and Figure 4As shown, the pulse identification module 2 also includes a fixed threshold detection module 22, which uses a preset fixed threshold to perform pulse detection, and the output ends of the automatic threshold detection module 21 and the fixed threshold detection module 22 are respectively connected to the input end of a multiplexer MUX23 controlled by a configured working mode, and the fixed threshold detection module 22 directly compares the input EEG signal with the preset fixed threshold; the fixed threshold detection module 22 includes a comparator 221, one input of the comparator 221 is, and the other output is the input EEG signal, which is used to determine whether the signal amplitude exceeds the fixed threshold, thereby detecting a pulse signal.

[0045] In the fixed threshold detection mode, pulse detection directly determines whether the current signal is a pulse by comparing the input signal with the preset fixed threshold. The input fixed threshold is a 16-bit unsigned number. The positive pulse detection formula is as follows: ; When the above conditions are met, the current signal is determined to be a positive pulse. The negative pulse detection formula is as follows: ; When the above conditions are met, the current signal is determined to be a negative pulse. In this way, the fixed threshold detection mode can perform pulse detection simply and efficiently, and is suitable for application scenarios where the signal characteristics are stable and the threshold is known. The advantage of this method is that it is simple to implement and has a small amount of calculation, and is particularly suitable for resource-constrained hardware implementation. The fixed threshold detection method has the advantages of simple implementation and small amount of calculation, and is suitable for a stable signal environment. The fixed threshold can be implemented by a register or a memory to store the fixed threshold. In this embodiment, a threshold setter is used to store and set the fixed detection threshold. The component is implemented by a hardware register, which can accurately set the threshold and ensure that it remains unchanged during the detection process. In the fixed threshold detection module 22, whenever there is data input, the signal will be passed to the comparator 221. According to the configured pulse detection mode, the comparator 221 can perform three modes: positive pulse detection, negative pulse detection, and positive and negative pulse detection. According to the comparison result, the module marks the detected pulse signal as a positive pulse or a negative pulse, and outputs the detection result to the subsequent processing unit. This processing architecture design ensures the efficiency and real-time performance of the fixed threshold detection method, while maintaining the advantages of low hardware overhead and simple implementation. The fixed threshold detection module 22 is simple in design and requires little calculation, and is particularly suitable for situations where signal characteristics are relatively stable.

[0046] In order to maintain efficient and reliable working performance in different application environments, the pulse detection module 2 combines the two methods of automatic threshold detection and fixed threshold detection through the automatic threshold detection module 21 and the fixed threshold detection module 22. Through the multiplexer MUX23, it can switch between the automatic threshold detection mode and the fixed threshold detection mode. The multiplexer MUX23 selects the appropriate detection method according to the application requirements to ensure the flexibility and adaptability of the detection. The multiplexer MUX23 is controlled by the mode signal to realize the mode switching of the dual-mode detection. The dual-mode detection includes two modes, automatic threshold detection and fixed threshold detection. It can select the best detection method according to the signal characteristics to ensure efficient and accurate pulse detection in complex signal environments. Through this design, the comprehensive pulse detection module takes into account the accuracy and stability of detection while ensuring high efficiency, and can meet the pulse detection requirements in various complex signal environments. The pulse identification module 3 solves the problem of realizing high-precision pulse detection under limited hardware resources through time division multiplexing technology and optimized detection algorithm. It combines the two methods of automatic threshold detection and fixed threshold detection to minimize the use of hardware resources while maintaining detection accuracy. This module ensures the high efficiency and real-time performance of pulse detection, and provides the system with reliable and accurate pulse recognition capabilities in complex signal environments.

[0047] The function of the waveform output module 3 is to record and output the waveform data near the pulse point. In this embodiment, the waveform output module 3 is specifically used to record the waveform data 1ms before and 2ms after the pulse point, and when the waveform data recording reaches 3ms, the waveform data is continuously sent through the AXI Stream interface. Figure 5As shown, the waveform output module 3 includes: a waveform data memory 31 for storing waveform data; a write address pointer module 32 for specifying the write address; a pulse counter 33 for calculating the number of waveform sampling points; a read address register 34 for storing the value of the write address pointer module 32 so as to find the starting point of the waveform when reading the pulse waveform; a channel FIFO 35 for storing the channel for outputting the waveform; the front end of the waveform data memory 31 is connected to a write port for writing input data, the write address of the write port is determined by the sum of the channel index and the value of the write address pointer module 32, and the write enable of the write port is controlled by the data valid signal; the write address pointer module 32 is a circular shift register, and the write address has two ranges: 0 to Length-1 and Length to 2*Length-1, where Le ngth is the number of sampling points of a complete waveform. The circular shift register will cycle between the two ranges after completing the waveform storage of a channel; after receiving the pulse signal, the pulse counter 33 sets the counter value to 2*Length / 3. Whenever valid data is input, the counter value is reduced by 1, and when the counter value is reduced to 0, the loop range of the write address pointer module 32 is switched, and the current value of the write address pointer module 32 is saved in the read address register 34, and the current channel number is output to the channel FIFO35; the non-empty signal of the channel FIFO35 is connected to the read enable signal of the waveform data memory 31. When the channel FIFO35 is not empty, the waveform data is read from the waveform data memory 31 according to the channel number of the channel FIFO35 and the value of the read address register 34 and output through the AXI interface.

[0048] The waveform output module 3 can be divided into a data receiving part and a data sending part. The data receiving part is responsible for recording the waveform data 1ms before each pulse point. When receiving data, since the subsequent pulse point position cannot be predicted, each channel sets a buffer with a width of 16 bits and a depth of 2 times Length, namely: waveform data memory 31. Length is the number of data corresponding to the 3ms pulse waveform. Taking the highest sampling frequency of 30kHz as an example, Length should be 90. The waveform data memory 31 adopts a ping-pong RAM structure. When a RAM is full of pulse waveforms, the new data will overwrite the original data. Therefore, it is necessary to send out this part of the data and use another part of the RAM to receive the new data. The write pointer of each channel has two operation modes: (1) Low address write mode: the pointer shifts cyclically in the range of 0 to Length-1. (2) High address write mode: when the low address is full and not sent, the pointer shifts cyclically in the range of Length to 2×Length-1. Whenever a valid data signal enters, the write pointer increments within the data range and calculates the write address of the RAM according to the channel index. When pulse data enters, a pulse counter is set to Length×2 / 3, and the counter is decremented every time new data enters the channel. When the counter is zero, a read address pointer is saved to ensure that the pulse waveform is sent from the first data point. At the same time, the write address range is switched to avoid overwriting of unsent data, and the channel number and chip select signal are sent to the pulse FIFO to ensure that the waveform data is sent in the order of waveform recording. The chip select signal indicates the address range, the low address is 0, and the high address is 1. The data sending part is responsible for sending the recorded waveform data to the host computer through the AXI Stream transmission protocol through the AXI interface for further processing. Under normal circumstances, AXI Stream continues to send a ready signal to the waveform output module 3. When the waveform output module 3 receives the ready signal and can read the channel information from the pulse FIFO, it starts to send data. The data sending process is as follows: Channel and frequency information sending: Before sending a complete waveform data each time, the current sampling frequency information and the channel information of the current waveform are sent in two cycles. Waveform data transmission: The waveform data is taken out in order of the address, the lower 8 bits are sent first, and then the upper 8 bits are sent, until the 3ms waveform data is sent. Through this design, the waveform output module 3 can efficiently record and transmit pulse waveform data to meet the needs of various real-time signal processing. The waveform recording and transmission of the waveform output module 3 solves the storage and management problems of high-throughput data through multiple sets of storage logic and efficient data transmission mechanism, ensuring that the system is efficient and reliable when processing and transmitting large amounts of neural signal data.

[0049] like Figure 1As shown, the neural pulse on-chip detection circuit of this embodiment also includes an accelerator interface 4 and a microprocessor 5. The microprocessor 5 is connected to the input module 1, the pulse recognition module 2 and the waveform output module 3 respectively through the accelerator interface 4 to perform parameter configuration on the input module 1, the pulse recognition module 2 and the waveform output module 3, including the path selection configuration in the input module 1, the pulse mode and detection parameter (such as threshold) configuration in the pulse recognition module 2, and the frequency mode configuration in the waveform output module 3, etc., which can be selected according to actual needs. In this embodiment, the accelerator interface 4 is connected to the pulse recognition module 2 and the waveform output module 3 for parameter configuration of the pulse recognition module 2 and the waveform output module 3, including: configuring the working mode for the multiplexer MUX23 of the pulse recognition module 2 to select the output of the automatic threshold detection module 21 or the fixed threshold detection module 22, the current window width width stored in the register of the automatic threshold detection module 21, the threshold factor P_Value (in this embodiment, the value is between 1 and 5), and the fixed threshold in the fixed threshold detection module 22; configuring the sampling frequency of the input signal for the waveform output module 3, and the sampling frequency of the input signal is used to control the number of data points of the waveform recorded when the waveform is output.

[0050] Figure 6 FIG. 1 is a schematic diagram of the working process of the on-chip neural pulse detection circuit in this embodiment. Figure 6As shown in the figure, the working process of the neural pulse on-chip detection circuit in this embodiment can be divided into the following stages: (1) Signal input stage: Each SPI engine continuously receives signals and reads 1 bit of signal per cycle. A complete 16-bit signal requires 16 cycles to be read in. Therefore, the signal input adopts a pipeline method, and the data of the first channel is one cycle later than the data of the 0th channel, and the data of the second channel is one cycle later than the first channel, and so on. When 16 channels of signals are connected at the same time, a new data will enter the chip for processing in each cycle. Each channel contains data from 16 channels, thereby realizing time division multiplexing of 256 channels of data. (2) Input module processing stage: After each channel of signal is restored to the original 16-bit data through the SPI engine, it is first stored in the FIFO of a single channel signal. The polling module takes out the data from the FIFO and stores it in a FIFO that stores 16 channels of data. Then the Fetch module takes out the data from the FIFO and sends it to the pulse recognition module. (3) Calculation of mean and data range stage: Taking the automatic threshold detection method as an example, after the data enters the pulse recognition module, the mean and data range are first calculated. The data of different channels are calculated in each cycle to realize pipeline operation. (4) Comparing pulse stage: After calculating the mean and data range, the pulse identification module determines whether the current data point is a pulse point according to the formula. This step is executed once per cycle to compare the pulse output of different channels. (5) Recording waveform data stage: After detecting the pulse signal, the waveform output module stores each waveform data that may be needed. (6) Entering the pulse FIFO stage: In the comparing pulse stage, if a channel detects a pulse signal and stores a complete waveform data in the recording waveform data stage, the channel data will enter the pulse FIFO. This stage may not occur in every cycle. (7) Sending waveform data stage: If the pulse FIFO is not empty, the waveform output module reads the channel number from the pulse FIFO and sends the channel data. This stage may not occur in every cycle, but if the channel number in the pulse FIFO is read, the waveform output module will send the complete waveform data in multiple consecutive cycles. The above stages are executed in a pipeline manner to improve the execution efficiency of the neural pulse on-chip detection circuit for EEG signals in this embodiment.

[0051] In summary, in order to solve the problem of time-division multiplexing of computing circuits caused by resource limitations and frequency differences, the problem of resource management and data synchronization in high-throughput data processing, and the problem of pulse detection algorithm implementation with a compromise between accuracy and hardware overhead, the neural pulse on-chip detection circuit for EEG signals in this embodiment mainly includes an input module 1, a pulse recognition module 2, and a waveform output module 3, wherein the input module 1 receives multi-channel EEG signals in a pipeline manner through an SPI engine, realizes 1-bit signal reception per cycle, and ensures the efficiency and real-time performance of data input. The pulse recognition module 2 utilizes time-division multiplexing technology to efficiently utilize computing resources, combines automatic threshold detection and fixed threshold detection methods, and reduces hardware resource usage while ensuring detection accuracy. The waveform output module 3 stores the detected pulse signal waveform data and sends it through the AXI Stream protocol. A large amount of neural signal data is efficiently managed and stored through multiple sets of storage logic to ensure rapid access and processing of data. The present invention realizes efficient, accurate and resource-efficient EEG signal pulse detection through optimized module design and advanced technical means, which can meet the needs of complex signal processing environments. The neural pulse on-chip detection circuit for EEG signals in this embodiment has the following characteristics: 1. Efficient multi-channel data processing: The parallel reception and processing of multi-channel EEG signals are realized through the SPI engine to ensure the efficiency and real-time performance of data input. 2. Time-division multiplexing technology: Time-division multiplexing technology is used to efficiently utilize computing resources, realize the processing of different tasks, and optimize the efficiency of the use of computing circuits. 3. Compromise between accuracy and hardware overhead: Combining the two methods of automatic threshold detection and fixed threshold detection, while ensuring the detection accuracy, the use of hardware resources is reduced as much as possible. 4. Efficient data management: Through multiple sets of storage logic, a large amount of neural signal data is efficiently managed and stored to ensure rapid access and processing of data. This design ensures the efficiency, accuracy and resource utilization of the neural pulse on-chip detection circuit for EEG signals in this embodiment in a complex signal processing environment.

[0052] In addition, this embodiment also provides an EEG signal detection device, including a detection electrode assembly and a neural pulse on-chip detection circuit, the detection electrode assembly includes detection electrodes of multiple channels, the detection electrodes of multiple channels are respectively connected to the input ends of the neural pulse on-chip detection circuit, and the neural pulse on-chip detection circuit is the aforementioned neural pulse on-chip detection circuit for EEG signals. As an optional implementation, the output end of the neural pulse on-chip detection circuit in this embodiment is connected to a computer device.

[0053] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A neural pulse on-chip detection circuit for electroencephalogram signals, characterized in that: include: An input module (1) is used to receive multiple EEG signals input from a serial peripheral interface through time division multiplexing; A pulse identification module (2) is used to perform pulse detection on the input EEG signal; A waveform output module (3), used for recording and outputting waveform data near the pulse point; The input module (1) comprises a serial peripheral interface for inputting multiple channels of electroencephalogram signals. The input module (1), the pulse recognition module (2) and the waveform output module (3) are connected in sequence. The waveform output module (3) has an output interface for outputting waveform data.

2. The on-chip neural pulse detection circuit for electroencephalogram signals according to claim 1, characterized in that: The input module (1) comprises a 16-channel SPI engine (11), 16 single-channel data FIFO buffers (12), a polling module (13), a common data FIFO buffer (14) and an extraction module (15). The electroencephalogram signal from each serial peripheral interface is sent to the single-channel data FIFO buffer (12) for buffering after the conversion from serial data to parallel data is completed by the corresponding SPI engine (11). The polling module (13) takes the buffered electroencephalogram signal from each of the 16 single-channel data FIFO buffers (12) in turn and sends it to the common data FIFO buffer (14). The extraction module (15) sends the 16-channel electroencephalogram signal buffered in the common data FIFO buffer (14) to the pulse recognition module (2).

3. The neural pulse on-chip detection circuit for electroencephalogram signals according to claim 2, characterized in that: The input of the SPI engine (11) is 1 bit, and the output is 16 bits. The SPI engine (11) comprises a shift register. Each 1-bit input signal is stored in the shift register. When the data stored in the shift register reaches 16 bits, the 16-bit data is output at one time. Each SPI engine (11) processes the data of 16 channels in a time division multiplexing (TDM) manner, so that the 16-channel SPI engines (11) can process a total of 256 channels of data to achieve high-throughput data input. Each SPI engine (11) is provided with a first circular shift register (16) for calculating a channel index. The width of the first circular shift register (16) is 8 bits, and the circular range of the first circular shift register (16) of each SPI engine (11) is different. Whenever the SPI engine (11) outputs a valid signal, the first circular shift register (16) is self-incremented once, and the 16-bit original signal data is combined with the 8-bit data in the first circular shift register (16) to form a 24-bit data output containing channel information.

4. The neural pulse on-chip detection circuit for electroencephalogram signals according to claim 3, characterized in that: The invention also comprises an accelerator interface (4) and a microprocessor (5). The microprocessor (5) is connected to the input module (1) via the accelerator interface (4) to configure parameters of the input module (1). The parameter configuration comprises a route selection configuration and a channel number configuration. The route selection configuration is used to select a specified route number so that the SPI engine (11) and the single-channel data FIFO buffer (12) of the corresponding route work, and the polling module (13) also takes data from the single-channel data FIFO buffer (12) of the corresponding route. The channel number configuration refers to configuring the channel selected by the SPI engine (11) and the cyclic range of the channel index of the first cyclic shift register (16), so that the SPI engine (11) sequentially inputs the input data of the selected channel.

5. The neural pulse on-chip detection circuit for electroencephalogram signals according to claim 1, characterized in that: The pulse identification module (2) comprises an automatic threshold detection module (21), wherein the automatic threshold detection module (21) comprises: a second circular shift register (211) for determining the state of the current channel; a maximum value memory (212) for respectively storing the maximum value of the current window; a minimum value memory (213) for respectively storing the minimum value of the current window; a partial sum memory (214) for respectively storing the partial sum of the current window; an average value memory (215) for respectively storing the average value of the previous window; and a range memory (216) for respectively storing the range of the previous window. range; a standard deviation parameter memory (217) for storing parameters for calculating the standard deviation; a calculation processing unit for performing data calculation, data comparison, and determining whether the current signal is a pulse signal; the second circular shift register (211) has three states. When the register value is 0, the current input value is stored in the maximum value memory (212), the minimum value memory (213), and the partial sum memory (214), and the register value is increased by 1; when the register value is between 0 and the current window width, the current input value is stored in the maximum value memory (212), the minimum value memory (213), and the partial sum memory (214). The maximum value, the minimum value and the partial sum are taken out from the sum memory (214), updated and rewritten, and the register value is increased by 1; when the register value is equal to the current window width width, the range and the average value are calculated, written into the range memory (216) and the average value memory (215) respectively, and the register value is set to 0; the second circular shift register (211), the maximum value memory (212), the minimum value memory (213), the partial sum memory (214), the average value memory (215) and the range memory (216) are all directly connected to the input channel index, and the data is read and written by Data valid signal control; the input of the standard deviation parameter memory (217) includes the current window width width, and the reading and writing of data is controlled by the data valid signal. When data enters, the calculation processing unit first updates the maximum value, minimum value and partial sum of the current window, and takes out the average value and range of the previous window, and then multiplies the range with the standard deviation parameter related to the window width to obtain an approximate standard deviation. Finally, according to the current input signal, the average value, the approximate standard deviation and the input threshold factor P_Value, it is judged whether the current input signal is a pulse signal and outputs it.

6. The on-chip neural pulse detection circuit for electroencephalogram signals according to claim 5, characterized in that: The pulse recognition module (2) further comprises a fixed threshold detection module (22), and the output ends of the automatic threshold detection module (21) and the fixed threshold detection module (22) are respectively connected to the input end of a multiplexer MUX (23) controlled by a configured working mode; the fixed threshold detection module (22) comprises a comparator (221), one input of the comparator (221) is a fixed threshold, and the other output is an input electroencephalogram signal.

7. The on-chip neural pulse detection circuit for electroencephalogram signals according to claim 6, characterized in that: The waveform output module (3) comprises: a waveform data memory (31) for storing waveform data; a write address pointer module (32) for specifying a write address; a pulse counter (33) for calculating the number of waveform sampling points; a read address register (34) for storing the value of the write address pointer module (32) so as to find the starting point of the waveform when reading the pulse waveform; and a channel FIFO (35) for storing the channel for which the waveform needs to be output. The front end of the waveform data memory (31) is connected to a write port for writing input data, the write address of the write port is determined by the sum of the channel index and the value of the write address pointer module (32), and the write enable of the write port is controlled by a data valid signal. The write address pointer module (32) is a circular shift register, and the write address has two ranges: 0 to Length-1 and Length to 2*Length-1, wherein Lengt h is the number of sampling points of a complete waveform, and the circular shift register will cycle between the two ranges after completing the waveform storage of a channel; after receiving the pulse signal, the pulse counter (33) sets the counter value to 2*Length / 3, and whenever valid data is input, the counter value is reduced by 1, and when the counter value is reduced to 0, the circulation range of the write address pointer module (32) is switched, and the current value of the write address pointer module (32) is saved in the read address register (34), and the current channel number is output to the channel FIFO (35); the non-empty signal of the channel FIFO (35) is connected to the read enable signal of the waveform data memory (31), and when the channel FIFO (35) is not empty, the waveform data is read from the waveform data memory (31) according to the channel number of the channel FIFO (35) and the value of the read address register (34) and output through the AXI interface.

8. The neural pulse on-chip detection circuit for electroencephalogram signals according to claim 4, characterized in that: The accelerator interface (4) is also connected to the pulse recognition module (2) and the waveform output module (3) respectively to configure parameters of the pulse recognition module (2) and the waveform output module (3), including: configuring the working mode of the multiplexer MUX (23) of the pulse recognition module (2) to select the output of the automatic threshold detection module (21) or the fixed threshold detection module (22), the current window width width stored in the register of the automatic threshold detection module (21), the threshold factor P_Value, and the fixed threshold in the fixed threshold detection module (22); configuring the sampling frequency of the input signal for the waveform output module (3), the sampling frequency of the input signal being used to control the number of data points of the waveform recorded when the waveform is output.

9. An electroencephalogram signal detection device, characterized in that: It comprises a detection electrode assembly and a neural pulse on-chip detection circuit, wherein the detection electrode assembly comprises detection electrodes of multiple channels, and the detection electrodes of multiple channels are respectively connected to the input ends of the neural pulse on-chip detection circuit, and the neural pulse on-chip detection circuit is the neural pulse on-chip detection circuit for electroencephalogram signals as claimed in any one of claims 1 to 8.

10. The electroencephalogram signal detection device according to claim 9, characterized in that: The output end of the neural pulse on-chip detection circuit is connected to a computer device.

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