A multi-channel electroencephalogram signal acquisition system based on auditory evoked potential

Abstract

The application is based on a multi-channel brain electrical signal acquisition system of auditory evoked potential: after receiving the brain electrical signal acquisition instruction through the communication circuit, the control circuit controls to send a trigger signal to the audio generation circuit, and the audio generation circuit generates an audio signal based on the audio source obtained through the audio source interface; the audio driving circuit generates an audio driving signal containing the audio signal based on the audio signal, and the control circuit controls the audio driving circuit to output the audio driving signal of the set time length through the earphone interface, so that the earphone outputs the sound stimulation to act on the collector; the audio driving circuit generates a synchronization signal based on the audio driving signal and transmits it to the signal acquisition circuit, and the signal acquisition circuit acquires the multi-channel brain electrical signals of multiple brain electrical electrodes through the signal acquisition interface and transmits the multi-channel brain electrical signals to the control circuit; the control circuit stores the multi-channel brain electrical signals in the storage circuit and uploads them to the upper computer through the communication circuit; the control circuit controls the system operation indication circuit to light up when the system operates normally.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electroencephalogram signal acquisition, in particular to a multi-channel electroencephalogram signal acquisition system based on auditory evoked potential. BACKGROUND

[0002] The electroencephalogram cap is worn on the head of the collector for detecting the electroencephalogram signal of the collector, and has the characteristics of comfortable wearing, good contact, normal signal acquisition, etc. The existing electroencephalogram cap for collecting electroencephalogram signal, earphone for emitting sound stimulation, electroencephalogram acquisition device containing electroencephalogram acquisition circuit and sound stimulation device containing sound stimulation generation circuit are generally designed separately, which occupies large space and is scattered and messy. For example, the application No. CN201510038162.9, the name of a portable electroencephalogram headgear, discloses that the electrode, earphone and other components are arranged on the electroencephalogram headgear. Although the electroencephalogram electrode and earphone are integrated on the electroencephalogram headgear in this existing patent, the electroencephalogram acquisition device and sound stimulation device are not integrated on the electroencephalogram headgear. Therefore, the present application designs a multi-channel electroencephalogram signal acquisition system based on auditory evoked potential, which integrates the electroencephalogram acquisition device and the sound stimulation device on the electroencephalogram cap, which is conducive to the generation of sound stimulation and signal acquisition, and occupies small space, is neat and orderly. SUMMARY

[0003] The present application provides a multi-channel electroencephalogram signal acquisition system based on auditory evoked potential.

[0004] The present application solves the above technical problems by the following technical scheme:

[0005] The present application provides a multi-channel electroencephalogram signal acquisition system based on auditory evoked potential, which is characterized in that it comprises an electroencephalogram cap and an earphone for the collector to wear, and an electroencephalogram acquisition device, a plurality of electroencephalogram electrodes are installed on the electroencephalogram cap, the electroencephalogram acquisition device is installed on the electroencephalogram cap, the electroencephalogram acquisition device comprises a shell, the shell is integrated with a power supply interface, a power supply circuit, an audio source interface, an audio generation circuit, an audio drive circuit, an earphone interface, a signal acquisition interface, a signal acquisition circuit, a control circuit, a storage circuit, a system operation indication circuit and a communication circuit;

[0006] The power supply circuit is used to access the external power supply through the power supply interface, and convert the external power supply into the power supply voltage to power the control circuit, the audio generation circuit, the audio drive circuit, the signal acquisition circuit, the storage circuit, the system operation indication circuit and the communication circuit;

[0007] The control circuit is in communication connection with the upper computer through a communication circuit, the sound source interface, the audio generation circuit and the control circuit are electrically connected in sequence, the control circuit is used for controlling to send a trigger signal to the audio generation circuit after receiving a brain electrical signal collection instruction through the communication circuit, the audio generation circuit is used for receiving the trigger signal and generating an audio signal based on the sound source obtained through the sound source interface;

[0008] The audio generation circuit and the audio driving circuit are electrically connected, the earphone interface, the audio driving circuit and the control circuit are electrically connected in sequence, the audio driving circuit is used for receiving the audio signal and generating an audio driving signal containing the audio signal based on the audio signal, and the control circuit is used for controlling the audio driving circuit to output the audio driving signal with a set time length through the earphone interface, so that the earphone outputs the sound stimulus with the set time length to act on the collector;

[0009] The audio driving circuit and the signal acquisition circuit are electrically connected, the brain electrical electrode, the signal acquisition interface, the signal acquisition circuit and the control circuit are electrically connected in sequence, the audio driving circuit is used for generating a synchronization signal based on the audio driving signal and transmitting the synchronization signal to the signal acquisition circuit, and the signal acquisition circuit is used for acquiring the multi-channel brain electrical signals sensed by the plurality of brain electrical electrodes through the signal acquisition interface and transmitting the multi-channel brain electrical signals to the control circuit;

[0010] The storage circuit and the communication circuit are both electrically connected with the control circuit, and the control circuit is used for storing the multi-channel brain electrical signals of the collector in the storage circuit and uploading the multi-channel brain electrical signals to the upper computer through the communication circuit;

[0011] The system operation indication circuit is electrically connected with the control circuit, and the control circuit is used for controlling the system operation indication circuit to light up when the system operates normally.

[0012] The positive progress effect of the present application is that:

[0013] The present application integrates the brain electrical signal acquisition assembly and the sound stimulus assembly to form the brain electrical signal acquisition device, and installs the brain electrical signal stimulation device on the brain electrical cap, which is beneficial to the generation of sound stimulus and the acquisition of signals, occupies small space, is neat and orderly, and the present application also optimizes the design of each circuit in the brain electrical signal acquisition device, so that the multi-channel brain electrical signals can be more accurately acquired. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 It is a schematic diagram of the multi-channel brain electrical signal acquisition system of the preferred embodiment of the present application.

[0015] Figures 2-4 It is a structural schematic diagram of the brain electrical cap of the preferred embodiment of the present application.

[0016] Figure 5The schematic diagram of the power supply circuit of the preferred embodiment of the present application.

[0017] Figure 6 The schematic diagram of the power supply circuit of the preferred embodiment of the present application.

[0018] Figure 7 The first DC-DC circuit diagram of the preferred embodiment of the present application.

[0019] Figure 8 The first protection circuit and communication circuit diagram of the preferred embodiment of the present application.

[0020] Figure 9 The first voltage stabilizing circuit, the first switch circuit and the audio driving circuit diagram of the preferred embodiment of the present application.

[0021] Figure 10 The second switch circuit and the audio generating circuit diagram of the preferred embodiment of the present application.

[0022] Figure 11 The third switch circuit and the storage circuit diagram of the preferred embodiment of the present application.

[0023] Figure 12 The fourth switch circuit, the filter circuit, the second DC-DC circuit, the second voltage stabilizing circuit and the third voltage stabilizing circuit diagram of the preferred embodiment of the present application.

[0024] Figure 13 The control circuit diagram of the preferred embodiment of the present application.

[0025] Figure 14 The signal acquisition interface and the electroencephalogram acquisition protection circuit diagram of the preferred embodiment of the present application.

[0026] Figure 15 The signal acquisition circuit diagram of the preferred embodiment of the present application.

[0027] Figure 16 The system operation indication circuit diagram of the preferred embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0029] As Figures 1-4As shown, the embodiment provides a multi-channel electroencephalogram signal acquisition system based on auditory evoked potential, which comprises an electroencephalogram cap 100 and an earphone 200 for a collector to wear, and an electroencephalogram acquisition device 300, the electroencephalogram cap 100 is provided with a plurality of electroencephalogram electrodes 101, and the electroencephalogram acquisition device 300 is installed on the electroencephalogram cap 100, the electroencephalogram acquisition device 300 comprises a shell 301, and the shell 301 is integrated with a power supply interface 302, a power supply circuit 303, an audio source interface 304, an audio generation circuit 305, an audio drive circuit 306, an earphone interface 307, a signal acquisition interface 308, a signal acquisition circuit 309, a control circuit 310, a storage circuit 311, a system operation indication circuit 312 and a communication circuit 313.

[0030] The power supply circuit 303 is used for accessing an external power supply through the power supply interface 302 and converting the external power supply into a power supply voltage to power the control circuit 310, the audio generation circuit 305, the audio drive circuit 306, the signal acquisition circuit 309, the storage circuit 311, the system operation indication circuit 312 and the communication circuit 313.

[0031] The control circuit 310 is in communication connection with a host computer through the communication circuit 313, the audio source interface 304, the audio generation circuit 305 and the control circuit 310 are electrically connected in sequence, and the control circuit 310 is used for controlling to send a trigger signal to the audio generation circuit 305 after receiving an electroencephalogram signal acquisition instruction through the communication circuit 313, and the audio generation circuit 305 is used for generating an audio signal based on an audio source obtained through the audio source interface 304 after receiving the trigger signal.

[0032] The audio generation circuit 305 and the audio drive circuit 306 are electrically connected, the earphone interface 307, the audio drive circuit 306 and the control circuit 310 are electrically connected in sequence, the audio drive circuit 306 is used for receiving the audio signal and generating an audio drive signal containing the audio signal based on the audio signal, and the control circuit 310 is used for controlling the audio drive circuit 306 to output the audio drive signal of a set time length through the earphone interface 307, so that the earphone 200 outputs the sound stimulation of the set time length to act on the collector, and the auditory evoked potential is realized.

[0033] The audio drive circuit 306 and the signal acquisition circuit 309 are electrically connected, the electroencephalogram electrode 101, the signal acquisition interface 308, the signal acquisition circuit 309 and the control circuit 310 are electrically connected in sequence, the audio drive circuit 306 is used for generating a synchronization signal based on the audio drive signal and transmitting the synchronization signal to the signal acquisition circuit 309, and the signal acquisition circuit 309 is used for acquiring the multi-channel electroencephalogram signals sensed by the plurality of electroencephalogram electrodes through the signal acquisition interface 308 and transmitting the multi-channel electroencephalogram signals to the control circuit 310.

[0034] The storage circuit 311 and the communication circuit 313 are electrically connected with the control circuit 310, and the control circuit 310 is configured to store the multi-channel brain electrical signals of the collector in the storage circuit 311, and upload to the upper computer through the communication circuit 313.

[0035] The system operation indication circuit 312 is electrically connected with the control circuit 310, and the control circuit 310 is configured to control the system operation indication circuit 312 to light up when the system operates normally.

[0036] As shown in the first embodiment of the present application, Figure 5 The power supply circuit 303 includes a power supply main switch circuit, a first DC-DC circuit, a first protection circuit, a first voltage stabilizing circuit, a first switch circuit, a second switch circuit, a third switch circuit, a fourth switch circuit, a filter circuit, a second DC-DC circuit, a second voltage stabilizing circuit and a third voltage stabilizing circuit.

[0037] The input end of the power supply main switch circuit is electrically connected with the power supply interface 302 (such as a Type-C interface), and the output end of the power supply main switch circuit is electrically connected with the control circuit 310 through the first DC-DC circuit, and the power supply main switch circuit is configured to control the control circuit 310 to be turned on and output a first power supply voltage VCC_5V based on the input voltage, and the first DC-DC circuit is configured to convert the first power supply voltage into a second power supply voltage VCC_3.3V and provide the second power supply voltage VCC_3.3V for the control circuit 310.

[0038] The output end of the power supply main switch circuit is electrically connected with the communication circuit 313 through the first protection circuit to provide a VBUS voltage for the communication circuit 313, and the output end of the first DC-DC circuit is electrically connected with the communication circuit 313 to provide the second power supply voltage VCC_3.3V for the communication circuit 313.

[0039] The output end of the power supply main switch circuit is electrically connected with the audio driving circuit 306 through the first voltage stabilizing circuit, and the first voltage stabilizing circuit is configured to stabilize the first power supply voltage VCC_5V as a stabilized power supply voltage VCC1_3V3A and provide a 3.3V stabilized power supply voltage VCC1_3V3A for the audio driving circuit 306, and the output end of the first DC-DC circuit is electrically connected with the audio driving circuit 306 through the first switch circuit to provide a 3.3V power supply voltage VCC1_3V3 for the audio driving circuit 306.

[0040] The output end of the first DC-DC circuit is electrically connected with the audio generating circuit 305 through the second switch circuit to provide a 3.3V power supply voltage VCC2_3V3 for the audio generating circuit 305.

[0041] The output end of the first DC-DC circuit is electrically connected with the storage circuit 311 through the third switch circuit, for providing a 3.3V power supply voltage VCC3_3V3 for the storage circuit 311.

[0042] The output end of the first DC-DC circuit is electrically connected with the input end of the fourth switch circuit, the output end of the fourth switch circuit is electrically connected with the signal acquisition circuit 309 through the filter circuit, for providing a filtered voltage DVDD_33 for the signal acquisition circuit 309, the output end of the fourth switch circuit is also electrically connected with the signal acquisition circuit 309 through the second DC-DC circuit and the second voltage stabilizing circuit, and is also electrically connected with the signal acquisition circuit 309 through the third voltage stabilizing circuit, for providing a bipolar power supply voltage (AVSS and AVDD respectively) for the signal acquisition circuit.

[0043] As shown in Figure 6 The power supply on-off switch circuit includes a total switch K3 (model K8-5854P-L1) and a power supply switch chip U4 (model TPS2553DRVR), the switch end of the total switch K3 is embedded on the shell 301, the IN pin (pin 6) of the power supply switch chip U4 is electrically connected with the power supply interface 302, is also electrically connected with the pin 2 of the total switch K3, and is grounded through the capacitor C30, the EN pin (pin 4) of the power supply switch chip U4 is electrically connected with the pin 3 of the total switch K3 through the resistor R14, is grounded through the resistor R77, and is grounded through the capacitor C32, the GND pin (pin 5) and the EP pin (pin 7) of the power supply switch chip U4 are grounded, The pin 3 of the power supply switch chip U4 is electrically connected with the power supply interface 302 through the power supply state indicating lamp D2 and the resistor R17, the ILIM pin (pin 2) is grounded through the resistor R15, and the OUT pin (pin 1) of the power supply switch chip U4 is used for outputting the first power supply voltage VCC_5V and is grounded through the capacitor C31.

[0044] As shown in Figure 7As shown, the first DC-DC circuit includes: a power management chip U1 (TPS62140RGTR). The two PVIN pins (pins 11 and 12), AVIN pin (pin 10), and EN pin (pin 13) of the power management chip U1 are electrically connected to the OUT pin (pin 1) of the power switch chip U4 to receive the first supply voltage VCC_5V. It is also grounded through series resistors R9 and R12, capacitors C105, C24, and C23. The FSW pin (pin 7) of the power management chip U1 is grounded through resistor R12, the DEF pin (pin 8) is grounded through resistor R11, and the SS / TR pin (pin 9) is grounded through capacitor C2. 9. Grounding; the two PGND pins (pins 15 and 16), AGND pin (pin 6), and EP pin (pin 17) of the power management chip U1 are all grounded; the FB pin (pin 5) of the power management chip U1 is grounded through resistor R13, and the VOS pin (pin 14) is grounded through a series of resistors R10 and R13; the three SW pins (pins 1, 2, and 3) of the power management chip U1 output the second supply voltage VCC_3.3V through inductors L1 and L8 in series. Inductors L1 and L8 are grounded through capacitors C25, C26, C27, and C28, respectively. The end of inductor L8 furthest from inductor L1 is grounded through capacitors C108 and C107, respectively.

[0045] like Figure 8 As shown, the first protection circuit includes: resistor R20 and diode D5. One end of resistor R20 is electrically connected to the OUT pin (pin 1) of power switch chip U4 to access the first supply voltage VCC_5V, and the other end is electrically connected to the cathode of diode D5. The anode of diode D5 is grounded, and the cathode is electrically connected to communication circuit 313 to provide VBUS voltage.

[0046] like Figure 9 As shown, the first voltage regulator circuit includes: a linear regulator U8 (model SOT23-5), whose VIN pin (pin 1) is electrically connected to the OUT pin (pin 1) of the power switch chip U4 to receive the first supply voltage VCC_5V, and is also grounded through capacitor C45 and capacitor C46; the EN pin (pin 3) of the linear regulator U8 is electrically connected to the PE1 pin of the main control chip U13 in the control circuit, the GND pin (pin 2) is grounded, and the BP pin (pin 4) is grounded through capacitor C49; the VOUT pin (pin 5) of the linear regulator U8 is electrically connected to the audio driver circuit 306, and is also grounded through capacitor C47 and capacitor C48, for providing a 3.3V regulated supply voltage VCC1_3V3A to the audio driver circuit 306.

[0047] likeFigure 9 As shown in the figure, the first switch circuit includes: a transistor Q3 (model number DTC143ZE) and a field effect transistor M2 (model number SOT1220), the base of the transistor Q3 is electrically connected to the PE1 pin of the main control chip U13 in the control circuit 310, the emitter of the transistor Q3 is grounded, the source of the field effect transistor M2 is electrically connected to the inductor L8 of the power management chip U1 through the resistor R21 to access the second power supply voltage VCC_3.3V, the source is also grounded through the capacitor C38, and the source is also electrically connected to the collector of the transistor Q3 through the resistor R22, the gate of the field effect transistor M2 is electrically connected to the collector of the transistor Q3, the drain of the field effect transistor M2 is electrically connected to the audio drive circuit 306, also grounded through the capacitor C39, and also grounded through the capacitor C40, used to provide a 3.3V voltage VCC1_3V3 for the audio drive circuit 306.

[0048] As shown in the figure, the first switch circuit includes: a transistor Q3 (model number DTC143ZE) and a field effect transistor M2 (model number SOT1220), the base of the transistor Q3 is electrically connected to the PE1 pin of the main control chip U13 in the control circuit 310, the emitter of the transistor Q3 is grounded, the source of the field effect transistor M2 is electrically connected to the inductor L8 of the power management chip U1 through the resistor R21 to access the second power supply voltage VCC_3.3V, the source is also grounded through the capacitor C38, and the source is also electrically connected to the collector of the transistor Q3 through the resistor R22, the gate of the field effect transistor M2 is electrically connected to the collector of the transistor Q3, the drain of the field effect transistor M2 is electrically connected to the audio drive circuit 306, also grounded through the capacitor C39, and also grounded through the capacitor C40, used to provide a 3.3V voltage VCC1_3V3 for the audio drive circuit 306. Figure 10 As shown in the figure, the first switch circuit includes: a transistor Q3 (model number DTC143ZE) and a field effect transistor M2 (model number SOT1220), the base of the transistor Q3 is electrically connected to the PE1 pin of the main control chip U13 in the control circuit 310, the emitter of the transistor Q3 is grounded, the source of the field effect transistor M2 is electrically connected to the inductor L8 of the power management chip U1 through the resistor R21 to access the second power supply voltage VCC_3.3V, the source is also grounded through the capacitor C38, and the source is also electrically connected to the collector of the transistor Q3 through the resistor R22, the gate of the field effect transistor M2 is electrically connected to the collector of the transistor Q3, the drain of the field effect transistor M2 is electrically connected to the audio drive circuit 306, also grounded through the capacitor C39, and also grounded through the capacitor C40, used to provide a 3.3V voltage VCC1_3V3 for the audio drive circuit 306.

[0049] As shown in the figure, the first switch circuit includes: a transistor Q3 (model number DTC143ZE) and a field effect transistor M2 (model number SOT1220), the base of the transistor Q3 is electrically connected to the PE1 pin of the main control chip U13 in the control circuit 310, the emitter of the transistor Q3 is grounded, the source of the field effect transistor M2 is electrically connected to the inductor L8 of the power management chip U1 through the resistor R21 to access the second power supply voltage VCC_3.3V, the source is also grounded through the capacitor C38, and the source is also electrically connected to the collector of the transistor Q3 through the resistor R22, the gate of the field effect transistor M2 is electrically connected to the collector of the transistor Q3, the drain of the field effect transistor M2 is electrically connected to the audio drive circuit 306, also grounded through the capacitor C39, and also grounded through the capacitor C40, used to provide a 3.3V voltage VCC1_3V3 for the audio drive circuit 306. Figure 11 As shown in the figure, the first switch circuit includes: a transistor Q3 (model number DTC143ZE) and a field effect transistor M2 (model number SOT1220), the base of the transistor Q3 is electrically connected to the PE1 pin of the main control chip U13 in the control circuit 310, the emitter of the transistor Q3 is grounded, the source of the field effect transistor M2 is electrically connected to the inductor L8 of the power management chip U1 through the resistor R21 to access the second power supply voltage VCC_3.3V, the source is also grounded through the capacitor C38, and the source is also electrically connected to the collector of the transistor Q3 through the resistor R22, the gate of the field effect transistor M2 is electrically connected to the collector of the transistor Q3, the drain of the field effect transistor M2 is electrically connected to the audio drive circuit 306, also grounded through the capacitor C39, and also grounded through the capacitor C40, used to provide a 3.3V voltage VCC1_3V3 for the audio drive circuit 306.

[0050] As shown in the figure, the first switch circuit includes: a transistor Q3 (model number DTC143ZE) and a field effect transistor M2 (model number SOT1220), the base of the transistor Q3 is electrically connected to the PE1 pin of the main control chip U13 in the control circuit 310, the emitter of the transistor Q3 is grounded, the source of the field effect transistor M2 is electrically connected to the inductor L8 of the power management chip U1 through the resistor R21 to access the second power supply voltage VCC_3.3V, the source is also grounded through the capacitor C38, and the source is also electrically connected to the collector of the transistor Q3 through the resistor R22, the gate of the field effect transistor M2 is electrically connected to the collector of the transistor Q3, the drain of the field effect transistor M2 is electrically connected to the audio drive circuit 306, also grounded through the capacitor C39, and also grounded through the capacitor C40, used to provide a 3.3V voltage VCC1_3V3 for the audio drive circuit 306. Figure 12As shown, the fourth switch circuit includes: a transistor Q5 (model DTC143ZE) and a field effect transistor M4 (model SOT1220), the base of the transistor Q5 is electrically connected to the PI9 pin of the main control chip U13 in the control circuit 310, the emitter of the transistor Q5 is grounded, the source of the field effect transistor M4 is electrically connected to the inductor L8 of the power management chip U1 through the resistor R52 to access the second power supply voltage VCC_3.3V, the source is also grounded through the capacitor C71, and the source is also electrically connected to the collector of the transistor Q5 through the resistor R53, the gate of the field effect transistor M4 is electrically connected to the collector of the transistor Q5, and the drain of the field effect transistor M4 is electrically connected to the filter circuit, the second DC-DC circuit and the third voltage stabilizing circuit respectively, and is also grounded through the capacitor C72, for providing a 3.3V voltage VCC4_3V3.

[0051] As shown in Figure 12 As shown, the filter circuit includes: an inductor L2, a capacitor C73, a capacitor C74 and a capacitor C75, one end of the inductor L2 is electrically connected to the drain of the field effect transistor M4, is also grounded through the capacitor C73, and is also grounded through the capacitor C74, the other end of the inductor L2 is electrically connected to the signal acquisition circuit, and is also grounded through the capacitor C75, for providing a filtered 3.3V voltage DVDD_33 for the signal acquisition circuit.

[0052] As shown in Figure 12 As shown, the second DC-DC circuit includes: a switching voltage regulator chip U11 (model TPS60403DBVR), the IN pin (pin 2) of the switching voltage regulator chip U11 is electrically connected to the drain of the field effect transistor M4 through the inductor L5, is also grounded through the inductor L5 and the capacitor C84 connected in series, is also grounded through the capacitor C85, and is also grounded through the capacitor C86; the GND pin (pin 4) of the switching voltage regulator chip U11 is grounded, the capacitor C83 is connected between the CFLY- pin (pin 3) and the CFLY+ pin (pin 5); the OUT pin (pin 1) of the switching voltage regulator chip U11 is electrically connected to the second voltage stabilizing circuit through the inductor L6, and is also grounded through the capacitor C87 and the capacitor C88 respectively.

[0053] As shown in Figure 12As shown, the second voltage stabilizing circuit comprises: a negative linear voltage stabilizing chip U12 (model number LT3094EMSE), the IN1 pin (pin 1), the IN2 pin (pin 2), the EP pin (pin 13), the PGFB pin (pin 5) and the EN / UV pin (pin 3) of the negative linear voltage stabilizing chip U12 are electrically connected with the inductor L6, and are further grounded through the capacitor C89 and the capacitor C90 respectively, the ILIM pin (pin 6) of the negative linear voltage stabilizing chip U12 is grounded through the resistor R57, the GND pin (pin 9) is grounded, the SET pin (pin 8) is grounded through the parallel resistor R56 and capacitor C94 respectively, the OUTS pin (pin 10), the OUT1 pin (pin 11) and the OUT2 pin (pin 12) of the negative linear voltage stabilizing chip U12 are electrically connected with the signal acquisition circuit 309 through the inductor L7, and are further grounded through the inductor L7 and the capacitor C93 in sequence, and are further grounded through the capacitor C91 and the capacitor C92, and are used to provide the bipolar power supply voltage -2.5V voltage AVSS for the signal acquisition circuit.

[0054] As shown in Figure 12 The third voltage stabilizing circuit comprises: a linear voltage stabilizing chip U10 (model number GM1200ACPZ), the IN pin (pin 1), the IN1 pin (pin 2), the PGFB pin (pin 6) and the EN / UV pin (pin 3) of the linear voltage stabilizing chip U10 are electrically connected with the drain of the field effect transistor M4 through the inductor L3, and are further grounded through the inductor L3 and the capacitor C76 in sequence, and are further grounded through the capacitor C77 and the capacitor C78 respectively; the ILIM pin (pin 5) of the linear voltage stabilizing chip U10 is grounded through the resistor R54, the two GND pins (pin 8 and pin 11) are grounded, and the SET pin (pin 7) is grounded through the parallel resistor R55 and capacitor C82 respectively; the OUTS pin (pin 9) and the OUT pin (pin 10) of the linear voltage stabilizing chip U10 are electrically connected with the signal acquisition circuit 309 through the inductor L4, and are further grounded through the inductor L4 and the capacitor C81 in sequence, and are further grounded through the capacitor C79 and the capacitor C80, and are used to provide the bipolar power supply voltage +2.5V voltage AVDD for the signal acquisition circuit.

[0055] In the scheme, as Figure 13As shown, the control circuit 310 comprises a master control chip U13, the master control chip U13 adopts STM32H743IIK6, the PA0 pin, the PA1 pin, the PA2 pin, the PA3 pin, the PE11 pin, the PE12 pin, the PE13 pin, the PE14 pin, the PC10 pin and the PC11 pin of the master control chip U13 are electrically connected with the audio generation circuit; the PE4 pin, the PE5 pin, the PE3 pin, the PE6 pin, the PE2 pin, the PB8 pin, the PB9 pin and the PE1 pin of the master control chip U13 are electrically connected with the audio driving circuit; the PB3 pin, the PA15 pin, the PB5 pin, the PG9 pin, the PG13 pin, the PC13 pin, the PI8 pin, the PI7 pin, the PC9 pin and the PI9 pin of the master control chip U13 are electrically connected with the signal acquisition circuit; the PB14 pin, the PB15 pin, the PG11 pin, the PB4 pin, the PC1 pin, the PD7 pin, the PA7 pin and the PD8 pin of the master control chip U13 are electrically connected with the storage circuit; the PB11 pin, the PB12 pin, the PD6 pin and the PD5 pin of the master control chip U13 are electrically connected with the communication circuit; the PA9 pin, the PA10 pin, the PA13 pin and the PA14 pin of the master control chip U13 are electrically connected with the debugging printing interface; the VDDA pin, the VBAT pin, the VREF+ pin and the VDD1-VDD14 pins of the master control chip U13 are connected with the second power supply voltage VCC_3.3V, the VSSA pin, the VREF- pin and the VSS1-VSS37 pins of the master control chip U13 are grounded, the BOOT0 pin of the master control chip U13 is grounded through the resistor R67, the VCAP1 pin is grounded through the capacitor C14, the VCAP2 pin is grounded through the capacitor C17, the PDR_ON pin is grounded through the resistor R68, the NRST pin of the master control chip U13 is electrically connected with the pin 2 of the micro switch K1 (model KMR221NGLFS), is also connected with the second power supply voltage VCC_3.3V through the resistor R2, and is also grounded through the capacitor C16, the pin 1 and the pin 4 of the micro switch K1 are grounded, and the PH0 pin and the PH1 pin of the master control chip U13 are connected with the crystal oscillator circuit.

[0056] In the scheme, as Figure 10As shown, the audio generation circuit includes: an audio generation chip U2 (model ESP32-C3), the 3V3 pin (pin 1) of the audio generation chip U2 is electrically connected to the drain of the field effect transistor M1 to access the 3.3V voltage VCC2_3V3; the EN pin (pin 2) of the audio generation chip U2 is electrically connected to the drain of the field effect transistor M1 through the resistor R74, is also electrically connected to the pin 2 of the micro switch K4 (model KMR221NGLFS), and is grounded through the capacitor C106; the pin 1 and the pin 4 of the micro switch K4 are grounded; the IO6 pin (pin 5) of the audio generation chip U2 is electrically connected to the PE12 pin of the master control chip U13, and the IO7 pin (pin 6) is electrically connected to the PE14 pin of the master control chip U13; the IO8 pin (pin 7) of the audio generation chip U2 is electrically connected to the PA0 pin of the master control chip U13, and is also electrically connected to the drain of the field effect transistor M1 through the resistor R75; the IO9 pin (pin 8) of the audio generation chip U2 is electrically connected to the PA1 pin of the master control chip U13, and is also electrically connected to the pin 3 of the audio source interface J2 (i.e. the audio source interface 304); the IO10 pin (pin 10) of the audio generation chip U2 is electrically connected to the PE11 pin of the master control chip U13; the RXD0 pin (pin 11) and the TXD0 pin (pin 12) of the audio generation chip U2 are respectively electrically connected to the pin 1 and the pin 2 of the audio source interface J2, the audio source interface J2 is a USB communication interface or a serial communication interface, and the pin 4 is grounded; the IO3 pin (pin 15) of the audio generation chip U2 is electrically connected to the PA2 pin of the master control chip U13, the IO2 pin (pin 15) is electrically connected to the PE13 pin of the master control chip U13, the IO1 pin (pin 17) is electrically connected to the PC11 pin of the master control chip U13, and the IO0 pin (pin 18) is electrically connected to the PC10 pin of the master control chip U13; all GND pins (pin 9, pin 19, pin 20, pin 21, pin 22, pin 23, pin 24, pin 25, pin 26, pin 27) of the audio generation chip U2 are grounded.

[0057] In the present scheme, as Figure 9As shown, the audio drive circuit includes: an audio drive chip U7 (model WM8978), the LRC pin (pin 7) of the audio drive chip U7 is electrically connected with the PE4 pin of the master control chip U13, the BCLK pin (pin 8) is electrically connected with the PE5 pin of the master control chip U13, the ADCDAT pin (pin 9) is electrically connected with the PE3 pin of the master control chip U13, the DACDAT pin (pin 10) is electrically connected with the PE6 pin of the master control chip U13, and the MCLK pin (pin 11) is electrically connected with the PE2 pin of the master control chip U13; the SCLK pin (pin 16) of the audio drive chip U7 is electrically connected with the PB8 pin of the master control chip U13, and is also connected with the 3.3V voltage VCC1_3V3 through the resistance R23; the SDIN pin (pin 17) of the audio drive chip U7 is electrically connected with the PB9 pin of the master control chip U13, and is also connected with the 3.3V voltage VCC1_3V3 through the resistance R24; the MODE pin (pin 18) of the audio drive chip U7 is grounded through the resistance R27; the EP pin (pin 33), the DGND pin (pin 12), the SPKGND pin (pin 24) and the AGND pin (pin 28) of the audio drive chip U7 are all grounded, and the resistance R28 is connected between the DGND pin (pin 12) and the SPKGND pin (pin 24); the VMID pin (pin 27) of the audio drive chip U7 is grounded through the capacitor C103; the ROUT1 pin (pin 29) of the audio drive chip U7 is electrically connected with the earphone interface J6 (i.e. the earphone interface 307) through the capacitor C43, the LOUT1 pin (pin 30) is electrically connected with the earphone interface J6 through the capacitor C44, and the LOUT1 pin (pin 30) is also electrically connected with the signal acquisition circuit 309 through the capacitor C44 and the resistance R25, for sending a synchronization signal; the SPKVDD pin (pin 26) and the AVDD pin (pin 31) of the audio drive chip U7 are both electrically connected with the VOUT pin (pin 5) of the linear voltage stabilizer U8; the SPKVDD pin (pin 26) of the audio drive chip U7 is grounded through the parallel capacitor C36 and capacitor C41 respectively, and the AVDD pin (pin 31) is grounded through the parallel capacitor C37 and capacitor C42 respectively, for providing the 3.3V stabilized power supply voltage VCC1_3V3A for the audio drive chip U7; the DBVDD pin (pin 14) and the DCVDD pin (pin 13) of the audio drive chip U7 are both electrically connected with the drain of the field effect transistor M2, for providing the 3.3V voltage VCC1_3V3 for the audio drive chip U7.

[0058] In the scheme, the 8 EEG electrodes 101 are arranged from front to back on the EEG cap 100, and the EEG acquisition protection circuit is also integrated in the shell 301, and the 8 EEG electrodes 101 are electrically connected with the signal acquisition circuit 309 through the signal acquisition interface 308 and the EEG acquisition protection circuit.

[0059] As shown in FIG. 6, the EEG collection protection circuit includes an ESD protection circuit D6, an ESD protection circuit D7, and an ESD protection circuit D8. Figure 14 As shown in FIG. 6, the EEG collection protection circuit includes an ESD protection circuit D6, an ESD protection circuit D7, and an ESD protection circuit D8.

[0060] Pin 2 of the ESD protection circuit D6 is connected to a -2.5V voltage AVSS and also grounded through a capacitor C99, pin 3 of the ESD protection circuit D6 receives a reference signal EEG_SRB1 through a signal collection interface J8 and is also electrically connected to the signal collection circuit through a resistor R40 to output the reference signal SRB1, pin 4 of the ESD protection circuit D6 receives a brain electrical signal EEG_IN2_P sensed by a second brain electrical electrode through the signal collection interface J8 and is also electrically connected to the signal collection circuit through a resistor R33 to output the brain electrical signal IN2_P, pin 5 of the ESD protection circuit D6 is connected to a +2.5V voltage AVDD and also grounded through a capacitor C96, and pin 6 of the ESD protection circuit D6 receives a brain electrical signal EEG_IN1_P sensed by a first brain electrical electrode through the signal collection interface J8 and is also electrically connected to the signal collection circuit through a resistor R32 to output the brain electrical signal IN1_P.

[0061] Pin 1 of the ESD protection circuit D7 receives a brain electrical signal EEG_IN3_P sensed by a third brain electrical electrode through the signal collection interface J8 and is also electrically connected to the signal collection circuit through a resistor R34 to output the brain electrical signal IN3_P, pin 2 of the ESD protection circuit D7 is connected to a -2.5V voltage AVSS and also grounded through a capacitor C100, pin 3 of the ESD protection circuit D7 receives a brain electrical signal EEG_IN4_P sensed by a fourth brain electrical electrode through the signal collection interface J8 and is also electrically connected to the signal collection circuit through a resistor R35 to output the brain electrical signal IN4_P, pin 4 of the ESD protection circuit D7 receives a brain electrical signal EEG_IN5_P sensed by a fifth brain electrical electrode through the signal collection interface J8 and is also electrically connected to the signal collection circuit through a resistor R36 to output the brain electrical signal IN5_P, pin 5 of the ESD protection circuit D7 is connected to a +2.5V voltage AVDD and also grounded through a capacitor C97, and pin 6 of the ESD protection circuit D7 receives a brain electrical signal EEG_IN6_P sensed by a sixth brain electrical electrode through the signal collection interface J8 and is also electrically connected to the signal collection circuit through a resistor R37 to output the brain electrical signal IN6_P.

[0062] Pin 1 of the ESD protection circuit D8 receives the EEG signal EEG_IN7_P induced by the seventh EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through resistor R38 to output the EEG signal IN7_P. Pin 2 of the ESD protection circuit D8 is connected to a -2.5V voltage AVSS and is also grounded through capacitor C101. Pin 3 of the ESD protection circuit D8 receives the EEG signal EEG_IN8_P induced by the eighth EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through resistor R39 to output the EEG signal IN8_P. Pin 4 of the ESD protection circuit D8 receives the bias signal EEG_BIAS through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through resistor R41 to output the bias signal BIAS. Pin 5 of the ESD protection circuit D8 is connected to a +2.5V voltage AVDD and is also grounded through capacitor C98.

[0063] like Figure 15 As shown, the signal acquisition circuit 309 includes: a signal acquisition chip U9 (model ADS1299-4PAG). The SRB1 pin (pin 17) of the signal acquisition chip U9 is connected to the reference signal SRB1; the IN1P pin (pin 16) is connected to the EEG signal IN1_P; the IN2P pin (pin 14) is connected to the EEG signal IN2_P; the IN3P pin (pin 12) is connected to the EEG signal IN3_P; the IN4P pin (pin 10) is connected to the EEG signal IN4_P; the IN5P pin (pin 8) is connected to the EEG signal IN5_P; the IN6P pin (pin 6) is connected to the EEG signal IN6_P; the IN7P pin (pin 4) is connected to the EEG signal IN7_P; and the IN8P pin (pin 2) is connected to the EEG signal IN8_P. A capacitor C55 and a resistor R49 are connected in parallel between the BIASINV pin (pin 61) and the BIASIOUT pin (pin 62) of the signal acquisition chip U9, and then connected through a resistor R5. The bias signal BIAS is connected to the signal acquisition chip U9. The VCAP1 pin (pin 28) is connected to the -2.5V voltage AVSS through capacitor C67, the VCAP2 pin (pin 30) is connected to the -2.5V voltage AVSS through capacitor C59, the VCAP3 pin (pin 55) is connected to the -2.5V voltage AVSS through capacitors C60 and C61 connected in parallel, and the VCAP4 pin (pin 26) is connected to the -2.5V voltage AVSS through capacitor C62. The RESV1 pin (pin 31) and the three DGND pins (pins 33, 49 and 51) of the signal acquisition chip U9 are all grounded. The VREFP pin (pin 24) of the signal acquisition chip U9 is connected to the reference voltage VREFP, the VREFN pin (pin 25) is connected to the -2.5V voltage AVSS, and capacitors C56 and C57 are connected in parallel between the VREFP pin (pin 24) and the VREFN pin (pin 25).

[0064] The GPIO1 pin (pin 42) of the signal acquisition chip U9 is grounded through the resistor R47, the GPIO2 pin (pin 44) is grounded through the resistor R46, the GPIO3 pin (pin 45) is grounded through the resistor R45, the GPIO4 pin (pin 46) is grounded through the resistor R44, and the CLKSEL pin (pin 52) is grounded through the resistor R48.

[0065] The CLK pin (pin 37) of the signal acquisition chip U9 is electrically connected to the PC9 pin of the master control chip U13, the pin (pin 35) is electrically connected to the PI7 pin of the master control chip U13, the pin (pin 36) is electrically connected to the PI8 pin of the master control chip U13, the START pin (pin 38) is electrically connected to the PC13 pin of the master control chip U13, the pin (pin 47) is electrically connected to the PG13 pin of the master control chip U13, the DOUT pin (pin 43) is electrically connected to the PG9 pin of the master control chip U13, and the DIN pin (pin 34) is electrically connected to the PB5 pin of the master control chip U13, the pin (pin 39) is electrically connected to the PA15 pin of the master control chip U13, and the SCLK pin (pin 40) is electrically connected to the PB3 pin of the master control chip U13.

[0066] The two DVDD pins (pin 48 and pin 50) of the signal acquisition chip U9 are connected to the filtered voltage DVDD_33 and are also grounded through the capacitor C52 and the capacitor C53, respectively; all the AVSS pins (pin 20, pin 23, pin 32, pin 58 and pin 57) and the AVSS1 pin (pin 53) of the signal acquisition chip U9 are connected to the-2.5V voltage AVSS, and all the AVDD pins (pin 19, pin 21, pin 22, pin 59 and pin 56) and the AVSS1 pin (pin 54) are connected to the +2.5V voltage AVDD.

[0067] As Figure 11As shown, the storage circuit 311 includes: a storage chip J7 (model TF-01A), a D0 pin (pin 7) of the storage chip J7 is electrically connected with a PB14 pin of the master control chip U13, and is also connected with a 3.3V voltage VCC3_3V3 through a resistor R66; a D1 pin (pin 8) of the storage chip J7 is electrically connected with a PB15 pin of the master control chip U13, and is also connected with the 3.3V voltage VCC3_3V3 through a resistor R65; a D2 pin (pin 1) of the storage chip J7 is electrically connected with a PG11 pin of the master control chip U13, and is also connected with the 3.3V voltage VCC3_3V3 through a resistor R64; a D3 pin (pin 2) of the storage chip J7 is electrically connected with a PB4 pin of the master control chip U13, and is also connected with the 3.3V voltage VCC3_3V3 through a resistor R63; a CLK pin (pin 5) of the storage chip J7 is electrically connected with a PC1 pin of the master control chip U13; a CMD pin (pin 3) of the storage chip J7 is electrically connected with a PD7 pin of the master control chip U13, and is also connected with the 3.3V voltage VCC3_3V3 through a resistor R62; a CD pin (pin 9) of the storage chip J7 is electrically connected with a PD8 pin of the master control chip U13, and is also connected with a second power voltage VCC_3.3V through a resistor R31; a VDD pin (pin 4) of the storage chip J7 is connected with the 3.3V voltage VCC3_3V3; a VSS pin (pin 6), an NC1 (pin 11), an NC2 (pin 12), an NC3 (pin 13) and a G# pin (pin 10) of the storage chip J7 are all grounded;

[0068] As Figure 8As shown, the communication circuit 313 includes a USB-to-serial chip U6 (model CH343) and a Type-C interface U5; the VIO pin (pin 1) and VDDS pin of the USB-to-serial chip U6 are both connected to the second power supply voltage VCC_3.3V and are also grounded through capacitor C35; the GND pin (pin 2) and EP pin (pin 17) of the USB-to-serial chip U6 are grounded; the TXD pin (pin 4) of the USB-to-serial chip U6 is electrically connected to the PD6 pin of the main control chip U13 through resistor R18, and the RXD pin (pin 5) is electrically connected to the PD5 pin of the main control chip U13 through resistor R19; the V3 pin (pin 5) of the USB-to-serial chip U6 is also grounded. 6) The second power supply voltage VCC_3.3V is connected and grounded through capacitor C33; the UD+ pin (pin 7) of the USB to serial port chip U6 is electrically connected to the DP1 and DP2 pins of the Type-C interface U5 through resistor R58, and the UD- pin (pin 8) is electrically connected to the DN1 and DN2 pins of the Type-C interface U5 through resistor R59; the VBUS pin (pin 9) of the USB to serial port chip U6 is electrically connected to the first protection circuit; the DP1 and DP2 pins of the Type-C interface U5 are grounded through electrostatic protection diode D4, the DN1 and DN2 pins are grounded through electrostatic protection diode D3, and the GND pin is grounded.

[0069] like Figure 16 As shown, the system operation indicator circuit 312 includes a resistor R16, a light-emitting diode D1, and a transistor Q2. The base of the transistor Q2 is electrically connected to the PD10 pin of the main control chip U13, the emitter is grounded, and the collector is electrically connected to the cathode of the light-emitting diode D1. The anode of the light-emitting diode D1 is connected to a 3.3V voltage VCC3_3V3 through the resistor R16.

[0070] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of the present invention is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but all such changes and modifications fall within the scope of protection of the present invention.

Claims

1. An auditory evoked potential based multi-channel electroencephalogram signal acquisition system, characterized in that, It includes a brain electrical cap and earphone for the collector to wear, a plurality of brain electrical electrodes are installed on the brain electrical cap, and a brain electrical collection device is installed on the brain electrical cap, the brain electrical collection device includes a shell, a power supply interface, a power supply circuit, an audio source interface, an audio generation circuit, an audio drive circuit, an earphone interface, a signal collection interface, a signal collection circuit, a control circuit, a storage circuit, a system operation indication circuit and a communication circuit are integrated in the shell; The power supply circuit is used for accessing an external power supply through the power supply interface, and converting the external power supply into a power supply voltage to power the control circuit, the audio generation circuit, the audio drive circuit, the signal collection circuit, the storage circuit, the system operation indication circuit and the communication circuit; The control circuit is in communication connection with the upper computer through the communication circuit, the audio source interface, the audio generation circuit and the control circuit are electrically connected in sequence, and the control circuit is used for controlling to send a trigger signal to the audio generation circuit after receiving a brain electrical signal collection instruction through the communication circuit; The audio generation circuit and the audio drive circuit are electrically connected, the earphone interface, the audio drive circuit and the control circuit are electrically connected in sequence, the audio drive circuit is used for receiving the audio signal and generating an audio drive signal containing the audio signal based on the audio signal, and the control circuit is used for controlling the audio drive circuit to output the audio drive signal of the set time length through the earphone interface, so that the earphone outputs the sound stimulation of the set time length to act on the collector; The audio drive circuit and the signal collection circuit are electrically connected, the brain electrical electrode, the signal collection interface, the signal collection circuit and the control circuit are electrically connected in sequence, the audio drive circuit is used for generating a synchronization signal based on the audio drive signal and transmitting the synchronization signal to the signal collection circuit, and the signal collection circuit is used for collecting the multi-channel brain electrical signals sensed by the plurality of brain electrical electrodes through the signal collection interface and transmitting the multi-channel brain electrical signals to the control circuit; The storage circuit and the communication circuit are both electrically connected with the control circuit, and the control circuit is used for storing the multi-channel brain electrical signals of the collector in the storage circuit and uploading the multi-channel brain electrical signals to the upper computer through the communication circuit; The system operation indication circuit is electrically connected with the control circuit, and the control circuit is used for controlling the system operation indication circuit to light up when the system runs normally; The power supply circuit includes a power supply main switch circuit, a first DC-DC circuit, a first protection circuit, a first voltage stabilizing circuit, a first switch circuit, a second switch circuit, a third switch circuit, a fourth switch circuit, a filter circuit, a second DC-DC circuit, a second voltage stabilizing circuit and a third voltage stabilizing circuit; The input end of the power supply main switch circuit is electrically connected with the power supply interface, the output end of the power supply main switch circuit is electrically connected with the control circuit through the first DC-DC circuit, the power supply main switch circuit is used for controlling the control circuit to be turned on and adjusting the first power supply voltage based on the input voltage, and the first DC-DC circuit is used for converting the first power supply voltage into the second power supply voltage and providing the second power supply voltage for the control circuit; The output end of the power supply master switch circuit is electrically connected with the communication circuit through the first protection circuit for providing VBUS voltage for the communication circuit, and the output end of the first DC-DC circuit is electrically connected with the communication circuit for providing second power supply voltage for the communication circuit; The output end of the power supply master switch circuit is electrically connected with the audio drive circuit through the first voltage stabilizing circuit, the first voltage stabilizing circuit is used for stabilizing the first power supply voltage as a stabilized power supply voltage and providing the stabilized power supply voltage for the audio drive circuit, and the output end of the first DC-DC circuit is electrically connected with the audio drive circuit through the first switch circuit for providing second power supply voltage for the audio drive circuit; The output end of the first DC-DC circuit is electrically connected with the audio generation circuit through the second switch circuit for providing second power supply voltage for the audio generation circuit; The output end of the first DC-DC circuit is electrically connected with the storage circuit through the third switch circuit for providing second power supply voltage for the storage circuit; The output end of the first DC-DC circuit is electrically connected with the input end of the fourth switch circuit, the output end of the fourth switch circuit is electrically connected with the signal acquisition circuit through the filtering circuit for providing filtered voltage for the signal acquisition circuit, the output end of the fourth switch circuit is also electrically connected with the signal acquisition circuit through the second DC-DC circuit and the second voltage stabilizing circuit and also electrically connected with the signal acquisition circuit through the third voltage stabilizing circuit for providing bipolar power supply voltage for the signal acquisition circuit.

2. The multi-channel electroencephalogram signal acquisition system based on auditory evoked potential according to claim 1, wherein, The power supply on-off circuit comprises a total switch K3 and a power supply switch chip U4, a switch end of the total switch K3 is embedded on a shell, an IN pin of the power supply switch chip U4 is electrically connected with a power supply interface, is also electrically connected with a pin 2 of the total switch K3, is also grounded through a capacitor C30, an EN pin of the power supply switch chip U4 is electrically connected with a pin 3 of the total switch K3 through a resistor R14, is also grounded through a resistor R77, is also grounded through a capacitor C32, a GND pin and an EP pin of the power supply switch chip U4 are both grounded, The power supply on-off circuit comprises a total switch K3 and a power supply switch chip U4, a switch end of the total switch K3 is embedded on a shell, an IN pin of the power supply switch chip U4 is electrically connected with a power supply interface, is also electrically connected with a pin 2 of the total switch K3, is also grounded through a capacitor C30, an EN pin of the power supply switch chip U4 is electrically connected with a pin 3 of the total switch K3 through a resistor R14, is also grounded through a resistor R77, is also grounded through a capacitor C32, a GND pin and an EP pin of the power supply switch chip U4 are both grounded, The power supply on-off circuit comprises a total switch K3 and a power supply switch chip U4, a switch end of the total switch K3 is embedded on a shell, an IN pin of the power supply switch chip U4 is electrically connected with a power supply interface, is also electrically connected with a pin 2 of the total switch K3, is also grounded through a capacitor C30, an EN pin of the power supply switch chip U4 is electrically connected with a pin 3 of the total switch K3 through a resistor R14, is also grounded through a resistor R77, is also grounded through a capacitor C32, a GND pin and an EP pin of the power supply switch chip U4 The first DC-DC circuit comprises: a power management chip U1, two PVIN pins, an AVIN pin and an EN pin of the power management chip U1 are electrically connected with an OUT pin of a power switch chip U4, are also grounded through series-connected resistors R9 and R12, are also grounded through capacitors C105, C24 and C23, a FSW pin of the power management chip U1 is grounded through a resistor R12, a DEF pin is grounded through a resistor R11, and an SS / TR pin is grounded through a capacitor C29, two PGND pins, an AGND pin and an EP pin of the power management chip U1 are grounded, a FB pin of the power management chip U1 is grounded through a resistor R13, a VOS pin is grounded through series-connected resistors R10 and R13, three SW pins of the power management chip U1 output second power supply voltage VCC_3.3V through series-connected inductors L1 and L8, the inductors L1 and L8 are respectively grounded through capacitors C25, C26, C27 and C28, and the end of the inductor L8 away from the inductor L1 is respectively grounded through capacitors C108 and C107.

3. The multi-channel electroencephalogram signal acquisition system based on auditory evoked potential of claim 2, wherein, The first protection circuit comprises: a resistor R20 and a diode D5, one end of the resistor R20 is electrically connected with the OUT pin of the power switch chip U4, the other end is electrically connected with the cathode of the diode D5, the anode of the diode D5 is grounded, and the cathode is electrically connected with the communication circuit to provide VBUS voltage. The first voltage stabilizing circuit comprises a linear voltage stabilizer U8, a VIN pin of the linear voltage stabilizer U8 is electrically connected with an OUT pin of the power switch chip U4, is further grounded through a capacitor C45, and is further grounded through a capacitor C46, an EN pin of the linear voltage stabilizer U8 is electrically connected with the control circuit, a GND pin is grounded, a BP pin is grounded through a capacitor C49, a VOUT pin of the linear voltage stabilizer U8 is electrically connected with the audio drive circuit, is further grounded through a capacitor C47, and is further grounded through a capacitor C48, and is used for providing a 3.3V voltage stabilizing power supply voltage VCC1_3V3A for the audio drive circuit; The first switch circuit comprises a triode Q3 and a field effect transistor M2, a base of the triode Q3 is electrically connected with the control circuit, an emitter of the triode Q3 is grounded, a source of the field effect transistor M2 is electrically connected with an inductor L8 of the power management chip U1 through a resistor R21 to access the second power supply voltage VCC_3.3V, the source is further grounded through a capacitor C38, and the source is further electrically connected with a collector of the triode Q3 through a resistor R22, a gate of the field effect transistor M2 is electrically connected with the collector of the triode Q3, and a drain of the field effect transistor M2 is electrically connected with the audio drive circuit, is further grounded through a capacitor C39, and is further grounded through a capacitor C40, and is used for providing a 3.3V voltage VCC1_3V3 for the audio drive circuit; The second switch circuit comprises a triode Q1 and a field effect transistor M1, a base of the triode Q1 is electrically connected with the control circuit, an emitter of the triode Q1 is grounded, a source of the field effect transistor M1 is electrically connected with an inductor L8 of the power management chip U1 through a resistor R6 to access the second power supply voltage VCC_3.3V, the source is further grounded through a capacitor C18, and the source is further electrically connected with a collector of the triode Q1 through a resistor R7, a gate of the field effect transistor M1 is electrically connected with the collector of the triode Q1, and a drain of the field effect transistor M1 is electrically connected with the audio generation chip generation circuit, is further grounded through a capacitor C19, and is further grounded through a capacitor C20, and is used for providing a 3.3V voltage VCC2_3V3 for the audio generation circuit; The third switch circuit comprises a triode Q4 and a field effect transistor M3, a base of the triode Q4 is electrically connected with the control circuit, an emitter of the triode Q4 is grounded, a source of the field effect transistor M3 is electrically connected with an inductor L8 of the power management chip U1 through a resistor R29 to access the second power supply voltage VCC_3.3V, the source is further grounded through a capacitor C50, and the source is further electrically connected with a collector of the triode Q4 through a resistor R30, a gate of the field effect transistor M3 is electrically connected with the collector of the triode Q4, and a drain of the field effect transistor M3 is electrically connected with the storage circuit, is further grounded through a capacitor C95, and is further grounded through a capacitor C51, and is used for providing a 3.3V voltage VCC3_3V3 for the storage circuit; The fourth switch circuit comprises a transistor Q5 and a field effect transistor M4, the base of the transistor Q5 is electrically connected with the control circuit, the emitter of the transistor Q5 is grounded, the source of the field effect transistor M4 is electrically connected with the inductor L8 of the power management chip U1 through the resistor R52 to access the second power supply voltage VCC_3.3V, the source is also grounded through the capacitor C71, and the source is also electrically connected with the collector of the transistor Q5 through the resistor R53; the gate of the field effect transistor M4 is electrically connected with the collector of the transistor Q5, the drain of the field effect transistor M4 is electrically connected with the filter circuit, the second DC-DC circuit and the third voltage stabilizing circuit respectively, and is also grounded through the capacitor C72, and is used to provide the 3.3V voltage VCC4_3V3; The filter circuit comprises an inductor L2, a capacitor C73, a capacitor C74 and a capacitor C75, one end of the inductor L2 is electrically connected with the drain of the field effect transistor M4, is also grounded through the capacitor C73, and is also grounded through the capacitor C74; the other end of the inductor L2 is electrically connected with the signal acquisition circuit, and is also grounded through the capacitor C75, and is used to provide the filtered voltage DVDD_33 for the signal acquisition circuit; The second DC-DC circuit comprises a switching voltage stabilizer chip U11, the IN pin of the switching voltage stabilizer chip U11 is electrically connected with the drain of the field effect transistor M4 through the inductor L5, is also grounded through the inductor L5 and the capacitor C84 connected in series, is also grounded through the capacitor C85, and is also grounded through the capacitor C86; the GND pin of the switching voltage stabilizer chip U11 is grounded, the capacitor C83 is connected between the CFLY- pin and the CFLY+ pin of the switching voltage stabilizer chip U11, and the OUT pin of the switching voltage stabilizer chip U11 is electrically connected with the second voltage stabilizing circuit through the inductor L6, and is also grounded through the capacitor C87 and the capacitor C88 respectively; The second voltage stabilizing circuit comprises a negative linear voltage stabilizing chip U12, the IN1 pin, the IN2 pin, the EP pin, the PGFB pin and the EN / UV pin of the negative linear voltage stabilizing chip U12 are electrically connected with the inductor L6, and are also grounded through the capacitor C89 and the capacitor C90 respectively; the ILIM pin of the negative linear voltage stabilizing chip U12 is grounded through the resistor R57, the GND pin is grounded, the SET pin is grounded through the parallel resistor R56 and the capacitor C94, the OUTS pin, the OUT1 pin and the OUT2 pin of the negative linear voltage stabilizing chip U12 are all electrically connected with the signal acquisition circuit through the inductor L7, are also grounded through the inductor L7 and the capacitor C93 in sequence, are also grounded through the capacitor C91, are also grounded through the capacitor C92, and are used to provide the bipolar power supply voltage -2.5V voltage AVSS for the signal acquisition circuit. The third voltage stabilizing circuit comprises a linear voltage stabilizing chip U10, an IN pin, an IN1 pin, a PGFB pin and an EN / UV pin of the linear voltage stabilizing chip U10 are electrically connected with a drain electrode of a field effect transistor M4 through an inductor L3, are sequentially grounded through the inductor L3 and a capacitor C76, are respectively grounded through a capacitor C77 and a capacitor C78, an ILIM pin of the linear voltage stabilizing chip U10 is grounded through a resistor R54, two GND pins are grounded, SET pins are respectively grounded through a parallel resistor R55 and a capacitor C82, OUTS and OUT pins of the linear voltage stabilizing chip U10 are electrically connected with the signal acquisition circuit through an inductor L4, are sequentially grounded through the inductor L4 and a capacitor C81, are grounded through a capacitor C79, are grounded through a capacitor C80, and are used for providing a +2.5V voltage AVDD in a bipolar power supply voltage for the signal acquisition circuit.

4. The multi-channel electroencephalogram signal acquisition system based on auditory evoked potential of claim 3, wherein, The control circuit comprises a main control chip U13, the main control chip U13 adopts an STM32H743IIK6, PA0, PA1, PA2, PA3, PE11, PE12, PE13, PE14, PC10 and PC11 pins of the main control chip U13 are electrically connected with the audio generation circuit; PE4, PE5, PE3, PE6, PE2, PB8, PB9 and PE1 pins of the main control chip U13 are electrically connected with the audio driving circuit; PB3, PA15, PB5, PG9, PG13, PC13, PI8, PI7, PC9 and PI9 pins of the main control chip U13 are electrically connected with the signal acquisition circuit; PB14, PB15, PG11, PB4, PC1, PD7, PA7 and PD8 pins of the main control chip U13 are electrically connected with the storage circuit; PB11, PB12, PD6 and PD5 pins of the main control chip U13 are electrically connected with the communication circuit; PA9, PA10, PA13 and PA14 pins of the main control chip U13 are electrically connected with the debugging print interface; The VDDA pin, VBAT pin, VREF+ pin and VDD1-VDD14 pins of the master control chip U13 are connected to the second power supply voltage VCC_3.3V, the VSSA pin, VREF- pin and VSS1-VSS37 pins of the master control chip U13 are grounded, the BOOT0 pin of the master control chip U13 is grounded through the resistor R67, the VCAP1 pin is grounded through the capacitor C14, the VCAP2 pin is grounded through the capacitor C17, the PDR_ON pin is grounded through the resistor R68, the NRST pin of the master control chip U13 is electrically connected with the pin 2 of the micro switch K1, is also connected to the second power supply voltage VCC_3.3V through the resistor R2, and is also grounded through the capacitor C16, the pin 1 and pin 4 of the micro switch K1 are grounded, and the PH0 pin and PH1 pin of the master control chip U13 are connected with the crystal oscillator circuit.

5. The multi-channel electroencephalogram signal acquisition system based on auditory evoked potential of claim 4, wherein, The audio generation circuit comprises an audio generation chip U2, the 3V3 pin of the audio generation chip U2 is electrically connected with the drain electrode of the field effect transistor M1 to connect the 3.3V voltage VCC2_3V3, the EN pin of the audio generation chip U2 is electrically connected with the drain electrode of the field effect transistor M1 through the resistor R74, is also electrically connected with the pin 2 of the micro switch K4, and is also grounded through the capacitor C106, the pin 1 and pin 4 of the micro switch K4 are grounded, the IO6 pin of the audio generation chip U2 is electrically connected with the PE12 pin of the master control chip U13, the IO7 pin is electrically connected with the PE14 pin of the master control chip U13, the IO8 pin of the audio generation chip U2 is electrically connected with the PA0 pin of the master control chip U13 and is also electrically connected with the drain electrode of the field effect transistor M1 through the resistor R75, the IO9 pin of the audio generation chip U2 is electrically connected with the PA1 pin of the master control chip U13 and is also electrically connected with the pin 3 of the audio source interface J2, the IO10 pin of the audio generation chip U2 is electrically connected with the PE11 pin of the master control chip U13, the RXD0 pin and TXD0 pin of the audio generation chip U2 are respectively electrically connected with the pin 1 and pin 2 of the audio source interface J2, the audio source interface J2 is a USB communication interface or a serial communication interface, and the pin 4 is grounded, the IO3 pin of the audio generation chip U2 is electrically connected with the PA2 pin of the master control chip U13, the IO2 pin is electrically connected with the PE13 pin of the master control chip U13, the IO1 pin is electrically connected with the PC11 pin of the master control chip U13, and the IO0 pin is electrically connected with the PC10 pin of the master control chip U13, and all the GND pins of the audio generation chip U2 are grounded.

6. The multi-channel electroencephalogram signal acquisition system based on auditory evoked potential of claim 5, wherein, The audio drive circuit comprises an audio drive chip U7, an LRC pin of the audio drive chip U7 is electrically connected with a PE4 pin of a master control chip U13, a BCLK pin is electrically connected with a PE5 pin of the master control chip U13, an ADCDAT pin is electrically connected with a PE3 pin of the master control chip U13, a DACDAT pin is electrically connected with a PE6 pin of the master control chip U13, and a MCLK pin is electrically connected with a PE2 pin of the master control chip U13, a SCLK pin of the audio drive chip U7 is electrically connected with a PB8 pin of the master control chip U13 and is also connected with a 3.3V voltage VCC1_3V3 through a resistor R23, a SDIN pin of the audio drive chip U7 is electrically connected with a PB9 pin of the master control chip U13 and is also connected with the 3.3V voltage VCC1_3V3 through a resistor R24, a MODE pin of the audio drive chip U7 is grounded through a resistor R27, an EP pin, a DGND pin, a SPKGND pin and an AGND pin of the audio drive chip U7 are all grounded, and a resistor R28 is connected between the DGND pin and the SPKGND pin, and a VMID pin of the audio drive chip U7 is grounded through a capacitor C103; A ROUT1 pin of the audio drive chip U7 is electrically connected with an earphone interface J6 through a capacitor C43, a LOUT1 pin is electrically connected with the earphone interface J6 through a capacitor C44, and the LOUT1 pin is also electrically connected with a signal acquisition circuit through the capacitor C44 and a resistor R25, for sending a synchronous signal; A SPKVDD pin and an AVDD pin of the audio drive chip U7 are both electrically connected with a VOUT pin of a linear voltage stabilizer U8, the SPKVDD pin of the audio drive chip U7 is grounded through a capacitor C36 and a capacitor C41 in parallel, and the AVDD pin is grounded through a capacitor C37 and a capacitor C42 in parallel, for providing a 3.3V stabilized power supply voltage VCC1_3V3A for the audio drive chip U7; A DBVDD pin and a DCVDD pin of the audio drive chip U7 are both electrically connected with a drain of a field effect transistor M2, for providing a 3.3V voltage VCC1_3V3 for the audio drive chip U7.

7. The multi-channel electroencephalogram signal acquisition system based on auditory evoked potential of claim 4, wherein, The EEG cap is provided with eight EEG electrodes in a front-to-back direction, and an EEG acquisition protection circuit is integrated in the shell, and the eight EEG electrodes are electrically connected with a signal acquisition circuit through a signal acquisition interface and the EEG acquisition protection circuit.

8. The multi-channel electroencephalogram signal acquisition system based on auditory evoked potential of claim 7, wherein, The EEG acquisition protection circuit comprises ESD protection circuits D6, D7 and D8. Pin 2 of the ESD protection circuit D6 is connected to a -2.5V voltage AVSS, and also grounded through a capacitor C99, pin 3 of the ESD protection circuit D6 receives a reference signal EEG_SRB1 through the signal acquisition interface J8, and also is electrically connected with the signal acquisition circuit through a resistor R40 to output the reference signal SRB1, pin 4 of the ESD protection circuit D6 receives a brain electrical signal EEG_IN2_P sensed by a second brain electrical electrode through the signal acquisition interface J8, and also is electrically connected with the signal acquisition circuit through a resistor R33 to output the brain electrical signal IN2_P, pin 5 of the ESD protection circuit D6 is connected to a +2.5V voltage AVDD, and also grounded through a capacitor C96, pin 6 of the ESD protection circuit D6 receives a brain electrical signal EEG_IN1_P sensed by a first brain electrical electrode through the signal acquisition interface J8, and also is electrically connected with the signal acquisition circuit through a resistor R32 to output the brain electrical signal IN1_P; Pin 1 of the ESD protection circuit D7 receives a brain electrical signal EEG_IN3_P sensed by a third brain electrical electrode through the signal acquisition interface J8, and also is electrically connected with the signal acquisition circuit through a resistor R34 to output the brain electrical signal IN3_P, pin 2 of the ESD protection circuit D7 is connected to a -2.5V voltage AVSS, and also grounded through a capacitor C100, pin 3 of the ESD protection circuit D7 receives a brain electrical signal EEG_IN4_P sensed by a fourth brain electrical electrode through the signal acquisition interface J8, and also is electrically connected with the signal acquisition circuit through a resistor R35 to output the brain electrical signal IN4_P, pin 4 of the ESD protection circuit D7 receives a brain electrical signal EEG_IN5_P sensed by a fifth brain electrical electrode through the signal acquisition interface J8, and also is electrically connected with the signal acquisition circuit through a resistor R36 to output the brain electrical signal IN5_P, pin 5 of the ESD protection circuit D7 is connected to a +2.5V voltage AVDD, and also grounded through a capacitor C97, pin 6 of the ESD protection circuit D7 receives a brain electrical signal EEG_IN6_P sensed by a sixth brain electrical electrode through the signal acquisition interface J8, and also is electrically connected with the signal acquisition circuit through a resistor R37 to output the brain electrical signal IN6_P; The pin 1 of the ESD protection circuit D8 receives the brain electrical signal EEG_IN7_P sensed by the seventh brain electrical electrode through the signal collection interface J8, and is electrically connected with the signal collection circuit through the resistor R38 to output the brain electrical signal IN7_P. The pin 2 of the ESD protection circuit D8 is connected to the -2.5V voltage AVSS and is grounded through the capacitor C101. The pin 3 of the ESD protection circuit D8 receives the brain electrical signal EEG_IN8_P sensed by the eighth brain electrical electrode through the signal collection interface J8 and is electrically connected with the signal collection circuit through the resistor R39 to output the brain electrical signal IN8_P. The pin 4 of the ESD protection circuit D8 receives the bias signal EEG_BIAS through the signal collection interface J8 and is electrically connected with the signal collection circuit through the resistor R41 to output the bias signal BIAS. The pin 5 of the ESD protection circuit D8 is connected to the +2.5V voltage AVDD and is grounded through the capacitor C98.

9. The multi-channel electroencephalogram signal acquisition system based on auditory evoked potentials of claim 8, wherein, The signal collection circuit comprises a signal collection chip U9. The SRB1 pin of the signal collection chip U9 is connected to the reference signal SRB1. The IN1P pin is connected to the brain electrical signal IN1_P. The IN2P pin is connected to the brain electrical signal IN2_P. The IN3P pin is connected to the brain electrical signal IN3_P. The IN4P pin is connected to the brain electrical signal IN4_P. The IN5P pin is connected to the brain electrical signal IN5_P. The IN6P pin is connected to the brain electrical signal IN6_P. The IN7P pin is connected to the brain electrical signal IN7_P. The IN8P pin is connected to the brain electrical signal IN8_P. The BIASINV pin and the BIASOUT pin of the signal collection chip U9 are connected to the bias signal BIAS through the resistor R50 after being connected in parallel with the capacitor C55 and the resistor R49. The VCAP1 pin of the signal collection chip U9 is connected to the -2.5V voltage AVSS through the capacitor C67. The VCAP2 pin is connected to the -2.5V voltage AVSS through the capacitor C59. The VCAP3 pin is connected to the -2.5V voltage AVSS through the capacitor C60 and the capacitor C61 connected in parallel. The VCAP4 pin is connected to the -2.5V voltage AVSS through the capacitor C62. The RESV1 pin and the three DGND pins of the signal collection chip U9 are grounded. The VREFP pin of the signal collection chip U9 is connected to the reference voltage VREFP. The VREFN pin is connected to the -2.5V voltage AVSS. The capacitor C56 and the capacitor C57 are connected in parallel between the VREFP pin and the VREFN pin. The CLK pin of the signal acquisition chip U9 is electrically connected with the PC9 pin of the main control chip U13, The PIN pin is electrically connected with the PI7 pin of the main control chip U13, The START pin is electrically connected with the PC13 pin of the main control chip U13, The DOUT pin is electrically connected with the PG9 pin of the main control chip U13, and the DIN pin is electrically connected with the PB5 pin of the main control chip U13, The SCLK pin is electrically connected with the PB3 pin of the main control chip U13. The two DVDD pins of the signal collection chip U9 are connected to the filtered voltage DVDD_33 and are grounded through the capacitor C52 and the capacitor C53 respectively. All the AVSS pins and the AVSS1 pin of the signal collection chip U9 are connected to the -2.5V voltage AVSS. All the AVDD pins and the AVSS1 pin are connected to the +2.5V voltage AVDD.

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