Soft decoding method and system of rotary transformer, control platform and storage medium

Abstract

The invention discloses a soft decoding method and system for a rotary transformer, a control platform and a storage medium, and the method is based on a DSP chip and an FPGA chip, and comprises the steps: enabling the DSP chip to generate an enable signal, inputting the enable signal to the FPGA chip, and enabling the FPGA chip to generate a high-frequency excitation signal applied to the rotary transformer according to the enable signal; the DSP chip obtains a feedback signal of the rotary transformer and obtains an interrupt signal of the FPGA chip, the rotary transformer generates the feedback signal according to the high-frequency excitation signal, and the FPGA chip generates the interrupt signal according to the phase delay time caused by the rotary transformer; and the DSP chip obtains a resolver angle value and / or a speed value according to the feedback signal and the interrupt signal. Therefore, the FPGA chip is enabled by the DSP chip, and the high-frequency excitation signal applied to the rotary transformer is generated through the FPGA chip, so that the burden when the excitation signal is applied to the rotary transformer by the DSP chip is reduced, and the soft decoding speed and precision can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of soft decoding of rotary transformers, and in particular to a soft decoding method of a rotary transformer, a computer-readable storage medium, a soft decoding system of a rotary transformer, and a rotary transformer. Background Art

[0002] Resolvers are widely used in motor drive and electronic technology applications because of their high precision and strong anti-interference ability. The magnitude of their output voltage changes with the rotor angular displacement, and the voltage amplitude of the output winding is in a sine and cosine function relationship with the rotor angle. However, the decoding chip used with resolvers is expensive. Therefore, high-precision resolver soft decoding can not only save space in the design and manufacturing process, but also the cost of soft decoding technology is lower, which helps to reduce the overall cost of the product.

[0003] Then the problem with the related technology is that the DSP-based soft decoding requires the control part to sample and demodulate the resolver feedback signal while generating a high-frequency excitation signal, which imposes a large resource burden on the DSP and affects the DSP processing capability, thereby resulting in low soft decoding efficiency and low soft decoding accuracy. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first object of the present invention is to provide a soft decoding method for a rotary transformer, which can reduce the burden of a DSP chip when applying an excitation signal to the rotary transformer, and help improve the soft decoding speed and accuracy.

[0005] A second object of the present invention is to provide a computer-readable storage medium.

[0006] The third objective of the present invention is to provide a soft decoding system for a rotary transformer.

[0007] A fourth objective of the present invention is to provide a rotary transformer.

[0008] To achieve the above-mentioned purpose, an embodiment of the first aspect of the present invention proposes a soft decoding method for a rotary transformer, based on a DSP chip and an FPGA chip, the method comprising: generating an enable signal by the DSP chip, and inputting the enable signal to the FPGA chip, wherein the FPGA chip generates a high-frequency excitation signal applied to the rotary transformer according to the enable signal; obtaining a feedback signal of the rotary transformer by the DSP chip, and obtaining an interrupt signal of the FPGA chip, wherein the rotary transformer generates the feedback signal according to the high-frequency excitation signal, and the FPGA chip generates the interrupt signal according to the phase delay time caused by the rotary transformer; obtaining the rotary transformer angle value and / or speed value by the DSP chip according to the feedback signal and the interrupt signal.

[0009] According to the soft decoding method of the rotary transformer proposed in the embodiment of the present invention, the DSP chip generates an enable signal, and inputs the enable signal to the FPGA chip, wherein the FPGA chip generates a high-frequency excitation signal applied to the rotary transformer according to the enable signal, and then the DSP chip obtains the feedback signal of the rotary transformer and obtains the interrupt signal of the FPGA chip, wherein the rotary transformer generates a feedback signal according to the high-frequency excitation signal, the FPGA chip generates an interrupt signal according to the phase delay time caused by the rotary transformer, and the DSP chip obtains the rotary transformer angle value and / or speed value according to the feedback signal and the interrupt signal. Thus, the DSP chip enables the FPGA chip, and the high-frequency excitation signal applied to the rotary transformer is generated by the FPGA chip, thereby reducing the burden of the DSP chip when applying the excitation signal to the rotary transformer, which helps to improve the speed and accuracy of soft decoding.

[0010] In addition, the soft decoding method of the rotary transformer according to the above embodiment of the present invention may also have the following additional technical features:

[0011] According to an embodiment of the present invention, the feedback signal includes a sine signal and a cosine signal.

[0012] According to one embodiment of the present invention, the FPGA chip generates a high-frequency excitation signal applied to the rotary transformer according to the enable signal, including: the FPGA chip generates a high-frequency PWM signal according to the enable signal, and inputs the high-frequency PWM signal to the excitation signal amplification circuit; the excitation signal amplification circuit filters the high-frequency PWM signal and converts the high-frequency PWM signal into the high-frequency excitation signal.

[0013] According to an embodiment of the present invention, the excitation signal amplifying circuit includes a Boost voltage-boosting unit, an excitation amplifying pre-stage unit and an excitation power amplifying unit.

[0014] According to one embodiment of the present invention, the FPGA chip generates the interrupt signal according to the phase delay time caused by the rotary transformer, including: the FPGA chip records the peak moment and valley moment of the high-frequency excitation signal; the DSP chip records the peak moment and valley moment of the feedback signal and feeds back to the FPGA chip; the FPGA chip obtains the phase delay time according to the peak moment and valley moment of the high-frequency excitation signal and the peak moment and valley moment of the feedback signal.

[0015] According to one embodiment of the present invention, the obtaining of the resolver angle value and / or speed value includes: the DSP chip determines the peak sampling value and the valley sampling value of the sine signal and the cosine signal according to the interrupt signal; the DSP chip performs an inverse tangent calculation on the peak sampling value and the valley sampling value of the sine signal and the cosine signal to obtain the resolver angle value and / or speed value.

[0016] According to an embodiment of the present invention, the DSP chip obtains the feedback signal through a feedback signal sampler, wherein the feedback signal sampler includes a secondary side signal conditioning circuit.

[0017] To achieve the above-mentioned purpose, a computer-readable storage medium is proposed in an embodiment of the second aspect of the present invention, on which a soft decoding program of a rotary transformer is stored. When the soft decoding program of the rotary transformer is executed by a processor, the soft decoding method of the rotary transformer of the above-mentioned embodiment of the present invention is implemented.

[0018] According to the computer-readable storage medium of the embodiment of the present invention, by executing the soft decoding program of the rotary transformer stored thereon, the burden of the DSP chip when applying the excitation signal to the rotary transformer can be reduced, which helps to improve the soft decoding speed and accuracy.

[0019] To achieve the above-mentioned purpose, a soft decoding system of a rotary transformer is proposed in an embodiment of the third aspect of the present invention, and the system includes a DSP chip and an FPGA chip, wherein the DSP chip is used to generate an enable signal and input the enable signal to the FPGA chip, wherein the FPGA chip generates a high-frequency excitation signal applied to the rotary transformer according to the enable signal; the DSP chip is also used to obtain a feedback signal of the rotary transformer and an interrupt signal of the FPGA chip, wherein the rotary transformer generates the feedback signal according to the high-frequency excitation signal, and the FPGA chip generates the interrupt signal according to the phase delay time caused by the rotary transformer; the DSP chip is also used to obtain the rotary transformer angle value and / or speed value according to the feedback signal and the interrupt signal.

[0020] According to the soft decoding system of the rotary transformer of the embodiment of the present invention, an enable signal is generated by a DSP chip, and the enable signal is input to an FPGA chip, wherein the FPGA chip generates a high-frequency excitation signal applied to the rotary transformer according to the enable signal, and then, the feedback signal of the rotary transformer is obtained by the DSP chip, and an interrupt signal of the FPGA chip is obtained, wherein the rotary transformer generates a feedback signal according to the high-frequency excitation signal, the FPGA chip generates an interrupt signal according to the phase delay time caused by the rotary transformer, and the DSP chip obtains the rotary transformer angle value and / or speed value according to the feedback signal and the interrupt signal. Thus, the FPGA chip is enabled by the DSP chip, and a high-frequency excitation signal applied to the rotary transformer is generated by the FPGA chip, thereby reducing the burden of the DSP chip when applying the excitation signal to the rotary transformer, which helps to improve the speed and accuracy of soft decoding.

[0021] To achieve the above-mentioned purpose, a control platform for a rotary transformer provided in an embodiment of a fourth aspect of the present invention includes a soft decoding system for the rotary transformer of the above-mentioned embodiment of the present invention.

[0022] The control platform of the rotary transformer according to the embodiment of the present invention can reduce the burden of the DSP chip when applying the excitation signal to the rotary transformer by adopting the soft decoding system of the rotary transformer, which helps to improve the soft decoding speed and accuracy.

[0023] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a flow chart of a soft decoding method of a rotary transformer according to an embodiment of the present invention;

[0025] Figure 2 is a flow chart of a soft decoding method of a rotary transformer according to an embodiment of the present invention;

[0026] Figure 3 is a flow chart of a soft decoding method of a rotary transformer according to an embodiment of the present invention;

[0027] Figure 4 is a timing diagram of an FPGA chip and interrupt sampling points according to a specific embodiment of the present invention;

[0028] Figure 5 is a schematic diagram of a flow chart of phase delay time calculation according to a specific embodiment of the present invention;

[0029] Figure 6 is a flow chart of a soft decoding method of a rotary transformer according to an embodiment of the present invention;

[0030] Figure 7 is a schematic diagram of a flow chart of calculating a resolver angle value and / or a velocity value according to a specific embodiment of the present invention;

[0031] Figure 8 is a structural schematic diagram of a soft decoding system of a rotary transformer according to an embodiment of the present invention;

[0032] Fig. 9 is a block diagram of a control platform of a rotary transformer according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0034] The following describes a soft decoding method for a rotary transformer, a computer-readable storage medium, a soft decoding system for a rotary transformer, and a rotary transformer according to embodiments of the present invention with reference to the accompanying drawings.

[0035] Figure 1 4 is a flow chart of a soft decoding method of a rotary transformer according to an embodiment of the present invention.

[0036] Specifically, in some embodiments of the present invention, the soft decoding method of the rotary transformer is based on a DSP (Digital Signal Processing) chip and an FPGA (Field Programmable Gate Array) chip, such as Figure 1 As shown, the method includes:

[0037] S101, the DSP chip generates an enable signal, and inputs the enable signal to the FPGA chip, wherein the FPGA chip generates a high-frequency excitation signal applied to the rotary transformer according to the enable signal.

[0038] It can be understood that, compared with the method of using the DSP chip alone to generate the excitation signal, in this embodiment of the present invention, the excitation signal is jointly generated by the DSP chip and the FPGA chip. Specifically, the DSP chip sends an enable signal to the FPGA chip, and the FPGA chip immediately outputs an arbitrary high-frequency PWM signal after receiving the enable signal. The PWM signal is filtered and modulated by the hardware circuit to output the high-frequency excitation signal required by the rotary transformer.

[0039] S102, the DSP chip obtains the feedback signal of the rotary transformer and the interrupt signal of the FPGA chip, wherein the rotary transformer generates the feedback signal according to the high-frequency excitation signal, and the FPGA chip generates the interrupt signal according to the phase delay time caused by the rotary transformer.

[0040] It can be understood that, in this embodiment of the present invention, the feedback signal of the rotary transformer is used to characterize the rotor position at different times, and the interrupt signal of the FPGA chip is used to trigger the DSP chip to perform real-time sampling of the feedback signal.

[0041] S103, the DSP chip obtains the resolver angle value and / or speed value according to the feedback signal and the interrupt signal.

[0042] It can be understood that in this embodiment of the present invention, after the DSP chip receives the interrupt signal output by the FPGA chip, it immediately samples the feedback signal of the rotary transformer. Figure 2 It can be seen that the interrupt signal moments after delay compensation are the peak and valley values ​​of the feedback signal respectively. Then, the resolver angle value and / or speed value can be calculated and obtained through the RDC (Resolver-to-digital converter) algorithm.

[0043] Specifically, in the above embodiment of the present invention, when powered on for the first time, the DSP chip enables the FPGA chip to generate a PWM signal of high-frequency excitation applied to the rotary transformer, and the DSP chip cooperates with the FPGA chip to obtain the phase delay time caused by the rotary transformer, and determines the sampling time corresponding to the phase delay time, and then, when the DSP chip detects the interrupt signal of the FPGA chip, the feedback signal of the rotary transformer is sampled in real time, wherein the rotary transformer generates a feedback signal according to the high-frequency excitation signal corresponding to the PWM signal of high-frequency excitation, the FPGA chip generates an interrupt signal according to the sampling time, and the DSP chip obtains the rotary transformer angle value and / or speed value according to the real-time sampling value. Thus, the burden of the DSP chip in applying the excitation signal to the rotary transformer is reduced, which helps to improve the soft decoding speed and accuracy of the rotary transformer and facilitates subsequent motor control.

[0044] Furthermore, in some embodiments of the present invention, the feedback signal includes a sine signal and a cosine signal.

[0045] It can be understood that, in this embodiment of the present invention, the rotary transformer can feed back the rotor position information at different times to the DSP chip in the form of two sine signals and a cosine signal.

[0046] Further, in some embodiments of the present invention, Figure 3As shown, the FPGA chip generates a high-frequency excitation signal applied to the rotary transformer according to the enable signal, including:

[0047] S201, the FPGA chip generates a high-frequency PWM signal according to the enable signal, and inputs the high-frequency PWM signal to the excitation signal amplification circuit.

[0048] It can be understood that in this embodiment of the present invention, the FPGA chip can output a high-frequency PWM signal (given the parallel advantage of FPGA, it can output any frequency of 400K and above) to the excitation signal amplification circuit in each cycle according to the enable signal from the DPS chip.

[0049] S202, the excitation signal amplifying circuit filters the high-frequency PWM signal and converts the high-frequency PWM signal into a high-frequency excitation signal.

[0050] It can be understood that, in this embodiment of the present invention, the excitation signal amplifying circuit can filter the high-frequency PWM signal output by the FPGA chip and convert it into a high-frequency excitation signal sinωt.

[0051] Furthermore, in some embodiments of the present invention, the excitation signal amplifying circuit includes a Boost boosting unit, an excitation amplifying pre-stage unit and an excitation power amplifying unit.

[0052] It can be understood that in this embodiment of the present invention, the excitation signal amplification circuit increases the excitation voltage amplitude through the Boost step-up unit, filters the excitation signal and applies a common-mode voltage through the excitation amplification pre-stage unit, and amplifies the excitation signal driving capability through the excitation power amplification unit.

[0053] It should be noted that, in the above embodiments of the present invention, different types of rotary transformer adjustments correspond to different amplification factors of the Boost unit, and rotary transformers based on different driving capabilities correspond to different amplification factors of the excitation power amplifier unit.

[0054] Furthermore, in some embodiments of the present invention, the DSP chip obtains the feedback signal through a feedback signal sampler, wherein the feedback signal sampler includes a secondary side signal conditioning circuit.

[0055] Specifically, in this embodiment of the present invention, the feedback signal sampler respectively amplifies the sine signal and cosine signal of the rotary transformer, and conditions the sine signal and cosine signal to a signal range acceptable to the ADC (Analog-to-digital converter) sampling circuit of the DSP chip through the secondary signal conditioning circuit, so that the DSP chip can calculate the rotary transformer angle value and / or speed value.

[0056] Further, in some embodiments of the present invention, Figure 4 As shown, the FPGA chip generates an interrupt signal according to the phase delay time caused by the rotary transformer, including:

[0057] S301, the FPGA chip records the peak moment and valley moment of the high-frequency excitation PWM signal.

[0058] It can be understood that in this embodiment of the present invention, the FPGA chip records the peak moment of the high-frequency excitation PWM signal (i.e., Figure 2 The high frequency excitation signal shown in the figure has a peak moment t1) and a valley moment (i.e. Figure 2 The high-frequency excitation signal shown is at a valley point in time t2).

[0059] S302, the DSP chip records the peak moment and the valley moment of the feedback signal, and feeds back to the FPGA chip.

[0060] It can be understood that in this embodiment of the present invention, the DSP chip records the peak moment of the feedback signal (i.e. Figure 2 The feedback signal shown in FIG. 1 has a peak value at time d1) and a valley value at time d2. Figure 2 The feedback signal shown shows a valley value at time d2) and is fed back to the FPGA chip.

[0061] S303, the FPGA chip obtains the phase delay time according to the peak moment and valley moment of the high-frequency excitation PWM signal and the peak moment and valley moment of the feedback signal.

[0062] It can be understood that in this embodiment of the present invention, the first phase delay time is determined according to the difference between the peak moment of the high-frequency excitation PWM signal and the peak moment of the feedback signal, and the second phase delay time is determined according to the valley moment of the high-frequency excitation PWM signal and the valley moment of the feedback signal, and then, the final phase delay time is determined by verifying whether the first phase delay time and the second phase delay time are consistent.

[0063] Combine the following Figure 5 The specific embodiment of the present invention is to explain the process calculation of the FPGA chip generating the interrupt signal accordingly: Specifically, as Figure 5 As shown, after the DSP chip is powered on and the DSP chip outputs an enable signal to trigger the FPGA chip to output a PWM signal of high-frequency excitation, step S1 is executed.

[0064] S10, the FPGA chip records the peak time t1 and the valley time t2 of the high-frequency excitation PWM signal.

[0065] S11, the DSP chip records the peak time d1 and the valley time d2 of the feedback signal, and feeds them back to the FPGA chip.

[0066] S12, the FPGA chip verifies whether d1-t1 is equal to d2-t2, if so, execute step S13, if not, return to execute step S10.

[0067] S13, the FPGA chip determines the phase delay time delay=d1-t1=d2-t2, and sets the trigger interrupt signal to the time t1+delay and the time t2+delay.

[0068] S14, the FPGA chip generates an interrupt signal at time t1+delay and time t2+delay, and outputs it to the DSP chip.

[0069] Further, in some embodiments of the present invention, Figure 6 As shown, obtaining the resolver angle value and / or speed value includes:

[0070] S401, the DSP chip determines the peak sampling value and the valley sampling value of the sine signal and the cosine signal according to the interrupt signal.

[0071] It can be understood that in this embodiment of the present invention, when the DSP chip receives the interrupt signal output by the FPGA chip, the feedback signal (sine signal and cosine signal) of the rotary transformer is sampled to obtain the peak sampling value and valley sampling value of the sine signal and the cosine signal.

[0072] S402, the DSP chip performs arc tangent calculation on the peak sampling values ​​and valley sampling values ​​of the sine signal and the cosine signal to obtain the resolver angle value and / or speed value.

[0073] It can be understood that in this embodiment of the present invention, after the peak and valley values ​​of the sine signal and the cosine signal are sampled by the DSP chip, the resolver angle is obtained through inverse tangent calculation and the corresponding interval, and then the speed of the motor is calculated.

[0074] Combine the following Figure 7 The specific embodiments of the present invention provide a corresponding description of the rotation calculation, specifically, as follows: Figure 7 As shown, after the FPGA chip outputs an interrupt signal, step S20 is executed:

[0075] S20, the DSP chip determines whether the peak sampling and valley sampling of the sine signal and the cosine signal are completed. If so, step S21 is executed; if not, the peak sampling and valley sampling of the sine signal and the cosine signal are continued.

[0076] S21, the DSP chip determines the peak sampling value and the valley sampling value of the sine signal and the cosine signal.

[0077] S22, the DSP chip performs arc tangent calculation on the peak sampling value and valley sampling value of the sine signal and the cosine signal, and finally obtains the resolver angle value and / or speed value by matching the corresponding angle interval.

[0078] Specifically, in some embodiments of the present invention, when power is turned on for the first time, an enable signal is generated by the DSP chip and input into the FPGA chip, wherein the FPGA chip generates a PWM signal of high-frequency excitation applied to the rotary transformer according to the enable signal, and the rotary transformer generates a feedback signal according to the high-frequency excitation signal. At the same time, the DSP chip scans the entire feedback outer envelope signal of the rotary transformer, and cooperates with the FPGA chip to jointly confirm the phase delay time between the feedback signal and the excitation signal caused by the rotary transformer, and records the delay time as the corresponding sampling time. After that, the FPGA chip outputs an interrupt signal to the DSP chip according to the recorded sampling time, thereby, the DSP chip obtains the feedback sine sampling value and cosine sampling value at the current moment according to the interrupt signal, and finally obtains the rotary transformer angle value and / or speed value.

[0079] In summary, according to the soft decoding method of the rotary transformer proposed in the embodiment of the present invention, the DSP chip generates an enable signal, and inputs the enable signal to the FPGA chip, wherein the FPGA chip generates a high-frequency excitation signal applied to the rotary transformer according to the enable signal, and then the DSP chip obtains the feedback signal of the rotary transformer and obtains the interrupt signal of the FPGA chip, wherein the rotary transformer generates a feedback signal according to the high-frequency excitation signal, the FPGA chip generates an interrupt signal according to the phase delay time caused by the rotary transformer, and the DSP chip obtains the rotary transformer angle value and / or speed value according to the feedback signal and the interrupt signal. Thus, the DSP chip enables the FPGA chip, and the high-frequency excitation signal applied to the rotary transformer is generated by the FPGA chip, thereby reducing the burden of the DSP chip when applying the excitation signal to the rotary transformer, which helps to improve the speed and accuracy of soft decoding.

[0080] Based on the soft decoding method of the rotary transformer of the aforementioned embodiment of the present invention, the embodiment of the present invention proposes a computer-readable storage medium, on which a soft decoding program of the rotary transformer is stored. When the soft decoding program of the rotary transformer is executed by a processor, the soft decoding method of the rotary transformer of the aforementioned embodiment of the present invention is implemented.

[0081] It should be understood that the specific implementation of the computer-readable storage medium of the embodiment of the present invention can refer to the specific implementation of the soft decoding method of the rotary transformer of the embodiment of the present invention, which will not be described again to reduce redundancy.

[0082] In summary, according to the computer-readable storage medium of the embodiment of the present invention, by executing the soft decoding program of the rotary transformer stored thereon, it is possible to reduce the burden on the DSP chip when applying the excitation signal to the rotary transformer, which helps to improve the soft decoding speed and accuracy.

[0083] Figure 5 4 is a block diagram of a soft decoding system of a rotary transformer according to an embodiment of the present invention.

[0084] Specifically, in some embodiments of the present invention, Figure 8 As shown, the soft decoding system 1000 of the rotary transformer includes a DSP chip 100 and an FPGA chip 200 .

[0085] Among them, the DSP chip 100 is used to generate an enable signal and input the enable signal to the FPGA chip 200, wherein the FPGA chip 200 generates a high-frequency excitation signal applied to the rotary transformer according to the enable signal; the DSP chip 100 is also used to obtain a feedback signal of the rotary transformer and an interrupt signal of the FPGA chip 200, wherein the rotary transformer generates a feedback signal according to the high-frequency excitation signal, and the FPGA chip 200 generates an interrupt signal according to the phase delay time caused by the rotary transformer; the DSP chip 100 is also used to obtain the rotary transformer angle value and / or speed value according to the feedback signal and the interrupt signal.

[0086] Furthermore, in some embodiments of the present invention, the feedback signal includes a sine signal and a cosine signal.

[0087] Further, in some embodiments of the present invention, Figure 8 As shown, the FPGA chip 200 generates a high-frequency PWM signal according to the enable signal, and inputs the high-frequency PWM signal to the excitation signal amplifier circuit; the excitation signal amplifier circuit filters the high-frequency PWM signal and converts the high-frequency PWM signal into a high-frequency excitation signal.

[0088] Furthermore, in some embodiments of the present invention, the excitation signal amplifying circuit includes a Boost boosting unit, an excitation amplifying pre-stage unit and an excitation power amplifying unit.

[0089] Furthermore, in some embodiments of the present invention, the FPGA chip 200 records the peak moment and valley moment of the high-frequency excitation signal; the DSP chip 100 records the peak moment and valley moment of the feedback signal and feeds back to the FPGA chip 200; the FPGA chip 200 obtains the phase delay time based on the peak moment and valley moment of the high-frequency excitation signal and the peak moment and valley moment of the feedback signal.

[0090] Furthermore, in some embodiments of the present invention, obtaining the resolver angle value and / or speed value includes: the DSP chip 100 determines the peak sampling value and valley sampling value of the sine signal and the cosine signal according to the interrupt signal; the DSP chip 100 performs arc tangent calculation on the peak sampling value and valley sampling value of the sine signal and the cosine signal to obtain the resolver angle value and / or speed value.

[0091] Further, in some embodiments of the present invention, Figure 8 As shown, the DSP chip 100 obtains the feedback signal through a feedback signal sampler, wherein the feedback signal sampler includes a secondary side signal conditioning circuit.

[0092] It should be understood that the specific implementation of the soft decoding system 100 of the rotary transformer in the embodiment of the present invention corresponds one-to-one to the specific implementation of the soft decoding method of the rotary transformer in the aforementioned embodiment of the present invention, and will not be described again here to reduce redundancy.

[0093] In summary, according to the soft decoding system of the rotary transformer of the embodiment of the present invention, an enable signal is generated by the DSP chip, and the enable signal is input to the FPGA chip, wherein the FPGA chip generates a high-frequency excitation signal applied to the rotary transformer according to the enable signal, and then, the feedback signal of the rotary transformer is obtained by the DSP chip, and the interrupt signal of the FPGA chip is obtained, wherein the rotary transformer generates a feedback signal according to the high-frequency excitation signal, the FPGA chip generates an interrupt signal according to the phase delay time caused by the rotary transformer, and the DSP chip obtains the rotary transformer angle value and / or speed value according to the feedback signal and the interrupt signal. Thus, the FPGA chip is enabled by the DSP chip, and the high-frequency excitation signal applied to the rotary transformer is generated by the FPGA chip, thereby reducing the burden of the DSP chip when applying the excitation signal to the rotary transformer, which helps to improve the speed and accuracy of soft decoding.

[0094] Fig. 9 is a block diagram of a control platform of a rotary transformer according to an embodiment of the present invention.

[0095] Specifically, in some embodiments of the present invention, Fig. 9 As shown, the control platform 2000 of the rotary transformer includes the soft decoding system 1000 of the rotary transformer according to the above-mentioned embodiment of the present invention.

[0096] It should be understood that the specific implementation of the control platform 2000 of the rotary transformer in the embodiment of the present invention can refer to the specific implementation of the soft decoding method of the rotary transformer in the aforementioned embodiment of the present invention, and will not be repeated here to reduce redundancy.

[0097] In summary, the control platform of the rotary transformer according to the embodiment of the present invention, by adopting the soft decoding system of the rotary transformer, can reduce the burden of the DSP chip when applying the excitation signal to the rotary transformer, which helps to improve the soft decoding speed and accuracy.

[0098] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing in a suitable manner if necessary, and then stored in a computer memory.

[0099] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0100] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0101] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0102] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0103] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0104] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0105] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A soft decoding method for a rotary transformer, characterized in that: Based on DSP chip and FPGA chip, the method includes: The DSP chip generates an enable signal, and inputs the enable signal to the FPGA chip, wherein the FPGA chip generates a high-frequency excitation signal applied to the rotary transformer according to the enable signal; The DSP chip obtains a feedback signal of the rotary transformer and an interrupt signal of the FPGA chip, wherein the rotary transformer generates the feedback signal according to the high-frequency excitation signal, and the FPGA chip generates the interrupt signal according to the phase delay time caused by the rotary transformer; The DSP chip obtains the resolver angle value and / or speed value according to the feedback signal and the interrupt signal.

2. The soft decoding method of the rotary transformer according to claim 1, characterized in that: The feedback signal includes a sine signal and a cosine signal.

3. The soft decoding method of the rotary transformer according to claim 2, characterized in that: The FPGA chip generates a high-frequency excitation signal applied to the rotary transformer according to the enable signal, including: The FPGA chip generates a high-frequency PWM signal according to the enable signal, and inputs the high-frequency PWM signal into an excitation signal amplifying circuit; The high-frequency PWM signal is filtered by the excitation signal amplifying circuit, and the high-frequency PWM signal is converted into the high-frequency excitation signal.

4. The soft decoding method of the rotary transformer according to claim 3, characterized in that: The excitation signal amplifying circuit comprises a Boost voltage-boosting unit, an excitation amplifying front-stage unit and an excitation power amplifying unit.

5. The soft decoding method of the rotary transformer according to claim 2, characterized in that: The FPGA chip generates the interrupt signal according to the phase delay time caused by the rotary transformer, including: The FPGA chip records the peak moment and the valley moment of the high-frequency excitation signal; The DSP chip records the peak moment and the valley moment of the feedback signal, and feeds back the peak moment and the valley moment to the FPGA chip; The FPGA chip obtains the phase delay time according to the peak moment and valley moment of the high-frequency excitation signal and the peak moment and valley moment of the feedback signal.

6. The soft decoding method of the rotary transformer according to claim 2, characterized in that: The obtaining of the resolver angle value and / or the speed value comprises: The DSP chip determines the peak sampling value and the valley sampling value of the sine signal and the cosine signal according to the interrupt signal; The DSP chip performs arc tangent calculation on the peak sampling values ​​and valley sampling values ​​of the sine signal and the cosine signal to obtain the resolver angle value and / or speed value.

7. The soft decoding method of the rotary transformer according to claim 1, characterized in that: The DSP chip obtains the feedback signal through a feedback signal sampler, wherein the feedback signal sampler includes a secondary side signal conditioning circuit.

8. A computer-readable storage medium, characterized in that: A soft decoding program of a rotary transformer is stored thereon, and when the soft decoding program of the rotary transformer is executed by a processor, a soft decoding method of a rotary transformer according to any one of claims 1 to 7 is implemented.

9. A soft decoding system for a rotary transformer, characterized in that: The system includes a DSP chip and an FPGA chip, wherein: The DSP chip is used to generate an enable signal and input the enable signal to the FPGA chip, wherein the FPGA chip generates a high-frequency excitation signal applied to the rotary transformer according to the enable signal; The DSP chip is also used to obtain a feedback signal of the rotary transformer and an interrupt signal of the FPGA chip, wherein the rotary transformer generates the feedback signal according to the high-frequency excitation signal, and the FPGA chip generates the interrupt signal according to the phase delay time caused by the rotary transformer; The DSP chip is also used to obtain the resolver angle value and / or speed value according to the feedback signal and the interrupt signal.

10. A control platform for a rotary transformer, characterized in that: The control platform comprises the soft decoding system of the rotary transformer according to claim 9.

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