Phased array equipment testing method and system

Abstract

The invention provides a phased array equipment test method and system, and the method comprises the steps: carrying out the application layer processing corresponding to a test mode on input test data based on configuration information and test parameters, and carrying out the data reconstruction on the application layer processing result data, a phased array data stream matched with the phased array equipment is obtained; the phased array data stream is issued to the phased array equipment, so that the phased array equipment executes corresponding phased array operation according to the phased array data stream, and a phased array operation result is returned; the phased array testing device can adapt to different phased array devices, the universality is improved, and the phased array testing efficiency is remarkably improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of phased array testing, and in particular, relates to a phased array equipment testing method and system. Background Art

[0002] As an important device in the phased array radar detection / communication system, the stability of the working performance of the phased array device will directly affect the system stability of the entire system. Therefore, before using the phased array device to perform corresponding phased array operations, it is necessary to test it first to ensure the stability of the equipment's working performance.

[0003] In the phased array device test, various functions are usually included, such as angle solution and compensation, sum and difference beamforming, calibration code correction and compensation, and unit code control. When executing the functional instructions corresponding to the above functions, it is often necessary to transmit the phased array data stream related to the functional instructions to the phased array device, so that the device performs the phased array operation corresponding to the phased array data stream. Based on this, the phased array data stream often needs to match the architecture parameters and / or data structure parameters of the phased array device to ensure that the test process matches the phased array device.

[0004] In the prior art, a test program that matches the architecture parameters and / or data structure parameters of a phased array device is usually generated in an FPGA platform using a hardware description language (HDL); however, since the code corresponding to the hardware description language cannot be parameterized in real time, the architecture parameters and / or data structure parameters of the phased array device will change after the phased array device is replaced. Therefore, it is necessary not only to modify the program parameters corresponding to the architecture parameters or data structure parameters in the test program accordingly, but also to adjust the code associated with the program parameters for adaptability, resulting in poor versatility of the existing phased array device test method, and it is difficult to quickly and conveniently match different types of phased array devices. In addition, after replacing the phased array device, it is often necessary to use the FPGA platform to re-verify the adjusted test program (verify the regenerated digital circuit). When there is a verification problem, it is necessary to return to the code design stage to adjust the code, resulting in further reduction in test efficiency. In addition, after replacing the phased array device, there is often a risk that the code cannot be fully verified, resulting in reduced test accuracy, etc.

[0005] Therefore, how to improve the adaptability and versatility of phased array equipment testing methods has become a technical problem that needs to be solved in this field. Summary of the invention

[0006] The object of the present invention is to provide a phased array device testing method and system, which are used to solve the technical problems that the existing phased array device testing method and system have poor adaptability to different phased array devices, resulting in weak versatility of the phased array device testing method and system, inconvenient use, etc.

[0007] In order to solve the above technical problems, the present application provides a phased array device testing method in a first aspect, characterized by comprising:

[0008] Acquire configuration information related to a phased array device, and acquire test parameters corresponding to a test mode; based on the configuration information and the test parameters, perform application layer processing corresponding to the test mode on input test data, and perform data reconstruction on the application layer processing result data, so as to obtain a phased array data stream adapted to the phased array device; send the phased array data stream to the phased array device, so that the phased array device performs corresponding phased array operations according to the phased array data stream, and returns phased array operation results; wherein the phased array device includes a chip and a plurality of antenna units connected to the chip.

[0009] In an optional embodiment, when the test mode is a wave control mode, the application layer processing includes phase processing and attenuation processing, and the performing data reconstruction on the application layer processing result data includes:

[0010] The phase processing result and the attenuation processing result are combined to obtain the first phased array data; based on the configuration information, the first phased array data is subjected to shift splicing processing to obtain the unit data corresponding to the antenna unit; and the unit data are sorted to obtain the phased array data stream.

[0011] In an optional embodiment, the implementation method of performing shift stitching processing on the first phased array data includes:

[0012] In the first phased array data, data segments corresponding to each of the antenna units are extracted; according to the position information of the data type corresponding to the data segment in the data transmission channel, shift operations corresponding to the position information are performed on each data segment corresponding to a single antenna unit; and the shifted data segments are spliced ​​to obtain the unit data corresponding to each antenna unit.

[0013] In an optional embodiment, the method for acquiring the phased array data stream includes:

[0014] The number of units in the configuration information is obtained, and a construction number is determined based on the number of units; according to the construction number and based on the test parameters, unit data construction is repeatedly performed on the test data to obtain unit data corresponding to a corresponding construction order; and according to the configuration information, the unit data corresponding to each construction order are sorted to obtain a phased array data stream.

[0015] In an optional embodiment, the unit data is constructed in a single execution, including:

[0016] Based on the configuration information and the test parameters, phase processing is performed on the test data to obtain a phase processing result corresponding to the current build order; and based on the configuration information and the test parameters, attenuation processing is performed on the test data to obtain an attenuation processing result corresponding to the current build order; according to the configuration information, data shifting and splicing processing is performed on the phase processing result and the attenuation processing result to obtain unit data corresponding to the current build number.

[0017] In an optional embodiment, sending the phased array data stream to the phased array device includes:

[0018] According to the number of unit mappings, the phased array data stream is divided into a plurality of phased array unit arrays; each of the phased array unit arrays is stored in a corresponding storage space according to a preset storage mapping relationship; the phased array unit arrays in each of the storage spaces are transmitted in parallel to a corresponding chip, so that the chip performs a corresponding phased array operation according to the phased array unit array; wherein the phased array unit array corresponds to a single chip.

[0019] In order to solve the above technical problems, the present application provides a phased array test system in a second aspect, which is connected between an external device and a phased array device, and is used to obtain configuration information, test parameters and test data input by the external device, and based on the configuration information and the test parameters, use the test data to perform a phased array test process on each test data; wherein the phased array device includes a chip and a plurality of antenna units connected to the chip; and the phased array test process adopts any of the phased array device test methods described above.

[0020] In an optional embodiment, the phased array test system includes:

[0021] A register unit for storing data; a transmission unit connected to the external device and the register unit, for obtaining the configuration information, the test parameters and the test data input by the external device, and storing the configuration information and the test parameters in the register unit; a phased array data processing unit, comprising a first end and a second end, the first end being connected to the register unit for obtaining the configuration information and the test parameters; the second end being connected to the transmission unit, for obtaining the test data, and performing corresponding phased array data processing on the test data in combination with the test parameters and the configuration information to obtain a processed phased array data stream; a sending unit, comprising a first end, a second end and a third end, the first end being connected to the phased array data processing unit for obtaining the phased array data stream; the second end of the sending unit being connected to the register unit, for storing each phased array unit array in the phased array data stream in the corresponding register unit; the third end of the sending unit being connected to the chip, for sending the phased array unit arrays stored in each register unit to the chip in parallel.

[0022] In an optional embodiment, the phased array data processing unit includes:

[0023] A test operation module is used to perform phase processing and attenuation processing in a wave control mode; a data adaptation module is connected to the test operation module and is used to perform data reconstruction on the phase processing result and attenuation processing result output by the test operation module to obtain a processed phased array data stream.

[0024] In an optional embodiment, the sending unit includes: a reading and writing module, a value assignment module, an addressing and writing module, a timing module and a control module; wherein,

[0025] The read-write module is connected to the phased array data processing unit, the chip and the register unit, and is used to store the phased array data stream input by the phased array data processing unit in the register unit; and is used for the chip to read data; the input end of the value assignment module is connected to the read-write module, and is used to obtain the read-write status information of the read-write module; the output end of the value assignment module is connected to the addressing and writing module, and is used to control whether to write data to the addressing and writing module according to the read-write status information; the addressing and writing module is respectively connected to the value assignment module and the register unit, and is used to store the input phased array data stream in the register unit; and is used for the chip to read data; The addressing and writing module is also connected to the timing module, so as to output each phased array unit array in the same phased array data stream to the chip in parallel based on the timing control of the timing module; the timing module is connected to the phased array data processing unit, the chip and the register unit, and is used to send the phased array unit arrays in each register unit to each chip in parallel; the control module is connected to the phased array data processing unit and the chip, and is used to control the chip to perform corresponding phased array operations according to the control instructions sent by the phased array data processing unit.

[0026] The phased array test device and method provided in the embodiment of the present application obtain configuration information related to the device to be tested, and obtain test data and test parameters related to the test process; perform corresponding phased array data processing on the test data based on the test parameters, and perform data reconstruction on the phased array data processing results based on the configuration information, so that the processing result data can be conveniently and efficiently adapted to the phased array device, and can adapt to the needs of different phased array devices without redesigning the hardware circuit. The test device and method of the present application have high adaptability. Compared with the prior art, it can better meet various needs in the actual research and development test process, which not only improves the versatility, but also significantly improves the efficiency of phased array testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram showing a flow chart of an embodiment of the phased array device testing method provided in the present application;

[0028] Figure 2 FIG. 2 is a flow chart of step S200 in an embodiment of the present application;

[0029] Figure 3 FIG. 2 is a flow chart of step S230 in an embodiment of the present application;

[0030] Figure 4 FIG. 2 is a flow chart of step S200 in another embodiment of the present application;

[0031] Figure 5 It is a schematic diagram of a process of constructing phased array unit data in a single execution in an embodiment of the present application;

[0032] Figure 6 A schematic diagram showing a flow chart of performing phase processing on the test data described in the present application in one embodiment;

[0033] Figure 7 A schematic diagram showing a flow chart of performing attenuation processing for the test data described in the present application in one embodiment;

[0034] Figure 8 FIG. 1 is a flow chart of step S300 in an embodiment of the present application;

[0035] Fig. 9 A schematic diagram showing an application environment of the phased array test system provided in the present application in one embodiment;

[0036] Fig.10 A schematic diagram showing a specific structure of the phased array test system provided in the present application in one embodiment;

[0037] Fig.11 FIG. 1 is a schematic diagram showing a specific structure of the phased array data processing unit in one embodiment of the present application;

[0038] Fig.12 It is a schematic diagram showing a specific structure of the sending unit described in the present application in one embodiment; DETAILED DESCRIPTION

[0039] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0040] It should be noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present application. It should be understood that other embodiments may be used, and mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application.

[0041] Also, as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms "comprises", "includes", "includes" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination.

[0042] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the technical solution in the embodiments of the present invention is further described in detail through the following embodiments and in combination with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the invention.

[0043] In order to solve the technical problems existing in the prior art, the present application first provides a phased array device testing method, which controls the phased array device to perform phased array operations corresponding to the test data according to the phased array test parameters input externally, so as to realize the testing process of the phased array device.

[0044] Among them, the phased array device includes multiple phased array chips (hereinafter referred to as "chips") and phased array antenna units (hereinafter referred to as "antenna units"). A single chip is connected to several antenna units, and sends phased array unit data (hereinafter referred to as "unit data") to the connected antenna units respectively, so as to efficiently realize efficient and coordinated control of multiple antenna units by a single chip; exemplarily, a single chip connects and controls 4 antenna units.

[0045] The unit data is phased array data corresponding to a single antenna unit, and is used to control the corresponding antenna unit to perform corresponding phased array operations.

[0046] See also Figure 1 , showing a flow chart of a phased array device testing method provided in an embodiment of the present application.

[0047] like Figure 1 As shown, when the method is executed, it includes the following sub-steps:

[0048] S100, obtaining configuration information related to the phased array device to be tested, and obtaining test parameters corresponding to the phased array test mode;

[0049] In this application, the configuration information includes first configuration information and second configuration information;

[0050] The first configuration information is a command parameter set for adapting the physical architecture of the antenna unit, that is, the first configuration information is a command parameter associated with the antenna unit.

[0051] The second configuration information is an instruction parameter set for adapting the data structure form of the chip, that is, the second configuration information is an instruction parameter associated with the data structure form of the chip.

[0052] In this embodiment, the first configuration information includes the number of units, unit corresponding information, unit location information, and the like.

[0053] Among them, the unit quantity is the number of antenna units included in the phased array device; the unit corresponding information is the correspondence information between the interface pins of the chip and the phased array units; and the unit position information is the information representing the position structure of each antenna unit in the phased array device.

[0054] Taking the unit position information as an example, the unit position information is configuration information for performing angle resolution, and the unit position information is associated with the position structure of each antenna unit in the phased array device. When the phased array device is replaced, the unit position information will change accordingly.

[0055] More specifically, taking a planar equidistant phased array as an example, the unit position information may be the sum of four information: the number of unit rows, the number of unit columns, the unit row spacing, and the unit column spacing.

[0056] In this embodiment, the second configuration information includes data length of the chip, unit transmission order, unit mapping quantity, phase shift information, attenuation bit information, transceiver status bit information, data location information, etc.

[0057] The data length is used to characterize the data bit length of the data transmission channel, which is equal to the length of a single chip data transmission;

[0058] The unit transmission sequence is used to characterize the sequence of data corresponding to different phased array units in the data transmission channel;

[0059] The unit mapping quantity represents the number of antenna units controlled by a single chip;

[0060] The phase shift information is used to arrange the calculated phase code according to the phase shift information to obtain the phase offset information that can control the beam direction; more specifically, the phase shift information includes the number of phase shifters and the wiring method, and the calculated phase code is arranged according to the number of phase shifters and the wiring method according to 0 to 2 k-1 After executing the first arrangement (k is the number of phase shifter bits), the second arrangement is executed based on the wiring method to obtain a phase shift mapping table; taking the six-phase shifter as an example, when the fourth line physically crosses the first line, the phase code after the first arrangement is converted from XX1XX0 to XX0XX1. For the state number corresponding to the number of phase shifter bits exceeds the actual phase shift state number, taking the nine-phase shifter as an example, its state number is 2 9 The actual number of states is 2 6 (The minimum step of the phase shift is 360° / 2 6 =5.625°); after executing the first arrangement, when executing the second arrangement, the 6-bit state must first be mapped into 9 bits, for example, 010101 is mapped into 100101001 corresponding to the same phase shift amount (this mapping relationship can be obtained by testing a state closer to the ideal phase shift amount), and then the phase offset mapping table is obtained according to the wiring method.

[0061] The attenuation bit information is used to arrange the calculated attenuation code according to the attenuation bit information to obtain the attenuation offset information that can control the beam amplitude, and its implementation method is the same as that of the phase shift information.

[0062] The transceiver status bit information is information used to indicate whether the transmission and reception are valid; more specifically, the transceiver status bit information includes the receive / transmit status length and the receive / transmit status valid code; taking the receive status length of 1 and the transmit status length of 1 as an example, when the receive status valid code is 1 and the transmit status valid code is 0, there are four cases, and T represents the transmit status bit and R represents the receive status bit; "T:0, R:0" corresponds to valid transmission and invalid reception, "T:0, R:1" corresponds to valid transmission and valid reception, "T:1, R:0" corresponds to invalid transmission and invalid reception, and "T:1, R:1" corresponds to invalid transmission and valid reception.

[0063] The data position information is used to characterize the specific positions where various types of phased array data are arranged in the unit data to adapt to the data structure requirements of the chip; exemplarily, the data position information includes the transmit / receive attenuation position, the transmit / receive phase shift position, the transmit / receive state position, etc.

[0064] Taking the transmit phase shift position as an example, the transmit phase shift position includes information for controlling the transmit phase shift state, and the information needs to be located at a specific position in the data stream.

[0065] Taking the data length as an example, the data length includes the number of data bits required for a single chip pin in the chip in a single transmission; exemplarily, when a single chip pin requires 108 bits of data in a single transmission operation, the data length is set to 108 bits accordingly to perform the transmission of each test data (such as beam test) based on the data length.

[0066] The phased array test mode is the working mode of the phased array device to be tested; that is, different test modes have corresponding phased array device test processes.

[0067] The test parameters are instruction parameters that need to be called when performing processing related to the test operation on the test data during the test of the phased array device; the test parameters are associated with the phased array test mode. Exemplarily, the test parameters include macro definition parameters, mapping tables, etc.; more specifically, the macro definition parameters include the number of calibration frequency points, the size of the storage space for single frequency correction codes, angle quantization accuracy, windowing information, attenuation threshold, pulse information, etc.; the mapping table includes unit factor compensation information, angle correction table, beamforming table, unit switch table, etc.

[0068] The correction code information is correction data of all units after calibration of the phased array device.

[0069] The number of calibration frequency points is used to characterize the number of center frequencies to be calibrated during the formal use of the phased array device.

[0070] The storage space size of the single frequency correction code is used to characterize the storage space size of the correction code corresponding to a certain frequency. More specifically, it includes storage type and storage size. For example, if the number of units is 64, the storage type can be selected as a flash chip, and the storage size is 64*4Bytes / 256Bytes=1 page.

[0071] The angle quantization accuracy is used to characterize the minimum step of angle information in the test data.

[0072] The windowing information is information used for calculation in the windowing process to enable the phased array device to work in different modes. More specifically, it includes windowing dimension, azimuth / elevation windowing type, azimuth / elevation sidelobe level, and azimuth / elevation sidelobe number.

[0073] The attenuation threshold is used to maintain the attenuation amount and / or shut down the unit when the attenuation exceeds the threshold. More specifically, it includes a receiving / transmitting first attenuation threshold and a receiving / transmitting second attenuation threshold.

[0074] The pulse information is information used by the control module to control the phased array device as a whole to enter the transmitting state / receiving state / load state, and more specifically includes pulse source, transmitting and receiving pulses, pulse width, and pulse period.

[0075] The unit factor compensation information is used to reduce the influence of the unit pattern on the beam pointing before the angle solution, so as to achieve a more accurate beam direction.

[0076] The angle correction table is an angle mapping table for reverse compensation through testing when the error is large.

[0077] The beamforming table is used to satisfy the formation of various beam shapes.

[0078] The unit switch table is used to control the opening or closing of all units in the phased array device.

[0079] In a specific embodiment, the configuration information and the test parameters are pre-stored in a first storage area of ​​the phased array test system; when a start instruction for chip testing is received, first identification information related to the phased array device and second identification information related to the test operation in the start instruction are extracted; in the first storage area, configuration information corresponding to the phased array device is extracted based on the first identification information, and test parameters related to the test operation are extracted based on the second identification information; and after starting the test of the phased array device, in response to the received communication frame, the test data is extracted from each of the communication frames, and the test data is transmitted to the phased array device.

[0080] It should be noted that, in some other specific implementations, the configuration information and the test parameters can also be set in the communication frame, that is, by receiving the communication frame, and extracting the configuration information, the test parameters and the test data from the communication frame, so as to realize the rapid acquisition of the configuration information related to the device to be tested and the rapid acquisition of the test data and test parameters related to the test process by receiving the communication frame, thereby further improving the versatility and convenience of the method described in the present application.

[0081] S200, based on the configuration information and the test parameters, performing application layer processing corresponding to the phased array test mode on the input test data, and performing data reconstruction on the application layer processing result data, so as to obtain a phased array data stream adapted to the phased array device;

[0082] The test data is the source data required in the phased array device test process; illustratively, when the phased array test process is a wave control mode, the test data includes a directional angle, a pitch angle, and the like.

[0083] The phased array data stream corresponds to a single-order phased array test; if n orders of phased array tests are performed in sequence, a total data stream consisting of n phased array data streams is generated accordingly.

[0084] For ease of understanding, this embodiment is described in detail with the phased array test mode being the wave control mode. When the phased array test mode is other modes, the execution logic of S200 is the same as that in this embodiment, and only the processing content of the phased array data processing specifically executed is different, which will not be repeated here.

[0085] In this embodiment, the phased array test mode is a wave control mode, and the test data is initial data obtained based on the wave control mode; the test parameters include correction code information, angle quantization accuracy, windowing information, attenuation threshold and unit factor compensation information, etc.; accordingly, based on the configuration information and the test parameters, the processing content of the corresponding phased array data processing performed on the test data includes phase processing and attenuation processing.

[0086] In a specific embodiment, when step S200 is executed, Figure 2 As shown, the following steps are included:

[0087] S210, performing phase processing on the test data based on the configuration information and the test parameters to obtain a phase processing result;

[0088] Specifically, phase processing is performed on a single batch of test data to obtain a phase processing result of the current batch.

[0089] S220, performing attenuation processing on the test data based on the configuration information and the test parameters to obtain an attenuation processing result;

[0090] Specifically, attenuation processing is performed on a single batch of test data to obtain an attenuation processing result of the current batch.

[0091] S230, performing data reconstruction on the phase processing result and the attenuation processing result to obtain the unit data corresponding to each antenna unit;

[0092] Specifically, when step S230 is executed, Figure 3 As shown, including:

[0093] S231, combining the phase processing result and the attenuation processing result to obtain first phased array data;

[0094] Specifically, the phase processing result and the attenuation processing result are physically combined to obtain combined first phased array data.

[0095] S232: Based on the configuration information, perform shift splicing processing on the first phased array data to obtain unit data corresponding to each of the antenna units.

[0096] Specifically, in the first phased array data, data segments corresponding to each of the antenna units are respectively extracted; wherein the data segments have corresponding data types;

[0097] Based on the data location information in the configuration information, determine the location information of each data type in the data transmission channel, that is, determine the location information of each data segment corresponding to a single antenna unit in the data transmission channel;

[0098] According to the position information of each data segment in the data transmission channel, for each data segment corresponding to a single antenna unit, respectively perform a shift operation corresponding to the position information;

[0099] The shifted data segments are concatenated to obtain the unit data corresponding to each antenna unit.

[0100] In a specific embodiment, the data types corresponding to the data segment include: transmission attenuation, reception attenuation, transmission phase and reception phase, and each data type is 32 bits.

[0101] S240: Based on the configuration information, perform shift splicing processing on the first phased array data to obtain unit data corresponding to each of the antenna units.

[0102] In another specific embodiment, when step S200 is executed, Figure 4 As shown, the following steps are included:

[0103] S201, obtaining the number of units in the first configuration information, and determining the number of construction times based on the number of units;

[0104] In this embodiment, the number of the unit data to be constructed is the same as the number of units.

[0105] S202, repeatedly executing unit data construction on the test data according to the construction number and based on the test parameters, so as to obtain the unit data corresponding to the corresponding construction order;

[0106] For example, when the number of units is 5, it is necessary to repeat the phased array unit data construction for 5 times on the test data; the data result obtained by the first phased array unit data construction is used as the unit data corresponding to the first construction order; the data result obtained by the second phased array unit data construction is used as the unit data corresponding to the second construction order; and so on, to obtain the unit data corresponding to each construction.

[0107] In an optional embodiment, the phased array unit data is constructed in a single execution, such as Figure 5 As shown, including:

[0108] S2021, performing phase processing on the test data based on the configuration information and the test parameters to obtain a phase processing result corresponding to the current order;

[0109] S2022, performing attenuation processing on the test data based on the configuration information and the test parameters to obtain an attenuation processing result corresponding to the current order;

[0110] It should be noted that, during a single execution, the test parameters correspond to the antenna units corresponding to the current construction order; for example, for the construction order corresponding to the first antenna unit, during the construction process of the phased array unit data corresponding to the construction order, the test parameters are the test parameters corresponding to the first antenna unit.

[0111] S2023: Perform a first data reconstruction on the phase processing result and the attenuation processing result according to the configuration information to obtain the unit data corresponding to the current order.

[0112] Wherein, the unit data has a preset data structure; the data structure includes the position and bit width of the phase information and the attenuation information;

[0113] Specifically, according to the data structure, data shifting and splicing processing are performed on the phase processing result and the attenuation processing result respectively, and the spliced ​​data string is set as the unit data corresponding to the current construction number.

[0114] Exemplarily, the width of a single unit data is 27 bits, and the 27 bits are allocated to different phased array data, i.e., bits 27-22 are transmit attenuation bits, bits 21-16 are transmit phase shift bits, bits 15-10 are receive attenuation bits, bits 9-4 are receive phase shift bits, bit 3 is a reserved bit, bit 2 is a transmit switch bit, and bit 1 is a receive switch bit; the phased array data corresponding to each antenna unit is encapsulated in the form of the unit data to ensure that the phased array data corresponding to each antenna unit can be transmitted through the 27-bit data transmission channel, thereby simplifying the complexity of data transmission and processing.

[0115] S203, sorting the unit data corresponding to each construction order according to the configuration information to obtain a phased array data stream.

[0116] Specifically, according to the unit position and unit mapping information in the configuration information, the unit data corresponding to each construction order is spliced ​​to obtain the phased array data stream.

[0117] In a specific implementation, the implementation method of performing phase processing on the test data is as follows: Figure 6 As shown, including:

[0118] S2021A, based on the test data and according to the correction code information in the test parameters, performing phased array scanning angle correction, unit pattern factor compensation and angle resolution to obtain the first phase array;

[0119] Specifically, according to the angle correction table and unit factor compensation information in the test parameters, phased array scanning angle correction and unit pattern factor compensation are performed; the frequency information, azimuth angle, elevation angle information and unit position information in the test data, as well as the angle quantization accuracy in the test parameters are calculated to obtain the first phase array.

[0120] Exemplarily, when the azimuth angle is 25.67 degrees and the quantization accuracy is 0.01, the input information is set to 2567; when the azimuth angle is a negative number, the input information is set in a complement manner.

[0121] S2021B, performing beamforming and corresponding sum and difference beamforming according to the test parameters to obtain a second phase array;

[0122] Specifically, the test parameters include a preset beamforming type; according to the selected beamforming type, corresponding beamforming and sum-difference beamforming are performed to obtain a second phase array;

[0123] More specifically, the method for acquiring the sum and difference beams includes:

[0124] Beamforming is performed according to the number of units and the unit positions in the phased array test parameters in combination with the arrangement in the test parameters, and corresponding phase flips are performed on the sum beam, azimuth difference beam and elevation difference beam in the phased array data.

[0125] S2021C, extracting a preset unit phase shift code from the test data, and generating a third phase array according to the unit phase shift code;

[0126] The unit phase shift code is pre-configured and used to compensate for the phase deviation of each unit caused by factors such as temperature change and equipment aging.

[0127] Specifically, the extracted unit phase shift code is used to generate a third group of phase arrays, so as to calibrate the phase of each unit in the phased array based on the third group of phase arrays to ensure correct formation and pointing of the beam.

[0128] S2021D, perform comprehensive processing on the first phase array, the second phase array, and the third phase array to obtain a comprehensive phase array, and use the comprehensive phase array as the phase processing result.

[0129] In a specific embodiment, the attenuation processing is performed on the test data as follows: Figure 7 As shown, including:

[0130] S2022A, performing windowing processing on the test data based on the test parameters to obtain a first amplitude array;

[0131] Specifically, a corresponding window function is determined according to the test parameters; based on the window function, a calculation is performed on the amplitude in the test data, and the calculation result is used as the first amplitude array.

[0132] S2022B, extracting a preset unit attenuation code from the phased array data, and generating a second amplitude array according to the unit attenuation code;

[0133] The unit attenuation code is attenuation information related to a communication unit (such as an antenna unit), and is used to determine the degree of signal loss during transmission.

[0134] Specifically, after the unit attenuation code is extracted, a second amplitude array is generated according to the obtained unit attenuation code, which is used to describe the signal strength of each unit after adjustment.

[0135] S2022C, comprehensively process the first amplitude array and the second amplitude array to obtain a comprehensive amplitude array; perform unit attenuation detection on the comprehensive amplitude array, and use the comprehensive amplitude array after detection as the attenuation processing result.

[0136] The comprehensive amplitude array includes the amplitude information and attenuation information of the signal corresponding to each unit.

[0137] Specifically, after obtaining the comprehensive amplitude array, detect whether the attenuation information corresponding to each unit is greater than a first threshold value. If so, turn off the current unit to prevent signal loss; if not, further detect whether the attenuation information corresponding to the current unit is greater than a second threshold value. When it is greater than the second threshold value, set the attenuation corresponding to the current unit to the second threshold value to prevent further signal loss; when it is less than or equal to the second threshold value, continue to keep the current attenuation information unchanged; based on this step, traverse all units until all units complete the unit attenuation detection.

[0138] The first threshold is greater than the second threshold; exemplarily, the first threshold is 10 and the second threshold is 5.

[0139] S300, sending the phased array data stream to a phased array device, so that the phased array device performs a corresponding phased array operation according to the phased array data stream and returns a phased array operation result.

[0140] Specifically, when step S300 is executed, Figure 8 As shown, including:

[0141] S301, dividing the phased array data stream into a plurality of phased array unit arrays according to the unit mapping quantity;

[0142] The phased array unit array is a phased array data string corresponding to a single chip, and is used to enable the chip to control each of the connected antenna units according to the phased array data string.

[0143] Specifically, the phased array data stream is divided according to the unit mapping quantity, so as to divide the phased array data stream into a plurality of phased array unit arrays; each of the phased array unit arrays corresponds to the chip one by one;

[0144] Exemplarily, when the phased array data stream is composed of 108 unit data and the number of unit mappings is 4, the number of phased array unit arrays is 27 (108 / 4=27).

[0145] S302, storing each phased array unit array in the phased array data stream into a corresponding storage space according to a preset storage mapping relationship;

[0146] The storage spaces correspond to the chips one to one, that is, the first chip corresponds to the first storage space, the second chip corresponds to the second storage space, and so on.

[0147] According to the storage mapping relationship, the phased array unit array is pre-stored in the cache area corresponding to the chip, so that each phased array unit array in the single batch phased array data stream is respectively stored in the cache area corresponding to each chip.

[0148] Exemplarily, the number of units is 128, the number of unit mappings is 4, the chip data is 32, the corresponding storage space is 32, and each storage space corresponds to a chip one-to-one; then the data corresponding to the first to fourth units are stored in the storage space corresponding to the first chip, the data corresponding to the fifth to eighth units are stored in the storage space corresponding to the second chip, and so on, and the data of the last four units are stored in the storage space corresponding to the thirty-second chip.

[0149] It should be noted that, since only part of the data segments in each unit data contain valid phased array data information, in order to better match the data transmission protocol requirements corresponding to the phased array chip, when constructing the phased array unit array, it is necessary to perform data extraction on each of the unit data to extract the data segments of valid phased array data information from each of the unit data. For example, when each unit data is 32 bits and the valid phased array data information is the last 27 bits of each unit data, the last 27 bits of the data segments in each unit data are cut out and stored in the corresponding storage area in sequence.

[0150] For example, when the phased array unit array is 108 bits, and the unit data of a single phased array corresponds to the phased array information containing 4 unit data, that is, the length of the data segment that can be extracted from each unit data is 27 bits, and shift splicing is performed on the extracted data segment. The actual coding length is 27*4=108 bits, and the last 27 bits of the four 32-bit registers are bit-spliced, and then 20 bits of 0 are added in front; for four u32 type values ​​A, B, C, and D, assuming that A is the high-order channel and D is the low-order channel, the specific operation can be A=(A>>15)&0xfff; B=(A<<17)+((B>>10)&0x1ffff); C=(B<<22)+(C>>5)&0x3fffff); D=(C<<27)+(D&0x7ffffff).

[0151] More specifically, for each data segment corresponding to a single antenna unit, the last 27 bits of data with relatively low medians in each data segment are taken out and shifted and spliced ​​to the corresponding data bits, that is, the transmit attenuation is shifted to the 27th bit, the transmit phase shift is shifted to the 21st bit, the receive attenuation is shifted to the 15th bit, and the receive phase shift is shifted to the 9th bit.

[0152] S303, based on a chip transmission protocol, transmitting the phased array unit arrays in each of the storage spaces to the corresponding chip in parallel, and enabling the chip to perform corresponding phased array operations according to the phased array unit arrays.

[0153] Specifically, after the storage, a corresponding enabling instruction and storage address information are sent to the chip, so that the chip obtains the phased array unit array in the corresponding storage space in parallel according to the storage address and the chip transmission protocol;

[0154] And, sending an enable instruction to the chip, so that the chip performs corresponding phased array operations according to the phased array unit array, and returns the phased array operation results, so as to obtain corresponding phased array test results according to the returned operation results.

[0155] Exemplarily, if the returned operation result is consistent with the reference result, it indicates that the phased array device is normal; if the returned operation result is inconsistent with the reference result, it indicates that the phased array device is abnormal.

[0156] In order to solve the technical problems existing in the prior art, the present application also provides a phased array test system for performing phased array test processing related to phased array testing, and sending phased array data streams to connected phased array devices so that the phased array devices perform corresponding phased array operations according to the phased array data stream results.

[0157] The phased array test processing includes performing corresponding application layer processing on the test data based on the phased array test items (such as phase test and attenuation test), and performing data reconstruction processing on the application layer processing results to convert the application layer processing result data into a phased array data stream that can be recognized and executed by the phased array device.

[0158] Specifically, the application layer operation includes but is not limited to phase processing and attenuation processing, etc.; the underlying data processing is the underlying data processing involved in the application layer operation, including but not limited to logical operations, data storage and data transmission, etc.

[0159] See also Fig. 9 , showing a schematic diagram of an application environment of the phased array test system provided in the present application in one embodiment.

[0160] like Fig. 9 As shown, one end of the phased array test system 100 is communicatively connected to the external device 200 for obtaining the configuration information, test parameters and test data input by the external device 200; and the other end of the phased array test system 100 is connected to the phased array device 300, so as to perform a phased array test process on each test data based on the configuration information and the test parameters and using the test data; that is, the phased array test system 100 performs phased array test processing on the received test data to obtain a phased array data stream, and transmits each phased array data stream to the phased array device 300, so that the phased array device 300 performs a corresponding phased array operation according to the phased array data stream to return a corresponding operation result.

[0161] Among them, the phased array device includes a chip 310 and an antenna unit 320; the chip 310 is a chipset composed of M chips; the antenna unit 320 is an antenna unit group composed of N antenna units; M and N are both integers greater than 2; the chipset works together to jointly perform phased array test operations on the antenna unit group; a single chip connects several antenna units to efficiently realize efficient and coordinated control of multiple antenna units by a single chip; exemplarily, a single chip connects and controls 4 antenna units.

[0162] Wherein, the phased array testing process adopts any of the phased array equipment testing methods described above.

[0163] In addition, those skilled in the art may appreciate that the external device described in this embodiment includes but is not limited to a PC, a terminal or a server, etc.

[0164] In some optional embodiments, the phased array test system includes a device, terminal or server equipped with an SDK (Software Development Kit) for implementing functional design of phased array device testing and implementing communication settings with the phased array device.

[0165] See also Fig.10 , which is a schematic diagram of the specific structure of the phased array test system in one embodiment. Fig.10 As shown, the phased array test system includes:

[0166] External transmission unit 110, phased array data processing unit 120, sending unit 130 and register unit 140;

[0167] The external transmission unit 110 is connected to the external device 200 and the register unit 140, and is used to obtain configuration information related to the phased array device 300, and to obtain test data and test parameters related to the test process, and store the configuration information and the test parameters in the register unit 140;

[0168] The phased array data processing unit 120 includes a first end and a second end, wherein the first end is connected to the register unit 140 and is used to obtain the configuration information and the test parameters; the second end of the phased array data processing unit 120 is connected to the transmission unit 110 and is used to obtain test data, and according to the phased array test mode, in combination with the test parameters and the configuration information, performs corresponding phased array data processing on the test data to obtain a processed phased array data stream;

[0169] The sending unit 130 includes a first end, a second end and a third end, wherein the first end is connected to the phased array data processing unit 120 and is used to obtain the phased array data stream;

[0170] The second end of the sending unit 130 is connected to the register unit, and is used to store each phased array unit array in the phased array data stream in the corresponding register unit;

[0171] The third end of the sending unit 130 is connected to the phased array device 300 , and is used to send the phased array unit arrays stored in each register unit to the phased array device 300 in parallel.

[0172] In an optional implementation, the phased array test system 100 is a controller; the external transmission unit 110 and the phased array data processing unit 120 are respectively corresponding functional units in the controller; illustratively, the phased array test system 100 is a microcontroller unit (MCU).

[0173] In an optional embodiment, the phased array data processing unit 120 is as follows: Fig.11 As shown, it includes: a test operation module 121 and a data adaptation module 122, and the test operation module 121 is connected to the data adaptation module 122.

[0174] The test operation module 121 is used to perform the application layer processing corresponding to the phased array test to obtain corresponding application layer processing result data; the application layer processing process includes but is not limited to phase processing and attenuation processing, etc.;

[0175] The data adaptation module 122 is connected to the test operation module 121 and is used to perform data reconstruction processing on each application layer processing result data output by the test operation module 121 so that the reconstructed application layer processing result data can adapt to the phased array device.

[0176] Specifically, when the test operation module 121 performs phase processing and attenuation processing under the wave control mode, the data adaptation module 122 is used to perform data reconstruction processing on the phase processing results and attenuation processing results output by the test operation module 121; wherein, the implementation method of the data reconstruction processing is the same as the implementation method in the above-mentioned embodiment, and will not be repeated here.

[0177] In a specific implementation, the test operation module includes a phase processing submodule and an attenuation processing submodule;

[0178] The phase processing submodule is used to implement phase processing on the phased array data; the specific implementation of the phase processing is the same as that in the above-mentioned embodiment, and will not be repeated here;

[0179] The attenuation processing submodule is used to implement attenuation processing on the phased array data; the specific implementation method of the attenuation processing is the same as that in the above-mentioned embodiment, and will not be repeated here.

[0180] In a specific implementation, the sending unit 130 is as follows: Fig.12 As shown, it includes: a read-write module 131, a value assignment module 132, an addressing and writing module 133, a timing module 134 and a control module 135; the following will be combined Fig.12 , and each module is introduced in detail.

[0181] 1) Reading and writing module 131

[0182] The read / write module 131 is connected to the data adapter module 122 in the phased array data processing unit through a bus, and is used to obtain each input data input by the data adapter module 122; and the read / write module 131 is also connected to the register unit and the chip, and is used to store the input data in the register unit and allow the chip to read the data; wherein the input data includes phase control information and read / write status information. Exemplarily, the data stored in the register unit is 32 bits.

[0183] 2) Value assignment module 132

[0184] The input end of the value assignment module 132 is connected to the read-write module 131, and is used to obtain the phase control information and read-write status information transmitted by the read-write module 131; its output end is connected to the addressing and writing module 133, and is used to control whether to write the phase control information to the addressing and writing module 133 according to the read-write status information.

[0185] The read-write status information includes a read-write status and a non-read-write status.

[0186] When the read-write status information is in the read-write state, the phase-controlled information is written into the addressing and writing module 133; when the read-write state is in the non-read-write state, the value assignment module 132 stops writing the phase-controlled information into the addressing and writing module 133 to prevent the timing module 134 from continuously coding (i.e. continuously writing information into the addressing and writing module 133).

[0187] More specifically, the input signals of the value assignment module 132 are: clk_100mhz, clear, slv_reg_wren, slv_reg_rden, slv_reg0[31:0]~slv_reg255[31:0], a total of 256 registers; and the output signals of the value assignment module 132 are: slv_reg0[31:0]~slv_reg255[31:0], a total of 256 registers.

[0188] Among them, slv_reg_wren is used to determine whether it is in the data writing state; slv_reg_rden is used to determine whether it is in the data reading state;

[0189] Clear is used to clear slv_reg0.

[0190] It should be noted that the value assignment module 132 only reads and writes the data stored in the register unit in the non-read and write stage; slv_reg0 is used as the input of the timing module 134. When it is equal to 1, the timing module 134 is started, and slv_reg0 is still 1 after executing its function; its value needs to be cleared to prevent the timing module 134 from continuously encoding; therefore, after the timing module 134 executes its function, the clear output is 1; the value assignment module 132 determines whether the read-write module 131 is in the working stage according to slv_reg_wren and slv_reg_rden, and clears slv_reg0 when it is in the non-read-write stage, and then the TR timing module 134 detects that slv_reg0 is 0 and clear is 1, and then sets clear to 0, and then enters the normal mode and waits for the next trigger.

[0191] 3) Addressing and writing module 133

[0192] The addressing and writing module 133 is connected to the value assignment module 132 and the register unit, and is used to write the input phased array data stream into the corresponding register unit in sequence according to the address; that is, each phased array unit array in the phased array data stream is written into the corresponding register unit according to the corresponding storage address;

[0193] Furthermore, the addressing and writing module 133 is also connected to the timing module 134 , so as to output each phased array unit array in the same phased array data stream to the chip in parallel based on the timing control of the timing module 134 .

[0194] More specifically, the input signals of the addressing and writing module 133 are: clk, address[31:0], data[127:0]; the output signals of the addressing and writing module 133 are: Data[0][127:0], Data[1][127:0], Data[2][127:0], Data[ND][127:0].

[0195] Among them, clk is 100mhz;

[0196] The input of address is slv_reg1, and the input of data is slv_reg2 to slv_reg5.

[0197] It should be noted that the position of the register unit can be specifically set according to the requirements; that is, the specific setting number of the register unit can be determined according to the length of data to be transmitted on a physical Data.

[0198] 4) Timing module 134

[0199] The timing module 134 is connected to the phased array data processing unit 120, the chip 310 and the register unit 140, and is used to send the phased array unit arrays in each register unit to each chip in parallel according to the timing of the chip and the input control signal.

[0200] Specifically, the phased array data processing unit 120 also transmits the corresponding control instruction to the timing module 134 to control the timing module 134 to send the phased array unit array to the chip; otherwise, the phased array unit array is only temporarily stored in the register unit, waiting to be switched when the next instruction arrives. This module can adjust the trigger timing to adapt to different chips by changing the timing; that is, by setting the timing pin as address data, using multiple modules to address and write numbers, so as to achieve adaptation to different chips.

[0201] In an optional implementation, the control instruction is a level trigger signal; that is, when the timing module 134 receives the level trigger signal, it sends the array of control units to the chip according to the chip protocol.

[0202] It should be noted that, in addition to the data pin, the chip also includes a clock pin, a chip select pin, and a latch pin. For different chips, the data structure is different, but the chip protocol and pins are basically the same. In the sending unit 130, the code cannot be parameterized in real time, so the preset timing module 134 needs to meet the chip protocol and pins consistent with the chip; of course, pins other than data, such as clock, chip select, etc., can also realize arbitrary waveforms by addressing and writing numbers, which will not be repeated here.

[0203] The control module 135 is connected to the phased array data processing unit 120 and the chip 310, and is used to control the chip to perform corresponding phased array operations, such as transmission state, reception state and load state, according to the control instructions issued by the phased array data processing unit 120, so as to realize the transmission and reception of electromagnetic waves and the silencing of the phased array device. The issued transmission and reception instruction information is stored in certain specific register units.

[0204] In summary, the phased array test device and method provided in the embodiment of the present application obtain configuration information related to the chip to be tested, and obtain test data and test parameters related to the test process; perform corresponding phased array data processing on the test data based on the test parameters, and perform data reconstruction on the phased array data processing results based on the configuration information, so that the processing result data can be conveniently and efficiently adapted to the phased array chip, and can adapt to the needs of different phased array chips without redesigning the hardware circuit. The test device and method of the present application have high adaptability. Compared with the prior art, it can better meet various needs in the actual research and development test process, which not only improves the versatility, but also significantly improves the efficiency of phased array testing.

[0205] The above contents are further detailed descriptions of the embodiments of the present invention in combination with specific implementation methods, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the field of the art to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

[0206] Finally, it should be noted that the above description is only a preferred embodiment of the present invention. Under the guidance of the present invention, ordinary technicians in this field can make various similar expressions without violating the purpose and claims of the present invention, and such changes all fall within the scope of protection of the present invention.

Claims

1. A phased array device testing method, characterized in that: include: Obtaining configuration information related to the phased array device and obtaining test parameters corresponding to the test mode; Based on the configuration information and the test parameters, performing application layer processing corresponding to the test mode on the input test data, and performing data reconstruction on the application layer processing result data, so as to obtain a phased array data stream adapted to the phased array device; Sending the phased array data stream to the phased array device, so that the phased array device performs corresponding phased array operations according to the phased array data stream and returns the phased array operation results; The phased array device includes a chip and a plurality of antenna units connected to the chip.

2. The phased array device testing method according to claim 1, characterized in that: When the test mode is the wave control mode, the application layer processing includes phase processing and attenuation processing, and the data reconstruction of the application layer processing result data includes: combining the phase processing result and the attenuation processing result to obtain first phased array data; Based on the configuration information, performing shift splicing processing on the first phased array data to obtain unit data corresponding to the antenna unit; The unit data are sorted to obtain the phased array data stream.

3. The phased array device testing method according to claim 2, characterized in that: The implementation method of performing shift stitching processing on the first phased array data includes: Extracting data segments corresponding to each of the antenna units from the first phased array data; According to the position information of the data type corresponding to the data segment in the data transmission channel, respectively performing a shift operation corresponding to the position information on each data segment corresponding to a single antenna unit; The shifted data segments are concatenated to obtain the unit data corresponding to each antenna unit.

4. The phased array device testing method according to claim 1, characterized in that: The method for acquiring the phased array data stream includes: Obtaining the number of units in the configuration information, and determining the number of construction times based on the number of units; According to the number of constructions, based on the test parameters, repeatedly executing unit data construction on the test data to obtain unit data corresponding to a corresponding construction sequence; The unit data corresponding to each construction order are sorted according to the configuration information to obtain a phased array data stream.

5. The phased array device testing method according to claim 4, characterized in that: The unit data is constructed in a single execution, including: Based on the configuration information and the test parameters, performing phase processing on the test data to obtain a phase processing result corresponding to the current build order; and based on the configuration information and the test parameters, performing attenuation processing on the test data to obtain an attenuation processing result corresponding to the current build order; According to the configuration information, data shifting and splicing processing is performed on the phase processing result and the attenuation processing result to obtain unit data corresponding to the current construction number.

6. The phased array device testing method according to claim 1, characterized in that: The sending the phased array data stream to the phased array device includes: Dividing the phased array data stream into a plurality of phased array unit arrays according to the number of unit mappings; Storing each of the phased array unit arrays in a corresponding storage space according to a preset storage mapping relationship; The phased array unit arrays in each of the storage spaces are transmitted in parallel to the corresponding chip, so that the chip performs the corresponding phased array operation according to the phased array unit arrays; Wherein, the phased array unit array corresponds to a single chip.

7. A phased array test system, characterized in that: connected between the external device and the phased array device, and used to obtain the configuration information, test parameters and test data input by the external device, and based on the configuration information and the test parameters, use the test data to perform a phased array test process on each of the test data; Wherein, the phased array device includes a chip and a plurality of antenna units connected to the chip; and the phased array test process adopts the phased array device test method as described in any one of claims 1 to 6.

8. The phased array test system according to claim 7, characterized in that: include: A register unit for storing data; a transmission unit, connected to the external device and the register unit, configured to obtain the configuration information, the test parameters and the test data input by the external device, and store the configuration information and the test parameters in the register unit; A phased array data processing unit, comprising a first end and a second end, the first end being connected to the register unit and used to obtain the configuration information and the test parameters; the second end being connected to the transmission unit and used to obtain test data, and performing corresponding phased array data processing on the test data in combination with the test parameters and the configuration information to obtain a processed phased array data stream; The sending unit comprises a first end, a second end and a third end, wherein the first end is connected to the phased array data processing unit and is used to obtain the phased array data stream; the second end of the sending unit is connected to the register unit and is used to store each phased array unit array in the phased array data stream in the corresponding register unit; the third end of the sending unit is connected to the chip and is used to send the phased array unit arrays stored in each register unit to the chip in parallel.

9. The phased array test system according to claim 8, characterized in that: The phased array data processing unit comprises: A test operation module, used for performing phase processing and attenuation processing in a wave control mode; The data adaptation module is connected to the test operation module and is used to perform data reconstruction on the phase processing result and the attenuation processing result output by the test operation module to obtain a processed phased array data stream.

10. The phased array test system according to claim 8, characterized in that: The sending unit includes: a reading and writing module, a value assignment module, an addressing and writing module, a timing module and a control module; wherein, The read / write module is connected to the phased array data processing unit, the chip and the register unit, and is used to store the phased array data stream input by the phased array data processing unit into the register unit; and is used for the chip to read data; The input end of the value assignment module is connected to the read-write module for obtaining the read-write status information of the read-write module; the output end of the value assignment module is connected to the addressing and writing module for controlling whether to write data to the addressing and writing module according to the read-write status information; The addressing and writing module is respectively connected to the value assignment module and the register unit, and is used to write the input phased array data stream into the corresponding register unit in sequence; and the addressing and writing module is also connected to the timing module, so as to output each phased array unit array in the same phased array data stream to the chip in parallel based on the timing control of the timing module; The timing module is connected to the phased array data processing unit, the chip and the register unit, and is used to send the phased array unit arrays in each register unit to each chip in parallel; The control module is connected to the phased array data processing unit and the chip, and is used to control the chip to perform corresponding phased array operations according to control instructions issued by the phased array data processing unit.

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