Phased array device testing method and system

Abstract

The application provides a phased array device testing method and system, wherein the method comprises: based on the configuration information and the test parameters, performing application layer processing corresponding to the test mode on input test data, and performing data reconstruction on the application layer processing result data to obtain phased array data flow adapted to the phased array device; and delivering the phased array data flow to the phased array device, so that the phased array device performs corresponding phased array operation according to the phased array data flow and returns phased array operation results; the application can adapt to different phased array devices, not only improving the universality, but also significantly improving the efficiency of phased array testing.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of phased array testing, in particular, relates to a phased array device testing method and system. BACKGROUND

[0002] As an important device in a phased array radar detection / communication system, the stability of the working performance of the phased array device will directly affect the system stability of the entire system; therefore, before performing corresponding phased array operations by using the phased array device, the phased array device needs to be tested to ensure the stability of the working performance of the device.

[0003] In the phased array device testing, various functions such as angle solution and compensation, sum-difference beam forming, calibration code correction and compensation, and unit code control are usually included; when executing the function instructions corresponding to the above functions, the phased array data stream related to the function instructions often needs to be transmitted to the phased array device, so that the device performs the phased array operation corresponding to the phased array data stream; based on this, the phased array data stream often needs to match the architecture parameters and / or data structure parameters of the phased array device to ensure that the testing process matches the phased array device.

[0004] In the prior art, a hardware description language (HDL) is usually used to generate a test program matching the architecture parameters and / or data structure parameters of the phased array device in the FPGA platform; however, since the code corresponding to the hardware description language cannot be parameterized in real time, when the phased array device is replaced, the architecture parameters and / or data structure parameters of the phased array device will change, so not only the program parameters in the test program corresponding to the architecture parameters or data structure parameters need to be modified accordingly, but also the code associated with the program parameters needs to be adjusted for adaptability, resulting in poor generality of the existing phased array device testing method, which is difficult to quickly and conveniently match different types of phased array devices. In addition, when the phased array device is replaced, the adjusted test program often needs to be re-executed for verification (the newly generated digital circuit is verified) by using the FPGA platform, and when there is a verification problem, the code needs to be adjusted in the code design stage, resulting in further reduction of testing efficiency. In addition to this, when the phased array device is replaced, there is often a risk that the code cannot be fully verified, resulting in reduced testing accuracy, etc.

[0005] Therefore, how to improve the adaptability and generality of the phased array device testing method has become a technical problem to be solved in the field. SUMMARY

[0006] The application aims to provide a phased array device testing method and system, which solves the technical problems of poor adaptability of the existing phased array device testing method and system to different phased array devices, weak generality of the phased array device testing method and system, and inconvenient use.

[0007] To solve the above technical problems, the application provides a phased array device testing method in the first aspect, which is characterized by comprising:

[0008] Obtaining configuration information related to the phased array device and obtaining test parameters corresponding to the test mode; based on the configuration information and the test parameters, performing application layer processing corresponding to the test mode on the input test data, and performing data reconstruction on the application layer processing result data to obtain phased array data flow adapted to the phased array device; and downloading the phased array data flow into the phased array device, so that the phased array device performs corresponding phased array operation according to the phased array data flow and returns the phased array operation result; wherein the phased array device comprises a chip and a plurality of antenna units connected to the chip.

[0009] In an optional embodiment, when the test mode is a wave control mode, the application layer processing includes phase processing and attenuation processing, and the data reconstruction on the application layer processing result data includes:

[0010] Combining the phase processing result and the attenuation processing result to obtain first phased array data; based on the configuration information, performing shift splicing processing on the first phased array data to obtain unit data corresponding to the antenna units; and sorting each unit data to obtain the phased array data flow.

[0011] In an optional embodiment, the implementation mode of the shift splicing processing on the first phased array data includes:

[0012] In the first phased array data, data segments corresponding to each antenna unit are extracted; according to the position information of the data type corresponding to the data segment in the data transmission channel, each data segment corresponding to a single antenna unit is respectively subjected to a shift operation corresponding to the position information; and the shifted data segment is spliced to obtain the unit data corresponding to each antenna unit.

[0013] In an optional embodiment, the acquisition mode of the phased array data flow includes:

[0014] obtaining a number of units in the configuration information, determining a number of constructions based on the number of units, repeatedly performing unit data construction on the test data based on the test parameters according to the number of constructions to obtain unit data corresponding to a respective construction order, and sorting the unit data corresponding to the respective construction order according to the configuration information to obtain the phased array data stream.

[0015] In an optional embodiment, the unit data construction is performed in a single execution, including:

[0016] performing phase processing on the test data based on the configuration information and the test parameters to obtain a phase processing result corresponding to a current construction order, performing attenuation processing on the test data based on the configuration information and the test parameters to obtain an attenuation processing result corresponding to the current construction order, and performing data shifting and splicing processing on the phase processing result and the attenuation processing result according to the configuration information to obtain unit data corresponding to the current construction order.

[0017] In an optional embodiment, the phased array data stream is transmitted to the phased array device, including:

[0018] dividing the phased array data stream into a plurality of phased array unit arrays according to a number of unit mappings, storing each phased array unit array in a corresponding storage space according to a preset storage mapping relationship, and transmitting each phased array unit array in the storage space to a corresponding chip in parallel, so that the chip performs a corresponding phased array operation according to the phased array unit array; wherein the phased array unit array corresponds to a single chip.

[0019] To solve the above technical problems, the present application provides a phased array test system in the second aspect, which is connected between an external device and a phased array device, used to obtain configuration information, test parameters and test data input by the external device, and perform a phased array test process on each test data based on the configuration information and the test parameters using the test data; wherein the phased array device includes a chip and a plurality of antenna units connected to the chip; the phased array test process uses any of the phased array device test methods described above.

[0020] In an optional embodiment, the phased array test system includes:

[0021] The register unit is used for storing data; the transmission unit is connected with the external device and the register unit, and is used for obtaining the configuration information, the test parameter and the test data input by the external device, and storing the configuration information and the test parameter in the register unit; the phased array data processing unit includes a first end and a second end, the first end is connected with the register unit, and is used for obtaining the configuration information and the test parameter; the second end is connected with the transmission unit, and is used for obtaining test data, and the test data is subjected to corresponding phased array data processing combined with the test parameter and the configuration information, so that processed phased array data flow is obtained; the delivery unit includes a first end, a second end and a third end, the first end is connected with the phased array data processing unit, and is used for obtaining the phased array data flow; the second end of the delivery unit is connected with the register unit, and is used for storing each phased array unit array in the phased array data flow in the corresponding register unit; and the third end of the delivery unit is connected with the chip, and is used for sending the phased array unit array stored in each register unit to the chip in parallel.

[0022] In an optional embodiment, the phased array data processing unit includes:

[0023] The test operation module is used for executing phase processing and attenuation processing in the wave control mode; the data adaptation module is connected with the test operation module, and is used for executing data reconstruction on the phase processing result and the attenuation processing result output by the test operation module, so that processed phased array data flow is obtained.

[0024] In an optional embodiment, the delivery unit includes a read-write module, a value assignment module, an addressing and writing number module, a timing module and a control module; wherein,

[0025] The read-write module is connected with the phased array data processing unit, the chip and the register unit, and is configured to store the phased array data stream input by the phased array data processing unit into the register unit, and to read data for the chip; the input end of the value assignment module is connected with the read-write module, and is configured to obtain read-write state information of the read-write module; the output end of the value assignment module is connected with the addressing write number module, and is configured to control whether to write data into the addressing write number module according to the read-write state information; the addressing write number module is connected with the value assignment module and the register unit respectively, and is configured to write the input phased array data stream into the corresponding register unit in sequence; and the addressing write number module is further connected with the timing module, so as to output each phased array unit array in the same phased array data stream to the chip in parallel based on the timing control of the timing module; the timing module is connected with the phased array data processing unit, the chip and the register unit, and is configured to send the phased array unit array in each register unit to each chip in parallel; and the control module is connected with the phased array data processing unit and the chip, and is configured to control the chip to perform a corresponding phased array operation according to a control instruction sent by the phased array data processing unit.

[0026] The phased array testing device and method provided by the embodiments of the present application can obtain configuration information related to a device to be tested, and obtain testing data and testing parameters related to a testing process; perform corresponding phased array data processing on the testing data based on the testing parameters, and perform data reconstruction on the phased array data processing result based on the configuration information, so that the processing result data can be conveniently and efficiently adapted to a phased array device without the need of redesigning a hardware circuit to adapt to the needs of different phased array devices. The testing device and method have high self-adaptability, and compared with the prior art, they can better meet various needs in actual research and development testing processes, improve the universality, and significantly improve the efficiency of phased array testing. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 A flowchart diagram in an embodiment of the phased array device testing method provided by the present application is shown;

[0028] Figure 2 A flowchart diagram in an embodiment of step S200 in the present application is shown;

[0029] Figure 3 A flowchart diagram in an embodiment of step S230 in the present application is shown;

[0030] Figure 4 A flowchart diagram in another embodiment of step S200 in the present application is shown;

[0031] Figure 5 A flowchart showing a process of constructing the phased array unit data in the embodiments of the present application is shown in FIG. 1;

[0032] Figure 6 A flowchart showing a process of performing phase processing on the test data in the embodiments of the present application is shown in FIG. 2;

[0033] Figure 7 A flowchart showing a process of performing attenuation processing on the test data in the embodiments of the present application is shown in FIG. 3;

[0034] Figure 8 A flowchart showing step S300 in the embodiments of the present application is shown in FIG. 4;

[0035] Figure 9 A schematic diagram of an application environment of the phased array test system provided by the present application in an embodiment is shown in FIG. 5;

[0036] Figure 10 A schematic diagram of a specific structure of the phased array test system provided by the present application in an embodiment is shown in FIG. 6;

[0037] Figure 11 A schematic diagram of a specific structure of the phased array data processing unit in the embodiments of the present application is shown in FIG. 7;

[0038] Figure 12 A schematic diagram of a specific structure of the issuing unit in the embodiments of the present application is shown in FIG. 8; DETAILED DESCRIPTION

[0039] The above description can be used by those skilled in the art to easily understand other advantages and effects of the present application. The present application can also be implemented or applied by using different specific embodiments, and the details in the description can be modified or changed based on different views and applications without departing from the spirit of the present application. It should be noted that the embodiments below and the features in the embodiments can be combined with each other without conflict.

[0040] It should be noted that in the following description, reference is made to the accompanying drawings, which illustrate several embodiments of the present application. It should be understood that other embodiments can also be used, and mechanical components, structures, electrical and operational changes can be made without departing from the spirit and scope of the present application.

[0041] As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", as used herein, specify the presence of stated features, operations, elements, components, items, and / or objects, but do not preclude the presence or addition of one or more other features, operations, elements, components, items, and / or objects. The terms "or" and "and / or" as used herein are to be interpreted as inclusive or meaning either or any combination.

[0042] In order to make the objects, technical solutions and advantages of the present application clearer, the further detailed description of the technical solutions in the embodiments of the present application will be given in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application.

[0043] To solve the technical problems in the prior art, the present application first provides a phased array device testing method, which controls the phased array device to perform phased array operations corresponding to the test data according to the externally input phased array test parameters, so as to realize the testing process of the phased array device.

[0044] The phased array device includes a plurality of phased array chips (hereinafter referred to as "chips") and phased array antenna units (hereinafter referred to as "antenna units"). A single chip is connected to a plurality of antenna units and transmits phased array unit data (hereinafter referred to as "unit data") to the connected antenna units, so as to efficiently realize efficient and cooperative control of a single chip on a plurality of antenna units. For example, a single chip is connected to and controls four antenna units.

[0045] The unit data is phased array data corresponding to a single antenna unit, which is used to control the corresponding antenna unit to perform corresponding phased array operations.

[0046] Referring to Figure 1 , a flowchart of the phased array device testing method provided by the embodiments of the present application is shown.

[0047] As Figure 1 shown, the method includes the following sub-steps when executed:

[0048] S100, obtaining configuration information related to the phased array device to be tested, and obtaining test parameters corresponding to the phased array test mode;

[0049] In the present application, the configuration information includes first configuration information and second configuration information.

[0050] The first configuration information is an instruction parameter set for adapting the physical architecture of the antenna unit, that is, the first configuration information is an instruction parameter associated with the antenna unit.

[0051] The second configuration information is an instruction parameter set for adapting the data structure form of the chip, that is, the second configuration information is an instruction parameter associated with the data structure form of the chip.

[0052] In this embodiment, the first configuration information includes the number of units, unit corresponding information, and unit position information.

[0053] The number of units represents the number of antenna units contained in the phased array device; the unit corresponding information represents the corresponding information between the interface pins of the chip and the phased array units; and the unit position information represents the position structure information of each antenna unit in the phased array device.

[0054] Taking the unit position information as an example, the unit position information is configuration information for performing angle calculation, and the unit position information is associated with the position structure of each antenna unit in the phased array device. When the phased array device is replaced, the unit position information will change accordingly.

[0055] More specifically, taking a planar equidistant phased array as an example, the unit position information can be the sum of the number of unit rows, the number of unit columns, the unit row spacing, and the unit column spacing.

[0056] In this embodiment, the second configuration information includes the data length of the chip, the unit transmission sequence, the unit mapping number, the phase shift information, the attenuation bit information, the transceiver state bit information, and the data position information.

[0057] The data length is used to represent the data bit length of the data transmission channel, which is equal to the length of the data transmission of a single chip;

[0058] The unit transmission sequence is used to represent the sequence of data corresponding to different phased array units in the data transmission channel.

[0059] The unit mapping number represents the number of antenna units controlled by a single chip.

[0060] The phase shift information is used to arrange the calculated phase code according to the phase shift information to obtain phase offset information that can control the beam direction. More specifically, the phase shift information includes the number of phase shifters and the wiring method. According to the number of phase shifters and the wiring method, the calculated phase code is arranged according to 0~2 k-1 After the first arrangement is executed, the second arrangement is executed based on the wiring mode to obtain the phase offset mapping table; for example, when the fourth wire and the first wire are physically crossed, the phase code after the first arrangement is converted from XX1XX0 to XX0XX1. For the number of states corresponding to the number of phase shifter bits exceeding the actual number of phase shift states, for example, the nine-bit phase shifter has 2 9 states and 2 6 actual states (representing the minimum step of the phase shift amount is 360° / 2 6 = 5.625°); then, after the first arrangement is executed, the six-bit state needs to be mapped to nine bits before the second arrangement is executed, for example, 010101 is mapped to 100101001 corresponding to the same phase shift amount (the mapping relationship can be obtained by testing the state closer to the ideal phase shift amount), and then the phase offset mapping table is obtained according to the wiring mode.

[0061] The attenuation bit information is used to arrange the calculated attenuation code according to the attenuation bit information to obtain the attenuation offset information that can control the beam amplitude, and the implementation manner is the same as that of the phase shifter bit.

[0062] The transceiver state bit information is information used to represent whether the reception / transmission is effective; more specifically, the transceiver state bit information includes the reception / transmission state length, the reception / transmission state effective code; for example, when the reception state length is 1 and the transmission state length is 1, there are four cases when the reception state effective code is 1 and the transmission state effective code is 0, which are explained below with T representing the transmission state bit and R representing the reception state bit; "T:0, R:0" corresponds to the transmission being effective and the reception being ineffective, "T:0, R:1" corresponds to the transmission being effective and the reception being effective, "T:1, R:0" corresponds to the transmission being ineffective and the reception being ineffective, and "T:1, R:1" corresponds to the transmission being ineffective and the reception being effective.

[0063] The data position information is used to represent the specific position of each type of phased array data arranged in the unit data to adapt to the data structure requirements of the chip; for example, the data position information includes the transmission / reception attenuation position, the transmission / reception phase shifter position, the transmission / reception state position, etc.

[0064] For example, the transmission phase shifter position includes information for controlling the transmission phase shifter state, which needs to be located at a specific position in the data stream.

[0065] For example, the data length includes the number of data bits required for a single chip pin in a single transmission in the chip; for example, when 108 bits of data are required for a single chip pin in a single transmission operation, the data length is set to 108 bits, and the transmission of each test data (such as beam test) is performed based on the data length.

[0066] The phased array test mode is the working mode of the phased array device to be tested; that is, different test modes have corresponding phased array device test processes.

[0067] The test parameters are the instruction parameters that need to be invoked when performing test data processing related to the test operation during the testing process of the phased array device; the test parameters are associated with the phased array test mode. For example, the test parameters include macro-defined parameters, mapping tables, etc.; more specifically, the macro-defined parameters include the number of calibration frequency points, the size of the storage space for single-frequency correction codes, angle quantization accuracy, windowing information, attenuation threshold, pulse information, etc.; the mapping tables include unit factor compensation information, angle correction tables, beamforming tables, unit switching tables, etc.

[0068] The correction code information consists of correction data for all elements after the phased array device has been calibrated.

[0069] The calibration frequency points are used to characterize the number of center frequencies to be calibrated during the formal use of the phased array equipment.

[0070] The size of the storage space for a single frequency point correction code is used to characterize the size of the space for storing the correction code corresponding to a certain frequency point. More specifically, it includes the storage type and storage size. Taking a unit quantity of 64 as an example, the storage type can be a flash chip, and the storage size is 64 * 4 Bytes / 256 Bytes = 1 page.

[0071] The angle quantization precision is used to characterize the minimum step size of angle information in the test data.

[0072] The windowing information is used for calculations during windowing processing to enable the phased array device to operate in different modes. More specifically, it includes windowing dimensions, azimuth / elevation windowing types, azimuth / elevation sidelobe levels, and the number of sidelobes in the azimuth / elevation directions.

[0073] The attenuation threshold is used to maintain the attenuation level and / or shut down the unit when the attenuation exceeds the threshold. More specifically, it includes a first attenuation threshold for receiving / transmitting and a second attenuation threshold for receiving / transmitting.

[0074] The pulse information is used by the control module to control the phased array device to enter the transmit / receive / load state. More specifically, it includes the pulse source, transmit / receive pulses, pulse width, and pulse period.

[0075] The unit factor compensation information is used to reduce the influence of the unit pattern on the beam pointing before angle calculation, so as to achieve a more accurate beam pointing.

[0076] The angle correction table is an angle mapping table that compensates for large errors through reverse testing.

[0077] The beamforming table is used to meet the formation of various beam shapes.

[0078] The unit switch table is used to control the opening or closing of all units in the phased array device.

[0079] In a specific embodiment, the configuration information and the test parameters are pre-stored in a first storage area of the phased array test system; when a start instruction of chip test is received, first identification information related to the phased array device and second identification information related to the test operation are extracted; in the first storage area, based on the first identification information, configuration information corresponding to the phased array device is extracted, and based on the second identification information, test parameters related to the test operation are extracted; and after starting the test of the phased array device, in response to the received communication frames, the test data is extracted from each communication frame, and the test data is transmitted to the phased array device.

[0080] It should be noted that in other specific embodiments, the configuration information and the test parameters can also be set in the communication frame, that is, by receiving the communication frame and extracting the configuration information, the test parameters and the test data from the communication frame, the configuration information related to the device to be tested is quickly obtained by receiving the communication frame, and the test data and the test parameters related to the test process are quickly obtained, further improving the universality and convenience of the method of the present application.

[0081] S200, based on the configuration information and the test parameters, performing application layer processing corresponding to the phased array test mode on the input test data, and performing data reconstruction on the application layer processing result data to obtain phased array data stream adapted to the phased array device;

[0082] The test data is the source data required in the test process of the phased array device; for example, when the phased array test process is the beam control mode, the test data includes the direction angle, the pitch angle, etc.

[0083] The phased array data stream corresponds to a single sequence of phased array test; if n sequences of phased array test are sequentially performed, a total data stream composed of n phased array data streams is correspondingly generated.

[0084] For ease of understanding, this embodiment expands the description with the phased array test mode being the beam control mode; when the phased array test mode is other modes, the execution logic of S200 is the same as in this embodiment, only the processing content of the specific phased array data processing is different, which will not be described here.

[0085] In the embodiment, the phased array test mode is a wave control mode, the test data is based on initial data obtained in the wave control mode, and the test parameters include correction code information, angle quantization precision, windowing information, attenuation threshold, and unit factor compensation information. Correspondingly, based on the configuration information and the test parameters, the processing content of the phased array data processing performed on the test data includes phase processing and attenuation processing.

[0086] In a specific embodiment, when step S200 is executed, it includes the following steps as shown in the following table: Figure 2

[0087] S210, performing phase processing on the test data based on the configuration information and the test parameters to obtain a phase processing result.

[0088] Specifically, phase processing is performed on a single batch of test data to obtain a phase processing result of the current batch.

[0089] S220, performing attenuation processing on the test data based on the configuration information and the test parameters to obtain an attenuation processing result.

[0090] Specifically, attenuation processing is performed on a single batch of test data to obtain an attenuation processing result of the current batch.

[0091] S230, performing data reconstruction on the phase processing result and the attenuation processing result to obtain unit data corresponding to each antenna unit.

[0092] Specifically, when step S230 is executed, it includes the following steps as shown in the following table: Figure 3

[0093] S231, combining the phase processing result and the attenuation processing result to obtain first phased array data.

[0094] Specifically, the phase processing result and the attenuation processing result are physically combined to obtain combined first phased array data.

[0095] S232, performing shift splicing processing on the first phased array data based on the configuration information to obtain unit data corresponding to each antenna unit.

[0096] Specifically, in the first phased array data, data segments corresponding to each antenna unit are extracted respectively, and the data segments have corresponding data types.

[0097] Based on data position information in the configuration information, position information of each data type in a data transmission channel is determined, i.e., position information of each data segment corresponding to a single antenna unit in the data transmission channel is determined.​​

[0098] According to the position information of each data segment in the data transmission channel, for each data segment corresponding to a single antenna unit, a shift operation corresponding to the position information is performed respectively;

[0099] The shifted data segments are spliced to obtain the unit data corresponding to each antenna unit.

[0100] In a specific embodiment, the data type corresponding to the data segment includes transmission attenuation, reception attenuation, transmission phase, and reception phase, and each data type is 32 bits.

[0101] S240, based on the configuration information, performing shift and splice processing on the first phased array data to obtain unit data corresponding to each antenna unit.

[0102] In another specific embodiment, when step S200 is executed, it includes the following steps as shown in the figure: Figure 4

[0103] S201, obtaining the number of units in the first configuration information, and determining the number of constructions based on the number of units;

[0104] In this embodiment, the number of unit data to be constructed is the same as the number of units.

[0105] S202, according to the number of constructions, repeatedly performing unit data construction on the test data based on the test parameters to obtain the unit data corresponding to the corresponding construction order;

[0106] For example, when the number of units is 5, the phased array unit data construction needs to be repeatedly performed 5 times on the test data; the data result obtained by the first phased array unit data construction is taken as the unit data corresponding to the first construction order; the data result obtained by the second phased array unit data construction is taken as the unit data corresponding to the second construction order; and so on, to obtain the unit data corresponding to each construction.

[0107] In an optional embodiment, the phased array unit data construction is performed once, which includes the following steps as shown in the figure: Figure 5

[0108] S2021, based on the configuration information and the test parameters, performing phase processing on the test data to obtain a phase processing result corresponding to the current order;

[0109] S2022, based on the configuration information and the test parameters, performing attenuation processing on the test data to obtain an attenuation processing result corresponding to the current order;

[0110] ​​It should be noted that the test parameter corresponds to the antenna unit corresponding to the current construction order in a single execution; for example, for the construction order corresponding to the first antenna unit, the test parameter corresponding to the first antenna unit in the phased array unit data construction process corresponding to the construction order.

[0111] S2023, according to the configuration information, performing first data reconstruction on the phase processing result and the attenuation processing result to obtain the unit data corresponding to the current order.

[0112] Among them, the unit data has a preset data structure; the data structure includes the positions and bit widths of phase information and attenuation information;

[0113] Specifically, according to the data structure, the phase processing result and the attenuation processing result are respectively executed data shift and splicing processing, and the spliced data string is set as the unit data corresponding to the current construction order.

[0114] Exemplarily, the width of a single unit data is 27 bits, which is allocated as different phased array data, i.e. the 27th-22nd bit is the transmit attenuation bit, the 21st-16th bit is the transmit phase shift bit, the 15th-10th bit is the receive attenuation bit, the 9th-4th bit is the receive phase shift bit, the 3rd bit is the reserved bit, the 2nd bit is the transmit switch bit, and the 1st bit is the receive switch bit; The phased array data corresponding to each antenna unit is packaged in the form of the unit data to ensure that the phased array data corresponding to each antenna unit can be transmitted through the 27-bit data transmission channel, thereby simplifying the complexity of data transmission and processing.

[0115] S203, according to the configuration information, sorting the unit data corresponding to each construction order to obtain a phased array data stream.

[0116] Specifically, according to the unit position and unit mapping information in the configuration information, splicing the unit data corresponding to each construction order to obtain the phased array data stream.

[0117] In a specific embodiment, the implementation of the phase processing on the test data includes: Figure 6 As shown, it includes:

[0118] S2021A, based on the test data, according to the correction code information in the test parameter, performing phased array scan angle correction, unit directional pattern factor compensation and angle calculation to obtain the first phase array;

[0119] Specifically, according to the angle correction table in the test parameter and the element factor compensation information, the scanning angle correction of the phased array and the element pattern factor compensation are performed; the frequency information, the azimuth angle information, the elevation angle information and the element position information in the test data are calculated, and the angle quantization precision in the test parameter is calculated to obtain the first phase array.

[0120] For example, when the azimuth angle is 25.67 degrees and the quantization precision is 0.01, the input information is set to 2567; when the azimuth angle is negative, the input information is set in the complement mode.

[0121] S2021B, according to the test parameter, performing beamforming and corresponding sum and difference beamforming to obtain a second phase array;

[0122] Specifically, the test parameter includes a preset beamforming type; according to the selected beamforming type, corresponding beamforming and sum and difference beamforming are performed to obtain a second phase array;

[0123] More specifically, the sum and difference beamforming includes:

[0124] According to the number of elements and the element position in the phased test parameter, the beamforming is performed in combination with the arrangement mode in the test parameter, and the sum beam, the azimuth difference beam and the elevation difference beam in the phased array data are correspondingly phase flipped.

[0125] S2021C, extracting a preset element phase shift code from the test data, and generating a third phase array according to the element phase shift code;

[0126] The element phase shift code is pre-configured and used to compensate for the phase deviation of each element caused by factors such as temperature change and equipment aging.

[0127] Specifically, the third group of phase arrays is generated by using the extracted element phase shift code, and the phases of the elements in the phased array are calibrated based on the third group of phase arrays to ensure the correct formation and pointing of the beam.

[0128] S2021D, the first phase array, the second phase array and the third phase array are comprehensively processed to obtain a comprehensive phase array, and the comprehensive phase array is taken as the phase processing result.

[0129] In a specific embodiment, the attenuation processing performed on the test data includes: Figure 7 As shown in the figure, the attenuation processing performed on the test data includes:

[0130] S2022A, based on the test parameter, performing windowing processing on the test data to obtain a first amplitude array;

[0131] Specifically, based on the test parameters, a corresponding window function is determined; based on the window function, the amplitude in the test data is calculated, and the calculation result is used as the first amplitude array.

[0132] S2022B, Extract a preset unit attenuation code from the phased array data, and generate a second amplitude array based on the unit attenuation code;

[0133] The unit attenuation code is attenuation information associated with a communication unit (such as an antenna unit), used to determine the degree of signal loss during transmission.

[0134] Specifically, after extracting the unit attenuation code, a second amplitude array is generated based on the obtained unit attenuation code to describe the signal strength of each unit after adjustment.

[0135] S2022C, The first amplitude array and the second amplitude array are combined to obtain a combined amplitude array; the unit attenuation detection is performed on the combined amplitude array, and the detected combined amplitude array is used as the attenuation processing result.

[0136] The integrated amplitude array includes signal amplitude information and attenuation information for each unit.

[0137] Specifically, after acquiring the comprehensive amplitude array, it is detected whether the attenuation information corresponding to each unit is greater than a first threshold. If so, the current unit is turned off to prevent signal loss. If not, it is further detected whether the attenuation information corresponding to the current unit is greater than a second threshold. When it is greater than the second threshold, the attenuation amount corresponding to the current unit is set to the second threshold to prevent further signal loss. When it is less than or equal to the second threshold, the current attenuation information is kept unchanged. Based on this step, all units are traversed until all units have completed the unit attenuation detection.

[0138] Wherein, the first threshold is greater than the second threshold; for example, the first threshold is 10 and the second threshold is 5.

[0139] S300, the phased array data stream is sent to the phased array device, so that the phased array device performs the corresponding phased array operation according to the phased array data stream and returns the phased array operation result.

[0140] Specifically, when step S300 is executed, such as... Figure 8 As shown, it includes:

[0141] S301, Based on the number of unit mappings, the phased array data stream is divided into several phased array unit arrays;

[0142] The phased array unit array is a phased array data string corresponding to a single chip, and is used to control each of the connected antenna units according to the phased array data string.

[0143] Specifically, the phased array data stream is divided according to the unit mapping number, so as to divide the phased array data stream into a plurality of phased array unit arrays; each of the phased array unit arrays is one-to-one corresponding to the chip.

[0144] For example, when the phased array data stream is composed of 108 unit data groups, and the unit mapping number is 4, then the phased array unit array is 27 (108 / 4=27) groups.

[0145] S302, according to the preset storage mapping relationship, each phased array unit array in the phased array data stream is stored in the corresponding storage space;

[0146] The storage space is one-to-one corresponding to the chip, that is, the first chip corresponds to the first storage space, the second chip corresponds to the second storage space, and so on.

[0147] According to the storage mapping relationship, the phased array unit array is pre-stored in the cache area corresponding to the chip, so that each phased array unit array in the single batch of phased array data streams is stored in the cache area corresponding to each chip.

[0148] For example, the unit number is 128, the unit mapping number is 4, the chip data is 32, the corresponding storage space is 32, and each storage space is one-to-one corresponding to the chip; the data corresponding to the first unit to the fourth unit is stored in the storage space corresponding to the first chip, the data corresponding to the fifth unit to the eighth unit is stored in the storage space corresponding to the second chip, and so on, and the data of the last four units is stored in the storage space corresponding to the thirty-second chip.

[0149] It should be noted that since only part of the data segments in each unit data contain valid phased array data information, in order to better match the data transmission protocol requirements corresponding to the phased array chip, data extraction is performed on each unit data when constructing the phased array unit array, so as to extract the data segments of the valid phased array data information in each unit data. For example, when each unit data is 32 bits, and the valid phased array data information is the last 27 bits of each unit data, the last 27 bits of each unit data are cut out and stored in the corresponding storage area in sequence.

[0150] For example, when the phased array unit array is 108 bits, the unit data of a single phased array corresponds to phased array information containing 4 unit data, i.e., the length of the data segment that can be extracted by each unit data is 27 bits, the obtained data segment is subjected to shift splicing, the actual coding length is 27*4=108 bits, the last 27 bits of four 32-bit registers are spliced, and 20 bits of 0 are supplemented in front; for four u32 type values A, B, C, and D, assuming that A is the high-bit channel and D is the low-bit channel, the specific operation can be A=(A>>15)&0xfff; B=(A<<17)+((B>>10)&0x1ffff); C=(B<<22)+(C>>5)&0x3fffff); D=(C<<27)+(D&0x7ffffff).

[0151] More specifically, for each data segment corresponding to a single antenna unit, the last 27 bits of data with relatively low bit numbers in each data segment are extracted and spliced to the corresponding data bits after shifting, i.e., the transmission attenuation bit is shifted to the 27th bit, the transmission phase shift bit is shifted to the 21st bit, the reception attenuation bit is shifted to the 15th bit, and the reception phase shift bit is shifted to the 9th bit.

[0152] S303, based on the chip transmission protocol, the phased array unit array in each of the storage spaces is transmitted to the corresponding chip in parallel, and the chip performs corresponding phased array operations according to the phased array unit array.

[0153] Specifically, after storage, the corresponding enable instruction and storage address information are sent to the chip, so that the chip acquires the phased array unit array in the corresponding storage space in parallel according to the storage address and the chip transmission protocol;

[0154] In addition, the enable instruction is sent to the chip, so that the chip performs corresponding phased array operations according to the phased array unit array and returns the phased array operation result, so as to obtain the corresponding phased array test result according to the returned operation result.

[0155] For example, if the returned operation result is consistent with the reference result, it indicates that the phased array device is normal, and if the returned operation result is inconsistent with the reference result, it indicates that the phased array device is abnormal.

[0156] To solve the technical problems in the prior art, the application also provides a phased array test system for performing phased array test processing related to phased array testing and sending a phased array data stream to a connected phased array device to make the phased array device perform corresponding phased array operations according to the phased array data stream result.

[0157] The phased array test processing includes performing corresponding application layer processing on the test data based on phased array test items (for example, phase test and attenuation test), and performing data reconstruction processing on the application layer processing result to convert the application layer processing result data into phased array data streams that can be recognized and executed by the phased array device.

[0158] Specifically, the application layer operation includes but is not limited to phase processing and attenuation processing, etc.; the underlying data processing is the underlying data processing involved in the application layer operation, including but not limited to logical operation, data storage and data transmission, etc.

[0159] Referring to Figure 9 , a schematic diagram of an application environment of the phased array test system provided in the embodiment is shown.

[0160] As Figure 9 shown, one end of the phased array test system 100 is communicatively connected to an external device 200, for obtaining configuration information, test parameters and test data input by the external device 200; and the other end of the phased array test system 100 is connected to a phased array device 300, for performing phased array test process on each test data based on the configuration information and the test parameters by using the test data; that is, the phased array test system 100 performs phased array test processing on the received test data to obtain phased array data streams, and transmits each phased array data stream to the phased array device 300, so that the phased array device 300 performs corresponding phased array operation according to the phased array data stream to return corresponding operation result.

[0161] The phased array device includes a chip group 310 composed of M chips and an antenna unit group 320 composed of N antenna units; M and N are both integers greater than 2; the chip group cooperatively works to jointly perform phased array test operation on the antenna unit group; a single chip is connected to several antenna units to efficiently realize efficient and cooperative control of a single chip on multiple antenna units; for example, a single chip is connected to and controls 4 antenna units.

[0162] The phased array test process adopts any phased array device test method as described above.

[0163] In addition, those skilled in the art can know that the external device in the embodiment includes but is not limited to PC, terminal or server, etc.

[0164] In some optional embodiments, the phased array testing system comprises a device, a terminal, a server or the like equipped with an SDK (Software Development Kit), for realizing the functional design of phased array device testing and realizing the communication setup with the phased array device.

[0165] Referring to Figure 10 , a specific structural schematic diagram of the phased array testing system in an embodiment is shown. As Figure 10 shown, the phased array testing system comprises:

[0166] an external transmission unit 110, a phased array data processing unit 120, a delivery unit 130 and a register unit 140;

[0167] The external transmission unit 110 is connected to the external device 200 and the register unit 140, for obtaining configuration information related to the phased array device 300 and obtaining test data and test parameters related to the testing process, and storing the configuration information and the test parameters in the register unit 140.

[0168] The phased array data processing unit 120 comprises a first end and a second end, the first end of which is connected to the register unit 140, for obtaining the configuration information and the test parameters; the second end of the phased array data processing unit 120 is connected to the transmission unit 110, for obtaining test data, performing corresponding phased array data processing on the test data according to the phased array testing mode, combining the test parameters and the configuration information, to obtain processed phased array data stream;

[0169] The delivery unit 130 comprises a first end, a second end and a third end, the first end of which is connected to the phased array data processing unit 120, for obtaining the phased array data stream;

[0170] The second end of the delivery unit 130 is connected to the register unit, for storing each phased array unit array in the phased array data stream in the corresponding register unit;

[0171] The third end of the delivery unit 130 is connected to the phased array device 300, for sending the phased array unit array stored in each register unit to the phased array device 300 in parallel.

[0172] In an optional embodiment, the phased array testing system 100 is a controller; the external transmission unit 110 and the phased array data processing unit 120 are respectively corresponding functional units in the controller; for example, the phased array testing system 100 is an MCU (Microcontroller Unit).

[0173] In an optional embodiment, the phased array data processing unit 120 comprises, as shown in the figure, a test operation module 121 and a data adaptation module 122, and the test operation module 121 is connected with the data adaptation module 122. Figure 11

[0174] The test operation module 121 is configured to perform the application layer processing corresponding to the phased array test to obtain corresponding application layer processing result data; the application layer processing process includes, but is not limited to, phase processing and attenuation processing, etc.

[0175] The data adaptation module 122 is connected with the test operation module 121, and is configured to perform data reconstruction processing on each application layer processing result data output by the test operation module 121, so that the reconstructed application layer processing result data can adapt to the phased array device.

[0176] Specifically, when the test operation module 121 performs phase processing and attenuation processing in the wave control mode, the data adaptation module 122 is configured to perform data reconstruction processing on the phase processing result and the attenuation processing result output by the test operation module 121; the implementation manner of the data reconstruction processing is the same as that in the above-mentioned embodiments, and will not be described here again.

[0177] In a specific embodiment, the test operation module comprises a phase processing sub-module and an attenuation processing sub-module.

[0178] The phase processing sub-module is configured to implement phase processing on the phased array data; the specific implementation manner of the phase processing is the same as that in the above-mentioned embodiments, and will not be described here again.

[0179] The attenuation processing sub-module is configured to implement attenuation processing on the phased array data; the specific implementation manner of the attenuation processing is the same as that in the above-mentioned embodiments, and will not be described here again.

[0180] In a specific embodiment, the issuing unit 130 comprises, as shown in the figure, a read-write module 131, a value assignment module 132, an addressing and writing number module 133, a timing module 134 and a control module 135; the modules will be introduced below. Figure 12 Figure 12

[0181] 1) Read-write module 131

[0182] ​​​The read-write module 131 is connected with the data adaptation module 122 in the phased array data processing unit through a bus, for obtaining each input data inputted by the data adaptation module 122; and the read-write module 131 is also connected with the register unit and the chip, for storing the input data into the register unit and reading out the data by the chip; wherein the input data includes phased information and read-write state information. Exemplarily, the data stored in the register unit is 32 bits.

[0183] 2) The value assignment module 132

[0184] The input end of the value assignment module 132 is connected with the read-write module 131, for obtaining the phased information and read-write state information transmitted by the read-write module 131; and the output end of the value assignment module 132 is connected with the addressing write number module 133, for controlling whether to write the phased information into the addressing write number module 133 according to the read-write state information.

[0185] Wherein, the read-write state information includes a read-write state and a non-read-write state.

[0186] When the read-write state information is the read-write state, the phased information is written into the addressing write number module 133; when the read-write state information is the non-read-write state, the value assignment module 132 stops writing the phased information into the addressing write number module 133, so as to prevent the timing module 134 from continuously writing information into the addressing write number module 133.

[0187] More specifically, the input signals of the value assignment module 132 include clk_100mhz, clear, slv_reg_wren, slv_reg_rden, and 256 registers of slv_reg0[31:0]-slv_reg255[31:0]; and the output signals of the value assignment module 132 include 256 registers of slv_reg0[31:0]-slv_reg255[31:0].

[0188] Wherein, slv_reg_wren is used to determine whether in a write data state; and slv_reg_rden is used to determine whether in a read data state.

[0189] Clear is used to clear slv_reg0.

[0190] It should be noted that the value assignment module 132 only reads and writes the data stored in the register unit in the non-reading and writing stage; slv reg0 is an input of the timing module 134, when it is equal to 1, the timing module 134 is started, and after the function is executed, slv reg0 is still 1; the value needs to be cleared to prevent the timing module 134 from constantly coding; therefore, after the timing module 134 executes the function, the clear output is 1; the value assignment module 132 judges whether the reading and writing module 131 is in the working stage according to slv reg wren and slv reg rden, when it is in the non-reading and writing stage, slv reg0 is cleared, then the TR timing module 134 detects that slv reg0 is 0 and clear is 1, will clear 0, and then enter the normal mode to wait for the next trigger.

[0191] 3) Addressing write number module 133

[0192] The addressing write number module 133 is connected with the value assignment module 132 and the register unit, and is used for writing the input phased array data stream into the corresponding register unit according to the address in sequence; that is, writing each phased array unit array in the phased array data stream into the corresponding register unit according to the corresponding storage address;

[0193] In addition, the addressing write number module 133 is also connected with the timing module 134, so as to output each phased array unit array in the same phased array data stream to the chip in parallel based on the timing control of the timing module 134.

[0194] More specifically, the input signals of the addressing write number module 133 are clk, address[31:0] and data[127:0]; the output signals of the addressing write number module 133 are Data[0][127:0], Data[1][127:0], Data[2][127:0] and Data[ND][127:0].

[0195] Among them, clk is 100mhz;

[0196] The input of address is slv reg1, and the input of data is slv reg2 to slv reg5.

[0197] It should be noted that the position of the register unit can be specifically set according to the demand; that is, the specific number of the register unit can be determined according to the length of the data to be transmitted on a physical data.

[0198] 4) Timing module 134

[0199] The timing module 134 is connected to the phased array data processing unit 120, the chip 310 and the register unit 140, and is configured to send the phased array unit array in each register unit to each chip in parallel according to the timing of the chip and the input control signal.

[0200] Specifically, the phased array data processing unit 120 also transmits a corresponding control instruction to the timing module 134 to control the timing module 134 to send the phased array unit array to the chip; otherwise, the phased array unit array is only temporarily stored in the register unit, waiting for the next instruction to switch. This module can adjust the trigger timing to adapt to different chips by changing the timing; that is, by setting the timing pin as address data, a plurality of modules are addressed to write numbers to achieve adaptation to different chips.

[0201] In an optional embodiment, the control instruction is a level trigger signal; that is, when the timing module 134 receives the level trigger signal, the phased array unit array is sent to the chip according to the chip protocol.

[0202] It should be noted that the chip includes clock pins, chip select pins and latch pins in addition to data pins. For different chips, their data structures are different, but their chip protocols and pins are basically the same. In the sending unit 130, the code cannot be parameterized in real time, so the preset timing module 134 needs to meet the chip protocol and pin of the chip. Of course, in addition to data, pins such as clock and chip select can also achieve arbitrary waveforms through addressing and writing numbers, which will not be described here.

[0203] The control module 135 is connected to the phased array data processing unit 120 and the chip 310, and is configured to control the chip to perform corresponding phased array operations such as transmit state, receive state and load state according to the control instruction sent by the phased array data processing unit 120, to realize the emission, reception and silence of electromagnetic waves and the phased array device. The transmit / receive instruction information sent exists in certain specific register units.

[0204] In summary, the phased array testing device and method provided by the embodiments of the present application can obtain configuration information related to the chip to be tested, and obtain test data and test parameters related to the test process; perform corresponding phased array data processing on the test data based on the test parameters, and perform data reconstruction on the phased array data processing result based on the configuration information, so that the processing result data can be conveniently and efficiently adapted to the phased array chip without the need to redesign the hardware circuit to adapt to the needs of different phased array chips. The testing device and method of the present application have high adaptive ability, and compared with the prior art, it can better meet various needs in actual research and development testing process, not only improving the universality, but also significantly improving the efficiency of phased array testing.

[0205] The above is a further detailed description of the embodiments of the present application in combination with specific embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, and all should be considered as falling within the protection scope of the present application.

[0206] Finally, it should be noted that the above description is only for the preferred embodiments of the present application, and those skilled in the art can make a variety of similar expressions under the inspiration of the present application without departing from the purpose of the present application and the claims. Such changes fall within the protection scope of the present application.

Claims

1. A testing method for a phased array device, characterized in that, include: Obtain configuration information related to the phased array device, and obtain test parameters corresponding to the test mode; Based on the configuration information and the test parameters, the input test data is processed using the application layer corresponding to the test mode, and the application layer processing result data is reconstructed to obtain a phased array data stream adapted to the phased array device. The phased array data stream is sent to the phased array device, which then performs corresponding phased array operations based on the data stream and returns the results of the phased array operations. The phased array device includes a chip and several antenna units connected to the chip; The method for acquiring the phased array data stream includes: acquiring the number of elements in the configuration information, determining the number of construction attempts based on the number of elements; repeatedly performing element data construction on the test data based on the test parameters according to the number of construction attempts, to obtain element data corresponding to the corresponding construction order; and sorting the element data corresponding to each construction order according to the configuration information to obtain the phased array data stream.

2. The phased array device testing method according to claim 1, characterized in that, When the test mode is wave-controlled mode, the application layer processing includes phase processing and attenuation processing. Then, the data reconstruction of the application layer processing result data includes: The phase processing results and attenuation processing results are combined to obtain the first phased array data; Based on the configuration information, the first phased array data is shifted and spliced ​​to obtain the unit data corresponding to the antenna unit. The data of each unit is sorted to obtain the phased array data stream.

3. The phased array device testing method according to claim 2, characterized in that, The implementation method for performing shift and splicing processing on the first phased array data includes: From the first phased array data, extract the data segments corresponding to each of the antenna elements; Based on the data type and position information in the data transmission channel corresponding to the data segment, a shift operation corresponding to the position information is performed on each data segment corresponding to a single antenna unit. The shifted data segments are spliced ​​together to obtain the unit data corresponding to each antenna element.

4. The phased array device testing method according to claim 1, characterized in that, The unit data is constructed in a single execution and includes: Based on the configuration information and the test parameters, phase processing is performed on the test data to obtain the phase processing result corresponding to the current construction order; and based on the configuration information and the test parameters, attenuation processing is performed on the test data to obtain the attenuation processing result corresponding to the current construction order. Based on the configuration information, the phase processing result and the attenuation processing result are subjected to data shifting and splicing processing to obtain the cell data corresponding to the current number of constructions.

5. The phased array device testing method according to claim 1, characterized in that, The step of sending the phased array data stream to the phased array device includes: Based on the number of unit mappings, the phased array data stream is divided into several phased array unit arrays; Each phased array element array is stored in its corresponding storage space according to a preset storage mapping relationship; The phased array unit arrays in each of the aforementioned storage spaces are transmitted in parallel to the corresponding chips, so that the chips can perform corresponding phased array operations based on the phased array unit arrays. The phased array unit array corresponds to a single chip.

6. A phased array testing system, characterized in that, Connected between an external device and a phased array device, it is used to acquire configuration information, test parameters, and test data input from the external device, and to perform a phased array test process on each test data based on the configuration information and the test parameters and using the test data. The phased array device includes a chip and several antenna units connected to the chip; the phased array testing process adopts the phased array device testing method as described in any one of claims 1 to 5.

7. The phased array testing system according to claim 6, characterized in that, include: Register units are used to store data; A transmission unit, connecting the external device and the register unit, is used to acquire the configuration information, test parameters, and test data input by the external device, and to store the configuration information and test parameters in the register unit; The phased array data processing unit includes a first end and a second end. The first end is connected to the register unit and is used to acquire the configuration information and the test parameters. The second end is connected to the transmission unit and is used to acquire test data, and, in combination with the test parameters and the configuration information, to perform corresponding phased array data processing on the test data to obtain a processed phased array data stream. The sending unit includes a first end, a second end, and a third end. The first end is connected to the phased array data processing unit and is used to acquire the phased array data stream. The second end of the sending unit is connected to the register unit and is used to store each phased array element array in the phased array data stream in the corresponding register unit. The third end of the sending unit is connected to the chip and is used to send the phased array element arrays stored in each register unit to the chip in parallel.

8. The phased array testing system according to claim 7, characterized in that, The phased array data processing unit includes: The test operation module is used to perform phase processing and attenuation processing in wave control mode; The data adaptation module, connected to the test operation module, is used to perform data reconstruction on the phase processing results and attenuation processing results output by the test operation module to obtain the processed phased array data stream.

9. The phased array testing system according to claim 7, characterized in that, The distribution unit includes: a read / write module, a value retrieval and assignment module, an addressing and writing module, a timing module, and a control module; wherein, The read / write module connects the phased array data processing unit, the chip, and the register unit, and is used to store the phased array data stream input by the phased array data processing unit into the register unit; and to allow the chip to read the data; The input terminal of the value acquisition and assignment module is connected to the read and write module to obtain the read and write status information of the read and write module; the output terminal of the value acquisition and assignment module is connected to the addressing and writing module to control whether to write data to the addressing and writing module according to the read and write status information. The addressing and writing module is connected to the value assignment module and the register unit respectively, and is used to write the input phased array data stream into the corresponding register unit in sequence; the addressing and writing module is also connected to the timing module, so as to output the arrays of each phased array unit in the same phased array data stream in parallel to the chip based on the timing control of the timing module; The timing module connects the phased array data processing unit, the chip, and the register unit, and is used to send the phased array unit array in each register unit to each chip in parallel; The control module connects the phased array data processing unit and the chip, and is used to control the chip to perform corresponding phased array operations according to the control instructions issued by the phased array data processing unit.

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