Satellite navigation time service method and system

Abstract

The invention discloses a satellite navigation time service method and system. The method comprises the following steps: performing PVT calculation by using observed quantity and message information to obtain an output result; detecting the filtering state of the clock speed under the condition that the PVT calculation fails; under the condition that the filtering state of the clock speed is detected to be a stable state, obtaining a filtering clock speed, and performing predictive clock adjustment by using the filtering clock speed; detecting the filtering state of the clock speed under the condition that the PVT calculation is successful; if the filtering state of the clock speed is detected to be a stable state, judging whether the receiver clock difference and the clock speed calculated by the PVT are abnormal or not; if the receiver clock difference and the clock speed calculated by the PVT are abnormal, obtaining a filtering clock speed, and performing predictive clock adjustment by using the filtering clock speed; wherein the predictive clock adjustment is that the PPS pulse per second of the next second is generated after the time of the receiver is multiplied by the filtering clock speed by 1 second, and PVT calculation is carried out. According to the scheme, the time service reliability and precision of the receiver in complex environments such as interference or shielding can be greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of satellite navigation technology, and in particular to a satellite navigation timing method and system. Background Art

[0002] The global navigation satellite system provides navigation, positioning, timing and other services. Nowadays, in the field of high-precision timing applications, timing navigation receivers are increasingly used due to their excellent cost-effectiveness. As a result, more and more application fields have put forward higher requirements for the reliability and accuracy of receiver timing: (1) Different navigation receivers use different crystal oscillators, and their nominal frequency accuracy and frequency stability vary greatly, which makes it impossible for the receivers to use a unified calibration method for timing. (2) Navigation receivers operating in complex environments such as interference or obstruction will be severely negatively affected in receiving satellite signals, which will cause abnormalities or even failures in the receiver's PVT solution, thereby affecting the reliability and accuracy of its timing.

[0003] In reality, many navigation receiver timing devices work in harsh environments such as mountain obstruction, tree obstruction, electromagnetic interference, etc. How to ensure and improve the reliability and accuracy of navigation receiver timing in these complex environments is a key technical point that must be solved. Summary of the invention

[0004] In order to solve the technical problem that the navigation receiver fails to locate or the positioning value jumps in complex environments such as interference or obstruction, resulting in inaccurate timing, the embodiments of the present invention provide a satellite navigation timing method and system, which can effectively improve the reliability of PPS second pulse output and achieve high-precision timing.

[0005] The technical solution of the embodiment of the present invention is achieved as follows: The embodiment of the present invention provides a satellite navigation timing method, which includes: acquiring observation quantities and telegram information; performing PVT solution using the observation quantities and the telegram information to obtain an output result of the PVT solution; the output result includes whether the PVT solution is successful, and the receiver clock error and clock speed when the PVT solution is successful; in the case of failure of the PVT solution, detecting the filtering state of the clock speed; in the case of detecting that the filtering state of the clock speed is in a stable state, acquiring the filtered clock speed, and using the filtered clock speed for predictive clock adjustment; in the case of successful PVT solution, detecting the filtering state of the clock speed; if the filtering state of the clock speed is detected to be in a stable state, then determining whether the receiver clock error and clock speed of the PVT solution are abnormal; if the receiver clock error and clock speed of the PVT solution are abnormal, acquiring the filtered clock speed, and using the filtered clock speed for predictive clock adjustment; wherein the predictive clock adjustment is to make the receiver time less than the filtering clock speed multiplied by 1 second before generating the next second of PPS second pulse and PVT solution.

[0006] In one embodiment, when the PVT solution fails, after detecting the filtering state of the clock speed, the method further includes: if it is detected that the filtering state of the clock speed is an initialization state, no clock adjustment is performed and no PPS second pulse is output.

[0007] In one embodiment, when the PVT solution is successful, after detecting the filtering state of the clock speed, the method also includes: if it is detected that the filtering state of the clock speed is an initialization state, real-time clock adjustment is performed using the receiver clock difference and clock speed when the PVT solution is successful, and the receiver clock speed when the PVT solution is successful is filtered.

[0008] In one embodiment, after determining whether the receiver clock difference and clock speed obtained by PVT solution are abnormal, the method further includes: if the receiver clock difference and clock speed obtained by PVT solution are normal, using the receiver clock difference and clock speed obtained when PVT solution is successful to perform real-time clock adjustment, and filtering the receiver clock speed obtained when PVT solution is successful.

[0009] In one embodiment, the filtering state of the clock speed is detected, including: putting the clock speed each time the PVT solution is successfully calculated into the filter for filtering; and using the filtered clock speed as the latest filtered clock speed; when the filtering state of the clock speed is an initialized state, when the cumulative number of filtering times exceeds a preset first threshold, it is determined that the filtering state of the clock speed is in a stable state.

[0010] In one embodiment, after using the filtered clock speed for predictive clock adjustment, the method further includes: determining whether the number of consecutive predictive clock adjustments reaches a preset second threshold; if it is determined that the number of consecutive predictive clock adjustments reaches the preset second threshold, switching the filtering state of the clock speed from a stable state back to an initialization state.

[0011] In one embodiment, filtering the receiver clock rate when the PVT solution is successful includes: filtering the receiver clock rate when the PVT solution is successful by using a mean filter or - Filtering method.

[0012] In one embodiment, whether the receiver clock difference and clock rate calculated by PVT are abnormal is determined, including: when the difference between the receiver clock rate calculated by PVT and the filtered clock rate is greater than a preset third threshold, determining that the receiver clock rate calculated by PVT is abnormal; or, when the receiver clock difference calculated by PVT is greater than a preset fourth threshold, determining that the receiver clock difference calculated by PVT is abnormal.

[0013] An embodiment of the present invention provides a satellite navigation timing system, comprising: a processor and a memory for storing a computer program that can be run on the processor; wherein the processor executes the steps of the above-mentioned method when running the computer program.

[0014] The embodiments of the present invention have the following beneficial effects: (1) The embodiments of the present invention can effectively improve the availability of timing.

[0015] In order to ensure the timing accuracy, the traditional method generally does not output the PPS second pulse after the PVT solution fails. The embodiment of the present invention can still predict and adjust the clock to output accurate PPS second pulses within a period of time when the PVT solution fails or the clock error or clock speed is abnormal, thereby greatly improving the availability of timing.

[0016] (2) The embodiments of the present invention can reduce the cost of a timing receiver.

[0017] The embodiment of the present invention can have relatively low requirements on the high stability of the crystal oscillator, does not require expensive ultra-high stability crystal oscillators, and can effectively reduce the cost of the timing receiver.

[0018] (3) The embodiments of the present invention can expand the application field of the timing receiver.

[0019] The embodiments of the present invention can still demonstrate good timing reliability and accuracy in complex environments such as interference or shielding, which is conducive to the promotion and application of timing receivers in more complex environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic diagram of the timing scheme for traditional navigation receivers; Figure 2 A schematic diagram of a flow chart of a satellite navigation timing method according to an embodiment of the present invention; Figure 3 A schematic diagram of a timing scheme for a navigation receiver according to an embodiment of the present invention; Figure 4 A schematic diagram of the clock adjustment process according to an embodiment of the present invention; Figure 5 1 is a diagram showing the internal structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] Before introducing the present embodiment, the following is an introduction to the present invention: In order to meet the application scenarios of high reliability and high precision timing, the navigation receiver needs to output high stability and high precision PPS second pulses. In the existing technology, there are mainly the following methods for high precision timing of satellite navigation: (1) Improve the stability of the crystal oscillator frequency of the navigation receiver. The less the crystal oscillator frequency is affected by ambient temperature and power supply voltage, the higher its stability. However, the more stable the crystal oscillator, the more expensive it will be, which is not conducive to reducing costs. At the same time, the actual frequency values ​​of different crystal oscillators are different from the nominal frequency values, which means that each timing device needs to be calibrated separately, which is not conducive to large-scale application.

[0022] (2) Improve the success rate and reliability of the navigation receiver's PVT solution. The higher the reliability of the PVT solution, the closer the solved clock error and clock speed are to the true value. The more accurate the PPS time of the next second output after adjusting the clock based on the clock error and clock speed will be. However, this solution places higher demands on the hardware and software of the entire navigation receiver. The receiver needs to support satellite signal reception and PVT solution of more systems and frequencies. The more satellites and signal components involved in the solution, the higher the success rate and reliability of the PVT solution. However, it will also increase the hardware cost and system power consumption of the receiver, increase the time consumption of the PVT solution and the system burden, resulting in limitations on the functional performance of other aspects of the receiver, making it difficult for the receiver to achieve fundamental improvements and breakthroughs. The block diagram of the traditional navigation receiver timing solution is shown in the figure below. Figure 1 shown.

[0023] from Figure 1 It can be seen that when the PVT solution fails, there is no clock adjustment operation and the PPS is not output, which reduces the availability of timing. If the PPS output is biased, the timing accuracy will be reduced. When the PVT solution is successful but the reliability is poor, the solved clock error or clock speed is often abnormal, abnormal clock adjustment will occur, and the PPS output will also be biased, resulting in a decrease in timing accuracy. It can be seen that in the traditional navigation receiver timing solution, the stable and reliable output of PPS is completely dependent on the success rate and reliability of the PVT solution. The reliability and accuracy of its timing face many challenges in complex environments such as interference or obstruction, and cannot be effectively guaranteed.

[0024] Based on this, this embodiment proposes a satellite navigation timing method, which performs predictive clock adjustment for PVT solution failure, solution anomaly, etc., which can greatly improve the reliability and accuracy of the receiver's timing in complex environments such as interference or obstruction.

[0025] The present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0026] The embodiment of the present invention provides a satellite navigation timing method, such as Figure 2 As shown, the method includes: Step 201: Obtain observations and message information; Step 202: Perform PVT solution using the observed quantity and the message information to obtain an output result of the PVT solution; the output result includes whether the PVT solution is successful, and the receiver clock error and clock speed when the PVT solution is successful; Step 203: if the PVT solution fails, detect the filtering state of the clock speed; if it is detected that the filtering state of the clock speed is stable, obtain the filtered clock speed, and use the filtered clock speed to perform predictive clock adjustment; Step 204: When the PVT solution is successful, the filtering state of the clock speed is detected; if the filtering state of the clock speed is detected to be stable, then determine whether the receiver clock difference and clock speed of the PVT solution are abnormal; if the receiver clock difference and clock speed of the PVT solution are abnormal, obtain the filtered clock speed, and use the filtered clock speed for predictive clock adjustment; wherein, the predictive clock adjustment is to reduce the receiver time by the filtered clock speed multiplied by 1 second before generating the next second's PPS second pulse and PVT solution.

[0027] This embodiment provides a high-reliability, high-precision satellite navigation timing method. Based on the short-term invariance of the receiver clock rate, the filtered clock rate is obtained by filtering the clock rate of the PVT solution, and the filtered clock rate is used to make an abnormal judgment on the clock difference and clock rate of the PVT solution. When the PVT solution fails or the judgment is abnormal, the filtered clock rate can still be used for predictive clock adjustment within a certain period of time, thereby achieving a high-reliability and high-precision timing effect. The specific characteristics are as follows: 1. The clock speed is short-term constant. The crystal oscillator of the navigation receiver has a high frequency stability (generally better than 1ppm). Under relatively stable environments such as ambient temperature and equipment power supply, it can be considered that the frequency output by the crystal oscillator over a period of time is a stable value, that is, the receiver clock speed is short-term constant.

[0028] 2. Clock speed filtering: the clock speed remains unchanged in a short period of time, but it will still change slowly with the ambient temperature, power supply voltage, etc. The clock speed calculated by PVT needs to be filtered to obtain the filtered clock speed, which can better represent the true value of the clock speed in the current state.

[0029] 3. Abnormal judgment: In complex environments such as interference or obstruction, satellite signals are missing or of poor quality, and the receiver is prone to PVT solution jumps, resulting in the calculated clock error or clock speed not meeting expectations. This situation is judged as an abnormality.

[0030] 4. Clock adjustment operation: The receiver PVT solves the clock difference and clock speed of the current solving moment (PPS second pulse output moment), and calculates the clock difference adjustment amount within the next second based on this and completes the clock adjustment operation. Then, the clock difference of the solving moment in the next second will be around 0, and the clock speed is basically consistent with the filtered clock speed.

[0031] 5. Predictive clock adjustment: When the PVT solution fails or the PVT solution is abnormal, the filtered clock speed is used to predict the clock adjustment amount within the next second and complete the clock adjustment operation.

[0032] 6. Limit the duration of predicted clock adjustment. The long-term accumulated predicted clock adjustment error will also reduce the timing accuracy, so the predicted clock adjustment cannot be continued for a long time. When the number of consecutive predicted clock adjustments reaches the set threshold, the clock speed filter state needs to be reset.

[0033] In order to improve the reliability and accuracy of the navigation receiver's timing, this embodiment proposes the idea of ​​clock speed filtering + anomaly detection + predictive clock adjustment based on the short-term invariant characteristics of the clock speed: when the PVT solution is successful and the solved clock error and clock speed detection are normal, the clock speed is filtered to obtain the filtered clock speed; when the PVT solution fails or the solved clock error and clock speed detection are abnormal, the filtered clock speed is used for predictive clock adjustment, and the number of predictive clock adjustments is limited to prevent the accumulation of prediction errors. The block diagram of the navigation receiver timing scheme of this embodiment is shown in the figure. Figure 3 shown.

[0034] 1. Data input: The input data of the method of the present invention is the output result of the PVT solution, which mainly includes: whether the PVT solution is successful, and the receiver clock error when the PVT solution is successful. and clock speed .

[0035] 2. Clock speed filter: (1) At the beginning, the clock speed filter is in the initialization state. At this time, as long as the PVT solution is successful, the current solved clock speed will be Put it into the filter for filtering and update the filter clock speed , when the cumulative filtering times exceed the preset first threshold (for example, 20 times), the clock speed filter is considered to have entered a stable state; (2) after the clock speed filter enters a stable state, the currently solved clock speed is considered to have entered a stable state only after the PVT solution is successful and it is determined that there is no abnormality. Put it into the filter to continue filtering; (3) When the clock speed filter is in a stable state and the PVT solution fails or is judged to be abnormal, a predictive clock adjustment will be performed. When the number of consecutive predictive clock adjustments exceeds the preset second threshold (for example, 10 times), the clock speed filter state is reset to the initialization state; (4) The filter can choose to use mean filtering or - Filtering and other different methods.

[0036] The crystal oscillator of the navigation receiver has a high frequency stability (generally better than 1ppm). Under relatively stable conditions such as ambient temperature and equipment power supply, it can be considered that the frequency output by the crystal oscillator over a period of time is a stable value. , this value is consistent with the crystal nominal value difference is the frequency difference, its ratio to the nominal value is the receiver clock rate (also called clock drift), which indicates the time deviation of 1s clock relative to the nominal time system. In the short term, it can be considered unchanged, but in the long term It still changes slowly. Therefore, it is necessary to filter the clock speed to reduce the random error of the system on the one hand and update it according to the long-term trend on the other hand. Therefore, the filtered clock speed can better represent the true value of the clock speed in the current state.

[0037] 3. Abnormality judgment: After the clock speed filter enters a stable state and the PVT solution is successful, there are two situations in which the PVT solution is considered abnormal: (1) The clock speed of the solution is and filter clock speed The phase difference is greater than the preset third threshold (e.g. 10ns / s); (2) Calculate the clock difference Greater than a preset fourth threshold (for example, 30ns).

[0038] The above point (1) is the result of the short-term invariance of the clock speed. The following will focus on point (2).

[0039] Figure 4 This is a schematic diagram of the clock adjustment process. After the clock adjustment is stable, the clock error calculated by the receiver is normally close to 0. At the moment, the clock error and clock speed calculated by PVT are and , Indicates the receiver The time (PPS pulse output time) is relative to the deviation of the large system time. Indicates the receiver The rate at which a moment deviates from the larger system time. If the receiver is not adjusted, the time of the receiver will gradually deviate from that of the large system. The clock difference is , then: Arranged Due to the clock speed It is very small, usually on the order of 10e-7, so it can be written as The "1" in the above formula represents the time of 1 second in the large system (the large system is composed of ultra-high stable atomic clocks, and the time of 1 second in the large system can be considered to be a standard 1 second clock). From the above formula, it can be seen that when the receiver is not adjusted, the clock error in the next second is the sum of the current clock error and the clock error accumulated after 1 second. If the clock is adjusted during this period, the receiver time will be less Then generate the next second's PPS pulse and PVT solution, then Solving the clock error It will be close to 0. After the receiver's clock is stabilized, the calculated clock error will normally be close to 0, thus achieving high-precision timing.

[0040] 4. Predictive clock adjustment: (1) After the clock speed filter enters a stable state, the PVT solution is successful and the detection judgment is normal, the clock error calculated by PVT is directly used and clock speed Perform real-time clock adjustment; when PVT solution fails or detection judgment is abnormal, use the filtered clock speed Perform predictive clock adjustment. The predictive clock adjustment process is similar to the real-time clock adjustment process, except that there is no real-time calculated clock error and clock speed or the real-time calculated clock error and clock speed are abnormal. However, we know that the clock error at this moment is normally around 0, and the clock speed is basically the same as the filtered clock speed, so The clock difference The predicted values ​​are: Adjust the receiver clock before the next second arrives, so that the receiver time will be off sooner. Then the PPS second pulse and PVT solution of the next second are generated, and the clock error can be kept close to 0 within a period of time (such as 10s), completing high-precision time synchronization.

[0041] (2) Filter clock speed There must be errors, which will cause errors in the predicted clock adjustment. After a long period of accumulation, the timing accuracy will be reduced, so the predicted clock adjustment cannot be performed for a long time. When the number of consecutive predicted clock adjustments exceeds the threshold (for example, 10 times), the clock speed filter state is reset to the initialization state to exit the filter clock adjustment to ensure high-precision timing effect.

[0042] 5. PPS second pulse output: When the original count value of the PPS inside the receiver reaches the threshold (the clock count value corresponding to 1s), a waveform with configured polarity and pulse width will be generated, called the PPS second pulse. The essence of the clock adjustment process is to dynamically adjust the threshold in real time to allow the receiver to generate the PPS second pulse in advance or lag in order to achieve the purpose of high-precision timing.

[0043] The high-reliability and high-precision satellite navigation timing method proposed in this embodiment performs predictive clock adjustment for situations such as PVT solution failure and solution anomaly, which greatly improves the reliability and accuracy of the receiver's timing in complex environments such as interference or obstruction.

[0044] In addition, this embodiment also conducts an experimental comparison between the method of this embodiment and the traditional method.

[0045] The navigation receiver is set to use Samsung six-frequency (B1I / B2I / L1CA / L2C / E1 / E5b) for PVT solution positioning, output 1Hz PPS second pulse, and perform stress test for 24 hours under different environments. The efficiency, variance, peak value and other indicators of PPS second pulse are statistically analyzed. The experimental results of the comparison between the traditional method and the method of the present invention are shown in Table 1 below: PPS effective rate: the ratio of the number of effective pulses per second actually output to the theoretical value. For example, if the theoretical value is 3600 pulses per hour and the actual output is 3500, the effective rate is 3500 / 3600=97.222%. The higher the PPS effective rate, the higher the PPS availability.

[0046] PPS variance: The actual output effective pulse-per-second data is statistically analyzed for variance. The smaller the PPS variance, the higher the PPS timing stability and reliability.

[0047] PPS peak value: the maximum value of the difference between the actual output effective second pulse and the statistical mean. A smaller PPS peak value means a smaller PPS timing jump value and a higher accuracy.

[0048] As can be seen from Table 1 above, compared with the traditional method, the method of this embodiment has obvious improvements in the efficiency, variance, peak value and other indicators of PPS second pulse under the environment of burst electromagnetic interference in the adjacent frequency period, tree occlusion and half wall occlusion. The PPS timing peak value is 100% within 20ns, and the improvement effect is very obvious.

[0049] This embodiment is based on the short-term invariant characteristic of the receiver clock rate and adopts the idea of ​​clock rate filtering + anomaly detection + predictive clock adjustment. It can effectively improve the reliability and accuracy of the receiver timing in complex environments such as interference or obstruction, and has high promotion value.

[0050] Its value is mainly reflected in the following aspects: (1) Effectively improve the availability of timing. In order to ensure the accuracy of timing, the traditional method generally does not output PPS second pulses after the PVT solution fails. The method of the present invention can still predict the clock and output accurate PPS second pulses within a period of time when the PVT solution fails or the clock error and clock speed are abnormal, which greatly improves the availability of timing. (2) Reduce the cost of the timing receiver. The method of the present invention has relatively low requirements for the high stability of the crystal oscillator and does not require expensive ultra-high stability crystal oscillators, which can effectively reduce the cost of the timing receiver. (3) Expand the application field of the timing receiver. The method of the present invention can still show good timing reliability and accuracy in complex environments such as interference or obstruction, which is conducive to the promotion and application of timing receivers in more complex environments.

[0051] In order to implement the method of an embodiment of the present invention, an embodiment of the present invention also provides a satellite navigation timing system, including: a processor and a memory for storing a computer program that can be run on the processor; wherein, when the processor is used to run the computer program, the steps of the above-mentioned method are executed.

[0052] The above-mentioned system provided in this embodiment belongs to the same concept as the above-mentioned method embodiment. The specific implementation process thereof is detailed in the method embodiment and will not be repeated here.

[0053] In order to implement the method of the embodiment of the present invention, the embodiment of the present invention also provides a computer program product, which includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps of the above method.

[0054] Based on the hardware implementation of the above program modules, and in order to implement the method of the embodiment of the present invention, the embodiment of the present invention further provides an electronic device (computer device). Specifically, in one embodiment, the computer device may be a terminal, and its internal structure diagram may be as follows: Figure 5As shown. The computer device includes a processor A01, a network interface A02, a display screen A04, an input device A05 and a memory (not shown in the figure) connected through a system bus. Among them, the processor A01 of the computer device is used to provide computing and control capabilities. The memory of the computer device includes an internal memory A03 and a non-volatile storage medium A06. The non-volatile storage medium A06 stores an operating system B01 and a computer program B02. The internal memory A03 provides an environment for the operation of the operating system B01 and the computer program B02 in the non-volatile storage medium A06. The network interface A02 of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor A01, the method of any one of the above embodiments is implemented. The display screen A04 of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device A05 of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0055] Those skilled in the art will understand that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0056] The device provided by the embodiment of the present invention includes a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, the method of any one of the above embodiments is implemented.

[0057] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0058] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0059] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0060] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0061] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0062] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0063] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0064] It can be understood that the memory of the embodiment of the present invention can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and direct RAMbus random access memory (DRRAM, Direct Rambus Random Access Memory).The memories described in the embodiments of the present invention are intended to include, but are not limited to, these and any other suitable types of memories.

[0065] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0066] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A satellite navigation timing method, characterized in that: The method comprises: Obtain observations and message information; Performing PVT solution using the observed quantity and the telegram information to obtain an output result of the PVT solution; the output result includes whether the PVT solution is successful, and the receiver clock error and clock speed when the PVT solution is successful; In the case of a PVT solution failure, the filtering state of the clock speed is detected; in the case of detecting that the filtering state of the clock speed is a stable state, the filtered clock speed is obtained, and the filtered clock speed is used to predict the clock adjustment; When the PVT solution is successful, the filtering state of the clock speed is detected; if the filtering state of the clock speed is detected to be stable, then determine whether the receiver clock difference and clock speed of the PVT solution are abnormal; if the receiver clock difference and clock speed of the PVT solution are abnormal, obtain the filtered clock speed, and use the filtered clock speed for predictive clock adjustment; wherein, the predictive clock adjustment is to make the receiver time less than the filtered clock speed multiplied by 1 second before generating the next second's PPS second pulse and PVT solution.

2. The satellite navigation timing method according to claim 1, characterized in that: In the case of a PVT solution failure, after detecting the filtering state of the clock speed, the method further includes: If it is detected that the filtering state of the clock speed is the initialization state, the clock will not be adjusted and the PPS second pulse will not be output.

3. The satellite navigation timing method according to claim 1, characterized in that: When the PVT solution is successful, after detecting the filtering state of the clock speed, the method further includes: If it is detected that the filtering state of the clock speed is the initialization state, the receiver clock difference and clock speed when the PVT solution is successful are used to perform real-time clock adjustment, and the receiver clock speed when the PVT solution is successful is filtered.

4. The satellite navigation timing method according to claim 1, characterized in that: After determining whether the receiver clock error and clock speed calculated by PVT are abnormal, the method further includes: If the receiver clock difference and clock speed calculated by PVT are normal, the receiver clock difference and clock speed when the PVT calculation is successful are used for real-time clock adjustment, and the receiver clock speed when the PVT calculation is successful is filtered.

5. The satellite navigation timing method according to claim 1, characterized in that: Detect the filtering status of the clock speed, including: The clock speed at each successful PVT solution is put into the filter for filtering; and the filtered clock speed is used as the latest filtered clock speed; When the filtering state of the clock speed is in the initialization state, when the accumulated number of filtering times exceeds a preset first threshold, it is determined that the filtering state of the clock speed is in the stable state.

6. The satellite navigation timing method according to claim 1, characterized in that: After predicting clock adjustment using the filtered clock rate, the method further includes: Determining whether the number of consecutive predicted clock adjustments reaches a preset second threshold; When it is determined that the number of consecutive predicted clock adjustments reaches a preset second threshold, the filtering state of the clock speed is switched from the stable state to the initialization state.

7. The satellite navigation timing method according to claim 1, characterized in that: Filter the receiver clock rate when the PVT solution is successful, including: The receiver clock rate when the PVT solution is successful is filtered by averaging or - Filtering method.

8. The satellite navigation timing method according to claim 1, characterized in that: Determine whether the receiver clock error and clock speed calculated by PVT are abnormal, including: When the difference between the receiver clock rate calculated by PVT and the filter clock rate is greater than a preset third threshold, it is determined that the receiver clock rate calculated by PVT is abnormal; or, When the receiver clock difference calculated by PVT is greater than a preset fourth threshold, it is determined that the receiver clock difference calculated by PVT is abnormal.

9. A satellite navigation timing system, characterized in that: include: A processor and a memory for storing a computer program that can be run on the processor; wherein, when the processor is used to run the computer program, the steps of the method according to any one of claims 1 to 8 are executed.

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