Multi-counting threshold grading reading method and system and digital silicon photomultiplier

Abstract

The invention discloses a multi-counting threshold grading reading method and system, a digital silicon photomultiplier and application thereof, and relates to the field of data processing. The multi-counting-threshold hierarchical reading method comprises the steps that first data output by at least one pixel unit set module is read in a hierarchical mode, the sum of photon counting data of all the pixel unit set modules is obtained, and the size of input data of each level of reading circuit is larger than that of output data of the reading circuit; the number of input data of each level of reading circuit is larger than the number of output data of each level of reading circuit. According to the multi-counting threshold hierarchical reading method provided by the invention, the output data of the pixel array is read in a hierarchical manner, so that the photon counting data of the whole pixel array can be read in real time, the introduction of a large number of TDCs is avoided, and the power consumption of the system is reduced.

Description

Technical Field

[0001] The present application relates to the field of data processing, and specifically to a multi-counting threshold classification readout method, system and digital silicon photomultiplier. Background Art

[0002] Analog silicon photomultipliers (SiPMs) convert light signals into scintillation pulses by summing the avalanche current output by each microcell (MC) at a node, and can directly use a single time-to-digital converter (TDC) to sample the scintillation pulses to extract the timestamp of the pulse event. In contrast, in digital SiPMs, each MC outputs a digital signal, and the digital outputs of all MCs are sent to the TDC for sampling through OR logic to obtain the timestamp. Under this architecture, the first digital SiPM chip was proposed by Thomas Frach et al. in 2009. The chip integrates MC, TDC and photon counters, each MC is connected to a separate transistor for active quenching, and is connected to the TDC through a configurable trigger network to obtain the time information of the event, and all MCs are connected to the counter through a separate synchronous bus to collect the number of MCs triggered during the event as the energy information of the event.

[0003] After that, Philips used this architecture to design a commercial digital SiPM named Digital Photon Counter (DPC). Seifert et al. used Philips' DPC to demonstrate the performance potential of digital SiPM in TOF-PET (Time Of Flight- Positron Emission Computed Tomography) detectors. A single DPC consists of a 2×2 pixel block array, TDC and trigger control module, and a single pixel block integrates 4 sub-pixel block arrays. For the trigger logic, DPC provides 4 different trigger count thresholds from high to low selected according to the number of sub-pixel blocks triggered. When the chip reaches the trigger count threshold and is triggered, it enters the verification logic. The MC array of each sub-pixel block is divided into multiple verification areas. Under this logic, the trigger event is verified to be a dark pulse or a real pulse event by logically connecting different verification areas. When the verification condition is not met, it is directly reset to wait for the next event to arrive. If the verification condition is met, it directly enters the chip acquisition state. After the acquisition is completed, the collected time and energy information are output. The single readout time of the chip is 680ns, and the event data is transmitted at a rate of 200M bits / s through two synchronous serial links. Since the overall architecture is relatively simple and the composition of the output data is relatively simple, the data that needs to be output is relatively small, and the pressure on data transmission is not great. However, the processing method of first identifying and then acquiring is adopted, and the verification logic is relatively complex, which leads to many events being screened out before data acquisition, limiting the counting rate of SiPM. At the same time, under this architecture, it is still affected by saturation, crosstalk, and dark counts, and the response to energy information is similar to that of analog SiPM; for time information, each flashing event only records a timestamp based on the trigger count threshold, which is more similar to a semi-digital SiPM.

[0004] Different from the architecture proposed by Frach, in 2011, the digital SiPM proposed by Veerappan is more similar to an image sensor. It borrows the concept of CMOS image sensor. Each individual MC is integrated with a corresponding processing module. The digital SiPM contains a 160×128 MC array, and each individual MC is integrated with an independent 10-bit wide TDC. There is a serial output interface at the top and bottom of each column. The 10-bit information of each pixel is output in parallel by column through a total of 320 independent serial interfaces. The maximum parallel working rate of all interfaces is 160M bits / s. Due to the large number of TDCs occupying most of the available area on the chip, the achievable fill factor is only less than 20%, the chip data readout time is greater than 4 microseconds, and the overall system power consumption is as high as 550 milliwatts.

[0005] It can be found that both the existing analog SiPM and digital SiPM have some drawbacks. On the one hand, due to the large parasitics of on-chip interconnects, bonding wires and external loads, the good inherent performance of the SPAD is not fully utilized, and the generated signal will deteriorate; on the other hand, it is highly sensitive to electronic noise and temperature changes. The existing digital SiPM architecture, which connects the pixel array to the counter and TDC photon counting digitization architecture by bus, is difficult to process photon counting data at a high speed; and the digital SiPM using micro-unit / TDC array improves the time performance, but the detection efficiency is low and the system power consumption is high.

[0006] The content of the background technology description is only for facilitating understanding of the relevant technology in this field and is not regarded as an admission of the prior art. Summary of the invention

[0007] Therefore, the present application intends to provide a multi-count threshold graded readout method, system and digital silicon photomultiplier, which can achieve high-speed and accurate readout of pulse event information with ideal circuit power consumption.

[0008] In a first aspect, a multi-count threshold hierarchical readout method is provided, the multi-count threshold hierarchical readout method comprising: The first data output by at least one pixel unit assembly module is read out in stages to obtain the sum of the photon counting data of all the pixel unit assembly modules, the size of the input data of each stage of the readout circuit is larger than the size of its output data, and the number of input data of each stage of the readout circuit is larger than the number of its output data.

[0009] In the embodiment of the present application, the number of levels of the graded readout includes any one of 2 to 20 levels.

[0010] In the embodiment of the present application, the number of levels of the graded readout is 3.

[0011] In the embodiment of the present application, the first data outputted by at least one pixel unit assembly module is read out in stages to obtain the sum of the photon counting data of all the pixel unit assembly modules, including: Performing a first-level conversion on the first data output by at least one pixel unit set module to obtain second data, wherein the second data includes at least two types of data with different weights; Grouping the data with the same weight in the second data into the same group, and performing the second-level transformation on all the group data to obtain the third data; The third data are added to obtain the sum of the photon counting data of all the pixel unit assembly modules.

[0012] In the embodiment of the present application, the adding of the third data is the adding of data with the same weight in the third data.

[0013] In the embodiment of the present application, the step of reading out the first data outputted by at least one pixel unit set module in a hierarchical manner includes: First, all the pixel unit assembly modules are divided into a plurality of large groups, each large group includes a plurality of pixel unit assembly modules, and the first data output by all the pixel unit assembly modules in the same large group are read out in stages.

[0014] In the embodiment of the present application, the first data outputted by at least one pixel unit assembly module is read out in stages to obtain the sum of the photon counting data of all the pixel unit assembly modules, including: All the pixel unit assembly modules are divided into multiple groups, and the first data output by each group is read out at the first level to obtain the second data. After all the second data are aggregated, the data with the same weight are read out at the second level to obtain the third data. After all the third data are aggregated, the data with the same weight are added to obtain the sum of the photon counting data of all the pixel unit assembly modules.

[0015] In the embodiment of the present application, the first data outputted by at least one pixel unit assembly module is read out in stages to obtain the sum of the photon counting data of all the pixel unit assembly modules, including: All the pixel unit assembly modules are divided into two large groups, each large group includes multiple pixel unit assembly modules, all the pixel unit assembly modules in the same large group are divided into multiple small groups, the first data output by each small group are read out at the first level together to obtain the second data, all the second data are aggregated and the data with the same weight are read out at the second level to obtain the third data, and all the third data are aggregated and the data with the same weight are added to obtain the sum of the photon counting data of all the pixel unit assembly modules in the large group.

[0016] In the embodiment of the present application, the first data outputted by at least one pixel unit assembly module is read out in stages to obtain the sum of the photon counting data of all the pixel unit assembly modules, including: Reading out the first data in multiple stages to obtain the second data; The second data is read out in stages for multiple times to obtain the third data.

[0017] In the embodiment of the present application, the step of reading the first data multiple times in a hierarchical manner to obtain the second data includes: The first data is read out through the first sub-grading and data compression is performed to obtain a plurality of first sub-data with different weights; Summarizing the first sub-data, and performing second sub-classification reading on the data with the same weight to obtain a plurality of second sub-data with different weights; The second sub-data are aggregated, and data with the same weight are added up to obtain the second data.

[0018] In the embodiment of the present application, the step of reading the second data multiple times in stages to obtain the third data includes: Summarizing the second data, and reading out the data with the same weight through the third sub-classification and performing data compression to obtain a plurality of third sub-data with different weights; Summarizing the third sub-data, and performing fourth sub-classification reading on the data with the same weight to obtain a plurality of fourth sub-data with different weights; The fourth sub-data are aggregated, and data with the same weight are added up to obtain the third data.

[0019] In a second aspect, a multi-count threshold grading readout system is provided, the multi-count threshold grading readout system comprising: At least two levels of readout circuits are used to read out the first data output by at least one pixel unit assembly module in a hierarchical manner to obtain the sum of the photon counting data of all the pixel unit assembly modules. The size of the input data of each level of readout circuit is larger than the size of its output data, and the number of input data of each level of readout circuit is larger than the number of its output data.

[0020] In the embodiment of the present application, the number of stages of the readout circuit includes any one of 2 to 20 stages.

[0021] In the embodiment of the present application, the number of stages of the readout circuit is 3.

[0022] In an embodiment of the present application, the readout circuit includes: A first-stage readout circuit, used for performing a first-stage conversion on the first data output by at least one pixel unit set module to obtain second data, wherein the second data includes at least two types of data with different weights; A second-stage readout circuit, used for performing a second-stage conversion on the data with the same weight in the second data to obtain third data; The third-level readout circuit is used to add the third data to obtain the sum of the photon counting data of all the pixel unit assembly modules.

[0023] In the embodiment of the present application, the adding of the third data is the adding of data with the same weight in the third data.

[0024] In an embodiment of the present application, the readout circuit includes two groups, each group of readout circuits is used to hierarchically read out the first data output by all the pixel unit collection modules located in the same large group, the number of the pixel unit collection modules is 2N, and N pixel unit collection modules constitute a large group.

[0025] In an embodiment of the present application, the readout circuit is used to perform a first-level readout of the first data output by each group together to obtain second data, and after aggregating all the second data, perform a second-level readout of the data with the same weight to obtain third data, and after aggregating all the third data, add the data with the same weight to obtain the sum of the photon counting data of all the pixel unit collection modules, and all the pixel unit collection modules are divided into n groups.

[0026] In an embodiment of the present application, the readout circuit includes two groups, and each group of the readout circuit is used to perform a first-level readout of the first data output by each small group in the same large group to obtain second data, and after all the second data are aggregated, the data with the same weight are performed a second-level readout to obtain third data, and after all the third data are aggregated, the data with the same weight are added to obtain the sum of the photon counting data of all pixel unit collection modules in the large group, and all the pixel unit collection modules constitute two large groups, each of which includes N pixel unit collection modules, and all the pixel unit collection modules in the same large group constitute n small groups.

[0027] In the embodiment of the present application, the first-level readout circuit is used to read out the first data in multiple stages to obtain the second data; The second-stage readout circuit is used for reading out the second data in multiple stages to obtain the third data.

[0028] In an embodiment of the present application, the first-level readout circuit includes: A first level readout circuit is used for performing data compression on the first data through a first sub-level readout to obtain a plurality of first sub-data with different weights; A first and second level readout circuit is used to aggregate the first sub-data and perform second sub-level readout on the data with the same weight to obtain a plurality of second sub-data with different weights; The first three-stage readout circuit is used to aggregate the second sub-data and add the data with the same weight to obtain the second data.

[0029] In an embodiment of the present application, the second-level readout circuit includes: A second primary readout circuit is used to aggregate the second data and perform data compression on the data with the same weight through a third sub-level readout to obtain a plurality of third sub-data with different weights; A second secondary readout circuit is used to aggregate the third sub-data and perform fourth sub-classification readout on the data with the same weight to obtain a plurality of fourth sub-data with different weights; The second third-level readout circuit is used to summarize the fourth sub-data and add the data with the same weight to obtain the third data.

[0030] In a third aspect, a multi-count threshold graded readout method or a multi-count threshold graded readout system according to the first aspect is provided for application in scientific instruments, medical equipment, high energy physics, deep space and deep sea exploration, extremely weak light imaging, radiation monitoring, autonomous driving, security equipment, consumer electronics or smart home appliances.

[0031] The multi-count threshold graded readout method provided in the present application can read out the photon counting data of the entire pixel array in real time by graded readout of the output data of the pixel array, avoiding the introduction of a large number of TDCs, and reducing system power consumption while ensuring data readout accuracy and efficiency.

[0032] Part of the optional features and other effects of the embodiments of the present application are described below, and part of them can be understood by reading this document. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The present application will be further described in the form of exemplary embodiments, which will be described in detail by the accompanying drawings. These embodiments are not restrictive, and in these embodiments, the same reference numerals represent the same structure, wherein: Figure 1 The structure diagram of the digital silicon photomultiplier according to the embodiment of the present application is shown; Figure 2 A flowchart of a multi-count threshold classification readout method according to an embodiment of the present application is shown; Figure 3 A flowchart of a multi-count threshold classification readout method according to a specific embodiment of the present application is shown; Figure 4 A flowchart of a multi-count threshold classification readout method according to a specific embodiment of the present application is shown; Figure 5 A flowchart of a multi-count threshold classification readout method according to a specific embodiment of the present application is shown; Figure 6 shows an architecture diagram of a readout circuit according to a specific embodiment of the present application; Figure 7 shows an architecture diagram of a first-level readout circuit according to a specific embodiment of the present application; Figure 8 shows an architecture diagram of a second-level readout circuit according to a specific embodiment of the present application; Fig. 9 shows an architecture diagram of a third-level readout circuit according to a specific embodiment of the present application; Fig.10 shows an architecture diagram of a readout circuit according to another specific embodiment of the present application; Fig.11 shows an architecture diagram of a second-stage readout circuit according to another specific embodiment of the present application; Fig.12 shows an architecture diagram of a readout circuit according to another specific embodiment of the present application; Fig.13 A schematic diagram of a power management module according to a specific embodiment of the present application is shown; Fig.14 A schematic diagram of a power management module according to another specific embodiment of the present application is shown. DETAILED DESCRIPTION

[0034] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0035] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on another element or there may also be a centered element. When an element is considered to be "connected" to another element, it may be directly connected to another element or there may be a centered element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are only for illustrative purposes. The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical solution of the present application can be practiced without one or more of these specific details, or other modes, components, materials, devices or operations, etc. may be adopted. In these cases, known structures, methods, devices, implementations, materials or operations will not be shown or described in detail.

[0036] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0037] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The term "and / or" or "and / or" includes any and all combinations of one or more related listed items.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0039] As mentioned above, among the technologies known to the inventors, digital SiPM shows great development potential in pulse event detection, and has higher detection performance and efficiency than analog SiPM. However, existing digital SiPM has problems such as difficulty in high-speed processing of photon counting data, low detection efficiency, and high system power consumption.

[0040] Moreover, since in an annihilation event, a large number of photons will arrive in the first few nanoseconds of the annihilation event, and the time when different MCs receive photons is random, the readout circuit needs to accurately count the pulse waveforms of a large number of triggered MCs in a very short time, which makes it difficult for the sequential logic circuit that introduces the clock to obtain the photon counting data in one clock cycle. Therefore, the present application proposes a hierarchical readout method. The hierarchical readout method can be applied in multiple fields, such as scientific instruments, medical equipment, high-energy physics, deep space and deep sea exploration, extremely weak light imaging, radiation monitoring, automatic driving, security inspection equipment, consumer electronics or smart home appliances. Taking medical equipment as an example, it can be applied to PET equipment. In this scenario, the digital SiPM, scintillation crystals and some electronic devices together constitute a detector. The front end of the digital SiPM is coupled with a scintillation crystal. After receiving the 511keV Gamma ray, the scintillation crystal converts it into visible light photons and outputs it to the digital SiPM, which is output after a series of processing on the visible light photons by the digital SiPM. The digital SiPM integrates MC array, digital interface circuit, readout circuit, comparator, TDC, etc. When a pulse event occurs, the visible light photons are detected by the MC array and converted into digital counting pulses through the digital interface circuit. The readout circuit uses a hierarchical readout method to count the counting data of the MC array and compares it with the preset counting threshold in the comparator. TDC records the time point when all counting data passes the counting threshold, and the data packaging module decodes and obtains all the "counting threshold-time" information pairs of the event. This process is also the process of the multiple counting threshold method.

[0041] In the embodiment of the present application, the provided hierarchical readout method digitally reads out the output data of the MC. Specifically, in the embodiment of the present application, the provided multi-count threshold hierarchical readout method includes: The first data outputted by at least one pixel unit assembly module is read out in stages to obtain the sum of the photon counting data of all the pixel unit assembly modules.

[0042] Figure 1 FIG. 4 shows an architecture diagram of a digital SiPM according to an embodiment of the present application using a hierarchical readout method. Figure 1As shown, the digital SiPM generally includes: a pixel array 100 and a readout circuit 200. The pixel array 100 includes a plurality of pixel unit assembly modules 110, each of which includes two or more pixels 111. Each of the pixel unit assembly modules 110 outputs data via a separate bus. The pixels 111 are used to detect visible light photons and can convert visible light photons into digital counting pulses. Originally, the information output by each pixel 111 needs to be read out. The present application simplifies this method to read out all pixels 111 in a pixel group only once, which can simplify the readout logic without losing information, and can reduce the amount of data that needs to be processed by the readout circuit 200 and improve the readout rate.

[0043] The pixel array 100 may include a×b pixels 111, wherein a and b are both integers greater than 2, and in one example, a and b are both 80. The pixel unit assembly module 110 includes c×d pixels 111, wherein c and d are both integers greater than 1, and at least one of c and d is greater than or equal to 2. It can be understood that, in some examples, all the pixel unit assembly modules 110 constitute the pixel array 100, and in other examples, one or some pixels 111 output data individually, not in the form of pixel unit assembly module 110, while other pixels 111 are grouped in a specific manner to form the pixel unit assembly module 110, and all pixels 111 that output data individually and all pixel unit assembly modules 110 together constitute the pixel array 100, and the number of pixels 111 included in each pixel unit assembly module 110 may be the same or different. Generally speaking, pixels 111 where visible light photons are relatively concentrated can be set to output data individually, and pixels 111 where visible light photons are relatively sparse can be set to output data together with a pixel unit collection module 110, thereby improving data processing efficiency and reducing data loss. Alternatively, pixels 111 where visible light photons are relatively concentrated can be set to output data with a pixel unit collection module 110 composed of relatively fewer pixels (each pixel unit collection module 110 includes relatively fewer pixels 111), and pixels 111 where visible light photons are relatively sparse can be set to output data with a pixel unit collection module 110 composed of relatively more pixels (each pixel unit collection module 110 includes relatively more pixels 111).

[0044] The first data may be a digital counting pulse.

[0045] The readout circuit 200 is connected to all the pixel unit assembly modules 110, and is used to read out the first data output by the pixel unit assembly module 110 in a hierarchical manner to obtain the sum of the photon counting data of all the pixel unit assembly modules 110. It can be understood that when there are pixels 111 that output data individually, the readout circuit 200 is also connected to all the pixels 111 that output data individually, and reads out the first data output by all the pixels 111 that output data individually and all the pixel unit assembly modules 110 in a hierarchical manner to obtain the sum of the photon counting data of all the pixel unit assembly modules 110.

[0046] In an example of the present application, the amount of input data of each level of readout circuit 200 is greater than the amount of output data, and the size of input data of each level of readout circuit 200 is greater than the size of output data. The amount of data can be reduced step by step, thereby achieving real-time readout of the overall array photon counting data and avoiding the introduction of a large number of TDCs.

[0047] In the present application, the number of levels of the graded readout includes any one of 2 to 20 levels.

[0048] Exemplarily, the number of levels of the graded readout is 3. Figure 2 As shown, the first data outputted by at least one pixel unit assembly module is read out in stages to obtain the sum of the photon counting data of all the pixel unit assembly modules, including: Step S100: performing a first-level conversion on the first data output by at least one pixel unit set module to obtain second data, wherein the second data includes at least two types of data with different weights; Step S200: grouping the data with the same weight in the second data into the same group, and performing a second-level transformation on all the group data to obtain third data; Step S300: Add the third data to obtain the sum of the photon counting data of all the pixel unit set modules.

[0049] In one example, the pixel array 100 includes 80×80 pixels 111, each of the pixel unit assembly modules 110 includes 2×2 pixels 111, and a total of 40×40 pixel unit assembly modules 110. In another example, the pixel array 100 includes 80×80 pixels 111, each of the pixel unit assembly modules 110 includes 2×4 pixels 111, and a total of 20×40 pixel unit assembly modules 110. In another example, the pixel array 100 includes 80×100 pixels 111, each of the pixel unit assembly modules 110 includes 2×2 pixels 111, and a total of 20×50 pixel unit assembly modules 110. In these examples, the first data output by all pixel unit collection modules 110 can be read out in three levels. In step S100, the number of high levels in the first data is converted into a 4-bit binary number (that is, the second data). In step S200, the data with the same weight in the second data are divided into a group, each group is processed separately, and the binary numbers of all groups are converted into new 4-bit binary numbers (that is, the third data). The number of each weight is counted. In step S300, the data with the same weight in the third data are added, specifically, the 4-bit binary numbers are added into an 8-bit binary number according to the corresponding weights, and the counting data of all pixel unit collection modules 110 are added, so as to obtain the number of all triggered pixel unit collection modules 110 in the pixel array 100 in an annihilation event.

[0050] It should be noted that, in the face of pixel arrays 100 of different sizes or different pixel unit assembly module 110 groups, it is only necessary to change the number of pixel unit assembly modules 110, the number of the previous level of classification and the number of input bits, to complete the statistics of the counting data. The number of input bits of the second level is determined by the number of the first level, and the number of the second level is determined by the output bits of the first level. The third level adds the output of the second level into a multi-bit binary number to complete the addition of the counting data between different groups. For different large groups, the same method as the small group addition method can be used for addition processing, or the data can be directly used for subsequent processing.

[0051] In one example, in order to increase the data processing speed, the pixel array 100 is divided into two large groups, the number of the pixel unit assembly modules 110 is 2N, and N pixel unit assembly modules 110 constitute a large group. Correspondingly, two groups of the readout circuits 200 are provided, and each large group of the pixel unit assembly modules 110 is respectively connected to a group of the readout circuits 200, so that the first data output by all the pixel unit assembly modules 110 in the same large group are read out in a hierarchical manner. Of course, it is understandable that when two groups of readout circuits 200 still cannot meet the requirements of the data processing speed, the number of groups of the readout circuits 200 can be further increased, and the pixel array 100 can be divided into more groups at the same time. However, since the number of the readout circuits 200 is larger, the complexity of the system structure is higher, so a balance should be struck between the two.

[0052] Furthermore, the group readout can further divide the pixel array 100 into n small groups. The multi-count threshold graded readout method includes: dividing all the pixel unit collection modules 110 into n small groups, performing a first-level readout of the first data output by each group together to obtain second data, aggregating all the second data and performing a second-level readout of data with the same weight to obtain third data, and aggregating all the third data and adding the data with the same weight to obtain the sum of the photon counting data of all the pixel unit collection modules 110.

[0053] Furthermore, the pixel array 100 may be first divided into a plurality of large groups, and then each large group may be further divided into a plurality of small groups. Exemplarily, the first data outputted by at least one pixel unit assembly module 110 is read out in stages to obtain the sum of the photon counting data of all the pixel unit assembly modules 110, including: dividing all the pixel unit assembly modules 110 into two large groups, each large group including N pixel unit assembly modules 110, dividing all the pixel unit assembly modules 110 in the same large group into n small groups, performing a first-stage readout of the first data outputted by each small group together to obtain second data, aggregating all the second data, performing a second-stage readout of data with the same weight to obtain third data, aggregating all the third data, and summing up the data with the same weight to obtain the sum of the photon counting data of all the pixel unit assembly modules 110 in the large group.

[0054] For example, for a pixel array 100 including 80×80 pixels 111, it is first divided into two large groups of pixel arrays 100, each pixel unit assembly module 110 includes 2×2 pixels 111, each large group includes 20×40 pixel unit assembly modules 110, and each large group is then divided into small groups according to columns, each column has 20 pixel unit assembly modules 110, and there are 40 columns, that is, 40 small groups. For another example, for a pixel array 100 including 80×80 pixels 111, it is first divided into two large groups of pixel arrays 100, each pixel unit assembly module 110 includes 2×4 pixels 111, each large group includes 20×20 pixel unit assembly modules 110, and each large group is then divided into small groups according to columns, each column has 20 pixel unit assembly modules 110, and there are 20 columns, that is, 20 small groups. For another example, for a pixel array 100 of 80×100 pixels 111, it is first divided into two large groups of pixel arrays 100, each pixel unit assembly module 110 includes 2×2 pixels 111, and then each large group includes 20×50 pixel unit assembly modules 110, and each large group is divided into small groups by column, each column has 20 pixel unit assembly modules 110, a total of 50 columns, or 50 small groups.

[0055] Furthermore, in an example of the present application, in each hierarchical readout step, further grading may be performed, thereby further improving data readout efficiency. Figure 3 As shown, the first data outputted by at least one pixel unit assembly module is read out in stages to obtain the sum of the photon counting data of all the pixel unit assembly modules, including: Step S110: reading the first data in multiple stages to obtain the second data; Step S210: The second data is read out in multiple stages to obtain the third data.

[0056] like Figure 4 As shown, step S110 may more specifically include: Step S111: the first data is read out through the first sub-level classification and data compression is performed to obtain a plurality of first sub-data with different weights; Step S112: Summarize the first sub-data, and read out the data with the same weight by second sub-classification to obtain a plurality of second sub-data with different weights; Step S113: Summarize the second sub-data, and add up the data with the same weight to obtain the second data.

[0057] like Figure 5 As shown, step S210 may more specifically include: Step S211: Summarize the second data, and perform data compression on the data with the same weight by reading out the data through the third sub-level classification to obtain a plurality of third sub-data with different weights; Step S212: Summarize the third sub-data, and read out the data with the same weight in a fourth sub-level manner to obtain a plurality of fourth sub-data with different weights; Step S213: Summarize the fourth sub-data, and add up the data with the same weight to obtain the third data.

[0058] In a previous example, the pixel array 100 includes 80×80 pixels 111, which are divided into two large groups, the upper and lower pixel arrays 100, each pixel unit assembly module 110 includes 2×2 pixels 111, each large group includes 20×40 pixel unit assembly modules 110, each column has 20 pixel unit assembly modules 110, a total of 40 columns, and every two columns in each large group are a small group, that is, a total of 20 small groups. Taking this example as an example, step S111 receives the first data output from all the small groups. Taking one of the small groups as an example, the first data A0-A1 is received. 39 , the first data A0-A 39 The number of medium and high level signals is compressed into a 3-bit binary number D i C i B i , and a total of six 3-bit numbers D0C0B0-D5C5B5 are obtained. These are the first sub-data. The weights of B0-B5 are the same, the weights of C0-C5 are the same, and the weights of D0-D5 are the same. Step S112 processes D0C0B0-D5C5B5 and obtains the count value E2E1E0 with a weight of 1, the count value E5E4E3 with a weight of 2, and the count value E8E7E6 with a weight of 4. These are the second sub-data. Step S113 adds the second sub-data according to the corresponding weights to obtain the second data, namely P0Q0R0S0. After obtaining the second data P0Q0R0S0-P0Q0R0S0 of the 20 small groups of pixel unit collection modules 110, 19 Q 19 R 19 S 19 Then, step S211 sets P0-P 19 、Q0-Q 19 , R0-R 19 and S0-S 19 The third sub-data is obtained by compression, for example, P0-P 19 The number of medium and high level signals is compressed into a 2-bit binary number C i_2 B i_2 , Q0-Q 19 , R0-R 19 and S0-S 19The same operation is performed. Step S222 compresses the third sub-data to obtain the fourth sub-data, for example, 0_2 -B 6_2 The obtained count value E with a weight of 1 2_2 E 1_2 E 0_2 , by C 0_2 -C 6_2 The count values ​​E with weight 2 are obtained respectively 5_2 E 4_2 E 3_2 Step S223 adds the fourth sub-data to obtain the third data, for example, 5_2 E 4_2 E 3_ 2E 2_2 E 1_2 E 0_2 The sum is 4 bits of count data H0I0J0K0, Q0-Q 19 , R0-R 19 and S0-S 19 The final corresponding third data are I1-L1, J2-M2, and K3-N3 respectively.

[0059] Then, in step S300, multi-level readout can also be performed. For example, continuing the above example, I0-K0 and I1-L1 are added to obtain M4L4K4J4I4, J2-M2 and K3-N3 are added to obtain N5M5L5K5J5, and H0 directly extracts the count data to obtain T0. Then, a half adder is used to add J4 and J5 to obtain J6 and K6, and count data T2 is extracted from J6, and count data T1 is extracted from I4. Finally, the bits of KN are added, and after completing the delay matching of each bit signal, the final 8-bit output signal is obtained, that is, the final count data T0-T7.

[0060] Since it is found from simulation that the number of transistor quenching the next group of pixel unit set modules 110 triggered will hardly exceed 15, therefore, in step S113, the maximum sum can be set to 4 bits, and the new 4-bit number S j R j Q j P j It becomes the counting data of the number of pixels in a small group of 40 pixel unit assembly modules 110 that are in an excited state.

[0061] In another example mentioned above, the pixel array 100 includes 80×80 pixels 111, which are divided into two large groups of pixel arrays 100, each pixel unit assembly module 110 includes 2×4 pixels 111, each large group includes 20×20 pixel unit assembly modules 110, each column has 20 pixel unit assembly modules 110, and there are 20 columns in total. In each large group, every two columns form a small group, that is, 10 small groups. Taking this example as an example, step S111 receives the first data output from all the small groups. Taking one of the small groups as an example, the first data A0-A is received. 39 , the first data A0-A 39 The number of medium and high level signals is compressed into a 3-bit binary number D i C i B i , a total of six 3-bit numbers D0C0B0-D5C5B5 are obtained, which are the first sub-data, B0-B5 have the same weight, C0-C5 have the same weight, and D0-D5 have the same weight. Step S112 processes D0C0B0-D5C5B5 to obtain count values ​​E2E1E0 with a weight of 1, count values ​​E5E4E3 with a weight of 2, and count values ​​E8E7E6 with a weight of 4, which are the second sub-data. Step S113 adds the second sub-data according to the corresponding weights to obtain the second data, namely P0Q0R0S0. After obtaining the second data P0Q0R0S0-P9Q9R9S9 of the 10 small groups of pixel unit collection modules 110, step S211 compresses the second data with the same weight to obtain the third sub-data, for example, compressing the number of high-level signals in P0-P8 into a 2-bit binary number C i_2 B i_2 It should be noted that in this special case, the weight of P9 is the same as that of C i_2 B i_2 The same, so it is placed in step S222 for processing. Of course, it can be understood that in other examples, there may be any one or more weights of P0-P9 that are the same as the weight of the next level, or there may be all P0-P9 that are different from the weight of the next level. When there is a same, the data with the same weight as the next level is moved to the next step for processing. When there is no same, that is, the weights of P0-P9 are the same, then P0-P9 are compressed together. Q0-Q9, R0-R9 and S0-S9 also perform the same operation. Step S222 compresses the third sub-data to obtain the fourth sub-data, for example, P9, B 0_2 -B 2_2 The obtained count value E with a weight of 1 2_2 E 1_2 E 0_2 , by C 0_2 -C 2_2 The count values ​​E with weight 2 are obtained respectively4_2 E 3_2 Step S223 adds the fourth sub-data to obtain the third data, for example, 2_2 E 1_2 E 0_2 E 4_2 E 3_2 The sum of the 4-bit counting data H0I0J0K0, Q0-Q9, R0-R9 and S0-S9 finally corresponds to the third data I1-L1, J2-M2 and K3-N3 respectively.

[0062] Then, in step S300, multi-level readout can also be performed. For example, continuing the above example, I0-K0 and I1-L1 are added to obtain M4L4K4J4I4, J2-M2 and K3-N3 are added to obtain N5M5L5K5J5, and H0 directly extracts the count data to obtain T0. Then, a half adder is used to add J4 and J5 to obtain J6 and K6, and count data T2 is extracted from J6, and count data T1 is extracted from I4. Finally, the bits of KN are added, and after completing the delay matching of each bit signal, the final 8-bit output signal is obtained, that is, the final count data T0-T7.

[0063] In another example mentioned above, for a pixel array 100 including 80×100 pixels 111, it is first divided into two large groups of pixel arrays 100, each pixel unit assembly module 110 includes 2×2 pixels 111, and each large group includes 20×50 pixel unit assembly modules 110, each column has 20 pixel unit assembly modules 110, a total of 50 columns, and every two columns in each large group form a small group, that is, 25 small groups. Taking this example as an example, step S111 receives the first data output from all the small groups. Taking one of the small groups as an example, the first data A0-A1 is received. 39 , the first data A0-A 39 The number of medium and high level signals is compressed into a 3-bit binary number D i C i B i , and six 3-bit numbers D0C0B0-D5C5B5 are obtained in total. These are the first sub-data. The weights of B0-B5 are the same, the weights of C0-C5 are the same, and the weights of D0-D5 are the same. Step S112 processes D0C0B0-D5C5B5 and obtains the count value E2E1E0 with a weight of 1, the count value E5E4E3 with a weight of 2, and the count value E8E7E6 with a weight of 4. These are the second sub-data. Step S113 adds the second sub-data according to the corresponding weights to obtain the second data, namely P0Q0R0S0. After obtaining the second data P0Q0R0S0-P0Q0R0S0 of the 25 small groups of pixel unit set modules 110, 24 Q 24 R24 S 24 Then, step S211 compresses the second data with the same weight to obtain the third sub-data, for example, P0-P 24 The number of medium and high level signals is compressed into a 2-bit binary number C i_2 B i_2 It should be noted that in this special case, P 24 The weight of C i_2 B i_2 The same, so it is put into step S222 for processing. Of course, it can be understood that in other examples, there may be P0-P 24 Any one or more weights in the same level are the same as the weights of the next level. There may also be P0-P 24 All the weights in the above are different from those in the next level. If there is a difference, the data with the same weight as the next level will be moved to the next step for processing. If there is no difference, that is, P0-P 24 The weights are the same, then P0-P 24 Compress together. Q0-Q 24 , R0-R 24 and S0-S 24 The same operation is performed. Step S222 compresses the third sub-data to obtain the fourth sub-data, for example, 24 , B 0_2 -B 7_2 , C 0_2 -C 7_2 The count values ​​E obtained respectively 8_2 E 7_2 E 6_2 E 5_ 2E 4_2 E 3_2 E 2_2 E 1_2 E 0_2 Step S223 adds the fourth sub-data to obtain the third data, for example, 8_2 E 7_2 E 6_2 E 5_2 E 4_ 2E 3_2 E 2_2 E 1_2 E 0_2 The sum is 4 bits of count data H0I0J0K0L0, Q0-Q 24 , R0-R 24 and S0-S 24 The final corresponding third data are I1-M1, J2-N2, and K3-Q3 respectively.

[0064] Then, in step S300, multi-level readout can also be performed. For example, continuing the above example, I0-L0 and I1-M1 are added to obtain M4L4K4J4I4, J2-N2 and K3-Q3 are added to obtain N5M5L5K5J5, and H0 directly extracts the count data to obtain T0. Then, a half adder is used to add J4 and J5 to obtain J6 and K6, and count data T2 is extracted from J6, and count data T1 is extracted from I4. Finally, the bits of KN are added, and after completing the delay matching of each bit signal, the final 8-bit output signal is obtained, that is, the final count data T0-T7.

[0065] The multi-count threshold graded readout method provided in the present application can read out the photon counting data of the entire pixel array 100 in real time by graded readout of the output data of the pixel array, thereby avoiding the introduction of a large number of TDCs and reducing system power consumption.

[0066] Corresponding to the above-mentioned multi-count threshold graded readout method, the present application also provides a multi-count threshold graded readout system. Exemplarily, the multi-count threshold graded readout system includes: at least two-stage readout circuits 200, which are used to graded readout the first data output by at least one pixel unit collection module 110 to obtain the sum of the photon count data of all the pixel unit collection modules 110.

[0067] like Figure 1As shown, the digital SiPM generally includes: a pixel array 100 and a readout circuit 200. The pixel array 100 includes a plurality of pixel unit assembly modules 110, each of which includes two or more pixels 111. Each of the pixel unit assembly modules 110 outputs data via an independent bus. The pixels 111 are used to detect visible light photons and can convert visible light photons into digital counting pulses. By simplifying the original output information of each pixel 111 to be read out as a group readout strategy in which all pixels 111 in a group are read out only once, the readout logic can be simplified without losing information, and the amount of data that the readout circuit 200 needs to process can be reduced and the readout rate can be improved. The pixel array 100 may include a×b pixels 111, wherein a and b are both integers greater than 2. In one example, a and b are both 80. The pixel unit assembly module 110 includes c×d pixels 111, wherein c and d are both integers greater than 1, and at least one of c and d is greater than or equal to 2. It can be understood that, in some examples, all of the pixel unit collection modules 110 constitute the pixel array 100, and in other examples, one or some pixels 111 output data individually and do not output data in the form of pixel unit collection module 110, while other pixels 111 are grouped in a specific manner to form the pixel unit collection module 110, and all pixels 111 that output data individually and all pixel unit collection modules 110 together constitute the pixel array 100, and the number of pixels 111 included in each pixel unit collection module 110 may be the same or different. Generally speaking, the pixels 111 with relatively concentrated visible light photons can be set to output data individually, and the pixels 111 with relatively sparse visible light photons can be set to output data together with the pixel unit assembly module 110, so as to improve the data processing efficiency and reduce data loss. Alternatively, the pixels 111 with relatively concentrated visible light photons can be set to output data with a relatively small number of pixels forming a pixel unit assembly module 110 (each pixel unit assembly module 110 includes relatively few pixels 111) and the pixels 111 with relatively sparse visible light photons can be set to output data with a relatively large number of pixels forming a pixel unit assembly module 110 (each pixel unit assembly module 110 includes relatively many pixels 111). The readout circuit 200 is connected to all the pixel unit assembly modules 110, and the readout circuit 200 is used to read out the first data output by the pixel unit assembly module 110 in a hierarchical manner to obtain the sum of the photon count data of all the pixel unit assembly modules 110.It can be understood that when there are pixels 111 that output data individually, the readout circuit 200 is also connected to all pixels 111 that output data individually, and obtains the sum of the photon counting data of all the pixel unit collection modules 110 by hierarchical reading based on all pixels 111 that output data individually and the first data output by all pixel unit collection modules 110.

[0068] In an example of the present application, the amount of input data of each level of readout circuit 200 is greater than the amount of output data, and the size of input data of each level of circuit is greater than the size of output data, so the amount of data can be reduced step by step, thereby achieving real-time readout of the overall array photon counting data and avoiding the introduction of a large number of TDCs.

[0069] In the present application, the number of stages of the readout circuit 200 includes any one of 2 to 20 stages.

[0070] Exemplarily, the number of stages of the readout circuit 200 is 3. Figure 6 As shown, the readout circuit 200 includes: a first-level readout circuit 210, a second-level readout circuit 220 and a third-level readout circuit 230. The first-level readout circuit 210 is used to perform a first-level conversion on the first data output by at least one pixel unit assembly module 110 to obtain second data, and the second data includes at least two data with different weights. The second-level readout circuit 220 is used to perform a second-level conversion on the data with the same weight in the second data to obtain third data. The third-level readout circuit 230 is used to add the third data to obtain the sum of the photon counting data of all the pixel unit assembly modules 110.

[0071] In one example, the pixel array 100 includes 80×80 pixels 111, each of the pixel unit assembly modules 110 includes 2×2 pixels 111, and a total of 40×40 pixel unit assembly modules 110. In another example, the pixel array 100 includes 80×80 pixels 111, each of the pixel unit assembly modules 110 includes 2×4 pixels 111, and a total of 20×40 pixel unit assembly modules 110. In another example, the pixel array 100 includes 80×100 pixels 111, each of the pixel unit assembly modules 110 includes 2×2 pixels 111, and a total of 20×50 pixel unit assembly modules 110. In these examples, the first data output by all pixel unit assembly modules 110 can be read out in three levels. The first-level readout circuit 210 converts the number of high levels in the first data into a 4-bit binary number (that is, the second data), the second-level readout circuit 220 divides the data with the same weight in the second data into a group, processes each group separately, converts the binary numbers of all groups into new 4-bit binary numbers (that is, the third data), and counts the number of each weight. The third-level readout circuit 230 adds the data with the same weight in the third data, specifically adds the 4-bit binary number into an 8-bit binary number according to the corresponding weight, completes the addition of the counting data of all pixel unit collection modules 110, and obtains the number of all triggered pixel unit collection modules 110 in the pixel array 100 in an annihilation event.

[0072] It should be particularly noted that, in the face of pixel arrays 100 of different sizes or different pixel unit assembly module 110 groups, it is only necessary to change the number of the previous level readout circuits and the number of input bits according to the number of pixel unit assembly modules 110 to complete the statistics of the counting data. The number of input bits of the second-level readout circuit 220 is determined by the number of the first-level readout circuit 210, and the number of the second-level readout circuit 220 is determined by the output bit number of the first level. The third-level readout circuit 230 adds the output of the second-level readout circuit 220 into a multi-bit binary number to complete the addition of the counting data between different groups. For different large groups, the same addition method as the small group addition method can be adopted for addition processing, or the data can be directly used for subsequent processing.

[0073] In one example, in order to increase the data processing speed, the pixel array 100 is divided into two large groups, the number of the pixel unit assembly modules 110 is 2N, and N pixel unit assembly modules 110 constitute a large group. Correspondingly, two groups of readout circuits 200 are provided, and each large group of the pixel unit assembly modules 110 is respectively connected to a group of the readout circuits 200, and each group of the readout circuits 200 is used to hierarchically read out the first data output by all the pixel unit assembly modules 110 in the same large group. Of course, it is understandable that when two readout circuits 200 still cannot meet the data processing speed requirements, the number of readout circuits 200 can be further increased, and the pixel array 100 can be divided into more groups at the same time. However, since the more the number of readout circuits 200, the higher the complexity of the system structure, a balance should be struck between the two.

[0074] Furthermore, the group readout can further divide the pixel array 100 into n small groups, and the readout circuit 200 is used to perform a first-level readout on the first data output by each small group to obtain second data, and after aggregating all the second data, perform a second-level readout on the data with the same weight to obtain third data, and after aggregating all the third data, add the data with the same weight to obtain the sum of the photon counting data of all the pixel unit collection modules 110, and all the pixel unit collection modules 110 are divided into n small groups.

[0075] Furthermore, the pixel array 100 can be divided into a plurality of large groups first, and then each large group can be divided into a plurality of small groups. Exemplarily, the readout circuit 200 includes two groups, and each group of the readout circuit 200 is used to read out the first data output by each small group in the same large group together at the first level to obtain the second data, and after all the second data are aggregated, the data with the same weight are read out at the second level to obtain the third data, and after all the third data are aggregated, the data with the same weight are added to obtain the sum of the photon counting data of all the pixel unit collection modules 110 in the large group, and all the pixel unit collection modules 110 constitute two large groups, each large group includes N pixel unit collection modules 110, and all the pixel unit collection modules 110 in the same large group constitute n small groups.

[0076] For example, for a pixel array 100 of 80×80 pixels 111, it is first divided into two large groups of pixel arrays 100, each pixel unit assembly module 110 includes 2×2 pixels 111, and each large group includes 20×40 pixel unit assembly modules 110. Each large group is then divided into small groups according to columns, and each column has 20 pixel unit assembly modules 110, for a total of 40 columns, that is, 40 small groups. For another example, for a pixel array 100 of 80×80 pixels 111, it is first divided into two large groups of pixel arrays 100, each pixel unit assembly module 110 includes 2×4 pixels 111, and each large group includes 20×20 pixel unit assembly modules 110. Each large group is then divided into small groups according to columns, and each column has 20 pixel unit assembly modules 110, for a total of 20 columns, that is, 20 small groups. For another example, for a pixel array 100 of 80×100 pixels 111, it is first divided into two large groups of pixel arrays 100, each pixel unit assembly module 110 includes 2×2 pixels 111, and then each large group includes 20×50 pixel unit assembly modules 110, and each large group is divided into small groups by column, each column has 20 pixel unit assembly modules 110, a total of 50 columns, or 50 small groups.

[0077] Furthermore, in an example of the present application, in each hierarchical readout step, grading can be further performed, thereby further improving the data readout efficiency. Exemplarily, the first-level readout circuit 210 is used to hierarchically read out the first data multiple times to obtain the second data; the second-level readout circuit 220 is used to hierarchically read out the second data multiple times to obtain the third data.

[0078] Specifically, the first-level readout circuit 210 includes: a first-level readout circuit 211, a first-level readout circuit 212, and a first-level readout circuit 213. The first-level readout circuit 211 is used to compress the first data through the first sub-level readout to obtain a plurality of first sub-data with different weights. The first-level readout circuit 212 is used to summarize the first sub-data, and perform the second sub-level readout on the data with the same weight to obtain a plurality of second sub-data with different weights. The first-level readout circuit 213 is used to summarize the second sub-data, and add the data with the same weight to obtain the second data.

[0079] Specifically, the second-level readout circuit 220 includes: a second-level readout circuit 221, a second-level readout circuit 222, and a second-level readout circuit 223. The second-level readout circuit 221 is used to summarize the second data, and perform data compression on the data with the same weight through the third sub-level readout to obtain a plurality of third sub-data with different weights. The second-level readout circuit 222 is used to summarize the third sub-data, and perform a fourth sub-level readout on the data with the same weight to obtain a plurality of fourth sub-data with different weights. The second-level readout circuit 223 is used to summarize the fourth sub-data, and add the data with the same weight to obtain the third data.

[0080] In the above example, the pixel array 100 includes 80×80 pixels 111, which are divided into two large groups, the upper and lower pixel arrays 100, each pixel unit assembly module 110 includes 2×2 pixels 111, each large group includes 20×40 pixel unit assembly modules 110, each column has 20 pixel unit assembly modules 110, a total of 40 columns, and every two columns in each large group are a small group, that is, a total of 20 small groups. Taking this example as an example, if Figure 6 and Figure 7 As shown, the first-stage readout circuit 210 includes 20 40-4 three-stage compressors (where 40-4 means 40-4 means compressing 40 pixel inputs into a 4-bit binary number), and each three-stage compressor includes a first first-stage readout circuit 211, a first second-stage readout circuit 212, and a first third-stage readout circuit 213. Each first first-stage readout circuit 211 includes 6 7-3 or 6-3 compressors (compression units) (where 7-3 means compressing 7 previous stage inputs into a 3-bit binary number, and 6-3 means compressing 6 previous stage inputs into a 3-bit binary number), receiving the first data output from the group, taking one of the groups as an example, receiving the first data A0-A 39 , the first data A0-A 39 The number of medium and high level signals is compressed into a 3-bit binary number D i C i B i, a total of six 3-bit numbers D0C0B0-D5C5B5 are obtained, which are the first sub-data, B0-B5 have the same weight, C0-C5 have the same weight, and D0-D5 have the same weight. Each of the first and second level readout circuits 212 includes three 6-3 compressors (compression units) for processing D0C0B0-D5C5B5, and obtains count values ​​E2E1E0 with a weight of 1, count values ​​E5E4E3 with a weight of 2, and count values ​​E8E7E6 with a weight of 4, which are the second sub-data. The first tertiary readout circuit 213 is a Lookahead CarryAdder, which is used to add the second sub-data according to the corresponding weights to obtain the second data, namely P0Q0R0S0. After obtaining the second data P0Q0R0S0-P0Q0R0S0 of the 20 small groups of pixel unit collection modules 110 19 Q 19 R 19 S 19 After that, the second-stage readout circuit 220 is used for subsequent operations. Figure 8 As shown, the second-stage readout circuit 220 includes four 20-4 compressors (where 20-4 means compressing 20 first-stage inputs into a 4-bit binary number), and each 20-4 compressor includes a second first-stage readout circuit 221, a second second-stage readout circuit 222, and a second third-stage readout circuit 223. Each second first-stage readout circuit 221 includes seven 3-2 compressors (where 3-2 means compressing three previous-stage inputs into a 2-bit binary number), which are used to compress P0-P19, Q0-Q19, R0-R19, and S0-S19 with the same weight to obtain the third sub-data, for example, P0-P 19 The number of medium and high level signals is compressed into a 2-bit binary number C i_2 B i_2 , Q0-Q 19 , R0-R 19 and S0-S 19 The same operation is performed. Each second secondary readout circuit 222 includes two 6-3 compressors (compression units) to compress the third sub-data to obtain the fourth sub-data, for example, 0_2 -B 6_2 The obtained count value E with a weight of 1 2_2 E 1_2 E 0_2 , by C 0_2 -C 6_2 The count values ​​E with weight 2 are obtained respectively 5_2 E 4_2 E 3_2The second third-level readout circuit 223 is a Lookahead CarryAdder, which is used to add the fourth sub-data to obtain the third data, for example, 5_2 E 4_2 E 3_2 E 2_2 E 1_2 E 0_2 The sum is 4 bits of count data H0I0J0K0, Q0-Q 19 , R0-R 19 and S0-S 19 The final corresponding third data are I1-L1, J2-M2, and K3-N3 respectively.

[0081] Then, the third-level readout circuit 230 can also perform multi-level readout, for example, continuing the above example, as Fig. 9 As shown, first, two 4-bit LCAs are used to add I0-K0 and I1-L1 to obtain M4L4K4J4I4, and J2-M2 and K3-N3 are added to obtain N5M5L5K5J5. H0 directly extracts the count data to obtain T0. Then, J4 and J5 are added by half adder HA to obtain J6 and K6, and count data T2 is extracted from J6, and count data T1 is extracted from I4. Finally, the bits of KN are added by a 4-bit LCA, and after completing the delay matching of each bit signal, the final 8-bit output signal is obtained, that is, the final count data T0-T7.

[0082] Since it is found from simulation that the number of transistor quenching the next group of pixel unit set modules 110 triggered will hardly exceed 15, therefore, in the first three-stage readout circuit 213, the maximum sum can be set to 4 bits, and the new 4-bit number S j R j Q j P j It becomes the counting data of the number of pixels in a small group of 40 pixel unit assembly modules 110 that are in an excited state.

[0083] In another example described above, the pixel array 100 includes 80×80 pixels 111, which are divided into two large groups, each pixel unit assembly module 110 includes 2×4 pixels 111, each large group includes 20×20 pixel unit assembly modules 110, each column has 20 pixel unit assembly modules 110, and there are 20 columns in total. In each large group, every two columns form a small group, that is, 10 small groups. Taking this example as an example, refer to Fig.10The first stage circuit includes 10 40-4 compressors (compression units), each of which includes a first primary readout circuit 211, a first secondary readout circuit 212, and a first tertiary readout circuit 213. The first stage circuit simultaneously receives the first data output from all groups. Take one of the groups as an example, receiving the first data A0-A 39 The first level readout circuit 211 reads the first data A0-A 39 The number of medium and high level signals is compressed into a 3-bit binary number D i C i B i , six 3-bit numbers D0C0B0-D5C5B5 are obtained in total, which are the first sub-data, and the weights of B0-B5 are the same, the weights of C0-C5 are the same, and the weights of D0-D5 are the same. The first and second level readout circuits 212 process D0C0B0-D5C5B5, and obtain the count values ​​E2E1E0 with a weight of 1, the count values ​​E5E4E3 with a weight of 2, and the count values ​​E8E7E6 with a weight of 4, which are the second sub-data. The first and third level readout circuits 213 add the second sub-data according to the corresponding weights to obtain the second data, namely P0Q0R0S0. After obtaining the second data P0Q0R0S0-P9Q9R9S9 of the 10 small groups of pixel unit set modules 110, the second level circuit is used for subsequent processing. The second-stage readout circuit 220 includes four 10-4 compressors (compression units), each of which includes a second first-stage readout circuit 221, a second second-stage readout circuit 222, and a second third-stage readout circuit 223. Fig.11 The second primary readout circuit 221 includes three 3-2 compressors (compression units) for compressing the second data with the same weight to obtain the third sub-data, for example, compressing the number of high-level signals in P0-P8 into a 2-bit binary number C i_2 B i_2 It should be noted that in this special case, the weight of P9 is the same as that of C i_2 B i_2The same, so it is placed in the second secondary readout circuit 222 for processing. Of course, it can be understood that in other examples, there may be any one or more weights of P0-P9 that are the same as the weight of the next level, or there may be all P0-P9 that are different from the weight of the next level. When there is a same, the data with the same weight as the next level is moved to the next level readout circuit for processing. When there is no same, that is, the weights of P0-P9 are the same, then P0-P9 are compressed together. Q0-Q9, R0-R9 and S0-S9 also perform the same operation. The second secondary readout circuit 222 includes two 4-3 compressors (compression units) for compressing the third sub-data to obtain the fourth sub-data, for example, P9, B 0_2 -B 2_2 The obtained count value E with a weight of 1 2_2 E 1_2 E 0_2 , by C 0_2 -C 2_2 The count values ​​E with weight 2 are obtained respectively 4_2 E 3_2 The second third-level readout circuit 223 is Adder21-4, which is used to add the fourth sub-data to obtain the third data. For example, 2_2 E 1_2 E 0_2 E 4_2 E 3_2 The sum of the 4-bit counting data H0I0J0K0, Q0-Q9, R0-R9 and S0-S9 finally corresponds to the third data I1-L1, J2-M2 and K3-N3 respectively.

[0084] Then, the third-level readout circuit 230Adder21_4 can also perform multi-level readout. For example, continuing the above example, first, two 4-bit LCAs are used to add I0-K0 and I1-L1 to obtain M4L4K4J4I4, and J2-M2 and K3-N3 are added to obtain N5M5L5K5J5. H0 directly extracts the count data to obtain T0. Then, a half adder HA is used to add J4 and J5 to obtain J6 and K6, and the count data T2 is extracted from J6, and the count data T1 is extracted from I4. Finally, a 4-bit LCA is used to add the bits of KN, and after completing the delay matching of each bit signal, the final 8-bit output signal is obtained, that is, the final count data T0-T7.

[0085] In another example mentioned above, for a pixel array 100 including 80×100 pixels 111, it is first divided into two large groups of pixel arrays 100, each pixel unit assembly module 110 includes 2×2 pixels 111, and each large group includes 20×50 pixel unit assembly modules 110, each column has 20 pixel unit assembly modules 110, and there are 50 columns in total. In each large group, every two columns form a small group, that is, 25 small groups. Taking this example as an example, see Fig.12 The first-level readout circuit 210 includes 25 40-4 compressors (compression units), each of which includes a first-level readout circuit 211, a first-level readout circuit 212, and a first-level readout circuit 213. The first-level readout circuit 210 simultaneously receives the first data output from all groups. Taking one of the groups as an example, the first-level readout circuit 211 receives the first data A0-A 39 , the first data A0-A 39 The number of medium and high level signals is compressed into a 3-bit binary number D i C i B i , a total of six 3-bit numbers D0C0B0-D5C5B5 are obtained, which are the first sub-data. The weights of B0-B5 are the same, the weights of C0-C5 are the same, and the weights of D0-D5 are the same. The first and second level readout circuits 212 process D0C0B0-D5C5B5 and obtain the count values ​​E2E1E0 with a weight of 1, the count values ​​E5E4E3 with a weight of 2, and the count values ​​E8E7E6 with a weight of 4, which are the second sub-data. The first tertiary readout circuit 213 adds the second sub-data according to the corresponding weights to obtain the second data, namely P0Q0R0S0. After obtaining the second data P0Q0R0S0-P0Q0R0S0 of the 25 small groups of pixel unit assembly modules 110, 24 Q 24 R 24 S 24 After that, the second-level readout circuit 220 performs subsequent processing. The second-level readout circuit 220 includes four 25-5 compressors (compression units), each of which includes a second-level readout circuit 221, a second-level readout circuit 222, and a second-level readout circuit 223. The second-level readout circuit 221 is used to compress the second data with the same weight to obtain the third sub-data, for example, P0-P 24 The number of medium and high level signals is compressed into a 2-bit binary number C i_2 B i_2 It should be noted that in this special case, P 24 The weight of C i_2 B i_2The same, so it is placed in the second secondary readout circuit 222 for processing. Of course, it can be understood that in other examples, there may be P0-P 24 Any one or more weights in the same level are the same as the weights of the next level. There may also be P0-P 24 All the weights in the above are different from those in the next level. If there is a difference, the data with the same weight as the next level will be moved to the next step for processing. If there is no difference, that is, P0-P 24 The weights are the same, then P0-P 24 Compress together. Q0-Q 24 , R0-R 24 and S0-S 24 The second secondary readout circuit 222 compresses the third sub-data to obtain the fourth sub-data, for example, 24 , B 0_2 -B 7_2 , C 0_2 -C 7_2 The count values ​​E obtained respectively 8_2 E 7_2 E 6_2 E 5_2 E 4_2 E 3_2 E 2_2 E 1_2 E 0_2 The second third-level readout circuit 223 adds the fourth sub-data to obtain the third data, for example, 8_2 E 7_2 E 6_2 E 5_2 E 4_2 E 3_2 E 2_2 E 1_2 E 0_2 The sum is 4 bits of count data H0I0J0K0L0, Q0-Q 24 , R0-R 24 and S0-S 24 The final corresponding third data are I1-M1, J2-N2, and K3-Q3 respectively.

[0086] Then, the third-level circuit Adder_8bits can also perform multi-level readout. For example, continuing the above example, I0-L0 and I1-M1 are added to obtain M4L4K4J4I4, J2-N2 and K3-Q3 are added to obtain N5M5L5K5J5, and H0 directly extracts the count data to obtain T0. Then, a half adder is used to add J4 and J5 to obtain J6 and K6, and the count data T2 is extracted from J6, and the count data T1 is extracted from I4. Finally, the bits of KN are added, and after completing the delay matching of each bit signal, the final 8-bit output signal is obtained, that is, the final count data T0-T7.

[0087] The multi-count threshold graded readout system provided in the present application can read out the photon counting data of the entire pixel array 100 in real time by graded readout of the output data of the pixel array 100, thereby avoiding the introduction of a large number of TDCs and reducing system power consumption.

[0088] Corresponding to the above multi-count threshold graded readout system, an embodiment of the present application further provides a digital silicon photomultiplier, which includes the multi-count threshold graded readout system provided in the above example. In addition to the above pixel array 100 and the readout circuit 200, in an example of the present application, the digital silicon photomultiplier further includes an interface circuit 700, and the interface circuit 700 is connected between the pixel 111 and the readout circuit 200.

[0089] Further, in one example of the present application, see Figure 1 The digital silicon photomultiplier also includes: a comparator 300, which is connected to the readout circuit 200 and is used to compare the counting data of the readout circuit 200 with a preset counting threshold. When the counting data crosses the preset counting threshold, a flip occurs, and the time corresponding to the flip is recorded, thereby obtaining a count-time sampling point of the pulse event.

[0090] Further, in one example of the present application, see Figure 1 The digital silicon photomultiplier further includes: a time-to-digital converter 400, which is connected to the comparator 300 and is used to measure the time difference between the flip time of the comparator 300 and the clock signal.

[0091] In another example of the present application, in order to enable each circuit to work effectively, the digital silicon photomultiplier also includes a power management module 500. The power management module 500 is used to adjust the power supply using different low voltage difference linear regulators to achieve different power supply to different functional modules according to the current power consumption changes and power supply requirements of different functional modules in the digital silicon photomultiplier.

[0092] Specifically, different power management strategies are adopted for the readout circuit 200 and the time-to-digital converter 400 .

[0093] For the readout circuit 200, it uses a multi-level combinational logic circuit to complete the processing of the large array SPAD digital counting pulse count data, and has a large circuit scale. When an annihilation event occurs, many photons will arrive at the same time and trigger the reversal of the readout circuit 200 in large quantities. The peak current of the readout circuit 200 can reach tens of milliamperes within a few nanoseconds. Under such a fast load current transient change, the low-dropout linear regulator selects a main pole compensation type structure. The architecture of the main pole compensation type low-dropout linear regulator is as follows Fig.13 As shown, the entire power management module 500 includes a bandgap reference circuit 510, an operational amplifier 550, a super source follower 560, a power PMOS 590, a feedback resistor network 570, and an external capacitor 580. The transient response stability of the output voltage of the low-dropout linear regulator is ensured by relying on a large external capacitor. Since the readout circuit 200 is a digital circuit, it has a good tolerance to power supply noise, so the chip external noise introduced by the dominant pole compensation type low-dropout linear regulator has little effect on the performance of the circuit.

[0094] As a module for collecting the time information of SiPM pulse waveform, the time digital converter 400 has a high requirement for measurement resolution. However, the time measurement module 420 such as the vernier delay line and the delay phase-locked loop in the time digital converter 400 is very sensitive to the noise of the internal power supply voltage of the chip and requires a low ripple noise power supply. Therefore, a capacitor-free low voltage drop linear regulator that can avoid the introduction of external noise is selected. Its architecture is shown in the figure below. Fig.14 As shown, the entire power management module 500 includes a bandgap reference circuit 510, an operational amplifier 550, a feedforward ripple cancellation circuit 560', a power PMOS 590, and a feedback resistor network 570, etc.

[0095] In another example of this application, see Figure 1 The digital silicon photomultiplier further includes: a data packing module 600, which is connected to the time-to-digital converter 400 and is used to decode, identify, pack, combine coarse counting codes, compress and output the output of the time-to-digital converter 400 to the outside.

[0096] In addition to the above-mentioned silicon photomultiplier, the present application also provides an application of a hierarchical readout method or hierarchical readout system of any of the above examples in scientific instruments, medical equipment, high energy physics, deep space and deep sea exploration, extremely weak light imaging, radiation monitoring, automatic driving, security equipment, consumer electronics or smart home appliances. Those skilled in the art should know that any application of the readout circuit or hierarchical readout system provided by the present application in scientific instruments, medical equipment, high energy physics, deep space and deep sea exploration, extremely weak light imaging, radiation monitoring, automatic driving, security equipment, consumer electronics or smart home appliances belongs to the protection scope of the present application.

[0097] Those skilled in the art will appreciate that the above modules can be distributed in the device according to the description of the embodiment, or can be changed accordingly and only used in one or more devices different from the embodiment. The multiple modules of the above embodiments can be combined into one module, or one module can be further divided into multiple sub-modules.

[0098] Although the present application provides the method operation steps as described in the above embodiments or flow charts, more or fewer operation steps may be included in the method based on routine or no creative labor. In the steps where there is no necessary causal relationship logically, the execution order of these steps is not limited to the execution order provided in the embodiments of the present application.

[0099] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0100] The embodiments of the present application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and its core idea of ​​the present application. At the same time, changes or deformations made by those skilled in the art based on the ideas of the present application, the specific implementation methods and the scope of application of the present application, all belong to the scope of protection of the present application. In summary, the content of this specification should not be construed as a limitation on the present application.

Claims

1. A multi-count threshold graded readout method, characterized in that: The multi-count threshold classification readout method comprises: The first data output by at least one pixel unit assembly module is read out in stages to obtain the sum of the photon counting data of all the pixel unit assembly modules, the size of the input data of each stage of the readout circuit is larger than the size of its output data, and the number of input data of each stage of the readout circuit is larger than the number of its output data.

2. The multi-count threshold graded readout method according to claim 1, characterized in that: The number of levels of the graded readout includes any one of 2 to 20 levels.

3. The multi-count threshold graded readout method according to claim 1, characterized in that: The number of levels of the graded readout is 3.

4. The multi-count threshold hierarchical readout method according to claim 1, characterized in that: The step of reading out the first data outputted by at least one pixel unit assembly module in a hierarchical manner to obtain the sum of the photon counting data of all the pixel unit assembly modules comprises: Performing a first-level conversion on the first data output by at least one pixel unit set module to obtain second data, wherein the second data includes at least two types of data with different weights; Grouping the data with the same weight in the second data into the same group, and performing the second-level transformation on all the group data to obtain the third data; The third data are added to obtain the sum of the photon counting data of all the pixel unit assembly modules.

5. The multi-count threshold graded readout method according to claim 4, characterized in that: The adding of the third data is adding of the data with the same weight in the third data.

6. The multi-count threshold hierarchical readout method according to claim 1, characterized in that: The step of reading out the first data outputted by at least one pixel unit set module in a hierarchical manner comprises: First, all the pixel unit assembly modules are divided into a plurality of large groups, each large group includes a plurality of pixel unit assembly modules, and the first data output by all the pixel unit assembly modules in the same large group are read out in stages.

7. The multi-count threshold graded readout method according to claim 1, characterized in that: The step of reading out the first data outputted by at least one pixel unit assembly module in a hierarchical manner to obtain the sum of the photon counting data of all the pixel unit assembly modules comprises: All the pixel unit assembly modules are divided into multiple groups, and the first data output by each group is read out at the first level to obtain the second data. After all the second data are aggregated, the data with the same weight are read out at the second level to obtain the third data. After all the third data are aggregated, the data with the same weight are added to obtain the sum of the photon counting data of all the pixel unit assembly modules.

8. The multi-count threshold hierarchical readout method according to claim 1, characterized in that: The step of reading out the first data outputted by at least one pixel unit assembly module in a hierarchical manner to obtain the sum of the photon counting data of all the pixel unit assembly modules comprises: All the pixel unit assembly modules are divided into two large groups, each large group includes multiple pixel unit assembly modules, all the pixel unit assembly modules in the same large group are divided into multiple small groups, the first data output by each small group are read out at the first level together to obtain the second data, all the second data are aggregated and the data with the same weight are read out at the second level to obtain the third data, and all the third data are aggregated and the data with the same weight are added to obtain the sum of the photon counting data of all the pixel unit assembly modules in the large group.

9. The multi-count threshold graded readout method according to claim 4, 7 or 8, characterized in that: The step of reading out the first data outputted by at least one pixel unit assembly module in a hierarchical manner to obtain the sum of the photon counting data of all the pixel unit assembly modules comprises: Reading out the first data in multiple stages to obtain the second data; The second data is read out in stages for multiple times to obtain the third data.

10. The multi-count threshold hierarchical readout method according to claim 9, characterized in that: The step of reading out the first data in multiple stages to obtain the second data includes: The first data is read out through the first sub-grading and data compression is performed to obtain a plurality of first sub-data with different weights; Summarizing the first sub-data, and performing second sub-classification reading on the data with the same weight to obtain a plurality of second sub-data with different weights; The second sub-data are aggregated, and data with the same weight are added up to obtain the second data.

11. The multi-count threshold hierarchical readout method according to claim 9, characterized in that: The step of reading the second data out in multiple stages to obtain the third data comprises: Summarizing the second data, and reading out the data with the same weight through the third sub-classification and performing data compression to obtain a plurality of third sub-data with different weights; Summarizing the third sub-data, and performing fourth sub-classification reading on the data with the same weight to obtain a plurality of fourth sub-data with different weights; The fourth sub-data are aggregated, and data with the same weight are added up to obtain the third data.

12. A multi-count threshold graded readout system, characterized in that: The multi-count threshold classification readout system comprises: At least two levels of readout circuits are configured to perform hierarchical readout of first data output by at least one pixel unit assembly module to obtain the sum of the photon counting data of all the pixel unit assembly modules, the size of input data of each level of readout circuit is larger than the size of its output data, and the number of input data of each level of readout circuit is larger than the number of its output data.

13. The multi-count threshold graded readout system according to claim 12, characterized in that: The number of stages of the readout circuit includes any one of 2 to 20 stages.

14. The multi-count threshold graded readout system according to claim 12, characterized in that: The number of stages of the readout circuit is three.

15. The multi-count threshold graded readout system according to claim 12, characterized in that: The readout circuit comprises: A first-stage readout circuit is configured to perform a first-stage conversion on the first data output by at least one pixel unit set module to obtain second data, wherein the second data includes at least two types of data with different weights; A second-stage readout circuit is configured to perform a second-stage conversion on the data with the same weight in the second data to obtain third data; The third-level readout circuit is configured to add the third data to obtain the sum of the photon counting data of all the pixel unit assembly modules.

16. The multi-count threshold graded readout system according to claim 15, characterized in that: The adding of the third data is adding of the data with the same weight in the third data.

17. The multi-count threshold graded readout system according to claim 12, characterized in that: The readout circuit includes two groups, each group of readout circuits is configured to hierarchically read out the first data output by all the pixel unit collection modules in the same large group, the number of the pixel unit collection modules is 2N, and N pixel unit collection modules constitute a large group.

18. The multi-count threshold graded readout system according to claim 12, characterized in that: The readout circuit is configured to perform a first-level readout on the first data output by each group together to obtain second data, aggregate all of the second data and then perform a second-level readout on the data with the same weight to obtain third data, aggregate all of the third data and then add the data with the same weight to obtain the sum of the photon counting data of all of the pixel unit collection modules, and all of the pixel unit collection modules are divided into n groups.

19. The multi-count threshold graded readout system according to claim 12, characterized in that: The readout circuit includes two groups, and each group of the readout circuits is configured to perform a first-level readout of the first data output by each small group in the same large group to obtain second data, and after summarizing all the second data, perform a second-level readout of the data with the same weight to obtain third data, and after summarizing all the third data, add the data with the same weight to obtain the sum of the photon counting data of all the pixel unit collection modules in the large group, and all the pixel unit collection modules constitute two large groups, each of which includes N pixel unit collection modules, and all the pixel unit collection modules in the same large group constitute n small groups.

20. The multi-count threshold graded readout system according to claim 15, characterized in that: The first-stage readout circuit is configured to read out the first data in multiple stages to obtain the second data; The second-stage readout circuit is configured to read out the second data in multiple stages to obtain the third data.

21. The multi-count threshold graded readout system according to claim 20, characterized in that: The first-stage readout circuit comprises: A first level readout circuit is configured to perform data compression on the first data through a first sub-level readout to obtain a plurality of first sub-data with different weights; A first and second level readout circuit is configured to aggregate the first sub-data and perform second sub-level readout on the data with the same weight to obtain a plurality of second sub-data with different weights; The first three-stage readout circuit is configured to aggregate the second sub-data and add the data with the same weight to obtain the second data.

22. The multi-count threshold graded readout system according to claim 21, characterized in that: The second-stage readout circuit comprises: a second first-level readout circuit configured to aggregate the second data, read out the data with the same weight through the third sub-level classification and perform data compression to obtain a plurality of third sub-data with different weights; A second secondary readout circuit is configured to aggregate the third sub-data and perform fourth sub-grading readout on data with the same weight to obtain a plurality of fourth sub-data with different weights; The second third-level readout circuit is configured to aggregate the fourth sub-data and add the data with the same weight to obtain the third data.

23. A digital silicon photomultiplier, characterized in that: Comprising a multi-count threshold graded readout system as described in any one of claims 12 to 22.

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