Heavy ion beam telescope readout electronics circuit system and use method thereof

Abstract

The invention relates to a heavy ion beam telescope readout electronics circuit system and a use method thereof. The system comprises a front-end readout control module, a data summarization module, a trigger and clock module and a computer, the front-end reading control module is used for receiving a control signal of the data summarization module and a clock and trigger signal provided by the trigger and clock module, and amplifying and digitally processing a voltage pulse signal output by a corresponding silicon pixel chip in the heavy ion beam telescope to obtain a processed data frame; the data summarization module is used for summarizing and processing the data frames processed by the plurality of front-end read-out control modules; determining the track of the particles; the trigger and clock module is used for generating multiple paths of trigger signals and multiple paths of clock signals; and the computer is used for controlling the front-end read-out control module, the data summarization module and the trigger and clock module. The high-energy physical experiment and nuclear detection system can be widely applied to the technical field of high-energy physical experiments and nuclear detection.

Description

Technical Field

[0001] The present invention relates to the field of high energy physics experiments and nuclear detection technology, and in particular to a heavy ion beam telescope readout electronics circuit system and a method of using the same. Background Art

[0002] The beam provided by the particle accelerator is the benchmark in the field of particle physics and nuclear physics. In the process of detector development, it is essential to use the beam to verify the principle, calibrate and optimize the detector. In order to cooperate with the principle verification, calibration and optimization tasks of the developed detector on the beam, especially when testing its track resolution, detection efficiency and other parameters, the beam terminal generally needs to provide a high-precision particle track detection system to measure the particle track information. This track detection system is generally called a beam telescope. Silicon pixel detectors have extremely low mass, and when used in low-energy beam measurements, the particle scattering effect has little effect on position measurement. Therefore, the advantages of silicon pixel detectors such as high position resolution, high integration, fast response time, low noise and extremely low mass give them a natural and unique advantage in the development of high-performance beam telescopes.

[0003] The prototype of the silicon pixel heavy ion beam telescope is mainly composed of a detector module, a readout electronics module, a computer, a mechanical platform, etc. Among them, the detector module is composed of a silicon pixel chip bound to a PCB board by wire bonding to form a layer group. Several layer groups (for example, 6) are used to form the two arms of the telescope, and the device under test is placed in the middle of the two arms. A trigger detector is placed on each side of the beam telescope for triggered readout; the readout electronics module is mainly composed of a silicon pixel chip front-end readout control module, a data aggregation module, a trigger and clock module; the mechanical platform is used to complete the movable and adjustable movement between each layer group and the detector under test; the computer is used to run the host computer control software. When the beam passes through the detector, the silicon pixel chips that make up the two arms and the particle impact information provided by the detector under test will reconstruct the accurate track of the particle. Using the particle track information reconstructed by the beam telescope, the performance indicators such as the track resolution and detection efficiency of the detector under test can be obtained.

[0004] However, there are still many challenges to overcome in order to successfully apply domestic silicon pixel chips to heavy ion beam telescopes. The most critical issues include: (1) Insufficient reliability of electronic systems: Traditional circuits are prone to single-particle effects (such as single-particle upset (SEU) and single-particle latch (SEL)) in strong radiation environments; (2) Data transmission bottleneck: The number of pixels in silicon pixel detector chips is huge, with the number of pixels on a single chip exceeding 2×10 5, how to ensure reliable data transmission rate and improve the flexibility and scalability of the system; (3) Low efficiency of offline analysis: Traditional track reconstruction relies on GPU offline processing, with delays of up to minutes, which makes it difficult to support real-time optimization of experiments. Summary of the invention

[0005] In view of the above problems, the object of the present invention is to provide a heavy ion beam telescope readout electronic circuit system and a method of using the system, which has high electronic system reliability, reliable data transmission and high off-line analysis efficiency.

[0006] To achieve the above-mentioned object, the present invention adopts the following technical solutions: In the first aspect, a heavy ion beam telescope readout electronics circuit system is provided, including a front-end readout control module, a data aggregation module, a trigger and clock module, and a computer; The front-end readout control module is used to receive the control signal of the data aggregation module and the clock and trigger signal provided by the trigger and clock module, and adopts a hybrid analog-digital architecture design to amplify and digitally process the voltage pulse signal output by the corresponding silicon pixel chip in the heavy ion beam telescope to obtain a processed data frame; and provide working power and signal bias voltage to the corresponding silicon pixel chip, wherein each of the front-end readout control modules corresponds to the signal of one silicon pixel chip or multiple silicon pixel chips; The data aggregation module is used to aggregate and process the data frames processed by the front-end readout control module; determine the particle track based on the processed data frames; and send the control signal of the computer to the front-end readout control module; The trigger and clock module is used to receive the hit signal of the trigger detector and fan out as a multi-channel trigger signal after matching, and provide it to the front-end readout control module, data summary module and device under test respectively; and generate a global synchronous clock signal and fan out as a multi-channel clock signal, and provide it to the front-end readout control module, data summary module and device under test respectively; The computer is used to control the front-end readout control module, the data aggregation module, and the trigger and clock module based on the control instructions of the host computer, and store the aggregated and processed data frames.

[0007] Further, the front-end readout control module includes a silicon pixel chip binding board docking connector, an analog conditioning and single-ended to differential circuit, a 32-channel analog-to-digital converter, a current monitoring circuit, a first clock circuit, a first power management circuit, a first clock connector, a first trigger connector, a first FPGA chip, a first optical fiber circuit, and a multi-channel digital-to-analog converter; The silicon pixel chip binding board docking connector is used to receive the voltage pulse signal output by the corresponding silicon pixel chip and send it to the analog conditioning and single-ended to differential circuit; and provide working power and signal bias voltage to the corresponding silicon pixel chip; The analog conditioning and single-ended to differential conversion circuit is used to process the voltage pulse signal output by the silicon pixel chip to obtain 64 differential signals and send them to the two 32-channel analog-to-digital converters; The 32-channel analog-to-digital converter is used to perform analog-to-digital conversion on the differential signal, obtain a digitized signal and send it to the first FPGA chip; The current monitoring circuit is used to monitor the operating current of the corresponding silicon pixel chip; The first clock circuit is used to provide a system global clock signal during debugging; The first power management circuit is used to send the working power of the corresponding silicon pixel chip to the silicon pixel chip binding board docking connector based on the control of the first FPGA chip; The first clock connector is used to receive the global clock signal of the trigger and clock module; The first trigger connector is used to receive a trigger signal from the trigger and clock module; The first FPGA chip is used to perform CRC check on the digitized signal and encapsulate it into a data frame, and send it to the data aggregation module through the first optical fiber circuit; and control the operation of the multi-channel digital-to-analog converter, the first power management circuit and the first optical fiber circuit based on the global clock signal and the trigger signal; The first optical fiber circuit is used to perform real-time data interaction with the data aggregation module; The multi-channel digital-to-analog converter is used to provide a signal bias voltage required for the normal operation of the silicon pixel chip.

[0008] Furthermore, the front-end readout control module also includes: Temperature monitoring circuit, used to monitor the ambient temperature; Humidity monitoring circuit, used to monitor ambient humidity.

[0009] Further, the data aggregation module includes a peripheral interface circuit, a clock generator chip, a second FPGA chip, a DDR4 chip, a FLASH chip and a second power management circuit, wherein the peripheral interface includes a PCIe4.0×16 interface, a 24-way 25 Gbps optical fiber interface, a second clock connector and a second trigger connector; The PCIe4.0×16 interface is used to receive control signals from the computer and to upload aggregated and processed data frames to the computer for storage; The 24-channel 25 Gbps optical fiber interface is used to receive the processed data frames sent by the front-end readout control module; and send the control signal of the computer to the front-end readout control module; The second clock connector is used to receive the global clock signal of the trigger and clock module; The second trigger connector is used to receive a trigger signal from the trigger and clock module; The clock generator chip is used to generate the reference clock required by each component of the data aggregation module; The second FPGA chip is used to use a target detection algorithm based on a neural network to reconstruct and fit the particle track based on the processed data frame to determine the particle track; The DDR4 chip is used to cache and temporarily store the aggregated data of the front-end readout control module; The FLASH chip is used to store and configure FPGA firmware update logic; The second power management circuit is used to provide power supply for various components of the data aggregation module.

[0010] Furthermore, the peripheral interface circuit further includes: HP-FMC expansion interface, used to achieve modular expansion of peripherals; The first JTAG debugging interface is used to perform online debugging on the second FPGA chip through JTAG.

[0011] Furthermore, the geometric dimensions of the data aggregation module are determined according to high-speed serial bus specifications.

[0012] Further, the trigger and clock module includes a trigger module and a clock module, wherein the trigger module includes two first LEMO connectors, two current-voltage conversion circuits, a high-speed identification circuit, a third FPGA chip, a second LEMO connector and an FPGA peripheral circuit, and the FPGA peripheral circuit includes a second clock circuit, a reset circuit, and a second JTAG debugging interface; The two first LEMO connectors are used to receive a hit signal for triggering the detector; The two current-voltage conversion circuits are used to convert and amplify the corresponding hitting signals to obtain voltage signals; The high-speed discrimination circuit is used to compare the voltage signal obtained by the current-voltage conversion circuit with a set threshold value to generate a digital trigger signal; The third FPGA chip is used to match and select the digital trigger signal, obtain a valid trigger signal and fan out into multiple LVTTL level trigger signals; The second LEMO connector is used to send multi-channel LVTTL level trigger signals to the front-end readout control module, the data summary module and the device under test through a single-ended coaxial line; The second clock circuit is used to provide a global clock signal for the FPGA system; The reset circuit is used to provide a reset signal for the FPGA system.

[0013] Furthermore, the FPGA peripheral circuit also includes a second JTAG debugging interface, which is used to perform online debugging on the third FPGA chip through JTAG and track the processor core status in real time.

[0014] Further, the clock module includes a temperature compensated oscillator, a clock fan-out chip and a third LEMO connector; The temperature compensated oscillator is used to generate a global clock signal; The clock fan-out chip is used to fan out the global clock signal generated by the temperature compensated oscillator into multiple low voltage differential signal level clock signals; The third LEMO connector is used to send multiple low-voltage differential signal level clock signals to the front-end readout control module, the data summary module and the device under test through differential coaxial lines.

[0015] On the other hand, a method for using a heavy ion beam telescope readout electronics circuit system is provided, comprising: The trigger and clock module receives the hit signal of the trigger detector, performs matching, and then fans out to multiple trigger signals, and provides them to the front-end readout control module, the data aggregation module, and the device under test respectively; The trigger and clock module generates a global synchronous clock signal and fans out multiple clock signals, which are provided to the front-end readout control module, the data aggregation module and the device under test respectively; The front-end readout control module receives the control signal of the data aggregation module and the clock and trigger signals provided by the trigger and clock module, and adopts a hybrid analog-digital architecture design to amplify and digitize the voltage pulse signal output by the corresponding silicon pixel chip in the heavy ion beam telescope to obtain the processed data frame; The front-end readout control module provides working power and signal bias voltage to the corresponding silicon pixel chip; The data aggregation module aggregates and processes the data frames processed by the front-end readout control modules, determines the trajectory of the particles based on the processed data frames, and uploads the aggregated and processed data frames to a computer for storage.

[0016] The present invention adopts the above technical solution, which has the following advantages: 1. The present invention can reduce costs by 80% and make the supply chain autonomous and controllable.

[0017] 2. The track resolution of the present invention reaches 5μm, and the real-time processing capability is improved several times, with leading performance.

[0018] 3. The present invention can adapt to extreme radiation and temperature environments and has high reliability.

[0019] 4. The present invention can support ultra-large-scale experimental devices, lay the foundation for large-scale particle experiments, and is flexible to expand.

[0020] 5. The present invention can efficiently complete the task of particle track reconstruction. The front-end readout control module is responsible for signal acquisition and processing, the data aggregation module realizes high-speed data transmission and online track reconstruction, and the trigger and clock modules ensure the synchronization and stability of the system. The modules work together to accurately measure particle tracks and evaluate detector performance, providing reliable technical support for particle physics research.

[0021] 6. In the prior art, particle track reconstruction and fitting are performed by using algorithms to process offline data, while the present application processes data online, with a fast processing speed and the ability to compress data in large quantities.

[0022] 7. The present invention can be applied not only to heavy ion beam telescopes, but also to other ion beam telescopes (such as protons), and can also be applied to readout electronics systems of large-scale physical experimental devices.

[0023] In summary, the present invention can be widely used in real-time monitoring of beam trajectory in particle accelerators, detector performance calibration and experimental data optimization, and is particularly suitable for precision measurement in high radiation and high particle flux environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Throughout the accompanying drawings, the same reference numerals are used to represent the same components. In the accompanying drawings: Figure 1 It is a schematic diagram of the structure of a heavy ion beam telescope readout electronics circuit system provided by one embodiment of the present invention; Figure 2 is a schematic diagram of the structure of a front-end readout control module provided by an embodiment of the present invention; Figure 3 is a structural diagram of a data aggregation module provided by an embodiment of the present invention; Figure 4 It is a schematic diagram of the structure of a trigger and clock module provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0025] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0026] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0027] Although the terms first, second, third, etc. can be used in the text to describe multiple elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another region, layer or section. Unless the context clearly indicates, terms such as "first", "second" and other numerical terms do not imply order or sequence when used in the text. Therefore, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section without departing from the teaching of the example embodiments.

[0028] The embodiment of the present invention provides a heavy ion beam telescope readout electronic circuit system, including a front-end readout control module, a data aggregation module, a trigger and clock module, and a computer; the front-end readout control module is used to receive the control signal of the data aggregation module and the clock and trigger signal provided by the trigger and clock module, and adopts a hybrid analog-digital architecture design to amplify and digitize the voltage pulse signal output by the corresponding silicon pixel chip in the heavy ion beam telescope to obtain a processed data frame; and provide working power and signal bias voltage to the corresponding silicon pixel chip, wherein each front-end readout control module corresponds to the signal of a silicon pixel chip or multiple silicon pixel chips; the data aggregation module is used to amplify and digitize the voltage pulse signal output by the corresponding silicon pixel chip in the heavy ion beam telescope to obtain a processed data frame; The data frames processed by the readout control module are summarized and processed; based on the processed data frames, the particle track is reconstructed and fitted to determine the particle track; and the computer control signal is sent to the front-end readout control module; the trigger and clock module is used to receive the hit signal of the trigger detector and fan out as a multi-channel trigger signal after matching, and provide it to the front-end readout control module, the data summary module and the device under test respectively; and generate a global synchronous clock signal and fan out as a multi-channel clock signal, which is provided to the front-end readout control module, the data summary module and the device under test respectively; the computer is used to control the front-end readout control module, the data summary module and the trigger and clock module based on the control instructions of the host computer. The present invention can break through the difficulties of traditional systems in radiation environment stability, data transmission efficiency and real-time processing capabilities. The present invention is mainly used in heavy ion beam telescopes in particle accelerators, and can accurately measure the track information of particles to realize the testing, calibration and optimization of detectors. The present invention can provide an autonomous and controllable high-performance detection method by adopting domestic silicon pixel detector chips. The present invention can not only meet the current needs of domestic particle accelerators, but also has a wide range of application prospects and can support future higher-intensity particle experimental devices. In addition, the present invention uses a neural network optimization algorithm to perform online particle track reconstruction, greatly improving the speed and accuracy of particle track reconstruction, effectively solving the challenges brought by the huge amount of data, and can be widely used in particle accelerator devices at home and abroad, providing an efficient testing method for particle physics research.

[0029] Example 1 like Figure 1 As shown, this embodiment provides a heavy ion beam telescope readout electronic circuit system, including a front-end readout control module 1, a data aggregation module 2, a trigger and clock module 3 and a computer 4.

[0030] The front-end readout control module 1 is used to receive the control signal of the data aggregation module 2 and the clock and trigger signal provided by the trigger and clock module 3. It adopts an analog-to-digital hybrid architecture design to amplify and digitize the voltage pulse signal output by the corresponding silicon pixel chip in the heavy ion beam telescope to obtain a processed data frame; and provide working power and signal bias voltage to the corresponding silicon pixel chip, wherein each front-end readout control module 1 corresponds to the signal of a silicon pixel chip or multiple silicon pixel chips.

[0031] The data aggregation module 2 is used to aggregate and process the data frames processed by the front-end readout control module 1; reconstruct and fit the particle track based on the processed data frames to determine the particle track; and send the control signal of the computer 4 to the front-end readout control module 1.

[0032] The trigger and clock module 3 is used to receive the hit signal of the trigger detector and fan out into multiple trigger signals after matching, and provide them to the front-end readout control module 1, the data aggregation module 2 and the device under test respectively; and generate a global synchronous clock signal and fan out into multiple clock signals, which are provided to the front-end readout control module 1, the data aggregation module 2 and the device under test respectively, so as to achieve clock synchronization of the entire system.

[0033] The computer 4 is used to control the front-end readout control module 1 , the data aggregation module 2 and the trigger and clock module 3 based on the control instructions of the host computer, and store the data frames aggregated and processed by the data aggregation module 2 .

[0034] In a preferred embodiment, the design of the front-end readout control module 1 of the present invention needs to meet the following main requirements: 1) strictly limit the use of resources such as power consumption, volume, number of leads, etc.; 2) be able to work stably in a radiation environment. Figure 2 As shown, the front-end readout control module 1 includes a silicon pixel chip binding board docking connector, an analog conditioning and single-ended to differential circuit, a 32-channel analog-to-digital converter, a current monitoring circuit, a temperature monitoring circuit, a humidity monitoring circuit, a first clock circuit, a first power management circuit, a first clock connector, a first trigger connector, a first FPGA chip, a first optical fiber circuit and a multi-channel digital-to-analog converter.

[0035] The silicon pixel chip binding board docking connector is used to receive the voltage pulse signal output by the corresponding silicon pixel chip and send it to the analog conditioning and single-ended to differential circuit; and provide working power and signal bias voltage to the corresponding silicon pixel chip.

[0036] The analog conditioning and single-ended to differential circuit is used to convert the voltage pulse signal output by the silicon pixel chip from single-ended to differential, amplify and adjust the bias, etc., to obtain 64 differential signals, and send them to two 32-channel analog-to-digital converters.

[0037] The 32-channel analog-to-digital converter is used to perform analog-to-digital conversion on the differential signal, obtain a digitized signal and send it to the first FPGA chip.

[0038] The current monitoring circuit is used to monitor the operating current of the corresponding silicon pixel chip.

[0039] The temperature monitoring circuit is used to monitor the ambient temperature.

[0040] The humidity monitoring circuit is used to monitor the ambient humidity.

[0041] The first clock circuit is used to provide a system global clock signal during debugging.

[0042] The first power management circuit is used to send the working power of the corresponding silicon pixel chip to the silicon pixel chip binding board docking connector based on the control of the first FPGA chip.

[0043] The first clock connector is used to receive the global clock signal of the trigger and clock module 3 .

[0044] The first trigger connector is used to receive a trigger signal from the trigger and clock module 3 .

[0045] The first FPGA chip is used to perform CRC check (cyclic redundancy check) on the digitized signal and encapsulate it into a 512-bit data frame, which is sent to the data aggregation module 2 through the first optical fiber circuit; and based on the global clock signal and trigger signal, control the operation of the multi-channel digital-to-analog converter, the first power management circuit and the first optical fiber circuit.

[0046] The first optical fiber circuit is used for real-time data interaction with the data aggregation module 2, including the data frames encapsulated by the uplink FPGA and the control commands transmitted downlink by the data aggregation module 2.

[0047] Multi-channel digital-to-analog converters are used to provide the signal bias voltage required for the normal operation of silicon pixel chips.

[0048] Specifically, the first FPGA chip can adopt the MICROCHIP M2S090T FPGA model; the 32-channel analog-to-digital converter can adopt the ADS52J90ZZE model with a dynamic range of 84 dB; the analog conditioning and single-ended to differential circuit can adopt the AD8138 model with a bandwidth of 200 MHz; the DC-DC in the first power management circuit can adopt the LTM4644, which has high integration and high efficiency, and the efficiency can reach more than 95%; the LDO in the first power management circuit can adopt the LT3045 model with a ripple <0.5 mV; the current monitoring circuit can adopt ±0.5 mA accuracy; the temperature monitoring circuit and the humidity monitoring circuit can adopt an accuracy of ±0.2℃.

[0049] Specifically, the first FPGA chip has an anti-radiation design: the FPGA key modules have a three-mode redundant design and are regularly reloaded with configurations; current-limiting resistors are added to the power inputs of all integrated circuit chips to suppress SEL and protect the chips from damage; the power network is embedded with a π-type filter circuit (cut-off frequency 10 kHz), and the radiation noise suppression ratio is >40 dB.

[0050] In a preferred embodiment, the data aggregation module 2 serves as a link between the front-end readout control module 1 and the computer 4, and can realize simultaneous communication of multiple (for example, 6) front-end readout control modules 1. The data aggregation module 2 mainly completes event caching, coincidence selection, online track reconstruction, event packaging, and interaction with the computer 4. Figure 3 As shown, the data aggregation module 2 includes a peripheral interface circuit, a clock generator chip, a second FPGA chip, a DDR4 chip, a FLASH chip and a second power management circuit, wherein the peripheral interface includes a PCIe4.0×16 interface, a 24-way 25 Gbps optical fiber interface, a second clock connector, a second trigger connector, a HP-FMC expansion interface and a first JTAG debugging interface.

[0051] The PCIe4.0×16 interface is used to receive control signals from the computer 4 and to uplink the aggregated and processed data frames to the computer 4 for storage.

[0052] The 24-channel 25 Gbps optical fiber interface is used to receive the processed data frames sent by the front-end readout control module 1 ; and to send the control signal of the computer 4 to the front-end readout control module 1 .

[0053] The second clock connector is used to receive the global clock signal of the trigger and clock module 3.

[0054] The second trigger connector is used to receive a trigger signal from the trigger and clock module 3 .

[0055] The clock generator chip is used to generate the reference clock required by each component of the data aggregation module 2.

[0056] The second FPGA chip is used to use a target detection algorithm based on a neural network to reconstruct and fit the particle track based on the processed data frame to determine the particle track. It should be noted that the target detection algorithm based on a neural network to determine the particle track is an algorithm disclosed in the prior art, and the specific process will not be described in detail here.

[0057] The DDR4 chip is used to cache and temporarily store the aggregated data of the front-end readout control module 1 .

[0058] The FLASH chip is used to store and configure the FPGA firmware update logic.

[0059] The second power management circuit is used to provide a stable and isolated power supply for each component of the data aggregation module 2.

[0060] The HP-FMC expansion interface is used to implement high-speed peripheral modular expansion.

[0061] The first JTAG debugging interface is used to perform online debugging on the second FPGA chip through JTAG and track the processor core status in real time.

[0062] Specifically, the geometric dimensions of the data aggregation module 2 are designed according to the PCIe (PCIe) specification, and can be directly installed on the PCIe slot of the computer 4 for use, and multiple data aggregation modules 2 can be installed on adjacent PCIe slots.

[0063] Specifically, the second FPGA chip may be a Xilinx UltraScale+ series FPGA chip; the DDR4 chip may be eight DDR4 chips with a capacity of 8 GB; and the FLASH chip may be a 512 Mbit FLASH chip.

[0064] Specifically, the total capacity of eight DDR4 chips is 64GB, and the maximum operating data rate is 3200 Mbps.

[0065] In a preferred embodiment, Figure 4 As shown, the trigger and clock module 3 includes a trigger module and a clock module, wherein the trigger module includes two first LEMO connectors, two current-voltage conversion circuits, a high-speed discrimination circuit, a third FPGA chip, a second LEMO connector and an FPGA peripheral circuit; the clock module includes a temperature compensated oscillator, a clock fan-out chip and a third LEMO connector; and the FPGA peripheral circuit includes a second clock circuit, a reset circuit and a second JTAG debugging interface.

[0066] The two first LEMO connectors are used to receive the hit signal for triggering the detector.

[0067] The two current-voltage conversion circuits are used to perform current-voltage conversion and amplify the corresponding hitting signals to obtain voltage signals.

[0068] The high-speed discrimination circuit is used to compare the voltage signal obtained by the current-voltage conversion circuit with the set threshold value to generate a digital trigger signal.

[0069] The third FPGA chip is used to match and select the digital trigger signal, obtain a valid trigger signal and fan out into multiple LVTTL level trigger signals.

[0070] The second LEMO connector is used to send the multi-channel LVTTL level trigger signal to the front-end readout control module 1, the data summary module 2 and the device under test through the single-ended coaxial line.

[0071] The temperature compensated oscillator is used to generate a high-precision, low-jitter global clock signal.

[0072] The clock fan-out chip is used to fan out the global clock signal generated by the temperature compensated oscillator into multiple low voltage differential signal (LVDS) level clock signals.

[0073] The third LEMO connector is used to send multiple low voltage differential signal (LVDS) level clock signals to the front-end readout control module 1, the data aggregation module 2 and the device under test through differential coaxial lines.

[0074] The second clock circuit is used to provide a global clock signal for the FPGA system The reset circuit is used to provide a reset signal for the FPGA system. The second JTAG debugging interface is used to perform online debugging of the third FPGA chip through JTAG and track the processor core status in real time.

[0075] Specifically, the temperature compensated oscillator may be an oscillator of model OH300-50503CV; and the clock fan-out chip may be a clock fan-out chip of model 8T39S11ANLGI.

[0076] Example 2 This embodiment provides a method for using a heavy ion beam telescope readout electronics circuit system, comprising the following steps: 1) The trigger and clock module 3 receives the hit signal of the trigger detector and fans out multiple trigger signals after matching, and provides them to the front-end readout control module 1, the data aggregation module 2 and the device under test respectively.

[0077] 2) The trigger and clock module 3 generates a global synchronous clock signal and fans out multiple clock signals, which are provided to the front-end readout control module 1, the data aggregation module 2 and the device under test respectively to achieve clock synchronization of the entire system.

[0078] 3) The data aggregation module 2 sends the control signal of the computer 4 to the front-end readout control module 1 .

[0079] 4) The front-end readout control module 1 receives the control signal from the data aggregation module 2 and the clock and trigger signals provided by the trigger and clock module 3, and adopts a hybrid analog-digital architecture design to amplify and digitize the voltage pulse signal output by the corresponding silicon pixel chip in the heavy ion beam telescope to obtain a processed data frame.

[0080] 5) The front-end readout control module 1 provides working power and signal bias voltage, etc. to the corresponding silicon pixel chip.

[0081] 6) The data aggregation module 2 aggregates and processes the data frames processed by the front-end readout control modules 1, determines the particle track based on the processed data frames, and uploads the aggregated and processed data frames to the computer 4 for storage.

[0082] The above embodiments are only used to illustrate the present invention, wherein the structure, connection mode and manufacturing process of each component may be changed. Any equivalent transformations and improvements based on the technical solution of the present invention should not be excluded from the protection scope of the present invention.

Claims

1. A heavy ion beam telescope readout electronics circuit system, characterized in that: It includes a front-end readout control module, a data aggregation module, a trigger and clock module, and a computer; The front-end readout control module is used to receive the control signal of the data aggregation module and the clock and trigger signal provided by the trigger and clock module, and adopts a hybrid analog-digital architecture design to amplify and digitally process the voltage pulse signal output by the corresponding silicon pixel chip in the heavy ion beam telescope to obtain a processed data frame; and provide working power and signal bias voltage to the corresponding silicon pixel chip, wherein each of the front-end readout control modules corresponds to the signal of one silicon pixel chip or multiple silicon pixel chips; The data aggregation module is used to aggregate and process the data frames processed by the front-end readout control module; determine the particle track based on the processed data frames; and send the control signal of the computer to the front-end readout control module; The trigger and clock module is used to receive the hit signal of the trigger detector and fan out as a multi-channel trigger signal after matching, and provide it to the front-end readout control module, data summary module and device under test respectively; and generate a global synchronous clock signal and fan out as a multi-channel clock signal, and provide it to the front-end readout control module, data summary module and device under test respectively; The computer is used to control the front-end readout control module, the data aggregation module, and the trigger and clock module based on the control instructions of the host computer, and store the aggregated and processed data frames.

2. A heavy ion beam telescope readout electronics circuit system as claimed in claim 1, characterized in that: The front-end readout control module includes a silicon pixel chip binding board docking connector, an analog conditioning and single-ended to differential circuit, a 32-channel analog-to-digital converter, a current monitoring circuit, a first clock circuit, a first power management circuit, a first clock connector, a first trigger connector, a first FPGA chip, a first optical fiber circuit, and a multi-channel digital-to-analog converter; The silicon pixel chip binding board docking connector is used to receive the voltage pulse signal output by the corresponding silicon pixel chip and send it to the analog conditioning and single-ended to differential circuit; and provide working power and signal bias voltage to the corresponding silicon pixel chip; The analog conditioning and single-ended to differential conversion circuit is used to process the voltage pulse signal output by the silicon pixel chip to obtain 64 differential signals and send them to the two 32-channel analog-to-digital converters; The 32-channel analog-to-digital converter is used to perform analog-to-digital conversion on the differential signal, obtain a digitized signal and send it to the first FPGA chip; The current monitoring circuit is used to monitor the operating current of the corresponding silicon pixel chip; The first clock circuit is used to provide a system global clock signal during debugging; The first power management circuit is used to send the working power of the corresponding silicon pixel chip to the silicon pixel chip binding board docking connector based on the control of the first FPGA chip; The first clock connector is used to receive the global clock signal of the trigger and clock module; The first trigger connector is used to receive a trigger signal from the trigger and clock module; The first FPGA chip is used to perform CRC check on the digitized signal and encapsulate it into a data frame, and send it to the data aggregation module through the first optical fiber circuit; and control the operation of the multi-channel digital-to-analog converter, the first power management circuit and the first optical fiber circuit based on the global clock signal and the trigger signal; The first optical fiber circuit is used to perform real-time data interaction with the data aggregation module; The multi-channel digital-to-analog converter is used to provide a signal bias voltage required for the normal operation of the silicon pixel chip.

3. A heavy ion beam telescope readout electronics circuit system as claimed in claim 2, characterized in that: The front-end readout control module also includes: Temperature monitoring circuit, used to monitor the ambient temperature; Humidity monitoring circuit, used to monitor ambient humidity.

4. A heavy ion beam telescope readout electronics circuit system as claimed in claim 1, characterized in that: The data aggregation module includes a peripheral interface circuit, a clock generator chip, a second FPGA chip, a DDR4 chip, a FLASH chip, and a second power management circuit, wherein the peripheral interface includes a PCIe4.0×16 interface, a 24-way 25 Gbps optical fiber interface, a second clock connector, and a second trigger connector; The PCIe4.0×16 interface is used to receive control signals from the computer and to upload aggregated and processed data frames to the computer for storage; The 24-channel 25 Gbps optical fiber interface is used to receive the processed data frames sent by the front-end readout control module; and send the control signal of the computer to the front-end readout control module; The second clock connector is used to receive the global clock signal of the trigger and clock module; The second trigger connector is used to receive a trigger signal from the trigger and clock module; The clock generator chip is used to generate the reference clock required by each component of the data aggregation module; The second FPGA chip is used to use a target detection algorithm based on a neural network to reconstruct and fit the particle track based on the processed data frame to determine the particle track; The DDR4 chip is used to cache and temporarily store the aggregated data of the front-end readout control module; The FLASH chip is used to store and configure FPGA firmware update logic; The second power management circuit is used to provide power supply for various components of the data aggregation module.

5. A heavy ion beam telescope readout electronics circuit system as claimed in claim 4, characterized in that: The peripheral interface circuit also includes: HP-FMC expansion interface, used to achieve modular expansion of peripherals; The first JTAG debugging interface is used to perform online debugging on the second FPGA chip through JTAG.

6. A heavy ion beam telescope readout electronics circuit system as claimed in claim 1, characterized in that: The geometrical dimensions of the data aggregation module are determined according to the high-speed serial bus specification.

7. A heavy ion beam telescope readout electronics circuit system as claimed in claim 1, characterized in that: The trigger and clock module includes a trigger module and a clock module, wherein the trigger module includes two first LEMO connectors, two current-voltage conversion circuits, a high-speed identification circuit, a third FPGA chip, a second LEMO connector and an FPGA peripheral circuit, and the FPGA peripheral circuit includes a second clock circuit and a reset circuit; The two first LEMO connectors are used to receive a hit signal for triggering the detector; The two current-voltage conversion circuits are used to convert and amplify the corresponding hitting signals to obtain voltage signals; The high-speed discrimination circuit is used to compare the voltage signal obtained by the current-voltage conversion circuit with a set threshold value to generate a digital trigger signal; The third FPGA chip is used to match and select the digital trigger signal, obtain a valid trigger signal and fan out into multiple LVTTL level trigger signals; The second LEMO connector is used to send multi-channel LVTTL level trigger signals to the front-end readout control module, the data summary module and the device under test through a single-ended coaxial line; The second clock circuit is used to provide a global clock signal for the FPGA system; The reset circuit is used to provide a reset signal for the FPGA system.

8. A heavy ion beam telescope readout electronics circuit system as claimed in claim 7, characterized in that: The FPGA peripheral circuit also includes a second JTAG debugging interface, which is used to perform online debugging on the third FPGA chip through JTAG and track the processor core status in real time.

9. A heavy ion beam telescope readout electronics circuit system as claimed in claim 7, characterized in that: The clock module includes a temperature compensated oscillator, a clock fan-out chip and a third LEMO connector; The temperature compensated oscillator is used to generate a global clock signal; The clock fan-out chip is used to fan out the global clock signal generated by the temperature compensated oscillator into multiple low voltage differential signal level clock signals; The third LEMO connector is used to send multiple low-voltage differential signal level clock signals to the front-end readout control module, the data summary module and the device under test through differential coaxial lines.

10. A method for using the heavy ion beam telescope readout electronics circuit system according to any one of claims 1 to 9, characterized in that: include: The trigger and clock module receives the hit signal of the trigger detector, performs matching, and then fans out to multiple trigger signals, and provides them to the front-end readout control module, the data aggregation module, and the device under test respectively; The trigger and clock module generates a global synchronous clock signal and fans out multiple clock signals, which are provided to the front-end readout control module, the data aggregation module and the device under test respectively; The data summary module sends the computer's control signal to the front-end readout control module; The front-end readout control module receives the control signal of the data aggregation module and the clock and trigger signals provided by the trigger and clock module, and adopts a hybrid analog-digital architecture design to amplify and digitize the voltage pulse signal output by the corresponding silicon pixel chip in the heavy ion beam telescope to obtain the processed data frame; The front-end readout control module provides working power and signal bias voltage to the corresponding silicon pixel chip; The data aggregation module aggregates and processes the data frames processed by the front-end readout control modules, determines the trajectory of the particles based on the processed data frames, and uploads the aggregated and processed data frames to a computer for storage.

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