Array substrate and display device

Abstract

An array substrate and a display device. The array substrate comprises a display area and a first frame area located at one side of the display area; in a vertical plane of the array substrate, the array substrate comprises a substrate and a plurality of heating lines located at one side of the substrate, the plurality of heating lines are configured to transfer heat to the array substrate; the plurality of heating lines are arranged at intervals along a first direction and extend along a second direction, the first direction intersects the second direction; each of the heating lines comprises a first line segment and a second line segment connected to each other, the first line segment is located in the display area, the second line segment is located in the first frame area, and the resistance of the second line segment is smaller than the resistance of the first line segment, which can solve the problem that the existing liquid crystal display is limited in application in a low-temperature use environment and has high heating efficiency.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to an array substrate and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) are a common type of display. An LCD uses two polarized materials with a liquid crystal solution between them. When an electric current passes through the liquid, it causes the crystals to rearrange, blocking light from passing through. Therefore, each crystal acts like a Venetian blind, both allowing and blocking light. Currently, LCDs are being developed towards being lighter, thinner, shorter, and smaller.

[0003] However, in low-temperature environments, the viscosity coefficient of liquid crystals is relatively high and they are prone to crystallization, which limits the application of liquid crystal displays in low-temperature environments. Summary of the Invention

[0004] This disclosure provides an array substrate and a display device that can solve the problem of limited application of existing liquid crystal displays in low-temperature environments and has high heating efficiency.

[0005] On one hand, embodiments of this disclosure provide an array substrate, the array substrate including a display area and a first border area located on one side of the display area; in a plane perpendicular to the array substrate, the array substrate includes a substrate and a plurality of heating lines located on one side of the substrate, the plurality of heating lines being configured to transfer heat to the array substrate; the plurality of heating lines are spaced apart along a first direction and extend along a second direction, the first direction intersecting the second direction;

[0006] Each heating wire includes a first segment and a second segment connected to each other. The first segment is located in the display area, and the second segment is located in the first frame area. The resistance of the second segment is less than that of the first segment.

[0007] In one exemplary embodiment, the material of the second line segment is molybdenum or aluminum.

[0008] In one exemplary embodiment, the sheet resistance of the second line segment ranges from 0.15Ω / □ to 0.38Ω / □.

[0009] In one exemplary embodiment, the line width of the second line segment ranges from 4.0 micrometers to 4.5 micrometers.

[0010] In an exemplary embodiment, the first border area includes a first sub-area and a second sub-area arranged sequentially along a direction away from the display area; the second sub-area includes at least one binding pin area, the at least one binding pin area includes a plurality of binding pins, and a plurality of second line segments are all located in the first sub-area; the first ends of the plurality of second line segments are electrically connected to the plurality of first line segments one-to-one, and the second ends of the plurality of second line segments are electrically connected to the plurality of binding pins one-to-one.

[0011] In one exemplary embodiment, each of the bonding pins includes a first pin line located on one side of the substrate, a connection electrode located on the side of the first pin line away from the substrate, and at least one insulating layer located between the first pin line and the connection electrode, the at least one insulating layer including at least one via, and the at least one via exposing a portion of the surface of the first pin line away from the substrate.

[0012] The second end of the first pin line is electrically connected to the second end of the second line segment, and the connection electrode is electrically connected to the first end of the first pin line via the at least one via. The surface of the connection electrode on the side away from the substrate is configured to be electrically connected to the flexible circuit board.

[0013] In one exemplary embodiment, the at least one insulating layer comprises an inorganic insulating layer.

[0014] In one exemplary embodiment, the first sub-region includes at least one driver chip region, the at least one driver chip region includes a plurality of driver chip pins, and the driver chip region is configured to connect to a driver chip.

[0015] In an exemplary embodiment, the first sub-region further includes two fan-out regions spaced apart along the first direction, and the at least one driver chip region is located between the two fan-out regions, and the plurality of second line segments are all located in the fan-out regions.

[0016] In an exemplary embodiment, the second line segment includes a first segment and a second segment stacked together, and the orthographic projection of the first segment onto the plane where the array substrate is located overlaps with the orthographic projection of the second segment onto the plane where the array substrate is located at least partially.

[0017] In one exemplary embodiment, each of the bonding pins includes a first pin line located on one side of the substrate, a second pin line located on the side of the first pin line away from the substrate, and a connection electrode located on the side of the second pin line away from the substrate;

[0018] The first end of the connecting electrode is electrically connected to the first end of the first pin line, and the second end of the connecting electrode is electrically connected to the first end of the second pin line; the second end of the first pin line is electrically connected to the second end of the first segment, the second end of the second pin line is electrically connected to the second end of the second segment, and the side surface of the connecting electrode away from the substrate is configured to be electrically connected to the flexible circuit board.

[0019] In an exemplary embodiment, the first segment and the first pin line are on the same layer, and the second segment and the second pin line are on the same layer.

[0020] On the other hand, this disclosure provides a display device, which includes an array substrate, a counter substrate, and a liquid crystal layer as described in any of the above embodiments; the array substrate and the counter substrate are disposed opposite to each other, and the liquid crystal layer is located between the array substrate and the counter substrate.

[0021] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0022] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0023] Figure 1 This is a front view schematic of an array substrate according to an embodiment of the present disclosure. Figure 1 ;

[0024] Figure 2 for Figure 1 Cross-sectional view of the AA mark in the middle Figure 1 ;

[0025] Figure 3 for Figure 1 Cross-sectional view of the AA mark in the middle Figure 2 ;

[0026] Figure 4 for Figure 1 Cross-sectional view of the AA mark in the middle Figure 3 ;

[0027] Figure 5 This is a front view schematic of an array substrate according to an embodiment of the present disclosure. Figure 2 ;

[0028] Figure 6 This is a partial cross-sectional schematic diagram of a display device according to an embodiment of the present disclosure.

[0029] Figure label:

[0030] AA - Display area, BB - Border area, B1 - First border area, B2 - Second border area, B11 - First sub-area, B12 - Second sub-area, B111 - Fan-out area, B112 - Driver chip area, B121 - Bonding pin area.

[0031] 10-Substrate, 11-First insulating layer, 12-Second insulating layer, 20-Heating wire, 21-First line segment, 22-Second line segment, 30-Binding pin, 31-First pin line, 32-Second pin line, 33-Connecting electrode, 40-Flexible circuit board, 50-Driver chip;

[0032] 100 - Array substrate, 200 - Opposite substrate, 300 - Liquid crystal layer, 400 - Black matrix, 500 - Color filter layer. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0034] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0035] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, not to limit the quantity. "Multiple" in this disclosure includes two or more quantities.

[0036] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0037] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0038] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0039] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0040] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having one or more functions.

[0041] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0042] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0043] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0044] This disclosure provides an array substrate, which includes a display area and a first border area located on one side of the display area; in a plane perpendicular to the array substrate, the array substrate includes a substrate and a plurality of heating lines located on one side of the substrate, the plurality of heating lines being configured to transfer heat to the array substrate; the plurality of heating lines are spaced apart along a first direction and extend along a second direction, the first direction intersecting the second direction;

[0045] Each heating wire includes a first segment and a second segment connected to each other. The first segment is located in the display area, and the second segment is located in the first frame area. The resistance of the second segment is less than that of the first segment.

[0046] The array substrate provided in this embodiment can be heated by setting multiple heating lines, which can improve the problems of high viscosity coefficient and easy crystallization of liquid crystal in low-temperature operating environments. Furthermore, by setting the resistance of the second line segment to be less than that of the first line segment, the heat loss of the heating line in the first frame area can be reduced, thereby improving the heating efficiency of the heating line in the display area.

[0047] Figure 1 This is a front view schematic of an array substrate according to an embodiment of the present disclosure. Figure 1 .like Figure 1 As shown, the array substrate may include a display area AA and a border area BB surrounding the display area AA. The border area BB may include a first border area B1 located on one side of the display area AA and a second border area B2 located on the remaining sides of the display area AA. For example, the first border area B1 may include the bottom border of the array substrate, and the second border area B2 may include the top border, left border, and right border of the array substrate.

[0048] In an exemplary embodiment, the display area AA may include: a plurality of data lines (not shown) and a plurality of gate lines (not shown) disposed on a substrate. The plurality of gate lines may extend along a first direction X and be arranged sequentially along a second direction Y different from the first direction X. The plurality of data lines may extend along the second direction Y and be arranged sequentially along the first direction X. The first direction X and the second direction Y may intersect; for example, the first direction X may be perpendicular to the second direction Y. The plurality of data lines and the plurality of gate lines may be located in different film layers; for example, the plurality of data lines may be located on the side of the plurality of gate lines away from the substrate.

[0049] In an exemplary embodiment, multiple data lines and multiple gate lines can intersect to form multiple sub-pixel regions. The region defined by the intersection of adjacent data lines and adjacent gate lines can be a sub-pixel region. One sub-pixel can be correspondingly disposed within a sub-pixel region. A sub-pixel region can include an open region and a non-open region surrounding the open region. The non-open region can be a region obscured by the black matrix of the opposing substrate of the array substrate, and the open region can be a region not obscured by the black matrix of the opposing substrate. Adjacent gate lines and data lines can both be located within the non-open region. The array substrate of this disclosure embodiment can be used to implement a display function, and the open region of each sub-pixel region can be configured for display. The non-open region surrounds the open region and is not displayed. However, this disclosure embodiment is not limited in this respect. In some examples, the array substrate can be used to implement other functions.

[0050] In an exemplary embodiment, the display area AA may include a plurality of pixel units disposed on a substrate. At least one pixel unit may include three sub-pixels (e.g., a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along a first direction X). The three sub-pixels of the pixel unit may be, for example, a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged sequentially in the order of blue sub-pixel, red sub-pixel, and green sub-pixel. At least one sub-pixel may include a pixel electrode (not shown) and a common electrode (not shown), and the orthographic projections of the pixel electrode and the common electrode of the sub-pixel onto the plane of the substrate may overlap. The common electrode of the plurality of sub-pixels in the display area AA may be an integral structure. The sub-pixel may also include a first transistor. The first transistor may be located adjacent to the intersection of a data line and a gate line. The first transistor may include a first gate, a first electrode, and a second electrode. The first gate may be electrically connected to the gate line, the first electrode of the first transistor may be electrically connected to the data line, and the second electrode may be electrically connected to the pixel electrode of a sub-pixel. The first transistor may be configured to provide data signals transmitted via the data line to the pixel electrode of the sub-pixel under the control of the gate line.

[0051] In one exemplary embodiment, the second border region B2 may include at least a gate driving circuit (e.g., including multiple cascaded shift registers), which may be electrically connected to multiple gate lines in the display region AA. The gate driving circuit may also include a second transistor.

[0052] In one exemplary embodiment, the second border region B2 may include a circuit region, a power line region, a crack dam region, and a dicing region sequentially disposed along the direction of the display region AA. The circuit region may be connected to the display region AA and may include at least gate drive circuitry (e.g., including multiple cascaded shift registers), which may be electrically connected to multiple gate lines in the display region AA. The power line region is connected to the circuit region and may include at least low-level power lines. The crack dam region is connected to the power line region and may include at least multiple cracks. The dicing region is connected to the crack dam region and may include at least a dicing groove, which may be configured such that after all film layers of the array substrate have been prepared, a dicing device can perform dicing along the dicing groove.

[0053] In one exemplary embodiment, such as Figure 1 As shown, the first border region B1 may include a first sub-region B11 and a second sub-region B12 sequentially arranged along a direction away from the display region AA. The first sub-region B11 may include at least one fan-out region B111 and at least one driver chip region B112. Figure 1 As shown, the first sub-region B11 may include two fan-out regions B111 and one driver chip region B112. The two fan-out regions B111 may be spaced apart along a first direction X, and the driver chip region B112 may be located between the two fan-out regions B111. The orthographic projection of the fan-out regions B111 onto the plane of the array substrate may be trapezoidal, and the orthographic projection of the driver chip region B112 onto the plane of the array substrate may be rectangular. The driver chip region B112 may include multiple driver chip pins, and the driver chip region B112 is configured to connect an integrated circuit (IC). The driver chip can be electrically connected to the data lines of the display area AA through the driver chip pins. The driver chip can be configured to generate signals required to drive sub-pixels and provide the driving signals to the data lines of the display area.

[0054] In one exemplary embodiment, such as Figure 1As shown, the second sub-region B12 may include at least one bonding pin area B121. For example, the second sub-region B12 may include two bonding pin areas B121, which are spaced apart along a first direction X. Fan-out areas B111 and bonding pin areas B121 can be grouped one-to-one. Bonding pin areas B121 may include multiple bonding pins, which can be configured to bond to at least one corresponding circuit board (e.g., a flexible printed circuit board (FPC)).

[0055] In one exemplary embodiment, such as Figure 1 As shown, the array substrate may further include a conductive layer located on one side of the substrate 10, and the conductive layer may include multiple heating lines 20. The multiple heating lines 20 are arranged at intervals along a first direction X and extend along a second direction Y. Each heating line 20 includes a first segment 21 and a second segment 22 connected to each other. The first segment 21 may be located in the display area AA, and the second segment 22 may be located in the first sub-area B11. The first end of the second segment 22 may be electrically connected to the first segment 21, and the second end of the second segment 22 may be electrically connected to a bonding pin. Figure 1 As shown, multiple first line segments 21 can be distributed at equal intervals along the first direction X.

[0056] In an exemplary embodiment, the first line segment 21 and the second line segment 22 may be located in the same conductive layer or in different conductive layers.

[0057] In an exemplary embodiment, the material of the second segment 22 can be molybdenum (Mo) or aluminum (Al), etc. At room temperature, the resistivity of molybdenum (Mo) is approximately 5.2 ohm-meters (Ω·m), and the resistivity of aluminum (Al) is approximately 2.83 × 10⁻⁶. -8 Ohm-meter (Ω·m). The formula for calculating sheet resistance is: Rs = ρ / t, where Rs represents sheet resistance, ρ represents the resistivity of the material, and t represents the film thickness. From the above formula, it can be seen that the lower the resistivity of the material, the lower the sheet resistance. When t is set to 2800 angstroms, the sheet resistance of the second segment 22 using aluminum (Al) is approximately 0.15 Ω / □ (Ω / sq), and the sheet resistance of the second segment 22 using molybdenum (Mo) is approximately 0.38 Ω / □ (Ω / sq).

[0058] In an exemplary embodiment, the linewidth of the second line segment 22 can range from 4.0 micrometers to 4.5 micrometers. Given a fixed material and length, the larger the cross-sectional area of ​​the second line segment 22, the lower its resistance. When the material of the second line segment 22 is aluminum (Al), its resistance is approximately 364 ohms when the linewidth is 4.0 micrometers. When the material of the second line segment 22 is aluminum (Al), its resistance is approximately 314.5 ohms when the linewidth is 4.5 micrometers. Therefore, increasing the linewidth of the second line segment 22 can reduce its resistance.

[0059] In an exemplary embodiment, the second line segment 22 may include a first segment and a second segment stacked together. The first segment is closer to the substrate 10 than the second segment, and the orthographic projections of the first segment and the second segment onto the plane of the array substrate may at least partially overlap. For example, the orthographic projections of the first segment and the second segment onto the plane of the array substrate may overlap. The second ends of both the first and second segments are electrically connected to bonding pins, and the first ends of both the first and second segments are electrically connected to the first line segment 21. By configuring the second line segment 22 to include the stacked first and second segments, a parallel wiring configuration can be formed, which can reduce the resistance of the heating wire in the first border area, reduce the heating loss generated by the heating wire in the first border area, and improve the heating efficiency of the heating wire. For example, when both the first and second segments are made of aluminum (Al), and the second line segment is constructed in parallel with the first segment, the resistance of the second line segment is approximately 210 ohms.

[0060] Figure 2 for Figure 1 Cross-sectional view of the AA mark in the middle Figure 1 In this embodiment of the disclosure, the thickness direction of the array substrate is defined as the third direction and denoted as Z. In this embodiment of the disclosure, the first direction X, the second direction Y, and the third direction Z are all perpendicular to each other.

[0061] like Figure 2 As shown, the bonding pin 30 may include a first pin line 31, a second pin line 32, and a connection electrode 33 located on one side of the substrate 10. The first pin line 31 is closer to the substrate 10 than both the second pin line 32 and the connection electrode 33, and the second pin line 32 is located between the first pin line 31 and the connection electrode 33. For example, the first segment and the first pin line 31 may be in the same layer, and the second segment and the second pin line 32 may be in the same layer.

[0062] like Figure 2As shown, the bonding pin 30 may further include a first insulating layer 11 located between the first pin line 31 and the second pin line 32, and a second insulating layer 12 located between the second pin line 32 and the connecting electrode 33. The second insulating layer 12 includes at least one first via K1 and at least one second via K2. Both the first insulating layer 11 and the second insulating layer 12 within the first via K1 are etched away, exposing a portion of the surface of the first pin line 31 away from the substrate 10. The second insulating layer 12 within the second via K2 is etched away, exposing a portion of the surface of the second pin line 32 away from the substrate 10. The first end of the connecting electrode 33 is electrically connected to the first end of the first pin line 31 via the first via K1, and the second end of the connecting electrode 33 is electrically connected to the first end of the second pin line 32 via the second via K2. The second end of the first pin line 31 is configured to be electrically connected to the second end of the first segment, and the second end of the second pin line 32 is configured to be electrically connected to the second end of the second segment. The surface of the connecting electrode 33 away from the substrate 10 is configured to be electrically connected to the flexible circuit board.

[0063] In an exemplary embodiment, the materials of the first insulating layer 11 and the second insulating layer 12 can be inorganic materials. Inorganic materials, for example, are silicon oxynitride (SiO2). x N y ) or silicon nitride (SiN) x ) or silicon oxide (SiO) x One or more of the following: ) The first insulating layer 11 and the second insulating layer 12 can be a single layer, a multi-layer, or a composite layer structure.

[0064] In an exemplary embodiment, the materials of the first lead 31 and the second lead 32 can be metallic materials, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, the materials of the first lead 31 and the second lead 32 can be alloys of metallic materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), for example, aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), or molybdenum-nickel-titanium alloy (MoNiTi). The first lead 31 and the second lead 32 can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Nb / Cu, MoNiTi / Cu, MoNb / Cu / MoNiTi, or MoNiTi / Cu / MoNiTi, etc.

[0065] In one exemplary embodiment, the material of the connecting electrode 33 can be a transparent conductive oxide material, which may include indium tin oxide (ITO) or indium zinc oxide (IZO). For example, the connecting electrode 33 can be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO.

[0066] In one exemplary embodiment, the substrate 10 may be a transparent substrate. For example, the substrate 10 may be a rigid substrate or a flexible substrate. For example, the material of the rigid substrate may include, but is not limited to, one or more of glass and quartz. The material of the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. However, the embodiments disclosed herein are not limited in this respect.

[0067] Figure 3 for Figure 1 Cross-sectional view of the AA mark in the middle Figure 2 .like Figure 3 As shown, the bonding pin 30 may include a first pin line 31 located on one side of the substrate 10 and a connection electrode 33. The first pin line 31 is closer to the substrate 10 than the connection electrode 33.

[0068] like Figure 3 As shown, the bonding pin 30 may further include a first insulating layer 11 and a second insulating layer 12 located between the first pin line 31 and the connecting electrode 33. The second insulating layer 12 includes at least one first via K1, within which both the first insulating layer 11 and the second insulating layer 12 are etched away, exposing a portion of the surface of the first pin line 31 away from the substrate 10. The connecting electrode 33 is electrically connected to a first end of the first pin line 31 via the first via K1. The second end of the first pin line 31 is configured to be electrically connected to a second end of the second line segment, and the surface of the connecting electrode 33 away from the substrate 10 is configured to be electrically connected to the flexible circuit board.

[0069] Figure 4 for Figure 1 Cross-sectional view of the AA mark in the middle Figure 3 .like Figure 4 As shown, the bonding pin 30 may include a first pin line 31 located on one side of the substrate 10 and a connection electrode 33. The first pin line 31 is closer to the substrate 10 than the connection electrode 33.

[0070] like Figure 4As shown, the bonding pin 30 may further include a first insulating layer 11 located between the substrate 10 and the first pin line 31, and a second insulating layer 12 located between the first pin line 31 and the connection electrode 33. The second insulating layer 12 includes at least one first via K1, within which the second insulating layer 12 is etched away, exposing a portion of the surface of the first pin line 31 away from the substrate 10. The connection electrode 33 is electrically connected to a first end of the first pin line 31 via the first via K1. The second end of the first pin line 31 is configured to be electrically connected to a second end of the second line segment, and the surface of the connection electrode 33 away from the substrate 10 is configured to be electrically connected to the flexible circuit board.

[0071] Figure 5 This is a front view schematic of an array substrate according to an embodiment of the present disclosure. Figure 2 .like Figure 5 As shown, the array substrate may further include a flexible circuit board 40, which can be bonded to multiple bonding pins. For example, the orthographic projection of the flexible circuit board 40 onto the plane of the array substrate may include the orthographic projections of two bonding pin areas B121 onto the plane of the array substrate.

[0072] like Figure 5 As shown, the array substrate may further include a driver chip 50. The orthographic projection of the driver chip 50 onto the plane of the array substrate may include the orthographic projection of the driver chip area B112 onto the plane of the array substrate. The driver chip 50 is bonded to multiple driver chip pins. The driver chip 50 can be electrically connected to the data lines of the display area AA via the driver chip pins. The driver chip 50 can be configured to generate signals required for driving sub-pixels and provide the driving signals to the data lines of the display area.

[0073] Figure 6 This is a partial cross-sectional schematic diagram of a display device according to an embodiment of the present disclosure, as shown below. Figure 6 As shown, the display device may further include a counter substrate 200 and a liquid crystal layer 300 disposed between the array substrate 100 and the counter substrate 200. The array substrate 100 may be any of the array substrates described in the above embodiments.

[0074] In one exemplary embodiment, such as Figure 6 As shown, the opposing substrate 200 may include a substrate, and a black matrix 400 and a color filter layer 500 disposed on the substrate. However, the embodiments disclosed herein are not limited thereto.

[0075] This disclosure also provides a display device. The display device includes the array substrate described in any of the foregoing embodiments. The display device can be any product or component with display function, such as a liquid crystal panel, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. This disclosure is not limited in this respect.

[0076] While the embodiments disclosed in this invention have been described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. An array substrate, characterized in that, The array includes a display area and a first border area located on one side of the display area; in a plane perpendicular to the array substrate, the array substrate includes a substrate and a plurality of heating lines located on one side of the substrate, the plurality of heating lines being configured to transfer heat to the array substrate; the plurality of heating lines are spaced apart along a first direction and extend along a second direction, the first direction intersecting the second direction; Each heating wire includes a first segment and a second segment connected to each other. The first segment is located in the display area, and the second segment is located in the first frame area. The second segment includes a first segment and a second segment stacked together. The orthographic projection of the first segment on the plane where the array substrate is located overlaps with the orthographic projection of the second segment on the plane where the array substrate is located at least partially. The resistance of the second segment is less than the resistance of the first segment. The first ends of multiple second line segments are electrically connected to the multiple first line segments one by one, and the second ends of multiple second line segments are electrically connected to multiple bonding pins one by one; Each of the bonding pins includes a first pin line located on one side of the substrate, a second pin line located on the side of the first pin line away from the substrate, and a connection electrode located on the side of the second pin line away from the substrate; a first end of the connection electrode is electrically connected to a first end of the first pin line, and a second end of the connection electrode is electrically connected to a first end of the second pin line; a second end of the first pin line is electrically connected to a second end of the first segment, and a second end of the second pin line is electrically connected to a second end of the second segment, and the surface of the connection electrode away from the substrate is configured to be electrically connected to the flexible circuit board.

2. The array substrate as described in claim 1, characterized in that, The material of the second line segment is molybdenum or aluminum.

3. The array substrate as described in claim 1, characterized in that, The sheet resistance of the second line segment ranges from 0.15Ω / □ to 0.38Ω / □.

4. The array substrate as described in claim 1, characterized in that, The line width of the second line segment ranges from 4.0 micrometers to 4.5 micrometers.

5. The array substrate as described in any one of claims 1 to 4, characterized in that, The first border area includes a first sub-area and a second sub-area arranged sequentially along a direction away from the display area; the second sub-area includes at least one binding pin area, the at least one binding pin area includes a plurality of binding pins, and the plurality of second line segments are all located in the first sub-area.

6. The array substrate as described in claim 5, characterized in that, The first sub-region includes at least one driver chip region, the at least one driver chip region includes a plurality of driver chip pins, and the driver chip region is configured to connect to a driver chip.

7. The array substrate as described in claim 6, characterized in that, The first sub-region further includes two fan-out regions spaced apart along the first direction, and the at least one driver chip region is located between the two fan-out regions, and the multiple second line segments are all located in the fan-out regions.

8. The array substrate as described in claim 5, characterized in that, The first segment and the first pin line are on the same layer, and the second segment and the second pin line are on the same layer.

9. A display device, characterized in that, It includes an array substrate, a counter substrate, and a liquid crystal layer as described in any one of claims 1 to 8; the array substrate and the counter substrate are disposed opposite to each other, and the liquid crystal layer is located between the array substrate and the counter substrate.

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