Mask pattern processing method and device, equipment, medium and product

Abstract

The invention discloses a mask pattern processing method, device and equipment, a medium and a product, and relates to the technical field of semiconductor integrated circuits. The mask pattern processing method comprises the following steps: performing photoetching rule inspection on a target mask pattern to obtain target pattern feature information of the target mask pattern; the target layout feature information is processed through a defect correction model, a target defect correction strategy of the target mask plate graph is obtained, and the defect correction model is a model obtained after a large model is finely adjusted according to historical layout feature information and a corresponding historical defect correction strategy; and based on the target defect correction strategy, performing defect correction on the target mask plate graph to obtain the target mask plate graph after defect correction.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor integrated circuit technology, and in particular, relates to a method, device, equipment, medium and product for processing a mask pattern. Background Art

[0002] At present, layout design and mask manufacturing are carried out before the actual chip manufacturing. Before the mask is transferred to the mask manufacturer, it will be tested through a simulation model, that is, the designed mask is simulated to obtain the outline after exposure, and then the defects of the mask are obtained through the Lithography Rule Check (LRC). In the case of defects in the mask, correction of the defects is a crucial link.

[0003] In the existing method, after the defects of the mask are obtained through LRC detection, experienced optical proximity correction (OPC) engineers usually manually adjust the graphic parameters around the defects in the mask to make compensation corrections.

[0004] However, existing methods rely on experienced engineers to correct defects and are unable to directly provide accurate correction solutions, resulting in low efficiency and poor accuracy of defect correction. Summary of the invention

[0005] The embodiments of the present application provide a method, device, equipment, medium and product for processing a mask pattern, which can improve the efficiency and accuracy of defect correction.

[0006] In one aspect of an embodiment of the present application, a method for processing a mask layout is provided, comprising:

[0007] Performing a lithography rule check on the target mask layout to obtain target layout feature information of the target mask layout, wherein the layout feature information includes layout defect information and surrounding environment information of the layout defect;

[0008] The target layout feature information is processed through the defect correction model to obtain the target defect correction strategy of the target mask layout. The defect correction model is a model obtained by fine-tuning the large model according to the historical layout feature information and the corresponding historical defect correction strategy. Based on the target defect correction strategy, the target mask layout is defect-corrected to obtain the target mask layout after defect correction.

[0009] In one aspect of an embodiment of the present application, a mask layout processing device is provided, comprising:

[0010] A layout inspection module is used to perform a lithography rule inspection on a target mask layout to obtain target layout feature information of the target mask layout, wherein the layout feature information includes layout defect information and surrounding environment information of the layout defect;

[0011] A strategy determination module is used to process the target layout feature information through a defect correction model to obtain a target defect correction strategy for the target mask layout. The defect correction model is a model obtained by fine-tuning the large model according to the historical layout feature information and the corresponding historical defect correction strategy.

[0012] The layout correction module is used to perform defect correction on the target mask layout based on the target defect correction strategy to obtain the target mask layout after defect correction.

[0013] According to one aspect of an embodiment of the present application, an electronic device is provided, which includes: a memory and a program or instruction stored in the memory and executable on a processor, wherein when the program or instruction is executed by the processor, a method for processing a mask pattern as provided in any aspect of the above-mentioned embodiment of the present application is implemented.

[0014] According to one aspect of an embodiment of the present application, a readable storage medium is provided, on which a program or instruction is stored. When the program or instruction is executed by a processor, a method for processing a mask pattern as provided in any aspect of the above-mentioned embodiment of the present application is implemented.

[0015] According to one aspect of an embodiment of the present application, a computer program product is provided. When instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes a method for processing a mask pattern as provided in any aspect of the above-mentioned embodiment of the present application.

[0016] In the mask layout processing method provided in the embodiment of the present application, the historical layout feature information and the corresponding historical defect correction strategy are used to fine-tune the large model to obtain a defect correction model. After the target mask layout is subjected to a lithography rule check and the target layout feature information of the target mask layout is obtained. It is only necessary to input the target layout feature information into the defect correction model to obtain the target defect correction strategy of the target mask layout, thereby completing the defect correction of the target mask layout according to the target defect correction strategy. In this way, the embodiment of the present application can directly determine the defect correction strategy corresponding to various layout defects through the defect correction model, thereby automatically completing the defect correction of the target mask layout. There is no need to rely on experienced engineers to correct defects, which can improve the efficiency and accuracy of defect correction. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 It is a flowchart of a method for processing a mask layout provided by an embodiment of the present application;

[0019] Figure 2 is a schematic diagram of a mask pattern under an ideal condition provided by an embodiment of the present application;

[0020] Figure 3 is a schematic diagram of a mask pattern of a bridge defect type provided by an embodiment of the present application;

[0021] Figure 4 It is a structural schematic diagram of a mask layout processing device provided by an embodiment of the present application;

[0022] Figure 5 It is a structural schematic diagram of a mask layout processing device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0023] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0024] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0025] It should be noted that the acquisition, storage, use, and processing of data in the technical solution of this application are in compliance with the relevant provisions of national laws and regulations.

[0026] It should be noted that in the embodiments of the present application, certain software, components, models and other existing solutions in the industry may be mentioned, and they should be regarded as exemplary. Their purpose is only to illustrate the feasibility of implementing the technical solution of the present application, but it does not mean that the applicant has or will necessarily use the solution.

[0027] In the existing method, after the defects of the mask are obtained through LRC detection, experienced OPC engineers usually manually adjust the graphic parameters around the defects in the mask to make corrections. However, the existing method relies on experienced engineers to correct the defects and cannot directly provide accurate correction solutions, resulting in low efficiency and poor accuracy of defect correction.

[0028] The purpose of the present application is to provide a method, device, equipment, medium and product for processing a mask layout. In the method for processing a mask layout provided in the embodiment of the present application, the historical layout feature information and the corresponding historical defect correction strategy are used to fine-tune the large model to obtain a defect correction model. After the target mask layout is subjected to a lithography rule check and the target layout feature information of the target mask layout is obtained. It is only necessary to input the target layout feature information into the defect correction model to obtain the target defect correction strategy of the target mask layout, thereby completing the defect correction of the target mask layout according to the target defect correction strategy. In this way, the embodiment of the present application can directly determine the defect correction strategy corresponding to various layout defects through the defect correction model, thereby automatically completing the defect correction of the target mask layout. There is no need to rely on experienced engineers to correct defects, which can improve the efficiency and accuracy of defect correction.

[0029] The following describes specific embodiments of the mask layout processing method, device, equipment, medium and product provided in the embodiments of the present application. The following first describes the mask layout processing method. Figure 1 A flowchart of a method for processing a mask layout is provided. The method for processing a mask layout can be applied to a server. The method for processing a mask layout can include the following S101 to S103.

[0030] S101, performing a lithography rule check on a target mask layout to obtain target layout feature information of the target mask layout, wherein the layout feature information includes layout defect information and surrounding environment information of the layout defect.

[0031] In this embodiment, the layout feature information includes layout defect information and surrounding environment information of the layout defect, and the target layout feature information includes layout defect information of the target mask layout and surrounding environment information of the layout defect of the target mask layout.

[0032] The layout defect information of the target mask layout is used to characterize the mask pattern defects existing in the target mask layout. For example, the mask pattern defects can be at least one of the defect patterns of the bridging defect type, the defect patterns of the necking defect type, and the defect patterns of the sub-resolution auxiliary pattern defect type.

[0033] The surrounding environment information of the layout defect may include the shape and coordinates of the graphics around the defect coordinates, as well as the distance between these graphics and the distance from these graphics to the defect. By considering the surrounding environment information of the defect location, it is possible to avoid introducing other defects in the surrounding area after the defect is corrected. Lithography rule checking refers to the use of lithography imaging models to know in advance the manufacturability problems that the design of the mask layout may face in the future before the lithography process is implemented, to ensure that the design of the mask layout meets the requirements of the lithography process, thereby avoiding manufacturing failures caused by improper design during the manufacturing process. For example, lithography rule checking can include critical dimension deformation checking, layout defect verification, line end deformation checking, through-hole coverage checking, auxiliary graphic imaging checking, and process window checking.

[0034] As an example, the server performs a lithography rule check on the target mask layout through lithography imaging simulation software to obtain the target layout feature information of the target mask layout. Specifically, the lithography imaging simulation software uses the optical imaging model and the corresponding process window to quickly and accurately detect regular hot spots on the full-chip photomask layout. By simulating the impact of various factors in the lithography process (such as light source, mask, photoresist, etc.) on layout imaging, possible layout errors can be predicted and discovered.

[0035] S102, processing the target layout feature information through the defect correction model to obtain a target defect correction strategy for the target mask layout, wherein the defect correction model is a model obtained by fine-tuning the large model according to the historical layout feature information and the corresponding historical defect correction strategy.

[0036] In this embodiment, the defect correction model is constructed based on machine learning or deep learning, and is trained by using historical layout feature information and corresponding historical defect correction strategies. On the basis of the defect correction model obtained by training, the defect correction model can be further fine-tuned according to new historical layout feature information and corresponding historical defect correction strategies to improve the recognition accuracy and efficiency of the defect correction model.

[0037] The target defect correction strategy is used to characterize the corresponding corrective measures that need to be taken for the defects of the target mask layout. For example, the defect correction strategy may include breaking edges, moving, deleting, enlarging, reducing, and adding or deleting sub-resolution auxiliary graphics on the defective graphics and / or the mask graphics around them.

[0038] As an example, the server inputs the target layout feature information of the target mask layout into the fine-tuned defect correction model, and the defect correction model analyzes the defect type to which the target layout feature information belongs, thereby outputting the corresponding target defect correction strategy.

[0039] S103, based on the target defect correction strategy, performing defect correction on the target mask layout to obtain a defect-corrected target mask layout.

[0040] In this embodiment, the server uses an electronic design automation tool to correct defects in the target mask layout according to the target defect correction strategy output by the defect correction model. Specifically, it may include breaking edges, moving, deleting, enlarging, reducing, and adding or deleting sub-resolution auxiliary graphics on the defect pattern in the target mask layout and / or the mask patterns around it. Thus, the target mask layout after defect correction is obtained.

[0041] In the mask layout processing method provided in this embodiment, the historical layout feature information and the corresponding historical defect correction strategy are used to fine-tune the large model to obtain a defect correction model. After the target mask layout is checked for lithography rules and the target layout feature information of the target mask layout is obtained. It is only necessary to input the target layout feature information into the defect correction model to obtain the target defect correction strategy of the target mask layout, so as to complete the defect correction of the target mask layout according to the target defect correction strategy. In this way, the embodiment of the present application can directly determine the defect correction strategy corresponding to various layout defects through the defect correction model, thereby automatically completing the defect correction of the target mask layout. There is no need to rely on experienced engineers to correct defects, which can improve the efficiency and accuracy of defect correction.

[0042] As an optional embodiment, before S102, the method for correcting the mask layout may further include:

[0043] Obtain target training data, target large model and target fine-tuning algorithm. The target training data includes historical map feature information and corresponding historical defect correction strategy.

[0044] Based on historical layout feature information, historical defect correction strategies and target fine-tuning algorithms, the target large model is trained until the training stop conditions are met to obtain a defect correction model.

[0045] In this embodiment, the historical layout feature information includes historical layout defect information of the historical mask layout and surrounding environment information of the layout defect of the historical mask layout.

[0046] Historical layout feature information usually comes from actual layout data during semiconductor manufacturing or design, which contains various known defects and the surrounding environment of the defects. Among them, historical layout feature information needs to be stored in a computer-readable form, such as an image file, a vector graphics file, or a specific layout description language file.

[0047] For each known defect in the historical layout feature information, one or more corresponding historical defect correction strategies need to be recorded. These historical defect correction strategies can be instructions for automatic correction operations (such as filling missing parts, removing redundant parts, adjusting sizes, etc.), or recommended manual correction steps.

[0048] The target large model is a deep learning model used for training, which should be capable of processing similar image or graphic data. For example, the target large model can be a large model of the BERT series and the GPT series.

[0049] The target fine-tuning algorithm is a fine-tuning algorithm used when training the target large model. For example, the target fine-tuning algorithm can be prefix tuning, adapter tuning, prompt tuning, P-Tuning, LoRA, etc.

[0050] As an example, the server inputs historical map feature information and corresponding historical defect correction strategies into the target large model as training data. Using the target fine-tuning algorithm, the parameters of the target large model are iteratively adjusted through methods such as back propagation and gradient descent to minimize the loss function.

[0051] Then, when the training stop condition is met, the training of the target large model is stopped to obtain the corresponding defect correction model. Specifically, the time to stop training can be determined based on the performance on the validation set (such as accuracy, recall, F1 score, etc.), the number of training rounds, and whether the loss value converges.

[0052] Through this embodiment, a defect correction model that can automatically recommend defect correction strategies for specific defects is constructed by combining historical layout feature information, historical defect correction strategies, large models, and fine-tuning algorithms. In this way, by constructing a defect correction model, the efficiency and accuracy of defect correction can be improved.

[0053] As an optional embodiment, the target mask layout includes a defect pattern of a bridge defect type;

[0054] S103 may specifically include:

[0055] Obtaining a bridge area in a target mask layout;

[0056] A first pattern correction operation is performed on the first mask patterns in the bridge area to separate the exposure profiles between the first mask patterns to obtain a target mask layout after defect correction, wherein the first mask patterns are mask patterns connected with the exposure profiles in the bridge area.

[0057] In this embodiment, the bridge defect type refers to a phenomenon in which exposure profiles between different mask patterns are connected, which is generally caused by the mask patterns being too close to each other or being affected by sub-resolution auxiliary patterns.

[0058] like Figure 2 As shown, a schematic diagram of a mask pattern under an ideal condition is provided, wherein the exposure profile 202 generated by each mask pattern is generally within the pattern boundary range 201 thereof.

[0059] like Figure 3 As shown, a schematic diagram of a mask pattern of a bridge defect type is provided, wherein the exposure profile 202 generated by each mask pattern obviously exceeds its pattern boundary range 201, and the exposure profiles 202 generated by each mask pattern are connected to each other.

[0060] The first mask pattern is a mask pattern in which the exposure contour connection phenomenon occurs in the bridge area of ​​the target mask pattern, that is, a defect pattern of the bridge defect type in the target mask pattern.

[0061] The first pattern correction operation is used to represent a correction operation for separating the exposure profiles between the first mask patterns, thereby overcoming the influence of the bridge defect.

[0062] As an example, the server marks the corresponding bridge area in the target mask layout according to the target layout feature information, and identifies the first mask pattern connected to all exposure contours in the bridge area.

[0063] Then, for each first mask pattern, first pattern correction operations such as line movement, scaling, rotation, deletion, and addition are respectively performed to separate the exposure profiles between the first mask patterns, thereby eliminating bridge defects. After the first pattern correction operation is completed, the defect-corrected target mask layout can be obtained, and the defect-corrected target mask layout is output as a file format that can be used for manufacturing, so as to prepare for subsequent manufacturing processes.

[0064] Through this embodiment, for a target mask layout with defective patterns of a bridge defect type, a first pattern correction operation is performed to separate the exposure profiles of the first mask patterns connected in the bridge region. In this way, the target mask layout with a bridge defect type can be accurately corrected, thereby improving the accuracy of the defect correction.

[0065] As an optional embodiment, the first image correction operation includes at least one of the following:

[0066] moving each first mask pattern along a target direction, where the target direction is a direction that increases the distance between the first mask patterns;

[0067] Deleting the sub-resolution auxiliary pattern whose distance from the first mask pattern is less than a preset distance threshold, or moving the sub-resolution auxiliary pattern in a direction away from the first mask pattern so that the distance between the sub-resolution auxiliary pattern and the first mask pattern is greater than or equal to the preset distance threshold;

[0068] The first distance and the second distance between each first mask pattern are increased, the first distance is the minimum distance between the inflection points of the two first mask patterns, and the second distance is the minimum distance between the inflection points of the two first mask patterns and the endpoints of the line segments. In this embodiment, as a first example, after the service end determines the first mask pattern in the bridge area, a target direction is determined according to the first mask pattern, and the target direction should increase the distance between the first mask patterns, thereby eliminating the bridge defect.

[0069] Then, use the move tool in the layout editing software to select the first mask pattern to be moved. Drag the first mask pattern along the target direction, or enter specific moving distance and angle parameters to move the first mask pattern to a new position. Finally, after the move operation is completed, verify the corrected mask layout to check whether the bridge defect has been eliminated. Stop the operation until the bridge defect has been eliminated.

[0070] As a second example, after the service end determines the first mask pattern in the bridge area. It is necessary to identify the sub-resolution auxiliary patterns associated with the first mask pattern, and these sub-resolution auxiliary patterns may be located near or inside the first mask pattern. Specifically, each sub-resolution auxiliary pattern whose distance from the first mask pattern is less than the preset distance threshold is a sub-resolution auxiliary pattern associated with the first mask pattern. The preset distance threshold is the distance threshold set when adding the sub-resolution auxiliary pattern to the first mask pattern. If the spacing between the sub-resolution auxiliary pattern and the first mask pattern is too small, a bridge defect may result. At this time, you can choose to delete these sub-resolution auxiliary patterns, or you can move the sub-resolution auxiliary patterns in a direction away from the first mask pattern to increase the distance between them until the distance between the sub-resolution auxiliary pattern and the first mask pattern is greater than or equal to the preset distance threshold. Then, the corrected first mask pattern is verified to check whether the bridge defect is eliminated, and the operation is stopped until the bridge defect is eliminated. At the same time, it is further confirmed whether the deletion or movement of the sub-resolution auxiliary pattern has a negative impact on the lithography process.

[0071] As a third example, after the service end determines the first mask pattern in the bridge area, use the adjustment tool in the layout editing software to select each first mask pattern whose distance needs to be increased. Then adjust the position of the inflection point or the length of the line segment in the first mask pattern according to actual needs to increase the minimum distance between the inflection points of each first mask pattern and the minimum distance between the inflection point of the first mask pattern and the end point of the line segment. Then, verify the corrected first mask pattern to check whether the bridge defect is eliminated, and stop the operation until the bridge defect is eliminated.

[0072] Through this embodiment, multiple first pattern correction operations are provided to separate the exposure profiles between the first mask patterns. In this way, the most appropriate first pattern correction operation can be selected for defect correction according to the specific defect conditions of the target mask layout, which can improve the accuracy of defect correction.

[0073] As an optional embodiment, the target mask pattern includes a defect pattern of a necking defect type;

[0074] S103 may specifically include:

[0075] Obtaining a necking region in a target mask layout;

[0076] A second graphic correction operation is performed on the second mask pattern in the necking area to obtain a target mask pattern after defect correction, wherein the second mask pattern is a mask pattern in which an exposure profile cannot be formed in the necking area, and the second graphic correction operation includes at least one of adjusting the position of the second mask pattern and enlarging the graphic size of the second mask pattern.

[0077] In this embodiment, the necking defect type refers to a defect type in which the mask pattern cannot form a corresponding exposure profile due to reasons such as the size of the mask pattern being too small or the photolithography effect being poor.

[0078] The second mask pattern is a mask pattern in which a corresponding exposure profile cannot be formed in the necking region of the target mask pattern, that is, a defect pattern of a necking defect type in the target mask pattern.

[0079] The second pattern correction operation is used to characterize the operation of overcoming the necking defect. For example, the second pattern correction operation may be to adjust the position of the second mask pattern or to enlarge the pattern size of the second mask pattern.

[0080] As an example, the server marks the corresponding necking region in the target mask layout according to the target layout feature information, and identifies all second mask patterns that cannot form an exposure profile in the necking region.

[0081] Then, for each second mask pattern, a second pattern correction operation is performed respectively so that each second mask pattern can form a corresponding exposure profile, thereby eliminating the necking defect. After the second pattern correction operation is completed, a defect-corrected target mask layout can be obtained, and the defect-corrected target mask layout is output as a file format that can be used for manufacturing, so as to prepare for the subsequent manufacturing process.

[0082] Specifically, for some second mask patterns, their positions can be slightly moved to avoid conflicts with adjacent patterns, thereby improving the lithography effect and reducing the possibility of necking. For other second mask patterns, their sizes may need to be directly increased to ensure that there is sufficient material filling during the lithography process to avoid necking.

[0083] Through this embodiment, a variety of second pattern correction operations are provided so that each second mask pattern in the target mask layout can form a corresponding exposure profile. In this way, the most appropriate second pattern correction operation can be selected to correct the defect according to the specific defect situation of the target mask layout, which can improve the accuracy of defect correction.

[0084] As an optional embodiment, the target mask layout includes a defect pattern of a sub-resolution auxiliary pattern defect type;

[0085] S103 may specifically include:

[0086] Acquire an abnormal sub-resolution auxiliary pattern in the target mask layout, where the abnormal sub-resolution auxiliary pattern is a sub-resolution auxiliary pattern that forms an exposure profile in the target mask layout;

[0087] A third pattern correction operation is performed on the sub-resolution auxiliary pattern to obtain a target mask layout after defect correction, and the third pattern correction operation includes at least one of a deletion operation on the sub-resolution auxiliary pattern and an area reduction operation on the sub-resolution auxiliary pattern.

[0088] In this embodiment, the sub-resolution auxiliary pattern will not form an exposure profile under an ideal state, and the sub-resolution auxiliary pattern defect type indicates that the sub-resolution auxiliary pattern forms a corresponding exposure profile.

[0089] The abnormal sub-resolution auxiliary pattern is a sub-resolution auxiliary pattern that forms an exposure profile in the target mask layout, that is, a defective pattern of the defect type of the sub-resolution auxiliary pattern in the target mask layout.

[0090] The third pattern correction operation is used to represent an operation of overcoming the defects of the sub-resolution auxiliary pattern. For example, the third pattern correction operation may be to delete the corresponding sub-resolution auxiliary pattern or to reduce the area of ​​the corresponding sub-resolution auxiliary pattern.

[0091] As an example, the server marks the corresponding abnormal sub-resolution auxiliary graphics in the target mask layout according to the target layout feature information.

[0092] Then, for each abnormal sub-resolution auxiliary pattern, a third pattern correction operation is performed respectively so that each abnormal sub-resolution auxiliary pattern will no longer form a corresponding exposure profile, thereby eliminating the sub-resolution auxiliary pattern defect. After the third pattern correction operation is completed, a defect-corrected target mask layout can be obtained, and the defect-corrected target mask layout is output as a file format that can be used for manufacturing, so as to prepare for subsequent manufacturing processes.

[0093] Specifically, for those abnormal sub-resolution auxiliary patterns that obviously do not meet the design requirements or may have a negative impact on chip performance, a deletion operation is directly performed, which usually requires removing all related parts of these patterns from the target mask layout.

[0094] For some cases, if the removal of abnormal sub-resolution auxiliary patterns may lead to significant changes in adjacent patterns or deterioration of the process window, they can be considered for area reduction. This usually requires reducing the size of the abnormal sub-resolution auxiliary patterns to the point where they no longer form an exposure profile while maintaining their positive impact on the lithography process.

[0095] Through this embodiment, a variety of third pattern correction operations are provided so that each abnormal sub-resolution auxiliary pattern in the target mask layout will no longer form a corresponding exposure profile. In this way, the most appropriate third pattern correction operation can be selected to correct the defect according to the specific defect situation of the target mask layout, which can improve the accuracy of defect correction.

[0096] As an optional embodiment, after S103, the method for correcting the mask layout may further include:

[0097] Performing a manufacturing rule check operation on the target mask layout to obtain a layout check result;

[0098] When the layout inspection result indicates that the target mask layout does not have a manufacturing rule violation problem, determining the target mask layout as a final mask layout;

[0099] When the layout inspection result indicates that the target mask layout has a manufacturing rule violation problem, the violation area of ​​the target mask layout is corrected until the target mask layout has no layout defects and no manufacturing rule violation problem, thereby obtaining a final mask layout.

[0100] In this embodiment, manufacturing rule checking is a process of verifying whether the design of the layout meets specific standards and specifications through predefined rules. These predefined rules usually cover multiple aspects such as circuit design, constraints, and test processes, and are intended to discover and correct problems that may affect testing or fault simulation.

[0101] As an example, after the server corrects the defects of the target mask layout and obtains the defect-corrected target mask layout, it further performs a manufacturing rule check on the defect-corrected target mask layout to obtain a layout check result to ensure that the defect-corrected target mask layout still meets the design requirements.

[0102] If the layout check result indicates that the target mask layout does not have any manufacturing rule violations, the target mask layout can be directly determined as the final mask layout for subsequent production and manufacturing processes; if the layout check result indicates that the target mask layout has manufacturing rule violations, the violation area needs to be corrected. And after the correction, the manufacturing rule check is performed again until the target mask layout has no layout defects and no manufacturing rule violations, and the target mask layout is determined as the final mask layout for subsequent production and manufacturing processes.

[0103] According to this embodiment, after the target mask layout is defect-corrected and the defect-corrected target mask layout is obtained, the target mask layout is once again subjected to manufacturing rule inspection, so as to ensure that the mask layout finally obtained can meet the requirements of production and manufacturing.

[0104] As an optional embodiment, before S101, the method for correcting the mask layout may further include:

[0105] For at least one mask pattern in the target mask layout, at least one sub-resolution auxiliary pattern is added within a range where the distance from the mask pattern is less than a preset distance threshold, to obtain an updated mask layout;

[0107] S101 may specifically include:

[0108] Perform lithography rule check on the updated mask layout to obtain target layout feature information of the updated mask layout.

[0109] In this embodiment, the updated mask layout is used to represent a mask layout obtained by adding a sub-resolution auxiliary pattern to at least one mask pattern in the target mask layout.

[0110] As an example, before the lithography rule check, in order to optimize the lithography effect, at least one mask pattern in the target mask layout needs to be preprocessed.

[0111] Specifically, the server first identifies all mask patterns from the target mask layout. Then, for mask patterns with poor exposure effects, sub-resolution auxiliary patterns are added. Sub-resolution auxiliary patterns are usually tiny auxiliary patterns that do not form actual circuit patterns. Their function is to improve the image contrast during the lithography process and reduce pattern deformation caused by diffraction and interference effects. The location and size of the sub-resolution auxiliary pattern are usually determined based on the lithography simulation results and process conditions.

[0112] After adding sub-resolution auxiliary patterns to each mask pattern, an updated mask layout is obtained. Finally, a lithography rule check is performed on the updated mask layout.

[0113] Through this embodiment, a sub-resolution auxiliary pattern is added to the mask pattern in the target mask layout, thereby improving the image contrast in the photolithography process and enhancing the exposure effect of the mask pattern.

[0114] A processing method based on the modified mask layout. Accordingly, the present application also provides a specific embodiment of a processing device for the mask layout.

[0115] like Figure 4 As shown, the mask layout processing device 400 provided in the embodiment of the present application includes a layout checking module 410 , a strategy determining module 420 and a layout correcting module 430 .

[0116] The layout checking module 410 is used to perform a lithography rule check on the target mask layout to obtain target layout feature information of the target mask layout, where the layout feature information includes layout defect information and surrounding environment information of the layout defect;

[0117] A strategy determination module 420 is used to process the target layout feature information through a defect correction model to obtain a target defect correction strategy for the target mask layout, wherein the defect correction model is a model obtained by fine-tuning the large model according to the historical layout feature information and the corresponding historical defect correction strategy;

[0118] The layout correction module 430 is used to perform defect correction on the target mask layout based on the target defect correction strategy to obtain the defect-corrected target mask layout.

[0119] In the mask layout processing device provided in this embodiment, the historical layout feature information and the corresponding historical defect correction strategy are used to fine-tune the large model to obtain a defect correction model. After the target mask layout is checked for lithography rules and the target layout feature information of the target mask layout is obtained. It is only necessary to input the target layout feature information into the defect correction model to obtain the target defect correction strategy of the target mask layout, so as to complete the defect correction of the target mask layout according to the target defect correction strategy. In this way, the embodiment of the present application can directly determine the defect correction strategy corresponding to various layout defects through the defect correction model, thereby automatically completing the defect correction of the target mask layout. There is no need to rely on experienced engineers to correct defects, which can improve the efficiency and accuracy of defect correction.

[0120] As an optional embodiment, before processing the target layout feature information through the defect correction model to obtain the target defect correction strategy of the target mask layout, the mask layout processing device 400 may further include the following modules:

[0121] A data acquisition module is used to acquire target training data, a target large model, and a target fine-tuning algorithm. The target training data includes historical layout feature information and corresponding historical defect correction strategies;

[0122] The model training module is used to train the target large model based on historical layout feature information, historical defect correction strategies and target fine-tuning algorithms until the training stop conditions are met to obtain a defect correction model.

[0123] As an optional embodiment, the target mask layout includes a defect pattern of a bridge defect type;

[0124] The layout correction module 430 is specifically used for:

[0125] Obtaining a bridge area in a target mask layout;

[0126] A first pattern correction operation is performed on the first mask patterns in the bridge area to separate the exposure profiles between the first mask patterns to obtain a target mask layout after defect correction, wherein the first mask patterns are mask patterns connected with the exposure profiles in the bridge area.

[0127] As an optional embodiment, the target mask pattern includes a defect pattern of a necking defect type;

[0128] The layout correction module 430 is specifically used for:

[0129] Obtaining a necking region in a target mask layout;

[0130] A second graphic correction operation is performed on the second mask pattern in the necking area to obtain a target mask pattern after defect correction, wherein the second mask pattern is a mask pattern in which an exposure profile cannot be formed in the necking area, and the second graphic correction operation includes at least one of adjusting the position of the second mask pattern and enlarging the graphic size of the second mask pattern.

[0131] As an optional embodiment, the target mask layout includes a defect pattern of a sub-resolution auxiliary pattern defect type;

[0132] The layout correction module 430 is specifically used for:

[0133] Acquire an abnormal sub-resolution auxiliary pattern in the target mask layout, where the abnormal sub-resolution auxiliary pattern is a sub-resolution auxiliary pattern that forms an exposure profile in the target mask layout;

[0134] A third pattern correction operation is performed on the sub-resolution auxiliary pattern to obtain a target mask layout after defect correction, and the third pattern correction operation includes at least one of a deletion operation on the sub-resolution auxiliary pattern and an area reduction operation on the sub-resolution auxiliary pattern.

[0135] As an optional embodiment, after performing defect correction on the target mask layout based on the target defect correction strategy to obtain the defect-corrected target mask layout, the mask layout processing device 400 may further include the following modules:

[0136] The layout checking module 410 is further used to perform a manufacturing rule checking operation on the target mask layout to obtain a layout checking result;

[0137] A layout determination module, used for determining the target mask layout as the final mask layout when the layout inspection result indicates that the target mask layout does not have a manufacturing rule violation problem;

[0138] The layout determination module is also used to correct the illegal area of ​​the target mask layout when the layout inspection result indicates that the target mask layout has a manufacturing rule violation problem, until the target mask layout has no layout defects and no manufacturing rule violation problem, thereby obtaining the final mask layout.

[0139] As an optional embodiment, before performing a lithography rule check on the target mask layout and obtaining target layout feature information of the target mask layout, the mask layout processing device 400 may further include the following modules:

[0140] A layout updating module, configured to add at least one sub-resolution auxiliary pattern to at least one mask pattern in the target mask layout within a range where the distance from the mask pattern is less than a preset distance threshold, to obtain an updated mask layout;

[0141] The layout checking module 410 is specifically used for:

[0142] Perform lithography rule check on the updated mask layout to obtain target layout feature information of the updated mask layout.

[0143] Processing method based on mask layout. Accordingly, the present application also provides a specific embodiment of a processing device for mask layout.

[0144] Figure 5 A schematic diagram of the hardware structure of a mask layout processing device provided in an embodiment of the present application is shown.

[0145] The mask layout processing device may include a processor 501 and a memory 502 storing computer program instructions.

[0146] Specifically, the processor 501 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0147] The memory 502 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 502 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, the memory 502 may include a removable or non-removable (or fixed) medium. In appropriate cases, the memory 502 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 502 is a non-volatile solid-state memory.

[0148] The processor 501 reads and executes the computer program instructions stored in the memory 502 to implement any one of the mask layout processing methods in the above embodiments.

[0149] In one example, the mask layout processing device may further include a communication interface 503 and a bus 510. Figure 5 As shown, the processor 501, the memory 502, and the communication interface 503 are connected via a bus 510 and communicate with each other.

[0150] The communication interface 503 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0151] Bus 510 includes hardware, software or both, and the parts of the processing equipment of the mask layout are coupled to each other. For example, but not limitation, the bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industrial standard architecture (EISA) bus, front-end bus (FSB), hypertransport (HT) interconnection, industrial standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnect (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 510 may include one or more buses. Although the present application embodiment describes and shows a specific bus, the present application considers any suitable bus or interconnection.

[0152] In addition, in combination with the mask layout processing method in the above embodiment, the embodiment of the present application can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by the processor, any mask layout processing method in the above embodiment is implemented.

[0153] In addition, in combination with the mask layout processing method in the above-mentioned embodiments, the embodiments of the present application may provide a computer program product for implementation. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the mask layout processing method provided in any aspect of the above-mentioned embodiments of the present application.

[0154] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0155] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0156] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0157] Aspects of the present disclosure are described above with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0158] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A method for processing a mask layout, characterized in that: include: Performing a lithography rule check on a target mask layout to obtain target layout feature information of the target mask layout, wherein the layout feature information includes layout defect information and surrounding environment information of the layout defect; The target layout feature information is processed by a defect correction model to obtain a target defect correction strategy for the target mask layout, wherein the defect correction model is a model obtained by fine-tuning a large model according to historical layout feature information and corresponding historical defect correction strategies; Based on the target defect correction strategy, the target mask layout is defect-corrected to obtain a defect-corrected target mask layout.

2. The method according to claim 1, characterized in that Before the target layout feature information is processed by the defect correction model to obtain the target defect correction strategy of the target mask layout, the method further includes: Obtaining target training data, a target large model, and a target fine-tuning algorithm, wherein the target training data includes the historical layout feature information and the corresponding historical defect correction strategy; Based on the historical layout feature information, the historical defect correction strategy and the target fine-tuning algorithm, the target large model is trained until the training stop condition is met to obtain the defect correction model.

3. The method according to claim 1, characterized in that The target mask layout includes a defect pattern of a bridge defect type; The method of performing defect correction on the target mask layout based on the target defect correction strategy to obtain a target mask layout after defect correction includes: Acquire a bridge region in the target mask layout; A first graphic correction operation is performed on the first mask patterns in the bridge area to separate the exposure profiles between the first mask patterns to obtain the target mask layout after defect correction, wherein the first mask patterns are mask patterns connected with the exposure profiles in the bridge area.

4. The method according to claim 3, characterized in that The first graphics correction operation includes at least one of the following: moving each of the first mask patterns along a target direction, wherein the target direction is a direction in which the distance between the first mask patterns increases; Deleting a sub-resolution auxiliary pattern whose distance from the first mask pattern is less than a preset distance threshold, or moving the sub-resolution auxiliary pattern in a direction away from the first mask pattern so that the distance between the sub-resolution auxiliary pattern and the first mask pattern is greater than or equal to the preset distance threshold; The first distance and the second distance between each of the first mask patterns are increased, wherein the first distance is the minimum distance between the inflection points of two first mask patterns, and the second distance is the minimum distance between the inflection points of two first mask patterns and the endpoints of a line segment.

5. The method according to claim 1, characterized in that The target mask pattern includes a defect pattern of a necking defect type; The method of performing defect correction on the target mask layout based on the target defect correction strategy to obtain a target mask layout after defect correction includes: Acquire a necking region in the target mask layout; A second graphic correction operation is performed on the second mask pattern in the necking area to obtain the target mask pattern after defect correction, wherein the second mask pattern is a mask pattern that cannot form an exposure profile in the necking area, and the second graphic correction operation includes at least one of adjusting the position of the second mask pattern and enlarging the graphic size of the second mask pattern.

6. The method according to claim 1, characterized in that The target mask layout includes a defect pattern of a sub-resolution auxiliary pattern defect type; The method of performing defect correction on the target mask layout based on the target defect correction strategy to obtain a target mask layout after defect correction includes: Acquire an abnormal sub-resolution auxiliary pattern in the target mask layout, wherein the abnormal sub-resolution auxiliary pattern is a sub-resolution auxiliary pattern that forms an exposure profile in the target mask layout; A third graphic correction operation is performed on the sub-resolution auxiliary graphic to obtain the target mask pattern after defect correction, wherein the third graphic correction operation includes at least one of a deletion operation on the sub-resolution auxiliary graphic and an area reduction operation on the sub-resolution auxiliary graphic.

7. The method according to any one of claims 1 to 6, characterized in that: After performing defect correction on the target mask layout based on the target defect correction strategy to obtain the defect-corrected target mask layout, the method further includes: Performing a manufacturing rule check operation on the target mask layout to obtain a layout check result; When the layout inspection result indicates that the target mask layout does not have a manufacturing rule violation problem, determining the target mask layout as a final mask layout; When the layout inspection result indicates that the target mask layout has a manufacturing rule violation problem, the violation area of ​​the target mask layout is corrected until the target mask layout has no layout defects and no manufacturing rule violation problem, thereby obtaining a final mask layout.

8. The method according to any one of claims 1 to 6, characterized in that: Before performing lithography rule checking on the target mask layout to obtain target layout feature information of the target mask layout, the method further includes: For at least one mask pattern in the target mask layout, add at least one sub-resolution auxiliary pattern within a range where the distance from the mask pattern is less than a preset distance threshold, to obtain an updated mask layout; The step of performing a lithography rule check on the target mask layout to obtain target layout feature information of the target mask layout includes: Performing a lithography rule check on the updated mask layout to obtain target layout feature information of the updated mask layout.

9. An electronic device, characterized in that: The device comprises: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the method for processing the mask layout as described in any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the method for processing a mask layout according to any one of claims 1 to 8 is implemented.

11. A computer program product, characterized in that When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the mask layout processing method as described in any one of claims 1 to 8.

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