A Method and Storage Medium for Linking PHY Reset with Port Reset Based on PCIe Switch

Abstract

The present invention discloses a method and storage medium for linking a port reset with a PHY reset based on a PCIe Switch, comprising: taking different linkage modes according to a reset type, wherein the reset type includes a basic reset and a hot reset; when the reset type is a basic reset: a port reset processing module latches the basic reset, and maps the basic reset into a corresponding port reset according to ports contained in a domain; the port reset is sent to a PHY reset processing module for PHY reset; a PCIe port controller performs a corresponding reset when receiving the reset; when the reset type is a hot reset: a hot reset signal is output to a PCIe switch module reset processing module; the PCIe switch module reset processing module converts the hot reset signal into a pulse valid signal, and sends the signal to the port reset processing module; the port reset processing module judges and processes the hot reset signal to form a port hot reset; the port hot reset is sent to a PHY reset processing module for PHY reset; and the PCIe port controller works normally after releasing the reset.

Description

Technical Field

[0001] The present invention relates to the PCIe field, and in particular to a method and a storage medium for linking a Port reset with a PHY reset based on a PCIe Switch. Background Art

[0002] PCI-Express (peripheral component interconnect express), referred to as PCIe, is a high-speed serial computer expansion bus standard, mainly used to expand the computer system bus data throughput and improve the communication speed of devices.

[0003] The PCIe basic reset is automatically handled by the hardware, which will reset the entire PCIe device, initialize all hardware logic related to the state machine, port status, and configuration registers in the configuration space.

[0004] PCIe Hot Reset is an In-band reset that does not use sideband signals. The PCIe device sends several TS1 Ordered Sets (where bit0 of the fifth character is 1) to the devices adjacent to its link. These TS1OS are sent simultaneously on all lanes and last for about 2ms. When the PCIe device receives a hot reset, the LTSSM enters the Recovery and Hot Reset state, then returns to the Detect state, and restarts the link initialization training. All state machines, hardware logic, port states, and registers in the configuration space (except Sticky bits) of the PCIe device will be initialized to the default state.

[0005] Conventional PCIe reset only processes the reset release sequence of Port reset and PHY reset during power-on initialization, and does not perform special processing on Port reset and PHY reset during operation. Summary of the invention

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention discloses a method for linking a PHY reset with a Port reset based on a PCIe Switch, comprising:

[0007] Different linkage modes are adopted according to the reset type, which includes basic reset and hot reset;

[0008] When the reset type is base reset:

[0009] The port reset processing module latches the basic reset and maps it to the corresponding port reset according to the ports included in the domain;

[0010] Send the Port reset to the PHY reset processing module for PHY reset;

[0011] When the PCIe Port controller receives a reset, it performs the corresponding reset;

[0012] When the reset type is a warm reset:

[0013] Output the warm reset signal to the reset processing module of the PCIe Switch module;

[0014] The reset processing module of the PCIe Switch module converts the warm reset signal into a pulse-valid signal and sends it to the Port reset processing module;

[0015] The Port reset processing module judges and processes the warm reset signal to form a Port warm reset;

[0016] Send the Port warm reset to the PHY reset processing module for PHY reset;

[0017] The PCIe Port controller works normally after releasing the reset.

[0018] Furthermore, the Port reset processing module latches the basic reset and maps it to the corresponding Port reset according to the ports included in the domain, including:

[0019] The basic reset is obtained from the software configuration register Virtual Switch;

[0020] The Port reset processing module latches the VS basic reset and maps it to the corresponding Port reset according to the ports included in the Virtual Switch domain.

[0021] Furthermore, when the reset type is a basic reset, the sending the Port reset to the PHY reset processing module for PHY reset includes:

[0022] Divide the Port reset into two paths, one path is sent to the PHY reset processing module, and the other path is sent to the reset processing module of the PCIe Switch module;

[0023] The PHY reset processing module judges whether to link the PHY reset according to the basic reset linkage controller register. If the basic reset linkage controller register is valid, it generates a PHY reset.

[0024] Furthermore, when the reset type is a basic reset, the sending the Port reset to the reset processing module of the PCIe Switch module includes:

[0025] The PCIe Switch module reset processing module generates a PL reset, a TL reset, and a sticky register reset.

[0026] Further, the output of the thermal reset signal to the PCIe Switch module reset processing module includes:

[0027] When the PCIe Port controller detects an UP thermal reset or a DP thermal reset, it outputs to the PCIe Switch module reset processing module.

[0028] Further, the PCIe Switch module reset processing module converts the thermal reset signal into a pulse-valid signal and sends it to the Port reset processing module, including:

[0029] The PCIe Switch module reset processing module generates a PL reset, a TL reset, and a non-sticky register reset and maintains the reset, while converting the thermal reset into a pulse-valid signal and outputting it to the Port reset processing module.

[0030] Further, the Port reset processing module judges and processes the thermal reset signal to form a Port thermal reset, including:

[0031] If it is an UP thermal reset, the UP thermal reset is mapped to the Port thermal reset of all ports within the Virtual Switch domain where the UP thermal reset is located;

[0032] If it is a DP thermal reset, it is mapped to the thermal reset of the Port itself.

[0033] Further, the sending of the Port thermal reset to the PHY reset processing module for PHY reset includes:

[0034] The Port thermal reset is divided into two paths, one path is sent to the PHY reset processing module, and the other path is sent to the PCIe Switch module reset processing module;

[0035] The PHY reset processing module judges whether to link the PHY reset according to the thermal reset linkage controller register. If the thermal reset linkage controller register is valid, it generates a PHY reset;

[0036] At the same time, the PCIe Switch module reset processing module detects the release of the UP / DP thermal reset and releases the PL reset, TL reset, and non-sticky register reset.

[0037] On the other hand, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the above method is implemented.

[0038] By adopting the above technical solution, the linkage between Port reset and PHY reset can be achieved during the working process of PCIe, improving the convenience of use. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In combination with the accompanying drawings and with reference to the following detailed description, the above and other features, advantages and aspects of the various embodiments of the present disclosure will become more apparent. The drawings are used to better understand the solution and do not constitute a limitation to the present disclosure. In the drawings, the same or similar reference numerals denote the same or similar elements, where:

[0040] Figure 1 is a flowchart of an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

[0042] Referring to Figure 1 , an embodiment of the present invention provides a method for Port reset linked with PHY reset based on a PCIe Switch, including the following steps:

[0043] S1: Different linkage methods are adopted according to the reset type, and the reset type includes basic reset and hot reset;

[0044] S2: When the reset type is basic reset:

[0045] S21: The Port reset processing module latches the basic reset and maps it to the corresponding Port reset according to the ports included in the domain;

[0046] Specifically, it includes:

[0047] The basic reset is obtained from the software configuration register Virtual Switch;

[0048] The Port reset processing module latches the VS basic reset and maps it to the corresponding Port reset according to the ports included in the Virtual Switch domain.

[0049] S22: Send the Port reset to the PHY reset processing module for PHY reset;

[0050] Specifically, it includes:

[0051] The Port reset is divided into two paths, one is sent to the PHY reset processing module, and the other is sent to the PCIe Switch module reset processing module;

[0052] The PHY reset processing module determines whether to link the PHY reset according to the basic reset linkage controller register. If the basic reset linkage controller register is valid, a PHY reset is generated;

[0053] At the same time, the PCIe Switch module reset processing module generates a PL reset (physical layer reset), a TL reset (transition layer reset), and a sticky register reset.

[0054] S23: When the PCIe Port controller receives a reset, it performs the corresponding reset.

[0055] S3: When the reset type is a warm reset:

[0056] S31: Output the warm reset signal to the PCIe Switch module reset processing module;

[0057] Specifically include:

[0058] When the PCIe Port controller detects an UP warm reset or a DP warm reset, it outputs to the PCIe Switch module reset processing module.

[0059] Among them, the UP warm reset is a warm reset operation initiated by the upstream device of the link. In the PCIe link, the upstream device is usually a device close to the Root Complex, which is responsible for sending data from downstream devices (such as expansion cards) to the upstream (such as the CPU or the main chipset). When the upstream device needs to re-initialize the link or solve link problems, it can initiate an UP warm reset to quickly restore the link state without restarting the entire system.

[0060] The DP warm reset is a warm reset operation initiated by the downstream device of the link. Downstream devices are usually devices far from the Root Complex, such as expansion cards or endpoint devices, which receive and process data from the upstream. When the downstream device needs to re-initialize the link or solve link problems, it can initiate a DP warm reset to quickly restore the link state without restarting the entire system.

[0061] S32: The PCIe Switch module reset processing module converts the warm reset signal into a pulse valid signal and sends it to the Port reset processing module;

[0062] Specifically include:

[0063] The PCIe Switch module reset processing module generates PL reset, TL reset, and non-sticky register reset and maintains the reset, while converting the thermal reset into a pulsed valid signal and outputting it to the Port reset processing module.

[0064] S33: The Port reset processing module judges and processes the thermal reset signal to form a Port thermal reset;

[0065] Specifically, it includes:

[0066] If it is an UP thermal reset, the UP thermal reset is mapped to the Port thermal reset of all ports within the Virtual Switch domain where the UP thermal reset is located;

[0067] If it is a DP thermal reset, it is mapped to the thermal reset of the Port itself.

[0068] S34: Send the Port thermal reset to the PHY reset processing module for PHY reset;

[0069] Specifically, it includes:

[0070] The Port thermal reset is divided into two paths, one path is sent to the PHY reset processing module, and the other path is sent to the PCIe Switch module reset processing module;

[0071] The PHY reset processing module judges whether to link the PHY reset according to the thermal reset linkage controller register. If the thermal reset linkage controller register is valid, it generates a PHY reset;

[0072] At the same time, the PCIe Switch module reset processing module detects the release of the UP / DP thermal reset and releases the PL reset, TL reset, and non-sticky register reset.

[0073] S35: The PCIe Port controller works normally after releasing the reset.

[0074] The above method for realizing the linkage of the PCIe Switch Port reset and the PHY reset can also be used for the reset design of other protocols; the implementation method of the method for realizing the linkage of the PCIe Switch Port reset and the PHY reset is not only used in chip design, but also applicable to other technologies such as FPGA design, etc., and the present invention is also applicable.

[0075] An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the above method is realized.

[0076] Those skilled in the art can understand that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as the general understanding of those of ordinary skill in the art to which the present invention pertains. It should also be understood that terms such as those defined in a general dictionary should be understood to have a meaning consistent with the meaning in the context of the prior art, and will not be interpreted in an idealized or overly formal sense unless specifically defined.

[0077] For method embodiments, for the sake of simplicity of description, they are all expressed as a series of combinations of actions. However, those skilled in the art should be aware that the embodiments of the present invention are not limited by the described order of actions, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0078] From the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of the present application.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for Port reset linked to PHY reset based on PCIe Switch, characterized in that, Including: Adopt different linkage methods according to the reset type, and the reset type includes basic reset and thermal reset; When the reset type is basic reset: The Port reset processing module latches the basic reset and maps it to the corresponding Port reset according to the ports included in the domain; The Port reset is divided into two paths. One path is sent to the PHY reset processing module. The PHY reset processing module judges whether to link the PHY reset according to the basic reset linkage controller register. If the basic reset linkage controller register is valid, a PHY reset is generated. The other path is sent to the PCIe Switch module reset processing module. The PCIe Switch module reset processing module generates a PL reset, a TL reset, and a sticky register reset; The PCIe Port controller performs corresponding resets when receiving a reset; When the reset type is thermal reset: Output the thermal reset signal to the PCIe Switch module reset processing module, including: when the PCIe Port controller detects a UP thermal reset or a DP thermal reset, it outputs to the PCIe Switch module reset processing module; The PCIe Switch module reset processing module converts the thermal reset signal into a pulse-valid signal and sends it to the Port reset processing module; The Port reset processing module judges and processes the thermal reset signal to form a Port thermal reset; The Port thermal reset is divided into two paths. One path is sent to the PHY reset processing module. The PHY reset processing module judges whether to link the PHY reset according to the thermal reset linkage controller register. If the thermal reset linkage controller register is valid, a PHY reset is generated. The other path is sent to the PCIe Switch module reset processing module. The PCIe Switch module reset processing module detects the release of the UP / DP thermal reset and releases the PL reset, the TL reset, and the non-sticky register reset; The PCIe Port controller works normally after the reset is released.

2. The method according to claim 1, characterized in that The Port reset processing module latches the basic reset and maps it to the corresponding Port reset according to the ports included in the domain, including: The basic reset is obtained from the software configuration register Virtual Switch; The Port reset processing module latches the VS basic reset and maps it to the corresponding Port reset according to the ports included in the Virtual Switch domain.

3. The method according to claim 1, wherein The PCIe Switch module reset processing module converts the thermal reset signal into a pulse-valid signal and sends it to the Port reset processing module, including: The PCIe Switch module reset processing module generates a PL reset, a TL reset, and a non-sticky register reset and keeps the reset. At the same time, it converts the thermal reset into a pulse-valid signal and outputs it to the Port reset processing module.

4. The method according to claim 1, wherein The Port reset processing module judges and processes the thermal reset signal to form a Port thermal reset, including: If it is a UP thermal reset, the UP thermal reset is mapped to the Port thermal reset of all ports within the Virtual Switch domain where the UP thermal reset is located; In the case of DP hot reset, it is mapped to the hot reset of the Port itself.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method described in one of claims 1-4.

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