Electrophysiological signal processing device and processing method

Abstract

The invention relates to the technical field of brain-computer interfaces, in particular to an electrophysiological signal processing device and method. The device comprises a multi-channel time sequence signal bus which comprises a plurality of segment processing nodes and is used for unidirectionally transmitting an electrophysiological signal by taking an electrophysiological signal sampling time point as a flow synchronizing signal; the electrophysiological signal processing unit comprises an electrophysiological analog-to-digital converter interface and is used for acquiring electrophysiological signals at each segment processing node and preprocessing the electrophysiological signals; the preprocessed electrophysiological signals are unidirectionally transmitted to a post-stage segment processing node through the multi-channel time sequence signal bus for electrophysiological state analysis; and the event synchronization unit receives an external trigger event signal through a trigger line and a coding line of the event synchronization unit, determines an electrophysiological signal sampling point corresponding to a trigger event occurrence time point, and is used for carrying out marking and synchronization processing on the electrophysiological signal, so that a collection, storage and calculation integrated system is provided, and the real-time performance and synchronization precision of data processing are improved.

Description

Technical Field

[0001] The present application relates to the field of brain-computer interface technology, and more specifically, to an electrophysiological signal processing device and processing method. Background Art

[0002] Brain-computer interface includes all means to obtain brain activity, but the only mature, cheap and applicable to daily life is the brain-computer interface based on EEG. Based on EEG, it is inseparable from the EEG acquisition device, and the brain-computer interface is essentially a computationally intensive task, which requires the stable acquisition of data from the electrodes on the human head, and relatively complex algorithm calculations and instruction classification, in order to output useful control instructions or obtain the status monitoring data of the human brain.

[0003] Various technologies related to brain-computer interfaces are developing at a high speed. Currently, one of the major pain points in the practical application of brain-computer interfaces is real-time performance. Due to the strong research flavor, almost all reported brain-computer interface systems are systems such as high-performance EEG machines + high-performance PCs. The EEG machine is only responsible for amplifying and collecting EEG signals, and all other data processing processes are performed by the PC. When it comes to large amounts of data, machine learning algorithms, etc., it may be necessary to call on expensive and energy-intensive GPUs to assist in implementation. This approach has a certain scale, and the advantage is that the software algorithm can be modified arbitrarily, but the problem that PC-based systems cannot avoid is poor real-time performance.

[0004] The real-time performance of data processing is an important primary indicator of brain-computer interface applications. It contributes greatly to the final brain-computer information exchange rate (ITR) and is a key link in determining performance in some brain-computer interface paradigms with real-time feedback and human error warning. Due to the non-real-time nature of the operating system and the complexity of the hardware and software driver interface, PCs require delayed synchronization in many cases and cannot perform many tasks that require precise synchronization triggering.

[0005] In addition, if the brain-computer interface must be implemented with a high-performance computer, it will seriously limit the practical application and popularization of the brain-computer interface. Therefore, how to provide a comprehensive system that can realize all brain-computer interface acquisition, storage and calculation processes and realize the integration of acquisition, storage and calculation has become a technical problem that needs to be solved. Summary of the invention

[0006] In view of this, the present application provides an electrophysiological signal processing device and a processing method to provide an integrated acquisition, storage and computing system to improve the real-time performance and synchronization accuracy of data processing.

[0007] In a first aspect, the present application provides an electrophysiological signal processing device, comprising a multi-channel time series signal bus, an electrophysiological signal processing unit mounted on the multi-channel time series signal bus, and an event synchronization unit; The multi-channel time series signal bus includes a plurality of segment processing nodes for unidirectionally transmitting the electrophysiological signal using the electrophysiological signal sampling time point as the stream synchronization signal; The electrophysiological signal processing unit includes an electrophysiological analog-to-digital converter interface, which is used to obtain electrophysiological signals at each segment processing node and preprocess the electrophysiological signals; the preprocessed electrophysiological signals are unidirectionally transmitted to one or more segment processing nodes of the subsequent stage through the multi-channel time series signal bus for electrophysiological state analysis; The event synchronization unit is connected to the electrophysiological analog-to-digital converter interface, receives an external trigger event signal through its own trigger line and encoding line, and determines the electrophysiological signal sampling point corresponding to the time point of the trigger event.

[0008] In one possible implementation, the electrophysiological signal processing unit further includes an electrode module, a preamplifier conditioning circuit and a multi-channel analog-to-digital converter; The electrode module is used to collect electrophysiological signals; The preamplifier conditioning circuit is used to amplify and filter the collected electrophysiological signals; The multi-channel analog-to-digital converter is used to convert the collected electrophysiological signals into digital signals at a preset sampling rate, and transmit the converted electrophysiological signals to the electrophysiological analog-to-digital converter interface through the analog-to-digital converter data output bus interface.

[0009] One possible implementation manner further includes a data storage unit for intercepting the electrophysiological signal at any segment processing node for storage.

[0010] In one possible implementation, the multi-channel time series signal bus is based on programmable logic, and the transmission of electrophysiological signals between adjacent segmented processing nodes is accomplished through high-speed synchronous FIFO logic.

[0011] In one possible implementation, the event synchronization unit includes a trigger line and an external encoding line for triggering the input of an electrophysiological signal, and classifying the event type through the trigger line, the external encoding line or the event synchronization unit itself.

[0012] In one possible implementation, the event type classification is performed by the trigger line, the external encoding line or the event synchronization unit itself, including: Classify events by corresponding predefined event codes to different trigger lines; or, Input the event type through the external encoding line and latch the event type using a trigger line; The event synchronization unit is directly connected to the electrophysiological analog-to-digital converter interface block, and the acquired event information is used as a data channel for transmission and processing.

[0013] In a second aspect, the present application provides an electrophysiological signal processing method, applied to the electrophysiological signal processing device as described in any one of the first aspects, comprising: Using the sampling time point of the electrophysiological signal as a stream synchronization signal, and using a multi-channel time series signal bus to transmit the electrophysiological signal in segments; At each segment processing node, the input electrophysiological signal is preprocessed and unidirectionally transmitted to one or more segment processing nodes at the subsequent stage through the multi-channel time series signal bus to perform electrophysiological state analysis; An external trigger event signal is received, an electrophysiological signal sampling point corresponding to the time point when the trigger event occurs is determined, and the electrophysiological signal is marked and synchronously processed based on the electrophysiological signal sampling point.

[0014] In one possible implementation, the preprocessing of the input electrophysiological signal includes amplifying and filtering the collected electrophysiological signal; and converting the collected electrophysiological signal into a digital signal according to a preset sampling rate based on a multi-channel analog-to-digital converter.

[0015] Compared with the prior art, the technical solution provided by this application has the following beneficial effects: 1. It can achieve theoretically optimal real-time data processing and improve the response and control speed of the biofeedback / control brain-computer interface paradigm. Since the dedicated physical bus is designed in accordance with the principle of sequential data processing, and the effective spectrum of the electrophysiological signal itself is not wide, in theory, it is possible to output a data processing result through the bus in one data sampling interval by using large-scale circuit calculations or parallel processors (groups) with sufficient frequency; and the delay from the actual sampling point of the data to the data being used to output the processing result is only determined by how many sequential signal processing links are mounted on the bus, which can be calculated by the following formula in theory: Delay time = sampling interval time * number of signal processing links.

[0016] Since the entire data processing process does not involve any data encoding or decoding, packaging and unpacking operations, and all data is processed in a streaming manner, a large amount of communication overhead is saved; and the pure hardware design directly avoids the delay caused by the weak processing result / control information output link of the traditional brain-computer interface system, thereby improving the response and control speed.

[0017] Second, the accuracy of external event synchronization recording can reach the highest theoretical level. Since the event synchronization recording module is designed with pure digital logic circuits, a direct trigger line node is reserved, and this module is directly connected to the electrophysiological analog-to-digital converter interface module and works synchronously with the sampling beat signal of the bus, the most theoretically accurate external event synchronization recording accuracy can be achieved, and the time point recording error will not exceed one sampling time interval under the most unfavorable conditions.

[0018] 3. It can realize low-power, high-energy-efficiency, and portable data processing. Since the signal acquisition, processing, and storage systems as a whole adopt a full hardware embedded processing solution, most of the digital logic circuits and acceleration processing cores are developed and selected to adapt to electrophysiological signals. Compared with general PCs, its power consumption is extremely low. Under the premise of achieving the same computational complexity of the brain-computer interface algorithm, the system energy efficiency ratio can be greatly improved, and the size is very small, which is convenient for designing as a portable or wearable product. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the structure of an electrophysiological signal processing device provided in Example 1 of the present application.

[0020] Figure 2 A flowchart of an electrophysiological signal processing method provided in Example 2 of the present application. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0022] In view of the limitations of existing brain-computer interface technology, this application uses a large-scale modular system-level programmable logic array chip as the core to build an embedded system that integrates brain-computer interface data storage and computing, and achieves data processing capabilities comparable to PC-side in a wearable size. Below, the technical solution provided by this application is described in detail in conjunction with specific embodiments.

[0023] Embodiment 1 See also Figure 1 , is a schematic diagram of the structure of an electrophysiological signal processing device provided in Example 1 of the present application. Figure 1 As shown in , the electrophysiological signal processing device includes a channel time series signal bus 1, an electrophysiological signal processing unit 2 and an event synchronization unit 3. Based on the entire processing flow of the electrophysiological signal processing device, the input electrophysiological signal is subjected to a series of preprocessing and intermediate processing via the electrophysiological signal processing unit 2, and finally transmitted to the corresponding segmented processing node for signal feature interpretation and classification, and the processing result of the electrophysiological signal is output, forming a unidirectional transmission hardware pipeline.

[0024] The entire pipeline is led by the multi-channel time series signal bus 1, and the sampling time point of the electrophysiological signal is used as the pipeline operation beat. In the beat formed by each sampling interval, if the theoretical optimal real-time performance is to be achieved, each segment processing node needs to complete an output update of the multi-channel data processing result for signal interpretation and classification, and complete the final analysis result output.

[0025] Specifically, the multi-channel time series signal bus 1 is composed of a plurality of segmented processing nodes, each of which is responsible for a specific signal processing task, and is intended to provide an efficient hardware sequential processing architecture for electrophysiological signal processing. The core is to use the sampling time point of the electrophysiological signal as the synchronization signal of the entire bus to ensure the real-time and accuracy of data processing. The conflict-free transmission of intermediate data is achieved through a sequential arbitrator. Each processing node only includes one input and one output, and the data transmission direction is unidirectional, thereby simplifying the system design and improving the reliability of data transmission. In addition, the master node of the bus is controlled by a processor core, but the data flow does not necessarily pass through the core, which provides greater flexibility and scalability for the system. The multi-transmission capability of the segmented processing node allows the digital signal storage module to intercept the signal at any node for storage, which facilitates the later analysis and processing of the data.

[0026] During the transmission of electrophysiological signals, the sampling time point is used as the synchronization signal to ensure the synchronization of the signal between various nodes. For example, in brain wave monitoring, the electrical activity signals of different brain regions need to be accurately synchronized in order to analyze the overall functional state of the brain. In addition, the multi-channel time series signal bus 1 is based on programmable logic. The bandwidth of electrophysiological signals is limited and only one-way transmission is required. The signal transmission between adjacent segmented processing nodes is completed through high-speed synchronous FIFO logic, with low delay, high throughput and low resource consumption, thereby greatly improving the speed and stability of signal transmission, reducing delays and errors in data transmission, and meeting the needs of real-time monitoring.

[0027] Furthermore, if Figure 1As shown in , each segment processing node includes an input end and an output end, and the output end allows unidirectional multi-transmission, that is, it is sent to one or more segment processing nodes of the subsequent stage, so that different analysis processes can be used to implement the algorithm process at a certain segment processing node, and finally converge the fusion output to improve the quality of the result. In one achievable way, in response to the needs of multi-channel electrophysiological signal processing, this solution realizes efficient processing of EEG data by mounting different types of digital logic circuits, DSP circuit modules, dedicated DSP cores (groups) and high-performance general-purpose processor cores on the physical bus. This design can select the most suitable processing circuit module or dedicated processor according to different processing requirements, thereby improving the efficiency and accuracy of data processing. For example, for algorithms such as filtering and waveform segmentation, a multi-core multi-transmission sequential hard DSP core can be used for implementation; and for the interpretation model based on machine learning, the hard NPU core can be used to complete the result output. This flexible modular design enables the system to adapt to various real-time processing algorithms and methods to meet the needs of different application scenarios.

[0028] At the same time, the unidirectional multi-transmitting structure can be directly output to the data storage unit 4. The data storage unit 4 can arbitrarily select the output result of a certain segment processing node for storage. In this embodiment, the data storage unit 4 uses hardware logic and adopts a standard SDIO interface to mount a large-capacity MicroSD card (TF card) for selective storage and writing of data. The data storage unit 4 is connected to the multi-channel time series signal bus 1, and can intercept electrophysiological signals at any segment processing node for storage, providing a rich data source for later analysis and processing of data.

[0029] The electrophysiological signal processing unit 2 is responsible for preprocessing and analyzing the collected electrophysiological signals. Figure 1 As shown in , the unit includes an electrode module 21, a preamplifier conditioning circuit 22, a multi-channel analog-to-digital converter 23 and an electrophysiological analog-to-digital converter interface module 24.

[0030] The electrode module 21 is specifically used to collect EEG signals from the cerebral cortex, and the collected weak EEG signals are first transmitted to the preamplifier conditioning circuit 22. The collected EEG signals are preliminarily amplified and filtered by the preamplifier conditioning circuit 2 to improve the quality and strength of the EEG signals, and ensure that the collected EEG signals have sufficient amplitude and low noise level, thereby improving the signal processing accuracy and reliability of the entire system.

[0031] The preamplifier conditioning circuit 22 is connected to a multi-channel analog-to-digital converter 23 to send the processed EEG signal to the next stage for analog-to-digital conversion.

[0032] The multi-channel analog-to-digital converter 23 is specifically used to convert the EEG signal conditioned by the preamplifier into a digital signal at a set sampling rate, and send the digitized EEG signal through a specific data output bus interface. Optionally, the specific data output bus interface can be an SPI serial bus. Of course, other data output buses can be set according to actual conditions, and the embodiments of the present application are not specifically limited.

[0033] The electrophysiological analog-to-digital converter interface module 24 is connected to the data output bus interface of the multi-channel analog-to-digital converter 23, and is used to receive the digitized EEG signal from the multi-channel analog-to-digital converter 23. The digitized EEG signal is introduced into the system-level chip for further processing, and the event synchronization information is combined with the EEG signal, providing a basis for achieving accurate event-related analysis.

[0034] The above-mentioned event synchronization recording module 3 is specifically used to determine the electrophysiological signal sampling point corresponding to the time point of the event by receiving the external trigger event signal, so as to realize the marking and synchronous processing of the electrophysiological signal. The unit includes a trigger line and a coding line, and can classify events according to different trigger signals and codes. Specifically, the event synchronization recording module 3 is connected to the external input trigger signal buffer module through its own trigger line and coding line, so as to receive the external trigger event signal, record the electrophysiological signal sampling point corresponding to the time point of the trigger event, and transmit and process the event information as a special data channel. Figure 1 As shown in , the event synchronization recording module is connected to the electrophysiological analog-to-digital converter interface 24 to achieve the most accurate event synchronization time point recording in theory, and provide accurate time point channel data flow and event type information for subsequent processing. Specifically, the event type can be encoded and input, or the event type can be judged through different trigger lines. There are three methods for distinguishing the type of trigger events in the trigger electrical signal input unit, and the three can exist at the same time: one is to classify events by directly corresponding to predefined event codes through different trigger lines; the second is to input event types through external encoding lines and use a specific trigger line to latch event types; the third is to directly connect the event synchronization recording module to the electrophysiological analog-to-digital converter interface module, and the output data is transmitted and processed as a special data channel, and the recording frequency is consistent with the signal sampling rate, thereby ensuring the accuracy and real-time performance of event synchronization recording.

[0035] This solution focuses on recording the electrophysiological signal sampling points corresponding to the time when the trigger event occurs with the highest accuracy. The event synchronization recording module is implemented with pure logic circuits, which has the characteristics of high efficiency and low latency. The module is directly connected to the trigger electrical signal input through several trigger lines, and can respond quickly to trigger events. The trigger electrical signal input provides three methods to distinguish the types of trigger events, including pre-defined event codes corresponding to non-trigger lines, inputting event types through external coding lines, and logical judgment by the event recording module itself. These methods can be used alone or in combination to meet the event classification needs in different scenarios.

[0036] Compared with the prior art, the technical solution provided in the first embodiment of the present application has the following beneficial effects: 1. It can achieve theoretically optimal real-time data processing and improve the response and control speed of the biofeedback / control brain-computer interface paradigm. Since the dedicated physical bus is designed in accordance with the principle of sequential data processing, and the effective spectrum of the electrophysiological signal itself is not wide, in theory, it is possible to output a data processing result through the bus in one data sampling interval by using large-scale circuit calculations or parallel processors (groups) with sufficient frequency; and the delay from the actual sampling point of the data to the data being used to output the processing result is only determined by how many sequential signal processing links are mounted on the bus, which can be calculated by the following formula in theory: Delay time = sampling interval time * number of signal processing links.

[0037] Since the entire data processing process does not involve any data encoding or decoding, packaging and unpacking operations, and all data is processed in a streaming manner, a large amount of communication overhead is saved; and the pure hardware design directly avoids the delay caused by the weak processing result / control information output link of the traditional brain-computer interface system, thereby improving the response and control speed.

[0038] Second, the accuracy of external event synchronization recording can reach the highest theoretical level. Since the event synchronization recording module is designed with pure digital logic circuits, a direct trigger line node is reserved, and this module is directly connected to the electrophysiological analog-to-digital converter interface module and works synchronously with the sampling beat signal of the bus, the most theoretically accurate external event synchronization recording accuracy can be achieved, and the time point recording error will not exceed one sampling time interval under the most unfavorable conditions.

[0039] 3. It can realize low-power, high-energy-efficiency, and portable data processing. Since the signal acquisition, processing, and storage systems as a whole adopt a full hardware embedded processing solution, most of the digital logic circuits and acceleration processing cores are developed and selected to adapt to electrophysiological signals. Compared with general PCs, its power consumption is extremely low. Under the premise of achieving the same computational complexity of the brain-computer interface algorithm, the system energy efficiency ratio can be greatly improved, and the size is very small, which is convenient for designing as a portable or wearable product.

[0040] Embodiment 2 See also Figure 2 , is a flow chart of an electrophysiological signal processing method provided in Example 2 of the present application. Figure 2 As shown in , the specific implementation steps of the above method include: Step 101: Using the sampling time point of the electrophysiological signal as a stream synchronization signal, the electrophysiological signal is transmitted in segments using a multi-channel time series signal bus.

[0041] Specifically, the sampling time point of the electrophysiological signal is used as the synchronization signal source of the bus, so that each processing node can accurately complete the data processing task within each sampling interval, avoiding waiting and delay in the data processing process. The advantage of this synchronization mechanism is that it can ensure that the entire process from signal acquisition to the final result output is carried out under strict time control, thereby achieving theoretically optimal real-time performance. In addition, since the data transmission is unidirectional and the data transfer between adjacent processing nodes is completed through high-speed synchronous FIFO logic, this design not only reduces latency, but also improves data throughput, allowing the system to efficiently process large-scale EEG data. In practical applications, this means that the system can complete the analysis and processing of a large number of EEG signals in a shorter time, providing strong support for real-time monitoring of brain status or output of control instructions.

[0042] Step 102: at each segment processing node, pre-process the input electrophysiological signal, and transmit it unidirectionally to one or more segment processing nodes at the subsequent stage through a multi-channel time series signal bus for electrophysiological state analysis.

[0043] The above preprocessing includes amplifying, filtering and analog-to-digital conversion of electrophysiological signals to facilitate subsequent electrophysiological state analysis. Electrophysiological state analysis includes but is not limited to feature extraction, pattern recognition, and state monitoring and evaluation.

[0044] Step 103: Receive an external trigger event signal, determine the electrophysiological signal sampling point corresponding to the time point when the trigger event occurs, and mark and synchronously process the electrophysiological signal based on the electrophysiological signal sampling point. Specifically, the reception of event signals is a key step in achieving accurate marking and synchronization of electrophysiological signals, and its accuracy directly affects the reliability and effectiveness of subsequent signal analysis. As the main channels for receiving event signals, the design and implementation of trigger lines and coding lines are crucial. The trigger line is used to receive external trigger event signals, such as stimulus signals in experiments, response signals of subjects, etc. The design of the trigger line needs to ensure the rapid transmission and accurate identification of signals. The coding line is used to input event type information and classify and encode different event signals. The design of the coding line needs to meet the requirements of diversity and flexibility, and be able to adapt to the changes in event types under different experimental conditions. Multiple coding lines can be set up, each corresponding to a specific event code, or a multi-level coding method can be used to achieve the transmission of multiple event codes on one coding line. For example, in cognitive neuroscience experiments, coding lines can be used to distinguish different cognitive tasks or stimulus types, and through different coding combinations, event signals can be associated with corresponding cognitive processes, providing important reference information for subsequent signal analysis.

[0045] Compared with the prior art, the technical solution provided in the second embodiment of the present application has the following beneficial effects: Based on the electrophysiological signal processing method provided by the present application, the sampling time point of the electrophysiological signal is used as the flow synchronization signal, and the multi-channel time series signal bus is used to realize the segmented transmission of the electrophysiological signal, which ensures the efficient and accurate transmission of the signal between multiple processing nodes, and reduces data delay and distortion. Each segmented processing node can independently pre-process the input electrophysiological signal, including operations such as amplification, filtering and analog-to-digital conversion, which not only improves the quality of the signal, but also enhances the parallel processing capability of the system, thereby speeding up the overall analysis speed. In addition, by receiving and parsing the external trigger event signal, the electrophysiological signal sampling point corresponding to the time point of the trigger event is accurately determined, and the electrophysiological signal is marked and synchronously processed accordingly, so that the system can accurately capture key physiological events in a complex experimental environment, providing reliable data support for subsequent research. This method significantly improves the accuracy and efficiency of electrophysiological signal processing, and is suitable for real-time monitoring and analysis scenarios of various electrophysiological signals such as electrocardiograms and electroencephalograms that require high time resolution and accuracy.

[0046] Although the embodiments of the present application have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. An electrophysiological signal processing device, characterized in that: It includes a multi-channel time series signal bus, an electrophysiological signal processing unit mounted on the multi-channel time series signal bus, and an event synchronization unit; The multi-channel time series signal bus includes a plurality of segment processing nodes for unidirectionally transmitting the electrophysiological signal using the electrophysiological signal sampling time point as the stream synchronization signal; The electrophysiological signal processing unit includes an electrophysiological analog-to-digital converter interface, which is used to obtain electrophysiological signals at each segment processing node and pre-process the electrophysiological signals; The pre-processed electrophysiological signal is unidirectionally transmitted through the multi-channel time series signal bus to one or more segmented processing nodes of the subsequent stage for electrophysiological state analysis; The event synchronization unit is connected to the electrophysiological analog-to-digital converter interface, receives an external trigger event signal through its own trigger line and encoding line, determines the electrophysiological signal sampling point corresponding to the time point of the trigger event, and is used to mark and synchronize the electrophysiological signal.

2. An electrophysiological signal processing device according to claim 1, characterized in that: The electrophysiological signal processing unit also includes an electrode module, a preamplifier conditioning circuit and a multi-channel analog-to-digital converter; The electrode module is used to collect electrophysiological signals; The preamplifier conditioning circuit is used to amplify and filter the collected electrophysiological signals; The multi-channel analog-to-digital converter is used to convert the collected electrophysiological signals into digital signals at a preset sampling rate, and transmit the converted electrophysiological signals to the electrophysiological analog-to-digital converter interface through the analog-to-digital converter data output bus interface.

3. The electrophysiological signal processing device according to claim 1, characterized in that: It also includes a data storage unit for intercepting the electrophysiological signal at any segment processing node for storage.

4. The electrophysiological signal acquisition device according to claim 1, characterized in that: The multi-channel time series signal bus is based on programmable logic, and the transmission of electrophysiological signals between adjacent segmented processing nodes is completed through high-speed synchronous FIFO logic.

5. The electrophysiological signal acquisition device according to claim 1, characterized in that: The event synchronization unit includes a trigger line and an external encoding line, which are used to trigger the input of electrophysiological signals, and classify event types through the trigger line, the external encoding line or the event synchronization unit itself.

6. The electrophysiological signal acquisition device according to claim 5, characterized in that: Event types are classified by trigger line, external encoding line or event synchronization unit itself, including: Classify events by corresponding predefined event codes to different trigger lines; or, Input the event type through the external encoding line and latch the event type using a trigger line; The event synchronization unit is directly connected to the electrophysiological analog-to-digital converter interface block, and the acquired event information is used as a data channel for transmission and processing.

7. A method for processing electrophysiological signals, characterized in that: Applied to the electrophysiological signal processing device according to any one of claims 1 to 5, the method comprises: Using the sampling time point of the electrophysiological signal as a stream synchronization signal, and using a multi-channel time series signal bus to transmit the electrophysiological signal in segments; At each segment processing node, the input electrophysiological signal is preprocessed and unidirectionally transmitted to one or more segment processing nodes at the subsequent stage through the multi-channel time series signal bus to perform electrophysiological state analysis; An external trigger event signal is received, an electrophysiological signal sampling point corresponding to the time point of occurrence of the trigger event is determined, and the electrophysiological signal is marked and synchronously processed based on the electrophysiological signal sampling point.

8. The electrophysiological signal processing method according to claim 7, characterized in that: The preprocessing of the input electrophysiological signal includes amplifying and filtering the collected electrophysiological signal; and converting the collected electrophysiological signal into a digital signal according to a preset sampling rate based on a multi-channel analog-to-digital converter.

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