A control method for a memristor-based approximate adder circuit and an approximate addition operation device

Abstract

The present invention discloses a control method for an approximate adder circuit based on memristors and an approximate addition operation device, belonging to the technical field of microelectronic logic operations; by utilizing the memory-computation integrated characteristic of memristors, and by setting the carry c i+1 to be one of the three input values of a i , b i , and c i , and by synchronously applying voltages to each port of the approximate adder circuit, a majority gate logic operation after carry inversion is realized, so as to obtain the sum results s1, s2,..., s n of each bit in parallel; through the above approximate addition design, the present invention does not need to wait for the carry calculation of the previous bit, and efficiently realizes parallel multi-bit addition operations with relatively fast calculation speed; moreover, the number of devices and operation steps required by the present invention are both less, and it can realize approximate addition operations with relatively fast calculation speed under the condition of using fewer devices and operation steps, reducing the consumption of hardware resources, and especially showing significant performance improvement when processing large data streams and high-speed operations.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic logic operations, and more specifically, relates to a control method for an approximate adder circuit based on a memristor and an approximate addition operation device. Background Art

[0002] Traditional computers adopt the von Neumann architecture, in which the storage unit and the processing unit are physically separated. Usually, the processing unit reads data from the storage unit, completes the corresponding arithmetic and logical operations, and then writes the data back to the storage unit. The reading of stored information and the transportation of data streams impose huge requirements on the peripheral reading circuit and the control circuit, bring great consumption and challenges to the data transmission bus, and cause great power consumption losses. In addition, engineers usually need to adjust the speeds among the processing unit, the storage unit, and even the bus to achieve the best match and reduce the idle consumption among the units. However, this matching is very difficult to achieve, often resulting in unreasonable resource allocation and utilization among the units. Therefore, better solving the "bottleneck problem" and the "memory wall" problem existing in the existing von Neumann architecture in computers has become the research focus in the field of computer architecture.

[0003] To break through these bottlenecks, the technology of computing in memory emerged. By integrating the computing and storage functions on the same hardware platform, this technology realizes advantages such as high computing parallelism, low latency, and low power consumption, and has gradually become a research hotspot in the academic and industrial circles. As a new type of non-volatile memory device, the memristor has advantages such as low power consumption, small size, and compatibility with the CMOS process, and has become an ideal candidate device for the in-memory computing architecture. The memristor can store information by changing its resistance state and can still maintain the resistance state after power-off, so it is naturally suitable for digital logic operations.

[0004] Approximate computing is a computing paradigm that can overcome the "power wall" of computer architectures. It allows a certain error to be introduced during the computing process in exchange for an improvement in computing speed, a reduction in energy consumption, or a saving of resources. This computing method is particularly suitable for application scenarios that are not very demanding on the result accuracy but are very sensitive to the response time or cost, and is widely used in fields such as image processing, artificial intelligence, and signal processing.

[0005] The design of a memristor-based approximate adder provides a novel hardware solution by combining the advantages of in-memory computing and the flexibility of approximate computing. However, in the process of performing multi-bit addition operations with existing memristor-based approximate adders, both the calculation of the sum result and the carry output require a large amount of computing resources and time. Moreover, the calculation of the output value of the next bit depends on the carry calculation of the previous bit. If the carry calculation of the previous bit is not completed, the calculation of the output value and the carry of the current bit cannot be performed, resulting in a huge waste of resources and time loss. Summary of the Invention

[0006] In view of the above-mentioned defects or improvement requirements of the prior art, the present invention provides a control method for a memristor-based approximate adder circuit and an approximate addition operation device, aiming to achieve multi-bit approximate addition operations at a relatively fast calculation speed with fewer devices and operation steps.

[0007] To achieve the above object, in a first aspect, the present invention provides a control method for a memristor-based approximate adder circuit, which is used to realize the approximate addition of an n-bit number a = a n ......a2a1 and b = b n ......b2b1;

[0008] The approximate adder circuit includes: a memristor array and n identical resistors R1, R2,..., R n ; The memristor array includes a plurality of identical memristors arranged in n rows and 3 columns. The positive electrodes of the memristors in the j-th column are all connected to the bit line BL j , and the negative electrodes of the memristors in the i-th row are all connected to the word line WL i ; One end of the word line WL i is suspended, and the other end is connected to one end of R i , and the other end of R i serves as the T 4i port; The connection points between the negative electrodes of the memristors in the i-th row and the word line WL i are all located between the suspended end of the word line WL i and R i ; n≥1; j = 1, 2, 3; i = 1, 2,..., n; The resistance values of the resistors are all the same as the low-resistance state resistance values of the memristors;

[0009] The above control method includes:

[0010] Initializing the memristor array: setting all the memristors on the output column to the high-resistance state, and writing the i-th bit numbers in the first input number and the second input number correspondingly into the memristors in the i-th row of the two input columns;

[0011] Connect voltages with an amplitude of 0 to the T1 port and the T2 port respectively, and connect a fixed voltage V to the T3 port cond , and connect voltages V1, V2,..., V 41 , T 42 ,..., T 4n to the ports one by one; read the logical values s1, s2,..., s n corresponding to the resistance states of the memristors in the output column; n Take s n ...... s2s1 and c n+1 as the approximate addition result of a and b and the carry respectively;

[0012] Among them, the two input columns are two columns arbitrarily selected from the memristor array; the output column is a column not selected in the memristor array; the T1 port and the T2 port are the ports of the bit lines where the two input columns are located, and the T3 port is the port of the bit line where the output column is located; the first input number and the second input number are two numbers arbitrarily selected from a, b, c; the third input number is the number not selected from a, b, c; c = c n ...... c2c1; when the third input number is a, c i+1 = a i ; when the third input number is b, c i+1 = b i ; when the third input number is c, c i+1 = c i , c1 is the preset initial carry; if the i-th bit number in the third input number is 0, then V i = V p , otherwise, V i = 2V p ; 2V p / 3 < V cond - V set < V p , max{V p , (V p + V cond ) / 3, (2V p + V cond ) / 4} < |V reset |; V set is the threshold for the memristor to change from the high-resistance state to the low-resistance state; V reset is the threshold for the memristor to change from the low-resistance state to the high-resistance state.

[0013] Further preferably, when the third input number is c, the above approximate addition circuit further includes: a memristor M4; the positive electrode of the memristor M4 is used as the T5 port, and the negative electrode is connected to the word line WL n and the connection point is located at the floating end of the word line WL n and Rn between;

[0014] The above control method further includes an optimization operation:

[0015] Set the memristor M4 to the high-resistance state and set the T3 port to the floating state;

[0016] Apply voltages with an amplitude of 0 to the T1 port and the T2 port respectively, apply a fixed voltage V cond at the T 4n port, and apply a voltage V; Read the logical value corresponding to the resistance state of the memristor M4 as the final result of c n+1 ;

[0017] Among them, if c1 is 0, then V i =V p , otherwise, V i =2V p .

[0018] Further preferably, V cond = 2V set ; V p =1.2V set .

[0019] Further preferably, write the corresponding logical value by setting the high and low resistance states of the memristor; among them, the high resistance state of the memristor corresponds to the logical value "0", and the low resistance state corresponds to the logical value "1".

[0020] In a second aspect, the present invention provides an approximate addition operation device, including: an approximate adder circuit and a controller;

[0021] The approximate addition circuit includes: a memristor array and n identical resistors R1, R2,..., R n ; The memristor array includes a plurality of identical memristors arranged in n rows and 3 columns. The positive electrodes of the memristors in the j-th column are all connected to the bit line BL j above, and the negative electrodes of the memristors in the i-th row are all connected to the word line WL i above; One end of the word line WL i is floating, and the other end is connected to one end of R i , and the other end of R i is used as the T 4i port; The connection points of the negative electrodes of the memristors in the i-th row and the word line WL i are all located between the floating end of the word line WL i and R i ; n≥1; j = 1, 2, 3; i = 1, 2,..., n; The resistance values of the resistors are all the same as the resistance value of the low resistance state of the memristor;

[0022] The controller is used to execute the control method provided in the first aspect of the present invention.

[0023] Further preferably, the above approximate addition circuit further includes: a memristor M4; the positive electrode of the memristor M4 serves as the T5 port, and the negative electrode is connected to the word line WL n and the connection point is located on the word line WL n between the floating end and R n ;

[0024] The controller is further configured to perform an optimization operation in the control method provided in the first aspect of the present invention.

[0025] Further preferably, the switching ratio of each memristor in the approximate addition circuit is greater than or equal to 100.

[0026] In a third aspect, the present invention provides a control system, including: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it executes the control method provided in the first aspect of the present invention.

[0027] In a fourth aspect, the present invention further provides a computer-readable storage medium, the computer-readable storage medium includes a stored computer program, wherein when the computer program is run by a processor, it controls the device where the storage medium is located to execute the control method provided in the first aspect of the present invention.

[0028] In a fifth aspect, the invention further provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, they implement the control method provided in the first aspect of the present invention.

[0029] Generally speaking, through the above technical solutions conceived by the present invention, the following beneficial effects can be achieved:

[0030] 1. The present invention provides a control method for an approximate addition circuit based on a memristor and a corresponding approximate addition operation device. Utilizing the memory-computation integrated characteristic of the memristor, by setting the carry c i+1 as one of the three input values of a i , b i and c i , and by synchronously applying voltages to each port of the approximate addition circuit, a majority gate logic operation after carry inversion is realized, so as to obtain the sum results s1, s2,..., s of each bit in parallel n; Through the above approximate addition design, the present invention does not need to wait for the carry calculation of the previous bit, and completes the carry calculation of all bits in the initial writing link. The calculation of the sum results of different bits can be carried out simultaneously, efficiently realizing parallel multi-bit addition operation with a relatively fast calculation speed; moreover, the number of devices and operation steps required by the present invention are both less, and it can realize approximate addition operation with a relatively fast calculation speed under the condition of using fewer devices and operation steps, reducing the consumption of hardware resources, especially showing significant performance improvement when dealing with large data streams and high-speed operations.

[0031] 2. Further, in the control method of the approximate addition circuit based on memristor and the corresponding approximate addition operation device provided by the present invention, when the third input number is c, by setting the memristor M4 to a high impedance state and setting the T3 port to a floating state; voltages with an amplitude of 0 are respectively connected to the T1 port and the T2 port, and a fixed voltage V cond , is connected to the T 4n port, and a voltage V is connected to the port, so that the carry c n+1 = a n b n is obtained in the memristor M4 as the final result of c n+1 ; Through the above operations, the accuracy of n-bit approximate calculation can be further improved.

[0032] 3. Further, in the control method of the approximate addition circuit based on memristor provided by the present invention, V cond = 2V set ; V p = 1.2V set . In the present invention, the results generated by majority logic calculation are stored in the resistance states of the memristors in the output column. Selecting the above two voltage values can make the change windows of the resistance states of the memristors in the output column caused by different inputs roughly the same, so as to more accurately realize the change of the resistance states of the memristors in the output column, and further improve the calculation accuracy.

[0033] 4. Further, in the control method of the approximate addition circuit based on memristor and the corresponding approximate addition operation device provided by the present invention, the switching ratio of each memristor in the approximate addition circuit is greater than or equal to 100. The switching ratio of the memristor directly affects the change window of the resistance state of the memristor in the output column. The larger the switching ratio, the larger the change window of the resistance state of the memristor in the output column. When the switching ratio is greater than or equal to 100, the memristors in the output column can more accurately realize the change of the resistance state, thereby further improving the calculation accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 FIG. is a schematic structural diagram of an approximate addition circuit provided by the present invention.

[0035] Figure 2 Schematic diagram of a gate-level and modular n-bit approximate adder when the third input number is b provided in Embodiment 1 of the present invention.

[0036] Figure 3 Schematic diagram of a gate-level and modular n-bit approximate adder when the third input number is c provided in Embodiment 2 of the present invention.

[0037] Figure 4 Schematic diagram of the structure of an approximate adder circuit when the third input number is c provided in Embodiment 2 of the present invention. Detailed implementation manners

[0038] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0039] To achieve the above objective, in a first solution, the present invention provides a control method for an approximate adder circuit based on a memristor, which is used to implement the approximate addition of an n-bit number a = a n ......a2a1 and b = b n ......b2b1.

[0040] The exact full adder algorithm needs to obtain the output value and the carry , c i+1 = a i b i +a i c i +b i c i , which mainly includes two parts. One part is to calculate the output value (approximate addition result) s i , and the other part is to calculate the carry c i+1 . The calculations of these two parts require a large amount of computing resources and time, and the calculation of the output value of the next bit depends on the carry calculation of the previous bit. If the carry calculation of the previous bit is not completed, the calculation of the output value and the carry of the current bit cannot be performed, resulting in a huge waste of resources and time loss. The approximate calculation algorithm proposed by the present invention does not need to wait for the carry calculation of the previous bit, because in the approximate algorithm, the carry is equal to one of the three input values of the previous bit, which means that the carry calculations of all bits are completed in the initial writing process, and the output values s i of different bits can be performed simultaneously. Therefore, the present invention proposes an approximate adder circuit capable of parallel calculation and its control method, which greatly improves the operation speed.

[0041] As shown Figure 1 in the figure, the approximate adder circuit includes: a memristor array and n identical resistors R1, R2,..., R n ; the memristor array includes a plurality of identical memristors arranged in n rows and 3 columns, and the positive electrodes of the memristors in the j-th column are all connected to the bit line BL j ; the negative electrodes of the memristors in the i-th row are all connected to the word line WL i ; one end of the word line WL i is suspended, and the other end is connected to one end of R i ; the other end of R i is used as the T 4i port; the connection points between the negative electrodes of the memristors in the i-th row and the word line WL i are all located between the suspended end of the word line WL i and R i ; n≥1; j = 1, 2, 3; i = 1, 2,..., n; the resistance values of the resistors are all the same as the low-resistance state resistance values of the memristors;

[0042] The above control method includes:

[0043] Initializing the memristor array: setting each memristor on the output column to the high-resistance state, and correspondingly writing the i-th bit numbers of the first input number and the second input number into the memristors in the i-th row of the two input columns;

[0044] Applying voltages with amplitudes of 0 to the T1 port and the T2 port respectively, applying a fixed voltage V cond to the T3 port, and applying voltages V1, V2,..., V 41 , T 42 ,..., T 4n to the ports one by one; reading the logic values s1, s2,..., s n corresponding to the resistance states of the memristors in the output column; n Taking s n ...... s2s1 and c n+1 as the approximate addition result of a and b and the carry respectively;

[0045] Among them, the two input columns are two columns arbitrarily selected from the memristor array; the output column is a column not selected from the memristor array; the T1 port and the T2 port are the ports of the bit lines where the two input columns are located respectively, and the T3 port is the port of the bit line where the output column is located; the first input number and the second input number are two numbers arbitrarily selected from a, b, c respectively; the third input number is the number not selected from a, b, c; c = c n ...... c2c1; when the third input number is a, c i+1 = a i ; when the third input number is b, c i+1= b i ; When the third input number is c, c i+1 = c i , where c1 is a preset initial carry, which can be 0 or 1 and is set by the user; if the i-th bit number in the third input number is 0, then V i =V p , otherwise, V i =2V p .

[0046] The principle of the above logical operation is that the resistance values of the memristors on the same row of the two input columns and the voltage value applied to the word line of that row affect the voltage of the lower electrode of the memristor on the output column of that row; if the voltage of the lower electrode is too small, the resistance state of the memristor changes from the high-resistance state to the low-resistance state, resulting in the output value "1"; otherwise, the resistance state of the memristor remains the high-resistance state and the output value is "0".

[0047] It should be noted that in order to make the memristors on the output column undergo correct resistive switching, the following conditions need to be met: 2V p / 3 < V cond -V set < V p ; In order to ensure that the information of the input memristors will not be damaged during the entire process of logical operation, the following conditions need to be met: max{V p ,(V p +V cond ) / 3, (2V p +V cond ) / 4} < |V reset |; where V set is the threshold value for the memristor to change from the high-resistance state to the low-resistance state; V reset is the threshold value for the memristor to change from the low-resistance state to the high-resistance state.

[0048] It should be noted that the approximate addition circuit control method proposed by the present invention significantly improves the operation speed while reducing the precision to an acceptable level by jointly optimizing the carry c i+1 and the output value s i . In the present invention, the carry c i+1 is equal to one of the three input values of the previous bit, and the output value s i is equal to the result of performing a one-step majority gate logic on the other two input values and the inverse of the output carry. Depending on the different input values selected by the carry c i+1 , this approximate addition has three expressions, including type A, type B, and type C:

[0049] In type A, the expression of the approximate addition is:

[0050]

[0051] Under type B, the expression of approximate addition is as follows:

[0052]

[0053] Under type C, the expression of approximate addition is as follows:

[0054]

[0055] As shown in Table 1, the truth tables of exact addition and approximate addition (type A, type B, and type C) are presented (taking the preset initial carry c1 = 0 as an example).

[0056]

[0057] For type A, the carry c i+1 = a i , and the carry of each bit is completed when it is written at the beginning without waiting for consumption. Each bit directly starts to calculate the output value s i , and only one-step majority gate logic calculation is required. As shown in Table 1, compared with exact addition, the error rate of the output value of the approximate addition operation at this time is 2 / 8, and the carry error rate is 6 / 8. The error rate is very low, and it is quite practical and efficient compared with the improved speed and saved area.

[0058] For type B, the carry c i+1 = b i , and the carry of each bit is completed when it is written at the beginning without waiting for consumption. Each bit directly starts to calculate the output value s i , and only one-step majority gate logic calculation is required. As shown in Table 1, compared with exact addition, the error rate of the output value of the approximate addition operation at this time is 2 / 8, and the carry error rate is 6 / 8. The error rate is very low, and it is quite practical and efficient compared with the improved speed and saved area.

[0059] For type C, as shown in Table 1, compared with exact addition, the error rate of the output value of the approximate addition operation at this time is 4 / 8, and the carry error rate is 2 / 8. The carry c i+1 = c i . Apparently, this type still needs to wait for the carry of the previous bit. However, after direct iteration, c i+1 = c i , c i = c i-1 ,..., c2 = c1. And in this embodiment, c1 = 0, so it can be found that c n+1 = c n = c n-1 =…=c2 = c1 = 0. Therefore, the calculation of the output value s i also degenerates into si = a i + b i , the operation becomes simpler, and the truth table can also be correspondingly simplified from Table 1 to Table 2. It can be seen from Table 2 that when the approximate algorithm starts to iterate, compared with the exact addition, the error rate of the output value of the approximate addition is 2 / 8, and the carry error rate is 2 / 8. The error rate is reduced by 50%, which can be accepted compared with the improved speed and the saved area.

[0060]

[0061] In an alternative embodiment, when the third input number is c, the carry c of the last step can be made n+1 = a n b n to further improve the accuracy of the n-bit approximate calculation. The carry c n+1 is also determined by only two input quantities and is also a parallel calculation. Specifically, the above approximate addition circuit further includes: a memristor M4; the positive electrode of the memristor M4 is used as the T5 port, and the negative electrode is connected to the word line WL n and the connection point is located between the floating end of the word line WL n and R n ;

[0062] The above control method further includes:

[0063] Setting the memristor M4 to a high resistance state and setting the T3 port to a floating state; among them, the nth row memristors in the two input columns respectively store a n and b n ;

[0064] Applying voltages with amplitudes of 0 to the T1 port and the T2 port respectively, applying a fixed voltage V cond to the T5 port, and applying a voltage V to the T 4n port; reading the logical value corresponding to the resistance state of the memristor M4 as the final result of c n+1 ;

[0065] Among them, if c1 is 0, then V i =V p , otherwise, V i =2V p .

[0066] In an alternative embodiment, V cond = 2V set ; V p =1.2V set .

[0067] In an alternative embodiment, corresponding logical values are written by setting the high and low resistance states of the memristor; wherein, the high resistance state of the memristor corresponds to the logical value "0", and the low resistance state corresponds to the logical value "1".

[0068] In an alternative embodiment, the switching ratio of each memristor in the above approximate adder circuit is greater than or equal to 100.

[0069] To further illustrate the control method of the approximate adder circuit based on memristors provided by the present invention, it is described in detail with specific embodiments as follows:

[0070] Embodiment 1

[0071] In this embodiment, taking the third input number as b, at this time c i+1 = b i , c = b n-1 ......b1c1, and the schematic diagrams of the gate-level and modular n-bit approximate adder corresponding thereto are as Figure 2 shown.

[0072] The control method of the approximate adder circuit includes:

[0073] Initializing the memristor array: setting each memristor on the output column to the high resistance state, and correspondingly writing a i and c i (i.e., b i-1 ) in the i-th row memristors of the two input columns;

[0074] Connect voltages with an amplitude of 0 to the T1 port and the T2 port respectively, connect a fixed voltage V cond to the T3 port, and connect voltages V1, V2,..., V 41 , T 42 ,..., T 4n to the T n ports one by one; read the logical values s1, s2,..., s n corresponding to the resistance states of each memristor in the output column; and use s n ......s2s1 and c n+1 = b n as the approximate addition result of a and b and the carry respectively.

[0075] Embodiment 2

[0076] In this embodiment, taking the third input number as c, presetting the initial carry c1 = 0, and the carry c n+1 = a n b n as an example, at this time c i+1 = c i , c n+1 = cn = c n-1 = … = c2 = c1, and the schematic diagrams of the corresponding gate - level and modular n - bit approximate adder are as follows Figure 3 as shown

[0077] As Figure 4 shown, the approximate addition circuit in this embodiment includes a total of 3n + 1 memristors and n resistors R1, R2,..., R n ; Taking the first two columns in the memristor array as input columns and the third column as the output column; The bit line where the first - column memristors are located is BL1, and the memristors in the first column are respectively denoted as M 11 , M 21 ,..., M n1 ; The bit line where the second - column memristors are located is BL2, and the memristors in the second column are respectively denoted as M 12 , M 22 ,..., M n2 ; The bit line where the third - column memristors are located is BL3, and the memristors in the third column are respectively denoted as M 13 , M 23 ,..., M n3 ; The word lines where the memristors in each row are located are respectively denoted as WL1, WL2,..., WL n . The approximate addition circuit further includes a memristor M4. The positive electrode of the memristor M4 is connected to the bit line BL4, and the negative electrode is connected to the word line WL n and the connection point is located between the floating end of the word line WL n and R n .

[0078] The control method of the above - mentioned approximate addition circuit includes:

[0079] Writing a1, a2,..., a n one - to - one into the memristors M 11 , M 21 ,..., M n1 , writing b1, b2,..., b n one - to - one into the memristors M 12 , M 22 ,..., M n2 , where "1" corresponds to the low - resistance state of the memristor and "0" corresponds to the high - resistance state of the memristor;

[0080] Applying voltage values 0, 0, V cond respectively at the ports of BL1, BL2, and BL3, and applying voltage value V n at the WL1, WL2,..., WL p ends simultaneously, then the majority - gate logic operation with the negation function can be realized for n bits simultaneously. At M 13 , M23 ,...,M n3 the sum results s1, s2,..., s are obtained n ; among them, the majority gate logic operation with an inversion function implemented for the i-th bit is .

[0081] Voltage values 0, 0, V are respectively applied to the ports of BL1, BL2, and BL4 cond ; no voltage is applied to the BL3 terminal, and it is in a floating state. At WL n a voltage value of 2V is applied to the terminal p , and according to the configurations of the memristors M n1 and M n2 , the voltage of the lower electrode of the memristor M4 is changed, so that the resistance state of the memristor M4 can be changed, serving as the calculation result c n+1 =a n b n .

[0082] The approximate adder circuit and its control method provided by the present invention can quickly implement the parallel operation of n-bit approximate addition, while saving area and reducing resource waste, and greatly improving the operation speed. In practical applications, a hybrid n-bit adder that combines approximate addition and exact addition is often used to comprehensively improve the circuit calculation speed and accuracy. The approximate adder is used for 1 to k bits, and the exact adder is used for k + 1 to n bits. Specifically, for the case where the high resistance R H of the memristor is 100 KΩ and the low resistance R L is 1 KΩ, the fixed-value resistor R is 1 KΩ.

[0083] As shown in Table 3, the power consumption of the logic proposed by the present invention is simulated and analyzed, and the overall power consumption of the n-bit hybrid full adder is analyzed. It can be seen from Table 3 that the speed and power consumption of the hybrid full adder are greatly improved in the case of power consumption compromise.

[0084]

[0085] Taking an 8-bit full adder as an example, the evaluation indexes of the algorithm of the hybrid full adder are simulated and analyzed, and the results in Tables 4 and 5 are obtained. It can be seen from Tables 4 and 5 that the calculation accuracy of the hybrid full adder provided by the present invention is within an acceptable range.

[0086]

[0087]

[0088] In summary, the present invention relates to an approximate adder circuit based on memristors and its control method, which can solve the problems of low speed, large area, and high power consumption existing in traditional adders for high-digit additions. By utilizing the in-memory computing characteristic of memristors, parallel addition operations can be effectively achieved. This circuit significantly improves the calculation speed and reduces the consumption of hardware resources by optimizing the calculation of carry and output values. Based on the high and low resistance state storage function of memristors, the present invention realizes a more efficient parallel addition operation through approximate addition operation control, especially showing a significant performance improvement when dealing with large data streams and high-speed operations. In addition, a hybrid n-bit adder that combines the precision and approximation of the adder structure can effectively save power consumption and area while improving the calculation speed. Through simulation analysis and experimental verification, the present invention shows high speed and low power consumption in the application of approximate adders.

[0089] In a second aspect, the present invention provides an approximate addition operation device, including: an approximate adder circuit and a controller;

[0090] The approximate adder circuit includes: a memristor array and n identical resistors R1, R2,..., R n ; The memristor array includes a plurality of identical memristors arranged in n rows and 3 columns. The positive electrodes of the memristors in the j-th column are all connected to the bit line BL j ; The negative electrodes of the memristors in the i-th row are all connected to the word line WL i ; One end of the word line WL i is suspended, and the other end is connected to one end of R i ; The other end of R i serves as the T 4i port; The connection points between the negative electrodes of the memristors in the i-th row and the word line WL i are all located between the suspended end of the word line WL i and R i ; n≥1; j = 1, 2, 3; i = 1, 2,..., n; The resistance values of the resistors are all the same as the low resistance state resistance values of the memristors;

[0091] The controller is used to execute the control method provided in the first aspect of the present invention.

[0092] In an optional implementation manner, the above approximate adder circuit further includes: a memristor M4; The positive electrode of the memristor M4 serves as the T5 port, and the negative electrode is connected to the word line WL n and the connection point is located between the suspended end of the word line WL n and R n ;

[0093] The controller is further used to execute the optimization operation in the control method provided in the first aspect of the present invention.

[0094] In an alternative embodiment, the switching ratio of each memristor in the above approximate addition circuit is greater than or equal to 100.

[0095] For the related art, it is the same as the control method provided in the first aspect of the present invention, which will not be elaborated here.

[0096] In a third aspect, the present invention provides a control system, including: a memory and a processor, where the memory stores a computer program, and when the processor executes the computer program, it executes the control method provided in the first aspect of the present invention.

[0097] For the related art, it is the same as the control method provided in the first aspect of the present invention, which will not be elaborated here.

[0098] In a fourth aspect, the present invention further provides a computer-readable storage medium, where the computer-readable storage medium includes a stored computer program, and when the computer program is run by a processor, it controls the device where the storage medium is located to execute the control method provided in the first aspect of the present invention.

[0099] For the related art, it is the same as the control method provided in the first aspect of the present invention, which will not be elaborated here.

[0100] In a fifth aspect, the invention further provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, they implement the control method provided in the first aspect of the present invention.

[0101] For the related art, it is the same as the control method provided in the first aspect of the present invention, which will not be elaborated here.

[0102] Those skilled in the art can easily understand that the above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A control method for an approximate adder circuit based on a memristor, characterized in that, For realizing the approximate addition of an n-bit number a = a n ......a2a1 and b = b n ......b2b1; the approximate addition circuit includes: a memristor array and n identical resistors R1, R2,..., R n ; the memristor array includes a plurality of identical memristors arranged in n rows and 3 columns. The positive electrodes of the memristors in the j-th column are all connected to the bit line BL j ; the negative electrodes of the memristors in the i-th row are all connected to the word line WL i ; one end of the word line WL i is suspended, and the other end is connected to one end of R i ; the other end of R i serves as the T 4i port; the connection points between the negative electrodes of the memristors in the i-th row and the word line WL i are all located between the suspended end of the word line WL i and R i ; n≥1; j = 1, 2, 3; i = 1, 2,..., n; the resistance values of the resistors are all the same as the low-resistance state resistance values of the memristors; the control method includes: Initialize the memristor array: Set each memristor on the output column to the high-resistance state, and write the i-th bit of the first input number and the second input number to the corresponding memristors in the i-th row of the two input columns; Connect a voltage with an amplitude of 0 to the T1 port and the T2 port, and connect a fixed voltage V to the T3 port. cond , in T 41 ,T 42 ,...,T 4n The ports are connected to voltages V1, V2, ..., V n ; Read the logical value s1, s2, ..., s corresponding to the resistance state of each memristor in the output column n ; will s n ...s2s1 and c n+1 As the approximate addition result and carry of a and b respectively; Among them, the two input columns are two arbitrarily selected columns from the memristor array; the output column is a column not selected from the memristor array; the T1 port and the T2 port are the ports of the bit lines where the two input columns are located, and the T3 port is the port of the bit line where the output column is located; the first input number and the second input number are two arbitrarily selected numbers from a, b, and c; the third input number is the number not selected from a, b, and c; c = c n ......c2c1; when the third input number is a, c i+1 = a i ; when the third input number is b, c i+1 = b i ; when the third input number is c, c i+1 = c i , c1 is a preset initial carry; if the i-th bit number in the third input number is 0, then V i = V p , otherwise, V i = 2V p ; 2V p / 3 < V cond - V set < V p , max{V p , (V p + V cond ) / 3, (2V p + V cond ) / 4} < |V reset |; V set is the threshold for the memristor to change from the high-resistance state to the low-resistance state; V reset is the threshold for the memristor to change from the low-resistance state to the high-resistance state.

2. The control method according to claim 1, wherein V cond = 2V set ; V p =1.2V set 。 3. The control method according to claim 1, wherein Write the corresponding logical value by setting the high and low resistance states of the memristor; among them, the high-resistance state of the memristor corresponds to the logical value "0", and the low-resistance state corresponds to the logical value "1".

4. The control method according to any one of claims 1 to 3, characterized in that The approximate addition circuit further includes: a memristor M4; the positive electrode of the memristor M4 serves as the T5 port, and the negative electrode is connected to the word line WL n and the connection point is located on the word line WL n between the floating end of and R n ; When the third input number is c, the control method further includes: Set the memristor M4 to the high-resistance state and set the T3 port to the floating state; Connect voltages with an amplitude of 0 to the T1 port and the T2 port respectively, and connect a fixed voltage V to the T5 port cond , and connect voltage V to the T 4n port; Read the logical value corresponding to the resistance state of the memristor M4 as the final result of c n+1 ; Wherein, if c1 is 0, then V i =V p , otherwise, V i =2V p .

5. An approximate addition operation device, characterized in that, Include: An approximate adder circuit and a controller; The approximate addition circuit includes: a memristor array and n identical resistors R1, R2,..., R n ; The memristor array includes a plurality of identical memristors arranged in n rows and 3 columns. The positive electrodes of the memristors in the j-th column are all connected to the bit line BL j ; The negative electrodes of the memristors in the i-th row are all connected to the word line WL i ; One end of the word line WL i is suspended, and the other end is connected to one end of R i ; The other end of R i serves as the T 4i port; The connection points between the negative electrodes of the memristors in the i-th row and the word line WL i are all located between the suspended end of the word line WL i and R i ; n≥1; j = 1, 2, 3; i = 1, 2,..., n; The resistance values of the resistors are all the same as the low-resistance state resistance values of the memristors; The controller is configured to execute the control method according to any one of claims 1-3.

6. The approximate addition operation device according to claim 5, wherein The approximate addition circuit further includes: a memristor M4; the positive electrode of the memristor M4 serves as the T5 port, and the negative electrode is connected to the word line WL n thereon, and the connection point is located between the floating end of the word line WL n and R n ; The controller is further configured to execute the control method according to claim 4.

7. The approximate addition operation device according to claim 5 or 6, characterized in that The switching ratio of each memristor in the approximate adder circuit is greater than or equal to 100.

8. A control system, characterized in that, Include: A memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it executes the control method according to any one of claims 1-4.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program, wherein when the computer program is run by a processor, it controls the device where the storage medium is located to execute the control method according to any one of claims 1-4.

10. A computer program product, characterized in that, Include computer program / instructions, and when the computer program / instructions are executed by a processor, the control method according to any one of claims 1-4 is implemented.

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