VLIW compiling optimization method oriented to delay slot and hardware circulation

Abstract

The invention discloses a VLIW compilation optimization method oriented to a delay slot and hardware circulation, relates to the technical field of compilation optimization, and solves the technical problems that in a traditional scheduling method, the filling efficiency of the delay slot is low, and relatively long pipeline delay exists in the hardware circulation. According to the method, the scheduling graph is generated based on the instruction, delay slot scheduling optimization is carried out on the program through the dependency relationship of the scheduling graph, the loop resource constraint of the single loop of the program is obtained, the loop dependency constraint of the single loop of the program is obtained, and the minimum starting interval is obtained based on the loop resource constraint and the loop dependency constraint; performing software pipeline scheduling based on the minimum starting interval; according to the method, hardware resources can be fully utilized, and the instruction level parallelism degree is improved, so that the execution efficiency of the loop body is improved.

Description

Technical Field

[0001] The invention belongs to the field of computer science and relates to a compiling optimization technology, in particular to a VLIW compiling optimization method oriented to delay slots and hardware loops. Background Art

[0002] In some processor architectures, the jump instructions of the pipeline usually require multiple clock cycles to complete the determination and update of the target address. During this period, the instructions after the jump cannot be executed immediately in the pipeline, and the instruction idle state may appear. This idle period is called a delay slot. In vector computing, vector instructions are usually used to process parallel computing of batch data. These instructions require multiple clock cycles to complete the calculation and write back the results. Delay slots exist not only in control flow jump instructions, but also may appear due to the long calculation time of vector instructions. Since vector computing involves a large amount of data operations and complex hardware pipeline processes, its execution time is often longer than that of scalar instructions. In the vector computing pipeline, subsequent instructions that depend on the calculation results of vector instructions need to wait for the calculation to be completed before they can be executed. This waiting state will cause idle time in the pipeline, that is, forming a delay slot similar to the control flow jump. The appearance of such delay slots will significantly affect the overall efficiency of the processor pipeline, especially in computationally intensive tasks, when vector instructions appear frequently, and its impact on performance is more significant. In order to avoid the waste of vacant delay slots, modern compilers will try to use instruction scheduling technology to fill other non-dependent instructions near the instruction into the delay slot to improve the efficiency of instruction execution. The instructions filled into the delay slot usually need to meet the following conditions: First, there is no data dependency, and there is no data dependency between the filling instruction and the jump instruction and its target instruction. Second, control flow security, the execution of the filling instruction will not affect the control flow logic or correctness of the program.

[0003] Existing delay slot scheduling technology mainly relies on the compiler to perform linear analysis in the instruction sequence, and fill the delay slot by judging the explicit data dependency between instructions to reduce performance loss. In this method, the compiler usually starts from the target instruction, traverses the instruction sequence forward or backward, and finds instructions that can be safely executed and do not conflict with the target instruction. The implementation process of this method includes optimizing the instruction sequence by combining static analysis and heuristic rules to a certain extent, and scheduling instructions within the basic block. However, the traditional method based on linear scanning is mainly limited to the limited accuracy of dependency analysis, usually only focusing on explicit dependencies, ignoring indirect dependencies and potential control flow dependencies, which may lead to incorrect filling or invalid optimization, thereby affecting the correctness or execution efficiency of the code, and may lead to low filling efficiency when there are insufficient available instructions near the target delay slot, which may cause the delay slot to be vacant, thereby failing to effectively improve the utilization of hardware resources. In the traditional scheduling method, the delay slot filling efficiency is low and there will be long pipeline delays in the hardware loop, which may greatly affect the program execution. Traditional hardware loops often rely on static scheduling strategies, are not easy to optimize flexibly, lack support for dynamic scheduling and reordering, and often cannot adapt to changes in different loop body sizes and hardware resources, resulting in low loop execution efficiency.

[0004] Therefore, the present invention discloses a VLIW compilation optimization method oriented to delay slots and hardware loops, which is used to solve the above technical problems. Summary of the invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art; to this end, the present invention proposes a VLIW compilation optimization method for delay slots and hardware loops, which is used to solve the technical problems of low delay slot filling efficiency and long pipeline delay in hardware loops in traditional scheduling methods. The present invention generates a scheduling graph based on instructions, optimizes the delay slot scheduling of the program through the dependency relationship of the scheduling graph, obtains the loop resource constraints of a single loop of the program, and obtains the loop dependency constraints of a single loop of the program, and obtains the minimum startup interval based on the loop resource constraints and the loop dependency constraints; and performs software pipeline scheduling based on the minimum startup interval to solve the above problems.

[0006] To achieve the above object, a first aspect of the present invention provides a VLIW compilation optimization method for delay slots and hardware loops, comprising:

[0007] Traverse the instruction sequence, analyze the instructions one by one and build a scheduling unit, and generate a scheduling graph through the scheduling unit; among them, the scheduling unit is the most basic operation unit in the scheduling graph;

[0008] Optimize the delay slot scheduling of the program through the dependencies of the scheduling graph;

[0009] Obtain loop resource constraints of a single loop of the program, and obtain loop dependency constraints of a single loop of the program, obtain a minimum start interval based on the loop resource constraints and the loop dependency constraints; and perform software pipeline scheduling based on the minimum start interval.

[0010] Preferably, analyzing the instructions one by one and constructing a scheduling unit includes:

[0011] A1: The scheduler starts from the end of the basic block of the program and traverses each instruction forward, marking the instruction being traversed as the target instruction;

[0012] A2: Obtain the definition and use of registers by the target instruction. If the target instruction defines a register and a subsequent instruction uses the register, the scheduler will record that there is a data dependency between the target instruction and the corresponding instruction that uses the register.

[0013] A3: Determine whether the target instruction has a control relationship with other instructions; if yes, the scheduler will record the control dependency relationship between the target instruction and other instructions with control relationship; if no, no operation will be performed;

[0014] A4: Analyze the memory access dependencies of the target instruction and other instructions, and encapsulate each instruction into a scheduling unit. The scheduling unit contains the operands and operators of the instruction itself, and the dependencies between the instruction and other instructions. The dependencies include data dependencies, control dependencies, and memory access dependencies.

[0015] Preferably, the analysis of memory access dependencies between the target instruction and other instructions includes:

[0016] Determine whether the target instruction performs a global memory call; if yes, mark the target instruction as a memory barrier node, and prohibit reordering of other instructions across the memory barrier node; if no, do nothing;

[0017] When the target instruction is a load or store instruction, the scheduler determines whether there are other instructions accessing the address based on the address accessed by the target instruction; if so, the scheduler will record the memory access dependency between the target instruction and other instructions accessing the address; if not, no operation is performed.

[0018] Preferably, generating a scheduling graph by a scheduling unit includes:

[0019] Each scheduling unit is marked as a node, and the dependencies between the nodes are represented by directed edges; a directed acyclic graph is generated by recording the dependencies between the instructions corresponding to the nodes, and the directed acyclic graph is marked as a scheduling graph.

[0020] Preferably, the delay slot scheduling optimization of the program through the dependency relationship of the scheduling graph includes:

[0021] The scheduler starts from the first instruction of the basic block, traverses the instructions in the basic block one by one, and identifies whether there is an instruction with a delay slot in the basic block; if so, fill the delay slot through the double pointer strategy; if not, do nothing; where the basic block refers to a sequence of statements executed sequentially in the program.

[0022] Preferably, the filling of the delay slot by the dual pointer strategy comprises:

[0023] The scheduler sequentially queries the scheduling units corresponding to each instruction in the basic block to see if they have dependencies; if yes, the extracted instructions are marked as non-dependent instructions; if no, the extracted instructions are marked as dependent instructions;

[0024] The scheduler maintains pointers 1 and 2. Pointer 1 starts from the first instruction of the basic block and traverses the instructions from top to bottom. Pointer 2 starts from the first instruction containing a delay slot and points to the position where the delay slot currently needs to be filled. It fills the delay slot with independent instructions until the position where the delay slot needs to be filled by the current instruction is filled. The scheduler will select other instructions containing delay slots to continue filling the delay slots until all delay slots are filled, or stop filling the delay slots when there are no instructions that can be scheduled.

[0025] Preferably, the obtaining of the cycle resource constraints of a single cycle of the program includes:

[0026] Obtain the total instruction demand and resource concurrency capability of a single program cycle, divide the total instruction demand into several instruction packages based on the resource concurrency capability, and mark the number of instruction packages as the loop resource constraint; resource concurrency capability refers to the ability to execute multiple independent tasks or operations simultaneously.

[0027] Preferably, the obtaining of the loop dependency constraint of a single loop of the program includes:

[0028] The execution cycle of each instruction package in a plurality of instruction packages into which the total instruction demand is divided according to the resource concurrency capability is obtained, and the number of execution cycles of the instruction package with the largest number among the plurality of execution cycles is marked as a cyclic dependency constraint.

[0029] Preferably, obtaining the minimum startup interval based on the cyclic resource constraint and the cyclic dependency constraint includes:

[0030] Extract the cyclic resource constraint and the cyclic dependency constraint, and mark the number with the largest value among the cyclic resource constraint and the cyclic dependency constraint as the minimum startup interval.

[0031] Preferably, the software pipeline scheduling based on the minimum startup interval includes:

[0032] B1: Check whether the instruction list is empty; if yes, do nothing; if no, increase the start interval based on the minimum start interval and jump to B2;

[0033] B2: At each start interval, the scheduler calculates the earliest start time, the latest start time, and the start and end time of each instruction, and checks whether each instruction has a time conflict with the previous and next instructions; if yes, skip the instruction; if no, jump to B3;

[0034] B3: Check whether the scheduling scheme exceeds the maximum number of stages allowed; if yes, do not use the detected scheduling scheme and continue to try other start intervals; if no, mark the current scheduling scheme as a suitable scheduling scheme and perform software pipeline scheduling through the suitable scheduling scheme.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. The present invention generates a scheduling graph based on instructions, optimizes the delay slot scheduling of the program through the dependency relationship of the scheduling graph, obtains the loop resource constraints of a single cycle of the program, and obtains the loop dependency constraints of a single cycle of the program, and obtains the minimum start interval based on the loop resource constraints and the loop dependency constraints; performs software pipeline scheduling based on the minimum start interval, and solves the technical problems of low delay slot filling efficiency and long pipeline delay in hardware loops in traditional scheduling methods; the present invention can make full use of hardware resources, improve instruction-level parallelism, and thus improve the execution efficiency of the loop body.

[0037] 2. The present invention uses a scheduling graph algorithm to construct a directed acyclic graph to accurately represent the dependencies between instructions, including data dependencies, control dependencies, and memory access dependencies. The use of a scheduling graph can avoid incorrect filling or inefficient optimization caused by inaccurate dependency analysis in traditional methods, ensuring the correctness and security of delay slot scheduling, thereby improving the utilization of delay slots and improving overall code efficiency.

[0038] 3. The software pipeline scheduling in the present invention optimizes the execution process of the loop body through cross-iteration instruction scheduling, especially on a highly parallel architecture, improves the parallelism of the instruction set, and can significantly improve the execution efficiency of the code. The traditional loop execution method often executes each iteration in sequence, and does not give full play to the characteristics of VLIW very long instruction word instruction level parallelism, resulting in low utilization of hardware resources. Software pipeline scheduling alternately executes computing tasks in different iterations, for example, by alternately executing the loading, calculation and storage operations of two iterations, the calculation of each iteration can be parallel to the data loading of the next iteration, which reduces waiting time, makes full use of hardware resources, improves instruction level parallelism, and thus improves the execution efficiency of the loop body. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 It is a schematic diagram of the operation steps of the present invention;

[0041] Figure 2 A schematic diagram of the operation steps of constructing a scheduling unit of the present invention;

[0042] Figure 3 A schematic diagram of an instruction sequence before delay slot scheduling of the present invention;

[0043] Figure 4 It is a schematic diagram of a scheduling diagram of the present invention;

[0044] Figure 5 A schematic diagram of an instruction sequence after delay slot scheduling is performed in the present invention;

[0045] Figure 6 A schematic diagram of an instruction sequence of a single cycle of the present invention;

[0046] Figure 7 It is a schematic diagram of an instruction packet of the present invention;

[0047] Figure 8 A schematic diagram of the largest number of instruction packets in the execution cycle of the present invention;

[0048] Fig. 9 It is a C code schematic diagram of the present invention;

[0049] Fig.10 A schematic diagram of the assembly code after using hardware loop of the present invention;

[0050] Fig.11 It is a schematic diagram of the assembly code after pipeline scheduling of the application software of the present invention. DETAILED DESCRIPTION

[0051] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] See also Figure 1-Figure 2The first aspect of the present invention provides a VLIW compilation optimization method for delay slots and hardware loops, comprising:

[0053] Traverse the instruction sequence, analyze the instructions one by one and build a scheduling unit, and generate a scheduling graph through the scheduling unit; among them, the scheduling unit is the most basic operation unit in the scheduling graph;

[0054] Optimize the delay slot scheduling of the program through the dependencies of the scheduling graph;

[0055] Obtain loop resource constraints of a single loop of the program, and obtain loop dependency constraints of a single loop of the program, obtain a minimum start interval based on the loop resource constraints and the loop dependency constraints; and perform software pipeline scheduling based on the minimum start interval.

[0056] It should be noted that the compiler can rearrange the instructions based on the dependencies of the scheduling graph to optimize the execution order of the instructions and reduce pipeline stalls, namely, NOP instructions in the delay slots.

[0057] It should be noted that software pipeline scheduling is used to optimize the scheduling of hardware loops. Specifically, this method calculates the minimum start interval and performs pipeline scheduling by analyzing the dependencies of the loops to increase instruction parallelism.

[0058] It should be noted that the minimum start interval ensures that during cross-iteration scheduling, instructions in subsequent loop iterations will not be executed before the instructions in the current loop iteration are completed.

[0059] In this application, the instructions are analyzed one by one and a scheduling unit is constructed, including:

[0060] A1: The scheduler starts from the end of the basic block of the program and traverses each instruction forward, marking the instruction being traversed as the target instruction;

[0061] A2: Obtain the definition and use of registers by the target instruction. If the target instruction defines a register and a subsequent instruction uses the register, the scheduler will record that there is a data dependency between the target instruction and the corresponding instruction that uses the register.

[0062] A3: Determine whether the target instruction has a control relationship with other instructions; if yes, the scheduler will record the control dependency relationship between the target instruction and other instructions with control relationship; if no, no operation will be performed;

[0063] A4: Analyze the memory access dependencies of the target instruction and other instructions, and encapsulate each instruction into a scheduling unit. The scheduling unit contains the operands and operators of the instruction itself, and the dependencies between the instruction and other instructions. The dependencies include data dependencies, control dependencies, and memory access dependencies.

[0064] It should be noted that by abstracting instructions into scheduling units, the compiler can more clearly identify the dependencies between instructions during the scheduling process, thereby providing accurate data support for subsequent optimization.

[0065] It should be noted that for the processing of step A2, the scheduler will ensure that:

[0066] 1. Data dependency: Consumer instructions can only be executed after producer instructions;

[0067] 2. Anti-dependency: that is, the instruction that uses the register appears first, and the instruction that defines the register appears later. It is necessary to ensure that the anti-dependency is handled correctly;

[0068] 3. Output dependency: If multiple instructions define the same register at the same time, the scheduler will ensure that the order of these instructions is correct.

[0069] In this application, the memory access dependency analysis of the target instruction and other instructions includes:

[0070] Determine whether the target instruction performs a global memory call; if yes, mark the target instruction as a memory barrier node, and prohibit reordering of other instructions across the memory barrier node; if no, do nothing;

[0071] When the target instruction is a load or store instruction, the scheduler determines whether there is an address accessed by other instructions based on the address accessed by the target instruction; if so, the scheduler will record that there is a memory access dependency between the target instruction and other instructions that access the address; if not, no operation is performed.

[0072] It should be noted that marking the target instruction as a memory barrier node and prohibiting the reordering of other instructions across the memory barrier node can avoid program behavior errors.

[0073] It should be noted that reordering means that during the program execution process, the compiler adjusts the actual execution order of instructions without changing the original code semantics in order to optimize the code execution efficiency.

[0074] It should be noted that when the scheduler records the memory load and store dependencies between the target instruction and other instructions of the accessed address, for instructions accessing the same memory address, if there are storage operations among them, it will ensure that the order of these instructions is correct.

[0075] In this application, a scheduling graph is generated by a scheduling unit, including:

[0076] Each scheduling unit is marked as a node, and the dependencies between nodes are represented by directed edges; a directed acyclic graph is generated by recording the dependencies between instructions corresponding to the nodes, and the directed acyclic graph is marked as a scheduling graph.

[0077] It is worth noting that the scheduling graph provides a basis for subsequent instruction reordering to ensure that instructions are executed in the correct order.

[0078] It should be noted that the dependency between nodes is the dependency between scheduling units, which can be further understood as the dependency between instructions.

[0079] It should be noted that representing the dependency relationship between nodes through directed edges can be understood as: if the instruction corresponding to node Z1 is instruction Z1, and the instruction corresponding to node Z2 is instruction Z2, and if the data output of instruction Z1 is used by instruction Z2, then there will be a directed edge from node Z1 to node Z2 in the scheduling graph.

[0080] It should be noted that each directed edge represents a dependency, such as data dependency, control dependency, and memory access dependency, to ensure that the dependency is maintained.

[0081] It should be noted that the construction of the scheduling graph gradually fills in the dependency graph by traversing the operands, operators, and dependencies of each instruction on other instructions in the program, and finally generates a comprehensive and accurate instruction dependency structure, thus completing the detailed construction of the scheduling graph.

[0082] In this application, the delay slot scheduling of the program is optimized through the dependency relationship of the scheduling graph, including:

[0083] The scheduler starts from the first instruction of the basic block, traverses the instructions in the basic block one by one, and identifies whether there is an instruction with a delay slot in the basic block; if so, fill the delay slot through the double pointer strategy; if not, do nothing; where the basic block refers to a sequence of statements executed sequentially in the program.

[0084] It should be noted that instructions with delay slots include unconditional jump instructions and vector calculation instructions; for example, unconditional jump instructions usually cause pipeline stalls because the target address of the jump may be delayed in calculation. After the jump instruction, the processor needs two execution delay slot instructions, usually empty "NOP" instructions, to fill the gap between calculation and processing.

[0085] It should be noted that a basic block is a sequence of statements executed sequentially in a program, and its core feature is that it has a single entry and a single exit. During execution, the program can only enter from the entry and exit from the exit. This feature ensures the orderly execution of statements in a basic block, and once execution begins, it is executed in order to the end without jumping.

[0086] In this application, the delay slot is filled by a double pointer strategy, including:

[0087] The scheduler sequentially queries the scheduling units corresponding to each instruction in the basic block to see if they have dependencies; if yes, the extracted instructions are marked as non-dependent instructions; if no, the extracted instructions are marked as dependent instructions;

[0088] The scheduler maintains pointers 1 and 2. Pointer 1 starts from the first instruction of the basic block and traverses the instructions from top to bottom. Pointer 2 starts from the first instruction containing a delay slot and points to the position where the delay slot currently needs to be filled. It fills the delay slot with independent instructions until the position where the delay slot needs to be filled by the current instruction is filled. The scheduler will select other instructions containing delay slots to continue filling the delay slots until all delay slots are filled, or stop filling the delay slots when there are no instructions that can be scheduled.

[0089] It is worth noting that through the dual pointer strategy, the scheduler can process the instructions of the basic block and the instructions of the delay slot at the same time, ensuring the maximum utilization of the processor's execution resources without violating the dependencies.

[0090] It should be noted that the scheduler sequentially queries the scheduling units corresponding to each instruction in the basic block to see if they have dependencies in order to identify which instructions have no dependencies and ensure that these instructions can be safely executed without affecting the behavior of the program; for example, if instruction 3 does not depend on any instructions before the jump instruction and does not affect the control flow or data consistency after the jump, then instruction 3 can be safely inserted into the delay slot. In this case, the scheduler will fill the delay slot pointed to by the pointer with instruction 3, and advance the pointer backward to continue scheduling the next delay slot. Once the current delay slot is filled, the scheduler will check if there are other delay slots to be filled. If there are still free delay slots, the scheduler will continue to look for new non-dependent instructions to fill these delay slots. If the current instruction has no more delay slots to be filled, the scheduler will select other instructions containing delay slots to continue delay slot scheduling until all delay slots are filled and stop filling the delay slots.

[0091] For example, the instruction sequence diagram before delay slot scheduling is as follows Figure 3 ;

[0092] The schematic diagram of the scheduling diagram is as follows Figure 4,The scheduling graph diagram clearly shows the dependencies between instructions;

[0093] It should be noted that, with clear dependency relationships, the non-dependent instructions can be scheduled to the delay slot. The schematic diagram of the instruction sequence after the delay slot scheduling is as follows: Figure 5 .

[0094] In this application, the loop resource constraints for obtaining a single loop of the program include:

[0095] Obtain the total instruction demand and resource concurrency capability of a single program cycle, divide the total instruction demand into several instruction packages based on the resource concurrency capability, and mark the number of instruction packages as the loop resource constraint; resource concurrency capability refers to the ability to execute multiple independent tasks or operations simultaneously.

[0096] It should be noted that the cycle resource constraint reflects the minimum time interval required for instruction scheduling under the hardware resource constraints.

[0097] It should be noted that the total instruction demand and resource concurrency capability of a single program cycle are obtained, the total instruction demand is divided into several instruction packages according to the resource concurrency capability, and the number of instruction packages is marked as a cycle resource constraint. An example can be given as follows:

[0098] If the instruction sequence diagram of a single cycle is as follows Figure 6 ;

[0099] At this time, due to the limitations of hardware and dependencies between instructions, the total instruction demand is divided into several instruction packages according to the resource concurrency capability. Figure 7 ;

[0100] At this time, there are 4 concurrent instruction packets in a single loop, so the value of the loop resource constraint is 4.

[0101] In this application, the loop dependency constraints of a single loop of the program are obtained, including:

[0102] The execution cycle of each instruction package in a plurality of instruction packages is obtained by dividing the total instruction demand according to the resource concurrency capability, and the number of execution cycles of the instruction package with the largest number among the plurality of execution cycles is marked as a cyclic dependency constraint.

[0103] It should be noted that the loop dependency constraint reflects the restrictions on scheduling imposed by data dependencies between instructions. It depends on the dependencies across iterations in the loop and calculates the minimum startup interval of the instruction set in the loop body while considering the loop dependency constraint.

[0104] It should be noted that the loop dependency constraint can ensure that the subsequent iterations can start correctly after the previous loop iteration is completed, avoiding dependency conflicts.

[0105] It should be noted that obtaining the execution cycle of each instruction package in a plurality of instruction packages by dividing the total instruction demand into the execution cycles of each instruction package according to the resource concurrency capability and marking the number of execution cycles of the largest number of instruction packages in the plurality of execution cycles as a circular dependency constraint can be illustrated as follows:

[0106] For example, the diagram of the largest number of instruction packets in several execution cycles is as follows Figure 8 ;

[0107] The current instruction package execution cycle requires five cycles, so the value of the loop dependency constraint is 5.

[0108] In this application, the minimum startup interval is obtained based on the cyclic resource constraint and the cyclic dependency constraint, including:

[0109] Extract the cyclic resource constraints and cyclic dependency constraints, and mark the number with the largest value among the cyclic resource constraints and cyclic dependency constraints as the minimum start interval.

[0110] It is worth noting that the minimum start interval refers to the minimum time interval between each loop iteration in order to meet the resource and dependency constraints in pipeline scheduling. In simple terms, the minimum start interval ensures that each new loop iteration can start execution without conflicting with the previous iteration or resource constraints.

[0111] It should be noted that extracting the cyclic resource constraint and the cyclic dependency constraint and marking the number with the largest value in the cyclic resource constraint and the cyclic dependency constraint as the minimum start interval can be illustrated as follows:

[0112] The cyclic resource constraint is 4 and the cyclic dependency constraint is 5, and the value of the minimum start interval is 5.

[0113] In this application, software pipeline scheduling is performed based on the minimum startup interval, including:

[0114] B1: Check whether the instruction list is empty; if yes, do nothing; if no, increase the start interval based on the minimum start interval and jump to B2;

[0115] B2: At each start interval, the scheduler calculates the earliest start time, the latest start time, and the start and end time of each instruction, and checks whether each instruction has a time conflict with the previous and next instructions; if yes, skip the instruction; if no, jump to B3;

[0116] B3: Check whether the scheduling scheme exceeds the maximum number of stages allowed; if yes, do not use the detected scheduling scheme and continue to try other start intervals; if no, mark the current scheduling scheme as a suitable scheduling scheme and perform software pipeline scheduling through the suitable scheduling scheme.

[0117] It should be noted that the start interval is increased sequentially based on the minimum start interval, and is increased to the maximum start interval at most; the size of a single increase and the maximum start interval are both manually set.

[0118] It should be noted that if a legal scheduling solution is found and satisfies the resource and dependency constraints, the scheduler will complete the scheduling and return success, otherwise it will return failure. The C code diagram is as follows Fig. 9 ;

[0119] The schematic diagram of the assembly code after using the hardware loop is as follows Fig.10 ;

[0120] The schematic diagram of the assembly code after the application software pipeline scheduling is as follows Fig.11 ;

[0121] Before applying software pipeline scheduling, 100 loops were required, processing five pipelines each time. After applying software pipeline scheduling, six pipelines need to be processed each time, but only 50 loops are required, which significantly improves the execution efficiency of the loop body.

[0122] Part of the data in the above formula is calculated by removing the dimension and taking its numerical value. The formula is a formula closest to the actual situation obtained by software simulation of a large amount of collected data; the preset parameters and preset thresholds in the formula are set by technical personnel in this field according to actual conditions or obtained through simulation of a large amount of data.

[0123] Working principle of the present invention:

[0124] Traverse the instruction sequence, analyze the instructions one by one and build a scheduling unit, and generate a scheduling graph through the scheduling unit; optimize the delay slot scheduling of the program through the dependency relationship of the scheduling graph; obtain the loop resource constraints of a single cycle of the program, and obtain the loop dependency constraints of a single cycle of the program, and obtain the minimum start interval based on the loop resource constraints and loop dependency constraints; perform software pipeline scheduling based on the minimum start interval.

[0125] The above embodiments are only used to illustrate the technical method of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical method of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical method of the present invention.

Claims

1. A VLIW compilation optimization method for delay slots and hardware loops, characterized by: Traverse the instruction sequence, analyze the instructions one by one and build a scheduling unit, and generate a scheduling graph through the scheduling unit; among them, the scheduling unit is the most basic operation unit in the scheduling graph; Optimize the delay slot scheduling of the program through the dependencies of the scheduling graph; Obtain loop resource constraints of a single loop of the program, and obtain loop dependency constraints of a single loop of the program, obtain a minimum start interval based on the loop resource constraints and the loop dependency constraints; and perform software pipeline scheduling based on the minimum start interval.

2. A VLIW compilation optimization method for delay slots and hardware loops according to claim 1, characterized in that: The step of analyzing the instructions one by one and constructing a scheduling unit includes: A1: The scheduler starts from the end of the basic block of the program and traverses each instruction forward, marking the instruction being traversed as the target instruction; A2: Obtain the definition and use of registers by the target instruction. If the target instruction defines a register and a subsequent instruction uses the register, the scheduler will record that there is a data dependency between the target instruction and the corresponding instruction that uses the register. A3: Determine whether the target instruction has a control relationship with other instructions; if yes, the scheduler will record the control dependency relationship between the target instruction and other instructions with control relationship; if no, no operation will be performed; A4: Analyze the memory access dependencies of the target instruction and other instructions, and encapsulate each instruction into a scheduling unit. The scheduling unit contains the operands and operators of the instruction itself, and the dependencies between the instruction and other instructions. The dependencies include data dependencies, control dependencies, and memory access dependencies.

3. A VLIW compilation optimization method for delay slots and hardware loops according to claim 2, characterized in that: The analysis of memory access dependencies between the target instruction and other instructions includes: Determine whether the target instruction performs a global memory call; if yes, mark the target instruction as a memory barrier node, and prohibit reordering of other instructions across the memory barrier node; if no, do nothing; When the target instruction is a load or store instruction, the scheduler determines whether there are other instructions accessing the address based on the address accessed by the target instruction; if so, the scheduler will record the memory access dependency between the target instruction and other instructions accessing the address; if not, no operation is performed.

4. The VLIW compilation optimization method for delay slots and hardware loops according to claim 1, characterized in that: The generating of the scheduling graph by the scheduling unit includes: Each scheduling unit is marked as a node, and the dependencies between the nodes are represented by directed edges; a directed acyclic graph is generated by recording the dependencies between the instructions corresponding to the nodes, and the directed acyclic graph is marked as a scheduling graph.

5. The VLIW compilation optimization method for delay slots and hardware loops according to claim 1, characterized in that: The delay slot scheduling optimization of the program through the dependency relationship of the scheduling graph includes: The scheduler starts from the first instruction of the basic block, traverses the instructions in the basic block one by one, and identifies whether there are instructions with delay slots in the basic block; if yes, fill the delay slots through the double pointer strategy; if no, do nothing; where the basic block refers to a sequence of statements executed sequentially in the program.

6. The VLIW compilation optimization method for delay slots and hardware loops according to claim 5, characterized in that: The method of filling the delay slot by using a dual pointer strategy includes: The scheduler sequentially queries the scheduling units corresponding to each instruction in the basic block to see if they have dependencies; if yes, the extracted instructions are marked as non-dependent instructions; if no, the extracted instructions are marked as dependent instructions; The scheduler maintains pointer 1 and pointer 2. Pointer 1 starts from the first instruction of the basic block and traverses the instructions from top to bottom; pointer 2 starts from the first instruction containing a delay slot and points to the position where the delay slot currently needs to be filled. It fills the delay slot with independent instructions until the position where the delay slot needs to be filled by the current instruction is filled. The scheduler will select other instructions containing delay slots to continue filling the delay slots until all delay slots are filled, or stop filling the delay slots when there are no instructions that can be scheduled.

7. The VLIW compilation optimization method for delay slots and hardware loops according to claim 1, characterized in that: The obtaining of the cycle resource constraints of a single cycle of the program includes: Obtain the total instruction demand and resource concurrency capability of a single program cycle, divide the total instruction demand into several instruction packages based on the resource concurrency capability, and mark the number of instruction packages as the loop resource constraint; resource concurrency capability refers to the ability to execute multiple independent tasks or operations simultaneously.

8. The VLIW compilation optimization method for delay slots and hardware loops according to claim 1, characterized in that: The obtaining of the loop dependency constraint of a single loop of the program includes: The execution cycle of each instruction package in a plurality of instruction packages into which the total instruction demand is divided according to the resource concurrency capability is obtained, and the number of execution cycles of the instruction package with the largest number among the plurality of execution cycles is marked as a cyclic dependency constraint.

9. The VLIW compilation optimization method for delay slots and hardware loops according to claim 1, characterized in that: The obtaining of the minimum startup interval based on the cyclic resource constraint and the cyclic dependency constraint includes: Extract the cyclic resource constraint and the cyclic dependency constraint, and mark the number with the largest value among the cyclic resource constraint and the cyclic dependency constraint as the minimum startup interval.

10. The VLIW compilation optimization method for delay slots and hardware loops according to claim 1, characterized in that: The software pipeline scheduling based on the minimum startup interval includes: B1: Check whether the instruction list is empty; if yes, do nothing; if no, increase the start interval based on the minimum start interval and jump to B2; B2: At each start interval, the scheduler calculates the earliest start time, the latest start time, and the start and end time of each instruction, and checks whether each instruction has a time conflict with the previous and next instructions; if yes, skip the instruction; if no, jump to B3; B3: Check whether the scheduling scheme exceeds the maximum number of stages allowed; if yes, do not use the detected scheduling scheme and continue to try other start intervals; if no, mark the current scheduling scheme as a suitable scheduling scheme and perform software pipeline scheduling through the suitable scheduling scheme.

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