Real number vector operation processing method and device, equipment and storage medium

Abstract

The invention provides a real number vector operation processing method and device, equipment and a storage medium, and the method comprises the steps: obtaining the vector length of a to-be-operated real number vector and a preset length threshold value, and if the vector length is greater than the preset length threshold value, calculating the real number vector based on a first target instruction set of a first programming language, and if the vector length is smaller than or equal to a preset length threshold value, the real number vector and the real number constant are calculated based on a second target instruction set of a second programming language to obtain an operation result, and the level of the first programming language is lower than that of the second programming language. By adopting a hybrid programming mode, the operation performance of real number vectors and real number constants of different scales can be improved to the maximum extent. And parallel calculation of a plurality of real number elements can be realized, so that the advantage of parallel data processing of the existing register is fully utilized, and the performance of the processor is greatly improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a real number vector operation processing method, device, equipment and storage medium. Background Art

[0002] The four arithmetic operations (i.e. addition, subtraction, multiplication and division) between real vectors and constants are the most commonly used vector operations in various fields. After performing the four arithmetic operations on each element of a real vector and the constant, the operation results of each element can be used as the operation results of the real vector.

[0003] In the prior art, when performing arithmetic operations on real vectors and constants, it is necessary to use the general registers of the central processing unit (CPU) to perform serial operations. However, for a processor with high-order registers, this method cannot fully utilize the storage space of the high-order registers, thus resulting in a waste of processor resources. Summary of the invention

[0004] The purpose of this application is to provide a real number vector operation processing method, device, equipment and storage medium to address the deficiencies in the above-mentioned prior art, so as to solve the problem that the prior art cannot fully utilize the storage space of high-order registers, thereby causing waste of processor resources.

[0005] To achieve the above objectives, the technical solutions adopted in this application are as follows: In a first aspect, the present application provides a real vector operation processing method for operating a real vector and a real constant, the method comprising: Obtaining the vector length of the real number vector to be calculated and a preset length threshold; If the vector length is greater than the preset length threshold, based on a first target instruction set of a first programming language, read a real vector and a real constant from a memory, and perform operations on the real vector and the real constant to obtain an operation result; If the vector length is less than or equal to the preset length threshold, based on a second target instruction set of a second programming language, a real number vector and a real number constant are read from a memory, and operations are performed on the real number vector and the real number constant to obtain an operation result, wherein the level of the first programming language is lower than the level of the second programming language.

[0006] In a second aspect, the present application provides a real number vector operation processing device, the device comprising: An acquisition module, used to acquire the vector length of the real number vector to be calculated and a preset length threshold; A first operation module, configured to read a real vector and a real constant from a memory based on a first target instruction set of a first programming language if the length of the vector is greater than the preset length threshold, and operate on the real vector and the real constant to obtain an operation result; A second operation module is used to read a real number vector and a real number constant from a memory and operate on the real number vector and the real number constant to obtain an operation result based on a second target instruction set of a second programming language if the vector length is less than or equal to the preset length threshold, wherein the level of the first programming language is lower than the level of the second programming language.

[0007] In the third aspect, an embodiment of the present application also provides an electronic device, comprising: a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium through the bus, and the processor executes the machine-readable instructions to perform the steps of a real number vector operation processing method as described in any one of the first aspects.

[0008] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of a real number vector operation processing method as described in any one of the first aspects are executed.

[0009] The beneficial effects of the present application are: by adopting a hybrid programming approach, a high-level language is used to implement small-scale real vector operations, and a low-level language is used to implement large-scale real vectors, so that the computing performance of real vectors and real constants of different sizes can be maximized. Among them, the low-level language can directly access and process hardware resources, the instructions are more streamlined, and the generated binary code occupies less memory resources, so the storage resources of the computer system can be better utilized, thereby effectively improving the computing performance of the algorithm in the scenario of large-scale operations. In addition, the method of the present application can realize the parallel calculation of multiple real elements, thereby making full use of the advantages of existing registers in parallel processing of data and achieving a significant improvement in processor performance.

[0010] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0012] Figure 1 A flowchart of a real number vector operation processing method provided by an embodiment of the present application is shown; Figure 2 A flowchart of performing operations on real vectors and real constants based on a first target instruction set of a first programming language provided by an embodiment of the present application is shown; Figure 3 A flowchart of reading a real number element provided by an embodiment of the present application is shown; Figure 4 Another flowchart of reading real number elements provided by an embodiment of the present application is shown; Figure 5 A flowchart of storing operation results provided by an embodiment of the present application is shown; Figure 6 A flowchart of another method for storing operation results provided by an embodiment of the present application is shown; Figure 7 An overall flow chart of performing real number vector operations based on a first target instruction set provided by an embodiment of the present application is shown; Figure 8 A flowchart of performing operations on real vectors and real constants based on a second target instruction set of a second programming language provided by an embodiment of the present application is shown; Fig. 9 An overall flow chart of performing real number vector operations based on a second target instruction set provided by an embodiment of the present application is shown; Fig.10 A schematic diagram of the structure of a real number vector operation processing device provided in an embodiment of the present application is shown; Fig.11 A schematic structural diagram of an electronic device 110 provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0013] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0014] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0015] In the prior art, when performing arithmetic operations on real vectors and constants, it is necessary to use the general registers of the CPU to perform serial operations. Performing four operations of addition, subtraction, multiplication and division with a constant a includes the following steps: Step S1: Get vector from memory First element put In register D0; Step S2: store the constant alpha into register D1; Step S3: Perform addition (subtraction / multiplication / division) operations on registers D0 and D1, and save the operation results to register D2, and store the calculation results in D2 to vector On the memory associated with the first element; Step S4: Repeat step S1 and step S3 until the N elements of vector A that require four arithmetic operations are completed.

[0016] In the above calculation process, when performing four arithmetic operations on real vectors and constants, multiple loops are required. Each loop process only performs four arithmetic operations on one element of the input vector and stores the operation results in the address memory of the output vector.

[0017] However, the current register capacity is generally large. Taking the registers provided by the ARM (Advanced RISC Machine) Cortex-A series processors as an example, the length of its registers can reach up to 128 bits, that is, it can process 128 bits of data in parallel each time, and only calculate the complex convolution and four arithmetic operations of one element each time, and there will be a large number of free positions left in the register. Therefore, for processors with high-bit registers, this method cannot fully utilize the storage space of high-bit registers, and thus will also lead to a waste of processor resources.

[0018] Based on the above problems, this application proposes a real number vector operation processing method. By using different programming methods to perform four arithmetic operations on real number vectors of different dimensions, parallel calculation of elements can be achieved, and the advantage of 128-bit register width for parallel processing of data can be fully utilized to achieve processor performance improvement.

[0019] Figure 1 The flowchart of the real vector operation processing method provided in the embodiment of the present application is a schematic diagram. The execution subject of the method can be a computer device with computing processing capabilities, and a processor with a high-bit memory is deployed on the computer device. Exemplarily, the processor can be an ARM Cortex-A series processor. Figure 1 As shown, the method includes: S101. Obtain the vector length of a real number vector to be calculated and a preset length threshold.

[0020] Wherein, the real vector includes multiple elements, and the vector length can be the number of elements in the real vector. For example, a real vector with a length of N can be expressed as .

[0021] The preset length threshold can be an integer greater than 1, and the specific value is not limited here. If the number of elements of the real vector is greater than the preset length threshold, it means that the real vector has a larger dimension. At this time, the instruction set corresponding to a lower-level programming language can be used for calculation, such as based on assembly language. If the number of elements of the real vector is less than the preset length threshold, it means that the real vector has a smaller dimension. At this time, the instruction set corresponding to a higher-level programming language can be used for calculation, such as based on C language.

[0022] S102: If the vector length is greater than a preset length threshold, based on a first target instruction set of a first programming language, read a real vector and a real constant from a memory, and perform operations on the real vector and the real constant to obtain an operation result.

[0023] Optionally, when the vector length of the real number vector is greater than a preset length threshold, it indicates that the dimension of the real number vector is large. At this time, in order to improve the computing performance of the processor, the first target instruction set of the first programming language may be used for computing processing.

[0024] The first programming language may be a low-level language, such as assembly language, machine language, or symbolic language. Taking assembly language as an example, assembly code is written by using assembly language to operate on real vectors, and then the assembly code is converted into machine code by a compiler to generate an executable file. Low-level languages ​​can directly access and process hardware resources, and the instructions are more concise. The generated binary code occupies less memory, so the storage resources of the computer system can be better utilized, and the computing performance of the algorithm can be effectively improved.

[0025] The first target instruction set includes multiple instructions, and data can be read from the memory and operated by calling the instructions in the first target instruction set of the first programming language. Taking the first programming language as an assembly language as an example, the first target instruction set includes multiple assembly instructions, and the C language function provided by the NEON intrinsics instruction set can be directly mapped to the NEON instruction, and the compiler will convert it into the corresponding assembly instruction. The assembly instructions in the first target instruction set in this application can be assembly instructions converted from NEON instructions, such as the fadd instruction for adding data in two registers, the prfm pldllkeep instruction for prefetching data in the memory into the cache, the ldp instruction for storing data in the memory into the register, and the stp instruction for storing data in the register into the memory, etc.

[0026] In the present application, different instructions in the first target instruction set can be used to perform operations on real vectors and real constants, including addition, subtraction, multiplication, division, etc. Taking the addition operation of real vectors and real constants as an example, each element of the real vector can be added to the real constant, and the result of the addition can be used as the operation result.

[0027] S103. If the vector length is less than or equal to a preset length threshold, based on a second target instruction set of a second programming language, real vectors and real constants are read from a memory, and operations are performed on the real vectors and real constants to obtain operation results, wherein the level of the first programming language is lower than the level of the second programming language.

[0028] The second programming language may be a high-level language, such as C, C++, Java, Python, etc.

[0029] Optionally, when the vector length of the real number vector is less than a preset length threshold, it indicates that the dimension of the real number vector is small. At this time, in order to improve the computing performance of the processor, a second target instruction set of a second programming language may be used for computing processing.

[0030] It should be noted that when running an executable file, both high-level languages ​​and low-level languages ​​will call the compiler for optimization. For large-scale data, the code written in a low-level language has higher performance after being optimized by the compiler. Small-scale data has higher performance after being optimized by the compiler. Taking C language as an example, when the scale of data is small, the code written in C language is optimized by the compiler again after self-optimization, which can effectively improve the computing performance of the algorithm. Therefore, in this application, a hybrid programming method is adopted for large-scale data and small-scale data, which can effectively improve the computing performance of the algorithm as a whole.

[0031] The second target instruction set includes a plurality of instructions, and data can be read from the memory and operated by calling the instructions in the second target instruction set of the second programming language. Taking the second programming language as an assembly language as an example, the first target instruction set includes instructions in the NEON intrinsics instruction set, such as the vaddq_f32 instruction for adding data in two registers, the vld1q_f32 instruction for storing data in the memory into the register, and the vst1q_f32 instruction for storing data in the register into the memory.

[0032] In the present application, different instructions in the second target instruction set can be used to perform operations on real vectors and real constants, including addition, subtraction, multiplication, division, etc. Taking the addition operation of real vectors and real constants as an example, each element of the real vector can be added to the real constant, and the result of the addition can be used as the operation result.

[0033] In an embodiment of the present application, the vector length of the real vector to be calculated and a preset length threshold are obtained. If the vector length is greater than the preset length threshold, the real vector and the real constant are read from the memory based on the first target instruction set of the first programming language, and the real vector and the real constant are calculated to obtain a calculation result. If the vector length is less than or equal to the preset length threshold, the real vector and the real constant are read from the memory based on the second target instruction set of the second programming language, and the real vector and the real constant are calculated to obtain a calculation result, wherein the level of the first programming language is lower than the level of the second programming language.

[0034] By adopting a hybrid programming approach, high-level languages ​​are used to implement small-scale real vector operations, and low-level languages ​​are used to implement large-scale real vector operations, so that the computing performance of real vectors and real constants of different sizes can be maximized. Among them, low-level languages ​​can directly access and process hardware resources, instructions are more streamlined, and the generated binary code occupies less memory resources, so the storage resources of the computer system can be better utilized, thereby effectively improving the computing performance of the algorithm in the scenario of large-scale operations. In addition, the method of the present application can realize the parallel calculation of multiple real elements, thereby making full use of the advantages of existing registers in parallel processing of data and achieving a significant improvement in processor performance.

[0035] The following is a further explanation of the first target instruction set based on the first programming language, reading real vectors and real constants from the memory, and performing operations on the real vectors and real constants to obtain operation results, such as Figure 2 As shown, the above step S102 includes: S201. Read a real number constant from a memory, copy the real number constant based on a first target instruction set to obtain a plurality of real number constants, and store the copied plurality of real number constants in a constant register.

[0036] Optionally, the real constant may be read from the memory using an instruction in the first target instruction set, and the real constant may be copied multiple times and stored in a constant register using an instruction in the first target instruction set.

[0037] S202. Read 2M real number elements in the real number vector based on the first target instruction set, and store the real number elements in a first register, a second register, a third register, and a fourth register in sequence, where M is an integer greater than 0.

[0038] In the first implementation method, instructions in the first target instruction set can be used to directly read 2M real number elements from the memory, and the read real number elements are stored in the first register, the second register, the third register and the fourth register in the order of reading, and the number of real number elements stored in each register is the same.

[0039] In the second implementation method, 2M real number elements can be read from the memory using instructions in the first target instruction set, and N real number elements can be pre-fetched from the memory using instructions in the first target instruction set, and the pre-fetched real number elements can be saved in the cache. The next time the real number elements are read, they can be read directly from the cache.

[0040] In the third implementation method, each time a real number element is read, M real number elements can be read from the memory using instructions in the first target instruction set, and M real number elements can be pre-fetched from the memory into the cache using instructions in the first target instruction set, that is, 2M real number elements are read from the memory each time, and the first M elements are stored in the first register, the second register, the third register, and the fourth register in the order of reading.

[0041] Exemplarily, assuming that the real number vector is of single-precision float type, taking the 128-bit register processing process of the ARM Cortex-A series processor as an example, 16 real number elements can be read each time, and 16 real number elements can be pre-fetched, and the first 16 real number elements read are stored in the register in the order of reading, and the pre-fetched real number elements are saved in the cache, 4 elements are stored in each register, and 4 copies of the real number constant can be stored in register D0.

[0042] S203, based on the first target instruction set, respectively operate the real constant in the constant register and the real elements in the first register, the second register, the third register and the fourth register, and store the operation results in the associated memory of the real vector.

[0043] Repeat steps S202-S203 until the operation on all real number elements in the real number vector is completed, and the operation result in the associated memory is used as the operation result of the real number vector and the real number constant.

[0044] Optionally, the real constant in the constant register is operated with the real elements in the first register, the second register, the third register, and the fourth register respectively using instructions in the first target instruction set, and the operation results of the real elements in each register and the real constant can be obtained. Then, the operation results can be stored in the associated memory of the real vector using instructions in the first target instruction set.

[0045] When storing the operation result in the associated memory of the real number vector, the operation result of each real number element and the real number constant may be stored in the associated memory of the real number vector in the order of each real number element.

[0046] It should be noted that when the number of elements of the real number vector is large, the above steps S202-S203 may need to be executed multiple times. After the calculation result of the last real number element of the real number vector is stored in the associated memory of the real number vector, the calculation result in the associated memory can be used as the calculation result of the real number vector and the real constant.

[0047] It should be understood that, in addition to the above steps S201-S203, the operation on the real vector and the real constant based on the first target instruction set of the first programming language may also include other implementations. In one possible implementation, the real constant may be read from the memory based on the first target instruction set, and the real elements in the real vector may be read in sequence, the real constant and the real elements currently read may be operated on to obtain the operation result, and the operation result may be stored in the associated memory of the real vector in the order of the read real elements.

[0048] The following is a further description of the second implementation method of reading 2M real number elements in the real number vector based on the first target instruction set. Figure 3 As shown, the above step S202 includes: S301. If the current loop is the first one, 2M real number elements in the real number vector are read from the memory based on the first target instruction set, and the first N real number elements of the unread elements in the memory are pre-fetched into the cache, where N is an integer greater than 0.

[0049] Optionally, when reading a real number element from the memory for the first time, instructions of the first target instruction set can be used to read 2M real number elements of the real number vector from the memory in sequence from front to back, and starting from the 2M+1th element, instructions in the first target instruction set can be used to prefetch N consecutive real number elements into the cache.

[0050] Wherein, N is an integer greater than 0, and N can also be set to an integer multiple of 2M, thereby reducing the number of times real elements are read from the memory, and subsequently the real elements are directly read from the cache, further improving the performance of the algorithm operation.

[0051] S302: If the current loop is not the first round and the number of unread elements in the cache is greater than or equal to 2M, read the first 2M real number elements of the unread elements from the cache based on the first target instruction set.

[0052] Optionally, after the first round of reading real number elements and pre-fetching real number elements into the cache, the real number elements can be directly read from the cache in each subsequent loop process. Before each reading of the real number elements in the cache, the number of unread real number elements in the cache can be compared with the number to be read. If the number to be read 2M is less than the number of unread real number elements in the cache, the instructions in the first target instruction set can be used to read the first 2M real number elements of the unread elements from the cache.

[0053] S303: If the current loop is not in the first round and the number of unread elements in the cache is less than 2M, read the first 2M real number elements of the unread elements from the memory based on the first target instruction set, and pre-fetch the first N real number elements of the unread elements in the memory into the cache.

[0054] If the number of real number elements read in this loop is greater than the number of unread real number elements in the cache, that is, the number of unread elements in the cache is less than 2M, the instructions in the first target instruction set can be used to read the first 2M real number elements of the unread elements from the memory.

[0055] As a possible implementation method, the number of real number elements pre-fetched can be set to an integer multiple of 2M of the number of real number elements read each time, so that the number of elements in the cache can be guaranteed to be exactly 0 after an integer number of cycles. When the number of elements in the cache is equal to 0, the first 2M elements of the unread elements can be re-read from the memory, and the first N real number elements of the unread elements can be pre-fetched into the cache.

[0056] In another possible implementation, the position of the real number element currently being read in the real number vector may also be recorded, for example, the array subscript of the real number element in the real number vector may be recorded. When the number of real number elements in the cache is less than 2M, the unread element corresponding to the array subscript may be determined in the memory based on the subscript of the next real number element to be read, and 2M real number elements may be read starting from the unread element using the instructions of the first target instruction set. Starting from the next unread real number element of the last real number element read, N real number elements may be pre-fetched from the memory into the cache using the instructions of the first target instruction set.

[0057] In an embodiment of the present application, by pre-fetching real number elements from the memory into the cache after reading the real number elements from the memory, the number of times data is read from the memory can be reduced for large-scale data computing scenarios, thereby improving the performance of the processor.

[0058] The above-mentioned S301-S303 steps are an implementation method of reading real elements. In another implementation method, M real elements of the real vector can be read from the memory based on the first target instruction set, and M real elements of the unread elements can be pre-fetched from the memory at the same time. After the operation of the M real elements read from the memory is completed, M real elements can be read from the cache for operation. After the operation of the M real elements in the cache is completed, the steps of reading the M real elements of the unread elements from the memory and pre-fetching the M real elements of the unread elements are re-executed until the operation of all real elements and real constants is completed.

[0059] The following is a further explanation of reading 2M real number elements of a real number vector from a memory based on the first target instruction set, and storing each real number element in the first register, the second register, the third register, and the fourth register in sequence, such as Figure 4 As shown, the above step S202 includes: S401, calling the first instruction in the first target instruction set, reading the first M real number elements in the 2M real number vectors, and storing the read real number elements in the first register and the second register.

[0060] The first target instruction set may be an assembly instruction set corresponding to the NEON intrinsics instruction set, and the first instruction may be an assembly instruction corresponding to the vld1q_f32 instruction in the NEON intrinsics instruction set, that is, the ldp instruction. The vld1q_f32 instruction is used to retrieve data from the memory and store the data in a register.

[0061] Optionally, when reading real number elements, the first M real number elements may be read sequentially from front to back according to the order of the real number elements in the real number vector, and the real number elements may be stored in the first register and the second register in the order of reading.

[0062] S402, calling the first instruction in the first target instruction set, reading the last M real number elements in the 2M real number vectors, and storing the real number elements in the third register and the fourth register.

[0063] After storing the first M real number elements in the register, the ldp instruction may be called again to sequentially read the next M real number elements from the memory, and store each real number element in the third register and the fourth register in the order of reading.

[0064] It should be noted that the above is an implementation method of reading and storing real number elements in registers. In a second implementation method, the first instruction can also be called to read 2M real number elements from the memory, and the real number elements are stored in the first register, the second register, the third register, and the fourth register in the order of reading.

[0065] In a third implementation, the first instruction may be called to read the first M real number elements from the memory, and the prefetch instruction in the first target instruction set may be called to prefetch the last M real number elements from the memory into the cache. In this case, in the above step S402, the first instruction may be to read the last M real number elements from the cache and store each real number element in the third register and the fourth register. The prefetch instruction may be the prfm pldllkeep instruction in the NEON intrinsics instruction set.

[0066] Next, the steps of reading a real constant from the memory, copying a plurality of real constants based on the first target instruction set, and storing the copied plurality of real constants in a constant register are described. The step S201 includes: The second instruction in the first target instruction set is called to copy the real constant, and the multiple copied real constants are stored in the constant register in sequence.

[0067] The second instruction may be an assembly instruction corresponding to the vdupq_n_f32 instruction in the NEON intrinsics instruction set. The vdupq_n_f32 instruction is used to copy an input constant and store the copied constant in a constant register.

[0068] Optionally, the number of copied real constants may be determined based on the number of registers storing real number elements. If the number of registers storing real number elements is 4, the real constant may be copied 4 times and stored in constant registers.

[0069] The following is a further explanation of the above-mentioned operation based on the first target instruction set on the real constant in the constant register and the real elements in the first register, the second register, the third register and the fourth register, and storing the operation results in the associated memory of the real vector. Figure 5 As shown, the above step S203 includes: S501. Call the third instruction in the first target instruction set, read real number elements from the first register, the second register, the third register and the fourth register respectively, read the real number constant from the constant register, perform operations on the real number elements and the real number constants, and store the operation results of each real number element in the fifth register corresponding to the first register, the sixth register corresponding to the second register, the seventh register corresponding to the third register and the eighth register corresponding to the fourth register respectively.

[0070] The third instruction may be an assembly instruction corresponding to an operation instruction in the NEON intrinsics instruction set, for example, an fadd instruction corresponding to an addition instruction vaddq_f32 instruction.

[0071] Optionally, the third instruction can be called four times to calculate the real elements in the first register, the second register, the third register and the fourth register with the real constant in the constant register, respectively, to obtain the operation results of the real elements in each register and the real constant, and save the operation result of the first register in the fifth register, the operation result of the second register in the sixth register, the operation result of the third register in the seventh register, and the operation result of the fourth register in the eighth register.

[0072] For example, assuming that you want to calculate the result of adding a real vector and a real constant, you can call the fadd instruction four times to calculate the addition results of the real elements and the real constant in the first register, the second register, the third register, and the fourth register, and store the addition results of the first register, the second register, the third register, and the fourth register in the fifth register, the sixth register, the seventh register, and the eighth register, respectively.

[0073] S502, calling the fourth instruction in the first target instruction set to store the operation results in the fifth register, the sixth register, the seventh register and the eighth register into the associated memory of the real number vector.

[0074] The fourth instruction may be an assembly instruction corresponding to the vst1q_f32 instruction in the NEON intrinsics instruction set, that is, the stp instruction. The vst1q_f32 instruction is used to store data in the register into the memory.

[0075] When the fourth instruction is called to store the operation results into the associated memory of the real number vector, the operation results may be stored in the associated memory of the real number vector in sequence according to the order of the real number elements corresponding to the operation results in the real number vector.

[0076] The following is a further explanation of calling the fourth instruction in the first target instruction set to store the operation results in the fifth register, the sixth register, the seventh register, and the eighth register into the associated memory of the real vector. Figure 6 As shown, the above step S502 includes: S601, calling the fourth instruction in the first target instruction set, storing the operation results in the fifth register and the sixth register into the position indicated by the current pointing address of the associated memory, and offsetting the current pointing address backward by a preset number of bytes to obtain a new current pointing address.

[0077] The current pointing address is used to indicate the starting location for data storage. By calling the fourth instruction, the calculation results in the fifth register and the sixth register can be stored in the location indicated by the current pointing address, and the current pointing address can be offset backward by a preset number of bytes to obtain a new current pointing address.

[0078] S602, calling the fourth instruction in the first target instruction set, storing the operation results in the seventh register and the eighth register into the position indicated by the new current pointing address, and offsetting the new current pointing address backward by a preset number of bytes to obtain the current pointing address for the next loop.

[0079] The preset number of bytes may be the total number of bytes of the operation results of the fifth register and the sixth register, and the new current address may point to the next location in the memory of the last operation result of the sixth register. The fourth instruction is called again to store the operation results in the seventh register and the eighth register into the associated memory, and the current address is continuously shifted backward by the preset number of bytes, and the new current address may point to the last operation result of the eighth register.

[0080] Next, combine Figure 7 The process of operating a real number vector and a real number constant based on a first programming language is described, wherein the data type of the real number vector is a single precision type.

[0081] Reference Figure 7 , real vector Since the vector length K of the real number vector is greater than the preset length threshold M, the real number vector and the real number constant can be operated based on the first programming language.

[0082] First, call the ldp instruction from vector The first 16 float real number elements a0, a1…a15 are read from the associated memory and stored in registers q0, q1, q2, and q3 respectively, with each register storing 4 elements. "ldp q0, q1, [% [ap]], 0x20" means reading 32 bytes from the address pointed to by ap, that is, reading 8 float data at a time and storing them in registers q0 and q1, q0 stores the first four a0-a3, q1 stores a4-a7, and the address pointed to by ap is offset 32 ​​bytes backward. The prfmpldllkeep prefetch instruction is called to prefetch 1024 bytes of data into the cache starting from the address pointed to by ap, so that the real number elements can be read directly from the cache the next time the data is read.

[0083] Then, the fadd instruction is called four times to add registers q0-q3 to register q8 respectively, where 4 constants b are stored in register q8, and the addition results are stored in registers q4-q7. Each register stores 16 added float elements / data in sequence.

[0084] Next, the stp instruction is called to store the 16 float elements in registers q4-q7 into the memory addresses associated with the first 16 elements of vector R in sequence: "stp q4,q5,[%[rp]],0x20" means storing 32 bytes at the memory address pointed to, that is, storing 8 float data at a time into the q4 and q5 registers, and offsetting the memory address pointed to by 32 bytes.

[0085] Call the vaddq_f32 instruction 8 times to add registers D1-D8 to register D0 respectively, and store the addition results in registers D1-D8, where each register stores the 32 added elements in sequence. Call the vst1q_f32 instruction to store the 32 float elements on registers D1-D8 in sequence into the first 32 items of vector R, where vector R is the associative memory of the real vector.

[0086] Repeat the above steps until the addition results of all real number elements of the real number vector and the real number constant are stored in the associated memory. If there are still remainders, the remaining real number elements are calculated using the conventional real number element and real number constant addition method.

[0087] The following is a further explanation of the second target instruction set based on the second programming language, reading real vectors and real constants from the memory, and performing operations on the real vectors and real constants to obtain operation results, such as Figure 8 As shown, the above step S203 includes: S801. Read a real number constant from a memory, and based on a second target instruction set, copy a plurality of the real number constants and store them in constant registers.

[0088] Alternatively, the real constant may be read from the memory using an instruction in the second target instruction set, and the real constant may be copied multiple times and stored in constant registers using an instruction in the second target instruction set.

[0089] S802. Based on the second target instruction set, starting from the memory pointing address in the memory, read nQ real elements of the real vector, store each real element in Q ninth registers in sequence, and modify the memory pointing address to the address of the next real element of the last real element read, where n is an integer greater than 0, and Q is an integer greater than 0.

[0090] In a first implementation, instructions in the second target instruction set may be used to sequentially read n real elements from the memory in the order in which the real elements are stored, store the read n real elements in the first register, and then loop through the steps of reading n real elements until the Q ninth registers store the real elements of the real vector. After each reading of a real element, the current memory address may be offset to the next memory address of the last real element read.

[0091] The second implementation method can use instructions in the second target instruction set to read nQ real elements from the memory in the storage order of the real elements, store the real elements in Q registers in the reading order, and offset the current memory address to the next memory address of the last real element read.

[0092] S803. Perform operations on the real constant in the constant register and the real elements in each ninth register based on the second target instruction set, and store the operation results in each ninth register.

[0093] Optionally, instructions in the second target instruction set can be used to copy multiple real constants and store them in constant registers, and instructions in the second target instruction set can be used to read real elements from the ninth register, read real constants from the constant registers, and operate the read real constants with the real elements.

[0094] When storing the operation result, the operation result may be stored at the position of each real number element in the ninth register according to the order of the real number elements.

[0095] S804. Store the operation results in each ninth register into the associated memory of the real number vector based on the second target instruction set.

[0096] Steps S802 to S804 are repeated until the operation on all real number elements in the real number vector is completed, and the operation result in the associated memory is used as the operation result of the real number vector and the real number constant.

[0097] Optionally, the associated memory is used to store calculation results. When the number of elements in the real vector is large, the calculation of the real vector and the real constant may require multiple rounds. After each round, the calculation result in the ninth register can be stored in the associated memory of the real vector. After completing the calculation of all real elements in the real vector and storing the calculation results in the associated memory, the calculation result in the associated memory can be used as the calculation result of the real vector and the real constant.

[0098] When storing the operation results in the associated memory, the operation results can be stored in the associated memory in sequence according to the order of the operation results in the ninth register, and the first operation result of the next round can be stored in the next memory position of the last operation result in the associated memory.

[0099] Optionally, the process of reading the real constant from the memory, and copying a plurality of the real constants based on the second target instruction set and storing them in constant registers includes: The fifth instruction in the second target instruction set is called to copy the real constant, and the multiple real constants obtained by copying are stored in the constant register in sequence.

[0100] The second target instruction set may be a NEON intrinsics instruction set, and the fifth instruction may be a vdupq_n_f32 instruction in the NEON intrinsics instruction set. The vdupq_n_f32 instruction is used to copy a plurality of input real constants and store the copied plurality of real constants in a constant register.

[0101] Exemplarily, the vdupq_n_f32 instruction may be used to copy the input constant b into four copies, and the four constants b may be stored in the constant registers in sequence.

[0102] It should be noted that the number of real constant copies can be determined based on the number of ninth registers. In a possible implementation, the number of real constant copies can be the same as the number of ninth registers, and each real constant is operated on a real element in a ninth register.

[0103] The following is a further description of the above-mentioned reading nQ real number elements of the real number vector from the memory pointing address in the memory based on the second target instruction set, and storing each real number element in Q ninth registers in sequence. The above-mentioned step S802 includes: The sixth instruction in the second target instruction set is called to read n real number elements of the real number vector from the memory, and store the read real number elements into the first ninth register.

[0104] Repeat the step of calling the sixth instruction in the second target instruction set, read n real number elements of the real number vector from the memory, and store the real number elements in the next ninth register, until nQ real number elements of the real number vector are stored in Q ninth registers respectively.

[0105] The sixth instruction may be the vld1q_f32 instruction in the NEON intrinsics instruction set. The vld1q_f32 instruction may be used to read n real number elements from the memory and store the read real number elements into the first ninth register in the order of reading.

[0106] Continue to call the vld1q_f32 instruction until nQ real elements are read from the real vector, and the read nQ real elements are stored in Q ninth registers respectively. When the real vector is of single precision type, the value of n can be 4 and the value of Q can be 8.

[0107] The following is a further description of the above-mentioned operation based on the second target instruction set on the real constant in the constant register and the real elements in each ninth register, and storing the operation results in each ninth register. The above-mentioned step S803 includes: The seventh instruction in the second target instruction set is called to read real number elements from each ninth register and real number constants from the constant register, perform four arithmetic operations on the real number elements and the real number constants, and store the operation results of each real number element in the position corresponding to the real number element in each ninth register.

[0108] Optionally, the seventh instruction may be an operation instruction in the NEON intrinsics instruction set. Taking the addition operation of a real vector and a real constant as an example, the seventh instruction may be a vaddq_f32 instruction.

[0109] The seventh instruction is called to read the real constant from the constant register and read the real elements from each ninth register, four arithmetic operations are performed on the real constant and the real elements, and the operation results are stored in the position where the real elements are located in the ninth register. After completing the operation on all real elements in the current ninth register, the operation results in the ninth register can be saved in the associated memory in sequence.

[0110] The process of storing the operation results in each ninth register into the associated memory of the real number vector based on the second target instruction set includes: The eighth instruction in the second target instruction set is called to store the operation results in each ninth register into the associated memory of the real number vector.

[0111] The eighth instruction may be a vst1q_f32 instruction in the NEON intrinsics instruction set, which is used to retrieve the operation result in the ninth register and store the retrieved operation result in the associated memory.

[0112] Fig. 9 The invention is a flowchart for operating a real vector and a real constant based on a second programming language, wherein the data type of the real vector is a single precision type.

[0113] Reference Fig. 9 , real vector Since the vector length K of the real number vector is less than the preset length threshold M, the real number vector and the real number constant can be operated based on the second programming language.

[0114] First, call the vld1q_f32 instruction from vector Read the first four float real number elements a0, a1, a2, and a3 from the associated memory and store them in register D1. Repeat the vld1q_f32 instruction to store the 28 elements of a4-a31 in registers D2-D8 respectively. Then use the vdupq_n_f32 instruction to copy 4 copies of the real number constant b and store them in register D0. Call the vaddq_f32 instruction 8 times to add registers D1-D8 to register D0 respectively, and store the addition results in registers D1-D8, where each register stores the 32 added elements in sequence. Call the vst1q_f32 instruction to store the 32 float elements in registers D1-D8 in sequence into the first 32 items of vector R, where vector R is used to indicate the location of the real number vector in the associated memory.

[0115] After repeating the above steps m times, the vector The result of adding the n elements of and the constant b is stored in the associated memory. If there are remainders, the remaining real elements are operated using the conventional real element and real constant addition method to obtain the operation result of the real vector and the real constant.

[0116] Based on the same inventive concept, a real number vector operation processing device corresponding to the real number vector operation processing method is also provided in the embodiment of the present application. Since the principle of solving the problem by the device in the embodiment of the present application is similar to the above-mentioned real number vector operation processing method in the embodiment of the present application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0117] Fig.10 A module structure diagram of a real number vector operation processing device provided in an embodiment of the present application, such as Fig.10 As shown, the device comprises: An acquisition module 1001 is used to acquire the vector length of the real number vector to be calculated and a preset length threshold; A first operation module 1002 is used for reading a real vector and a real constant from a memory based on a first target instruction set of a first programming language if the vector length is greater than a preset length threshold, and performing an operation on the real vector and the real constant to obtain an operation result; The second operation module 1003 is used to read the real vector and the real constant from the memory and operate on the real vector and the real constant to obtain the operation result based on the second target instruction set of the second programming language if the vector length is less than or equal to the preset length threshold, wherein the level of the first programming language is lower than the level of the second programming language.

[0118] As a possible implementation manner, the first operation module 1002 is specifically configured to: A. reading a real constant from a memory, copying the real constant based on a first target instruction set to obtain a plurality of real constants, and storing the copied plurality of real constants in a constant register; B. Read 2M real number elements in the real number vector based on the first target instruction set, and store the real number elements in a first register, a second register, a third register, and a fourth register in sequence, where M is an integer greater than 0; C. Based on the first target instruction set, respectively operate the real constant in the constant register and the real elements in the first register, the second register, the third register, and the fourth register, and store the operation results in the associated memory of the real vector; D. Repeat steps BC until the operation on all real elements in the real vector is completed, and the operation result in the associated memory is used as the operation result of the real vector and the real constant.

[0119] As a possible implementation manner, the first operation module 1002 is specifically configured to: If the current loop is in the first round, 2M real number elements in the real number vector are read from the memory based on the first target instruction set, and the first N real number elements of the unread elements in the memory are pre-fetched into the cache, where N is an integer greater than 0; If the current loop is not the first loop, and the number of unread elements in the cache is greater than or equal to 2M, the first 2M real number elements of the unread elements are read from the cache based on the first target instruction set; If the current loop is not the first round and the number of unread elements in the cache is less than 2M, the first 2M real number elements of the unread elements are read from the memory based on the first target instruction set, and the first N real number elements of the unread elements are pre-fetched from the memory into the cache.

[0120] As a possible implementation manner, the first operation module 1002 is specifically configured to: Calling a first instruction in a first target instruction set, reading first M real number elements in the 2M real number vectors, and storing the read real number elements in a first register and a second register; The first instruction in the first target instruction set is called to read the last M real number elements in the 2M real number vectors, and store the real number elements in the third register and the fourth register.

[0121] As a possible implementation manner, the first operation module 1002 is specifically configured to: The second instruction in the first target instruction set is called to copy the real constant, and the multiple copied real constants are stored in the constant register in sequence.

[0122] As a possible implementation manner, the first operation module 1002 is specifically configured to: Calling the third instruction in the first target instruction set, reading real number elements from the first register, the second register, the third register, and the fourth register respectively, reading real number constants from the constant register, performing operations on the real number elements and the real number constants, and storing the operation results of each real number element in a fifth register corresponding to the first register, a sixth register corresponding to the second register, a seventh register corresponding to the third register, and an eighth register corresponding to the fourth register respectively; The fourth instruction in the first target instruction set is called to store the operation results in the fifth register, the sixth register, the seventh register and the eighth register into the associated memory of the real number vector.

[0123] As a possible implementation manner, the first operation module 1002 is specifically configured to: Calling the fourth instruction in the first target instruction set, storing the operation results in the fifth register and the sixth register into the location indicated by the current pointing address of the associated memory, and shifting the current pointing address backward by a preset number of bytes to obtain a new current pointing address; The fourth instruction in the first target instruction set is called, the operation results in the seventh register and the eighth register are stored in the position indicated by the new current pointing address, and the new current pointing address is offset backward by a preset number of bytes to obtain the current pointing address for the next loop.

[0124] As a possible implementation manner, the second operation module 1003 is specifically configured to: A. Read a real constant from the memory, and based on the second target instruction set, copy a plurality of the real constants and store them in constant registers; B. Based on the second target instruction set, starting from the memory pointing address in the memory, read nQ real elements of the real vector, store each real element in Q ninth registers in sequence, and modify the memory pointing address to the address of the next real element of the last real element read, where n is an integer greater than 0, and Q is an integer greater than 0; C. Based on the second target instruction set, respectively operate the real constant in the constant register and the real elements in each ninth register, and store the operation results in each ninth register; D. storing the operation results in each ninth register into an associated memory of the real number vector based on the second target instruction set; E. Repeat steps BD until the operation on all real elements in the real vector is completed, and the operation result in the associated memory is used as the operation result of the real vector and the real constant.

[0125] As a possible implementation manner, the second operation module 1003 is specifically configured to: The fifth instruction in the second target instruction set is called to copy the real constant, and the multiple real constants obtained by copying are stored in the constant register in sequence.

[0126] As a possible implementation manner, the second operation module 1003 is specifically configured to: Call the sixth instruction in the second target instruction set to read n real number elements of the real number vector from the memory, and store the read real number elements into the first ninth register; Repeat the step of calling the sixth instruction in the second target instruction set, read n real number elements of the real number vector from the memory, and store the real number elements in the next ninth register, until nQ real number elements of the real number vector are stored in Q ninth registers respectively.

[0127] As a possible implementation manner, the second operation module 1003 is specifically configured to: The seventh instruction in the second target instruction set is called to read real number elements from each ninth register and real number constants from the constant register, perform four arithmetic operations on the real number elements and the real number constants, and store the operation results of each real number element in the position corresponding to the real number element in each ninth register.

[0128] As a possible implementation, based on the second target instruction set, storing the operation results in each ninth register into the associated memory of the real number vector includes: The eighth instruction in the second target instruction set is called to store the operation results in each ninth register into the associated memory of the real number vector.

[0129] The present application embodiment also provides a computer device 110, such as Fig.11 1 is a schematic diagram of the structure of a computer device 110 provided in an embodiment of the present application, including: a processor 1101, a memory 1102, and optionally, a bus 1103. The memory 1102 stores machine-readable instructions executable by the processor 1101 (for example, Fig.10 In the device, the execution instructions corresponding to the acquisition module 1001, the first operation module 1002 and the second operation module 1003 are obtained, etc.), when the computer device 110 is running, the processor 1101 communicates with the memory 1102 through the bus 1103, and when the machine-readable instructions are executed by the processor 1101, the steps of the real number vector operation processing method in the above method embodiment are executed.

[0130] The embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the real number vector operation processing method in the above method embodiment are executed.

[0131] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0132] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or part of the technical solution that contributes to the prior art or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), disk or optical disk and other media that can store program code.

[0133] The above are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims

1. A real number vector operation processing method, characterized in that: For performing operations on real vectors and real constants, the method comprises: Obtaining the vector length of the real number vector to be calculated and a preset length threshold; If the vector length is greater than the preset length threshold, based on a first target instruction set of a first programming language, read a real vector and a real constant from a memory, and perform operations on the real vector and the real constant to obtain an operation result; If the vector length is less than or equal to the preset length threshold, based on a second target instruction set of a second programming language, a real number vector and a real number constant are read from a memory, and operations are performed on the real number vector and the real number constant to obtain an operation result, wherein the level of the first programming language is lower than the level of the second programming language.

2. The method according to claim 1, characterized in that The first target instruction set based on the first programming language reads a real number vector and a real number constant from a memory, and operates the real number vector and the real number constant to obtain an operation result, including: A. reading a real number constant from a memory, copying the real number constant based on a first target instruction set to obtain a plurality of real number constants, and storing the copied plurality of real number constants in a constant register; B. Read 2M real number elements in the real number vector based on the first target instruction set, and store the real number elements in a first register, a second register, a third register, and a fourth register in sequence, where M is an integer greater than 0; C. performing operations on the real constant in the constant register and the real elements in the first register, the second register, the third register, and the fourth register respectively based on the first target instruction set, and storing the operation results in the associated memory of the real vector; D. Repeat steps BC until the operation on all real elements in the real vector is completed, and use the operation result in the associated memory as the operation result of the real vector and the real constant.

3. The method according to claim 2, characterized in that The step of reading 2M real number elements in a real number vector based on a first target instruction set includes: If the current loop is in the first round, 2M real number elements in the real number vector are read from the memory based on the first target instruction set, and the first N real number elements of the unread elements in the memory are pre-fetched into the cache, where N is an integer greater than 0; If the current loop is not the first round, and the number of unread elements in the cache is greater than or equal to 2M, read the first 2M real number elements of the unread elements from the cache based on the first target instruction set; If the current loop is not the first round and the number of unread elements in the cache is less than 2M, the first 2M real number elements of the unread elements are read from the memory based on the first target instruction set, and the first N real number elements of the unread elements are pre-fetched from the memory into the cache.

4. The method according to claim 2, characterized in that: The method of reading 2M real number elements of the real number vector from the memory based on the first target instruction set and storing each of the real number elements in a first register, a second register, a third register and a fourth register in sequence includes: Calling a first instruction in a first target instruction set, reading first M real number elements in the 2M real number vectors, and storing the read real number elements in a first register and a second register; The first instruction in the first target instruction set is called to read the last M real number elements in the 2M real number vectors, and store the real number elements in the third register and the fourth register.

5. The method according to claim 2, characterized in that: The step of reading a real constant from a memory, duplicating a plurality of the real constants based on a first target instruction set, and storing the duplicated plurality of real constants in a constant register comprises: The second instruction in the first target instruction set is called to copy the real constant, and the multiple real constants obtained by copying are stored in the constant register in sequence.

6. The method according to claim 2, characterized in that The method of performing operations on the real constant in the constant register and the real elements in the first register, the second register, the third register, and the fourth register respectively based on the first target instruction set, and storing the operation results in the associated memory of the real vector, includes: Calling a third instruction in the first target instruction set, reading real number elements from the first register, the second register, the third register, and the fourth register respectively, reading a real number constant from the constant register, performing operations on the real number elements and the real number constants, and storing the operation results of each real number element in a fifth register corresponding to the first register, a sixth register corresponding to the second register, a seventh register corresponding to the third register, and an eighth register corresponding to the fourth register; The fourth instruction in the first target instruction set is called to store the operation results in the fifth register, the sixth register, the seventh register and the eighth register into the associated memory of the real number vector.

7. The method according to claim 6, characterized in that The calling of the fourth instruction in the first target instruction set to store the operation results in the fifth register, the sixth register, the seventh register, and the eighth register into the associated memory of the real number vector includes: Calling the fourth instruction in the first target instruction set, storing the operation results in the fifth register and the sixth register into the location indicated by the current pointing address of the associated memory, and shifting the current pointing address backward by a preset number of bytes to obtain a new current pointing address; Call the fourth instruction in the first target instruction set, store the operation results in the seventh register and the eighth register into the position indicated by the new current pointing address, and offset the new current pointing address backward by a preset number of bytes to obtain the current pointing address for the next loop.

8. The method according to claim 1, characterized in that: The second target instruction set based on the second programming language reads a real number vector and a real number constant from the memory, and operates the real number vector and the real number constant to obtain an operation result, including: A. reading a real constant from a memory, and based on a second target instruction set, copying a plurality of the real constants and storing the copies in constant registers; B. Based on the second target instruction set, starting from the memory pointing address in the memory, read nQ real elements of the real vector, store each of the real elements in Q ninth registers in sequence, and modify the memory pointing address to the address of the next real element of the last real element read, where n is an integer greater than 0, and Q is an integer greater than 0; C. performing operations on the real constant in the constant register and the real elements in each of the ninth registers based on the second target instruction set, and storing the operation results in each of the ninth registers; D. storing the operation results in each of the ninth registers into the associated memory of the real number vector based on the second target instruction set; E. Repeat steps BD until the operation on all real elements in the real vector is completed, and use the operation result in the associated memory as the operation result of the real vector and the real constant.

9. The method according to claim 8, characterized in that The step of reading a real constant from a memory and duplicating a plurality of the real constants based on a second target instruction set and storing the copies in constant registers comprises: The fifth instruction in the second target instruction set is called to copy the real constant, and the multiple real constants obtained by copying are stored in the constant register in sequence.

10. The method according to claim 8, characterized in that The method of reading nQ real number elements of the real number vector from the memory pointing address in the memory based on the second target instruction set, and sequentially storing each of the real number elements in Q ninth registers, includes: Call the sixth instruction in the second target instruction set to read n real number elements of the real number vector from the memory, and store the read real number elements into the first ninth register; Repeat the step of calling the sixth instruction in the second target instruction set, read n real number elements of the real number vector from the memory, and store the real number elements in the next ninth register, until the nQ real number elements of the real number vector are stored in Q ninth registers respectively.

11. The method according to claim 8, characterized in that The method of respectively operating the real constant in the constant register and the real elements in each of the ninth registers based on the second target instruction set, and storing the operation results in each of the ninth registers, includes: Call the seventh instruction in the second target instruction set, read the real number elements from each of the ninth registers, and read the real number constants from the constant registers, perform four arithmetic operations on the real number elements and the real number constants, and store the operation results of each real number element in the position corresponding to the real number element in each of the ninth registers.

12. The method according to claim 8, characterized in that The step of storing the operation results in each of the ninth registers into the associated memory of the real number vector based on the second target instruction set includes: The eighth instruction in the second target instruction set is called to store the operation results in each of the ninth registers into the associated memory of the real number vector.

13. A real number vector operation processing device, characterized in that: include: An acquisition module, used to acquire the vector length of the real number vector to be calculated and a preset length threshold; A first operation module, configured to read a real vector and a real constant from a memory based on a first target instruction set of a first programming language if the length of the vector is greater than the preset length threshold, and operate on the real vector and the real constant to obtain an operation result; A second operation module is used to read a real number vector and a real number constant from a memory and operate on the real number vector and the real number constant to obtain an operation result based on a second target instruction set of a second programming language if the vector length is less than or equal to the preset length threshold, wherein the level of the first programming language is lower than the level of the second programming language.

14. An electronic device, characterized in that: include: A processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the storage medium communicate via the bus, and the processor executes the machine-readable instructions to perform the steps of a real number vector operation processing method as described in any one of claims 1 to 12.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the real number vector operation processing method as claimed in any one of claims 1 to 12 are executed.

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