Method, device, equipment and product for loading boot program on chip

Abstract

The present disclosure provides a method, device, equipment and product for loading a boot program on a chip, and relates to the field of integrated circuit chips. The present invention comprises: the main core of the chip loads a first boot program and wakes up the slave core of the chip; after the main core loads the second boot program, it writes identification data in a specified storage address; if the slave core can read the identification data in the specified storage address, the slave core loads the second boot program. The method, device, equipment and product for loading a boot program on a chip disclosed by the present invention can realize that after the main core loads the second boot program, the remaining slave cores load the second boot program, avoiding the problem that the slave core loads the boot program abnormally due to the slave core loading the second boot program before the main core, causing the chip to fail to work normally. It has the characteristics of small computational complexity, low resource occupation, high reliability and wide application range.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit chips, and in particular relates to a method, device, equipment and product for loading a boot program on a chip. Background Art

[0002] With the continuous development of integrated circuit chip technology, multi-core chips have become widely used. Multi-core chips can include a master core and several slave cores within a single chip. The master core and the slave cores work together to effectively improve chip performance. However, under existing technology, the chip must load the boot program after power-up. Due to the different speeds and methods of loading the boot program between the master and slave cores within the chip, the slave cores are prone to abnormal loading of the boot program, causing the chip to malfunction. Summary of the Invention

[0003] In view of this, the present invention aims to overcome the defects in the prior art and proposes a method, device, equipment and product for loading a boot program on a chip.

[0004] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0005] In a first aspect, the present invention discloses a method for loading a boot program onto a chip, comprising:

[0006] The master core of the chip loads the first boot program and wakes up the slave core of the chip;

[0007] After the main core loads the second boot program, it writes identification data into the specified storage address;

[0008] If the slave core can read the identification data in the designated storage address, the slave core loads the second boot program.

[0009] In another embodiment of the present invention, the first boot program is a boot ROM program.

[0010] In another embodiment of the present invention, the second boot program is a second segment loader SPL.

[0011] In another embodiment of the present invention, the designated storage address is a designated storage address set in a chip memory.

[0012] In another embodiment of the present invention, if the slave core can read the identification data in the specified storage address, including: the data read by the slave core from the specified storage address is the same as the identification data, then it is determined that the slave core can read the identification data in the specified storage address.

[0013] In another embodiment of the present invention, if the slave core cannot read the identification data in the designated storage address, the slave core reads the data in the designated storage address again according to a set time interval.

[0014] In a second aspect, the present invention discloses a device for loading a boot program on a chip, the device comprising:

[0015] A first loading module is used for the master core of the chip to load the first boot program and wake up the slave core of the chip;

[0016] The first loading module includes a first boot program module, which is used to determine whether the first boot program is a boot ROM program;

[0017] A write identification module is used to write identification data into a specified storage address after the main core loads the second boot program;

[0018] The write identification module includes a second boot program module, which is used to determine that the second boot program is a second segment loader SPL;

[0019] The write identification module includes a storage module, and the storage address used by the storage module to specify is a specified storage address set in the chip memory;

[0020] The second loading module is configured to load the second boot program from the slave core if the slave core can read the identification data from the designated storage address.

[0021] The second loading module includes a determination module for determining if the slave core can read identification data in the specified storage address, including: if the data read from the slave core from the specified storage address is the same as the identification data, then determining that the slave core can read identification data in the specified storage address.

[0022] The device for loading a boot program on a chip further comprises a cyclic reading module for rereading data from the designated storage address from the core according to a set time interval if the core cannot read identification data from the designated storage address.

[0023] In a third aspect, the present invention discloses an electronic device comprising: one or more processors; a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors execute the above method.

[0024] In a fourth aspect, the present invention discloses a computer-readable storage medium having a computer program stored thereon, which implements the above method when executed by a processor.

[0025] In a fifth aspect, the present invention discloses a computer program product, comprising a computer program, which implements the above method when executed by a processor.

[0026] The present invention discloses a method, device, equipment, and product for loading a boot program on a chip, comprising: a main core of a chip loads a first boot program and wakes up a slave core of the chip; after the main core loads a second boot program, identification data is written to a specified storage address; if the slave core can read the identification data at the specified storage address, the slave core loads the second boot program. The method, device, equipment, and product for loading a boot program on a chip disclosed by the present invention can achieve the goal of loading the second boot program on the main core before the remaining slave cores, thereby avoiding the problem of abnormal loading of the slave core boot program due to the slave core loading the second boot program before the main core, which causes the chip to malfunction. The method has the characteristics of low computational complexity, low resource occupation, high reliability, and wide application range. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0028] Figure 1 A schematic diagram of an application scenario of a method for loading a boot program onto a chip according to an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of a method for loading a boot program onto a chip according to an embodiment of the present invention;

[0030] Figure 3 A schematic diagram of a boot program for a method of loading a boot program onto a chip according to an embodiment of the present invention;

[0031] Figure 4 This is a flow chart of a method for loading a boot program onto a chip according to an embodiment of the present invention;

[0032] Figure 5 A schematic diagram of a device for loading a boot program onto a chip according to an embodiment of the present invention;

[0033] Figure 6 The figure is a schematic diagram of an electronic device for loading a boot program onto a chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0035] In the description of the present invention, it should be further clarified that the terms "first," "second," etc. are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0036] The application scenarios of the method, device, equipment and product for loading a boot program on a chip disclosed in the present invention are as follows: Figure 1 As shown, under the existing technical conditions, the chip needs to load the boot program after power-on. Since the speed and method of loading the boot program of the main core and the slave core in the chip are different, it is easy for the slave core to load the second boot program before the main core, resulting in an abnormality in the boot program loading of the slave core, causing the chip to fail to work normally. The present invention discloses a method, device, equipment and product for loading a boot program on a chip, which loads the first boot program through the main core of the chip and wakes up the slave core of the chip; after the main core loads the second boot program, it writes identification data in a specified storage address; if the slave core can read the identification data in the specified storage address, the slave core loads the second boot program, realizing the waiting function of the slave core loading the second boot program, avoiding the abnormality of the slave core loading the boot program, causing the chip to fail to work normally, and has the characteristics of small computational complexity, low resource occupation, high reliability and wide application range.

[0037] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0038] In one embodiment of the present invention, Figure 2 As shown, a method for loading a boot program on a chip includes:

[0039] Step S201: The master core of the chip loads the first boot program and wakes up the slave core of the chip;

[0040] In this embodiment, illustratively, the chip includes a master core and several slave cores. The master core ID can be expressed as hart id0, and the slave core IDs can be expressed as hart id1, hart id2, hart id3, etc.

[0041] After the master core loads the first boot program, it wakes up all slave cores to load the boot program.

[0042] Step S202: After the main core loads the second boot program, it writes identification data into a designated storage address;

[0043] For example, after the main core loads the first boot program, it needs to further load the second boot program. At the same time, the slave core also needs to load the second boot program. However, under existing technical conditions, the loading speeds of the main core and the slave core are different, and it cannot be guaranteed that the slave core will load the second boot program only after the main core has loaded the second boot program. At this time, when the slave core loads the second boot program, the main core needs to load the second boot program to provide necessary support. Therefore, if the slave core loads the second boot program before the main core, an abnormal situation will occur in the slave core loading the second boot program, causing the chip to fail to work normally.

[0044] Step S203: If the slave core can read the identification data in the designated storage address, the slave core loads the second boot program.

[0045] In this embodiment, in step S202 and step S203, as Figure 2 and Figure 4 As shown, after the main core loads the second boot program, it will write identification data in the specified storage address. For example, the identification data can be 0xabcdef. Therefore, if the main core has loaded the second boot program, the slave core can read 0xabcdef from the specified storage address. The identification data can be pre-set data. When the slave core can read this pre-set data from the specified storage address, it proves that the main core has loaded the second boot program. If the slave core does not read this pre-set data from the specified storage address, it proves that the main core has not loaded the second boot program. In order to avoid abnormalities in the loading of the second boot program by the slave core, the slave core needs to wait until the main core has loaded the second boot program, that is, read the identification data from the specified storage address, and then start loading the second boot program.

[0046] In this embodiment, this method implements the waiting function of loading the second boot program from the core, avoiding the problem of abnormal loading of the boot program from the core, which causes the chip to fail to work normally. It has the characteristics of small computational complexity, low resource occupation, high reliability and wide application range.

[0047] In this embodiment, if Figure 3 As shown, the first boot program is a boot ROM program.

[0048] In this embodiment, the boot ROM program is a BootRom boot program, which is a ROM fixed program inside the chip.

[0049] In this embodiment, if Figure 3 As shown, the second boot program is the second segment loader SPL.

[0050] In this embodiment, the second segment loader SPL is a Secondary Program Loader (SPL).

[0051] For example, in actual situations, when loading a boot program on a chip, it is necessary to first load the BootRom boot program and then load the second-segment loader SPL to complete the process of loading the boot program after the chip is powered on.

[0052] In one embodiment of the present invention, Figure 4 As shown, if the slave core can read the identification data in the specified storage address, including: the data read by the slave core from the specified storage address is the same as the identification data, then it is determined that the slave core can read the identification data in the specified storage address.

[0053] In this embodiment, to determine whether the data read from the core from the specified storage address is the same as the identification data, a comparison method is used to determine whether the identification data has been written and whether the main core has loaded the second segment loading program SPL. This has the advantages of high reliability, low computational complexity and low resource usage.

[0054] In this embodiment, the identification data is preset data, for example, 0xabcdef. The identification data written by the slave core based on the known master core is 0xabcdef. The data read by the slave core from the specified storage address is compared with 0xabcdef to see if it is the same. If the master core has not written it, the data read by the slave core from the specified storage address is different from 0xabcdef.

[0055] In this embodiment, the identification data can be flexibly set as needed, and has the characteristic of good applicability.

[0056] In this embodiment, the identification data can be preset as needed, and the slave core performs a comparison based on the data that is known to be written by the master core, and ultimately determines whether the second-segment loader SPL can be loaded.

[0057] In this embodiment, if Figure 4 As shown, the designated storage address is a designated storage address set in the chip memory.

[0058] In this embodiment, the designated storage address is a preset setting. Later, the master core writes the preset identification data of the storage address, and the slave core reads the designated storage address.

[0059] In this embodiment, if Figure 4 As shown, if the slave core cannot read the identification data from the specified storage address, that is, the data read from the specified storage address by the slave core is different from the identification data, the slave core reads the data from the specified storage address again according to the set time interval.

[0060] In this embodiment, the time interval is pre-set as needed to facilitate debugging of the method.

[0061] like Figure 5 As shown, the present invention also discloses a device for loading a boot program on a chip, the device comprising:

[0062] A first loading module 501 is used for the master core of the chip to load the first boot program and wake up the slave core of the chip;

[0063] The first loading module 501 includes a first boot program module, which is used to determine whether the first boot program is a boot ROM program;

[0064] The identification writing module 502 is used to write identification data into a specified storage address after the main core loads the second boot program;

[0065] The write identification module 502 includes a second boot program module for determining that the second boot program is a second segment loader SPL;

[0066] The write identification module 502 further includes a storage module, and the storage module is used to specify a storage address that is set in the chip memory;

[0067] The second loading module 503 is configured to load the second boot program from the slave core if the slave core can read the identification data from the designated storage address.

[0068] The second loading module 503 also includes a determination module for determining whether the slave core can read the identification data at the specified storage address if the slave core can read the identification data at the specified storage address, including: if the data read by the slave core from the specified storage address is the same as the identification data, then determining whether the slave core can read the identification data at the specified storage address.

[0069] The device for loading a boot program on a chip further comprises a cyclic reading module for rereading data from the designated storage address from the core according to a set time interval if the core cannot read identification data from the designated storage address.

[0070] The present invention also discloses an electronic device, such as Figure 6 As shown, an embodiment is disclosed, which is a block diagram of an electronic device suitable for the above-mentioned method of loading a boot program on a chip.

[0071] The electronic device 60 of this embodiment includes a processor 601, which can perform various appropriate actions and processes according to the program stored in the ROM 602 or the program loaded from the storage part 608 into the RAM 603. The processor 601 may include, for example, a general-purpose microprocessor, an instruction set processor and / or a related chipset and / or a dedicated microprocessor, etc. The processor 601 may also include onboard memory for caching purposes. The processor 601 may include a single processing unit or multiple processing units for performing different actions of the method flow according to the embodiment of the present invention.

[0072] RAM 603 stores various programs and data required for the operation of electronic device 60. Processor 601, ROM 602, and RAM 603 are interconnected via bus 604. Processor 601 executes the programs in ROM 602 and / or RAM 603 to perform various operations according to the method flow of the embodiment of the present invention. It should be noted that the programs may also be stored in one or more memories other than ROM 602 and RAM 603, and processor 601 may also execute the programs stored in one or more memories to perform various operations according to the method flow of the embodiment of the present invention.

[0073] According to an embodiment of the present invention, the electronic device 60 may further include an I / O interface 605, which is also connected to the bus 604. The electronic device 60 may further include one or more of the following components connected to the I / O interface 605: an input unit 606 including a keyboard, a mouse, etc.; an output unit 607 including a cathode ray tube, a liquid crystal display, and a speaker; a storage unit 608 including a hard disk; and a communication unit 609 including a network interface card such as a LAN card or a modem. The communication unit 609 performs communication processing via a network such as the Internet. A drive 6010 is also connected to the I / O interface 605 as needed. Removable media 6011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed in the drive 6010 as needed, so that computer programs read therefrom can be installed into the storage unit 608 as needed.

[0074] The present invention also provides a computer-readable storage medium.

[0075] The computer-readable storage medium may be included in the electronic device / device system described in the above embodiments, or may exist independently and not be incorporated into the electronic device / device. The computer-readable storage medium carries one or more programs that, when executed, implement the method according to the embodiments of the present invention.

[0076] According to embodiments of the present invention, a computer-readable storage medium may be a non-volatile computer-readable storage medium. Examples include, but are not limited to, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) or flash memory, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0077] Embodiments of the present invention also include a computer program product.

[0078] The computer program product includes a computer program, which contains program code for executing the method provided by the embodiment of the present invention. When the computer program product runs on an electronic device, the program code is used to enable the electronic device to implement the method provided by the embodiment of the present invention.

[0079] In one embodiment, the computer program may be stored on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may be transmitted and distributed in the form of a signal over a network medium. The program code contained in the computer program may be transmitted using any appropriate network medium, including but not limited to wireless, wired, or any suitable combination thereof.

[0080] According to an embodiment of the present invention, the program code for executing the computer program provided by the embodiment of the present invention can be written by any combination of one or more programming languages. Specifically, these computing programs can be implemented using high-level procedural and / or object-oriented programming languages. Programming languages ​​include, but are not limited to, Java, C++, Python, C language or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network or a wide area network, or can be connected to an external computing device.

[0081] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of the systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram may represent a module, program segment, or portion of code, which contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the boxes may occur in an order different from that marked in the accompanying drawings. For example, two boxes shown in succession may actually be executed substantially in parallel, or they may sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, as well as the combination of boxes in the block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or may be implemented using a combination of dedicated hardware and computer instructions. It will be understood by those skilled in the art that the features described in the various embodiments and / or claims of the present invention may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in the present invention. In particular, without departing from the spirit and teachings of the present invention, the features described in the various embodiments and / or claims of the present invention may be combined and / or coupled in various ways, and all such combinations and / or couplings fall within the scope of the present invention.

[0082] The embodiments of the present invention have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Although each embodiment has been described above separately, this does not mean that the measures in each embodiment cannot be advantageously used in combination. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A method for loading a boot program onto a chip, characterized in that: include: The master core of the chip loads the first boot program and wakes up the slave core of the chip; After the main core loads the second boot program, the main core writes identification data into the designated storage address; If the slave core can read the identification data from the designated storage address, the slave core loads the second boot program.

2. The method for loading a boot program onto a chip according to claim 1, wherein: The first boot program is a boot ROM program.

3. The method for loading a boot program onto a chip according to claim 1, wherein: The second boot program is a second segment loader SPL.

4. The method for loading a boot program onto a chip according to claim 1, wherein: The designated storage address is a designated storage address set in the chip memory.

5. The method for loading a boot program onto a chip according to claim 1, wherein: If the slave core can read the identification data in the specified storage address, it includes: if the data read by the slave core from the specified storage address is the same as the identification data, then it is determined that the slave core can read the identification data in the specified storage address.

6. The method for loading a boot program onto a chip according to claim 1, wherein: The method further includes: if the slave core cannot read the identification data in the designated storage address, then according to a set time interval, the slave core reads the data in the designated storage address again.

7. A device for loading a boot program onto a chip, characterized by: The device comprises: A first loading module, configured to load a first boot program into a master core of a chip and wake up a slave core of the chip; A writing identification module, configured to write identification data into a designated storage address after the main core loads the second boot program; The second loading module is configured to enable the slave core to load the second boot program if the slave core can read the identification data from the designated storage address.

8. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors are caused to perform the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that When the computer program is executed by a processor, it implements the method described in any one of claims 1 to 6.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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